FUJITSU SEMICONDUCTOR FACT SHEET NP501-00016-3v0-E FRAM MB85RS64 MB85RS64 is a 64K-bits FRAM LSI with serial interface (SPI), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES Bit configuration Serial Peripheral Interface ：8,192 words × 8 bits ：SPI(Serial Peripheral Interface) Correspondent to SPI mode 0 (0,0) and mode 3 (1,1) Operating frequency ：20 MHz (Max.) High endurance ：1 trillion Read/writes per byte Data retention ：10 years ( + 85°C ), 95 years ( + 55°C ), over 200 years ( + 35°C ) Operating power supply voltage ：2.7V to 3.6V Low power consumption ：Operating power supply current 1.5mA (Typ＠20MHz) Standby current 5μA (Typ) Operation ambient temperature range ：- 40°C to + 85°C Package ：8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name Package Shipping form MB85RS64PNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube MB85RS64PNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Embossed Carrier tape PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) June 2013 1/2 Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RS64 PIN ASSIGNMENT (TOP VIEW) Pin No. Pin name Description Chip Select pin CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI 1 /CS 3 /WP This is an input pin to make chips select. When /CS is the "H" level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When /CS is the "L" level, device is in select (active) status. /CS has to be the "L" level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register is protected in related with /WP and WPEN bit of the status register. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When /HOLD is the "L" level, hold operation is activated, SO becomes High-Z, SCK and SI become don't care. While the hold operation, /CS has to be retained the "L" level. 7 /HOLD 6 SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 4 VDD GND Serial Clock pin Serial Data Input pin Serial Data Output pin Supply Voltage pin Ground pin BLOCK DIAGRAM SCK HOLD Control Circuit CS Row Decoder Serial-Parallel Converter Address Counter SI FRAM Cell Array 8,192 8 FRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter NP501-00016-3v0-E June 2013 2/2 Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved