FRAM MB85RDP16LX

FUJITSU SEMICONDUCTOR
FACT SHEET
NP501-00033-1v0-E
FRAM
MB85RDP16LX
MB85RDP16LX is a Data-Processing FRAM in a configuration of 2,048 words × 8 bits incorporating a 43-bit or 46-bit binary counter, where
FRAM (Ferroelectric Random Access Memory) is able to retain data without using a back-up battery, can be used for 1013 read/write
operations and takes no wait time to write data, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RDP16LX can be accessed via Serial Peripheral interface (SPI) or Dual SPI.
This Data-Processing FRAM features short power up time, fast memory access and ultra-low power consumption. Together with the 43-bit or
46-bit binary counter function, MB85RDP16LX fits perfectly into energy harvesting and rotary encoder applications.
FEATURES
• Non-volatile memory configuration
• Binary counter bit (for POS0/1/2/3)
• Binary counter bit (for DIBC/DDBC)
• Binary counter operation
• Interface
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Operating frequency
High endurance
Data retention
Operating power supply voltage
Low power consumption
• Operation ambient temperature
• Package
: 2,048 words × 8 bits
: 43-bit range (42bit mantissa + sign bit)
: 46-bit range (45bit mantissa + sign bit)
: Judged by the input position data or directly Increment and Decrement
: SPI (Serial Peripheral Interface) / Dual SPI
Corresponding to SPI mode 0 (0, 0) and mode 3 (1, 1)
: 15 MHz (Max for SPI) / 7.5MHz (Max for Dual SPI)
: 1013 times / byte
: 10 years (+105°C)
: 1.65 V to 1.95 V
: Operating power supply current 0.7 mA (Max@15MHz)
Standby current 11μA (Max @+105°C), 1μA (+25°C)
: 40°C to +105°C
: 8-pin plastic SON (LCC-8P-M04)
RoHS compliant
ORDERING INFORMATION
Product name
Package
Shipping form
MB85RDP16LXPN-G-AMEWE1
Plastic SON,8-pins
(LCC-8P-M04)
2.0mm×3.0mm,0.5mm pitch
Embossed Carrier tape
PACKAGE EXAMPLE OF REFERENCE
8-pin plastic SON
(LCC-8P-M04)
October 2014
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Copyright FUJITSU SEMICONDUCTOR LIMITED
MB85RDP16LX
 PIN ASSIGNMENT
Pin No.
Pin name
1
/CS
3
/WP
7
/RST
6
SCK
5
SI (IO0)
2
SO (IO1)
8
4
VDD
GND
(TOP VIEW)
__
CS
SO
(IO1)
__
WP
VSS
1
8
2
7
VDD
___
RST
3
6
SCK
4
5
SI
(IO0)
(LCC-8P-M04)
Description
Chip Select pin
This is an input pin to activate the device. When /CS is the “H” level,
device is in deselect (standby) status and SO/SI become High-Z. Inputs
from other pins are ignored at this time. When /CS is the “L” level,
device is in select (active) status. /CS has to be the “L” level before
inputting op-code.
Write Protect pin
This is an input pin to control writing to a status register. The writing
of status register is protected in relation with /WP and WPEN bit of the
status register.
Reset pin
This is an input pin to reset the device internally. When /RST is the
"L" level, the interface is inactive and the SPI state machine is reset.
/RST pin need to be "L" at power on.
Serial Clock pin
This is a clock input pin to input/output serial data. Inputs are latched
synchronously to the rising edge, Outputs occur synchronously to the
falling edge.
Serial Data Input pin(Serial Data Input Output 0)
This inputs op-code, addresses or writing data and outputs reading
data. This is High-Z during standby.
Serial Data Output pin(Serial Data Input Output 1)
This outputs reading data or status register and inputs addresses or writing
data. This is High-Z during standby.
Supply Voltage pin
Ground pin
(*)When using Dual SPI instructions, the SI and SO pins become bidirectional IO0 and IO1 pins.
BLOCK DIAGRAM
SI(IO0)
NP501-00033-1v0-E
October 2014
Copyright FUJITSU SEMICONDUCTOR LIMITED
2/2