FUJITSU SEMICONDUCTOR FACT SHEET NP501-00025-1v0-E FRAM MB85RS2MT MB85RS2MT is a 2M-bits FRAM LSI with serial interface (SPI), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES • Bit configuration • Serial Peripheral Interface • • • • • • • 262,144 words × 8 bits SPI(Serial Peripheral Interface) Correspondent to SPI mode 0 (0,0) and mode 3 (1,1) Operating frequency 25 MHz (Max) For FSTRD command 2.7V to 3.6V, 40 MHz (Max) High endurance 1013 times/byte Data retention 10 years (+85 ) Operating power supply voltage 1.8V to 3.6V Low power consumption Operating power supply current 10.6mA (Max@25 MHz) (TBD) Standby current 150μA (Max) (TBD) Sleep current 10μA (Max) (TBD) Operation ambient temperature range -40 to +85 Package 8-pin plastic SOP (FPT-8P-M08) 8-pin plastic DIP (DIP-8P-M03) RoHS compliant ORDERING INFORMATION Product name Package Shipping form MB85RS2MTPF-G-JNE2 Plastic SOP,8-pins (FPT-8P-M08) 5.30mm×5.24mm,1.27mm pitch Tube MB85RS2MTPF-G-JNERE2 Plastic SOP,8-pins (FPT-8P-M08) 5.30mm×5.24mm,1.27mm pitch Embossed Carrier tape MB85RS2MTPH-G-JNE1 Plastic DIP,8-pins (DIP-8P-M03) 6.35mm×9.40mm,2.54mm pitch Tube PACKAGE EXAMPLE OF REFERENCE Plastic ・ SOP、8-pins (FPT-8P-M08) July 2013 Plastic ・ DIP、8-pins (DIP-8P-M03) 1/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RS2MT PIN ASSIGNMENT (TOP VIEW) Pin No. Pin name Description Chip Select pin 1 /CS 3 /WP 7 /HOLD 6 SCK 5 SI 2 SO 8 4 VDD VSS This is an input pin to make chips select. When /CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When /CS is “L” level, device is in select (active) status. /CS has to be “L” level before inputting op-code. Write Protect pin This is a pin to control writing to a status register. The writing of status register is protected in related with /WP and WPEN. Hold pin (FPT-8P-M08) This pin is used to interrupt serial input/output without making chips deselect. When /HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. While the hold operation, /CS has to be retained “L” level. Serial Clock pin (TOP VIEW) This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. Supply Voltage pin Ground pin (DIP-8P-M03) BLOCK DIAGRAM NP501-00025-1v0-E July 2013 2/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved