FUJITSU SEMICONDUCTOR FACT SHEET NP501-00031-1v0-E FRAM MB85RS512T The MB85RS512T is a 512K bits FRAM LSI with serial interface (SPI), using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Since the FRAM is able to write with high-speed operation even though it is a nonvolatile memory, the MB85RS512T is suitable for the log management and the storage of the resume data, etc. FEATURES • Bit configuration • Serial Peripheral Interface • Operating frequency • • • • High endurance Data retention Operating power supply voltage Low power consumption • Operation ambient temperature range • Package : 65,536 words × 8 bits : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0,0) and mode 3 (1,1) : 1.8 V to 2.7 V, 25 MHz (Max) 2.7 V to 3.6 V, 30 MHz (Max) For FSTRD command 2.7 V to 3.6 V, 40 MHz (Max) : 1013 times/byte : 10 years (+85 °C) : 1.8 V to 3.6 V : Operating power supply current 6 mA (Typ@30 MHz) 10 mA (Max@30 MHz) Standby current 120 μA (Max) Sleep current 10 μA (Max) : -40 °C to +85 °C : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name MB85RS512TPNF-G-JNE1 MB85RS512TPNF-G-JNERE1 Package Shipping form Minimum shipping quantity Plastic SOP,8-pins (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube 1* Embossed Carrier tape 1500 *: Please contact our sales office about minimum shipping quantity. OUTLINE OF PACKAGE Plastic ・ SOP、8-pins (FPT-8P-M02) September 2014 1/2 Copyright 2014 FUJITSU SEMICONDUCTOR LIMITED MB85RS512T PIN ASSIGNMENT Pin No. Pin name Description Chip Select pin This is an input pin to make chips select. When /CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When /CS is “L” level, device is in select (active) status. /CS has to be “L” level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register is protected in related with /WP and WPEN. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When /HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. While the hold operation, /CS has to be retained “L” level. Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. Supply Voltage pin Ground pin (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI 1 /CS 3 /WP 7 /HOLD 6 SCK 5 SI 2 SO 8 4 VDD VSS BLOCK DIAGRAM SCK HOLD Control Circuit CS Row Decoder Serial-Parallel Converter Address Counter SI FRAM Cell Array 65,536 ✕ 8 FRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter NP501-00031-1v0-E September 2014 Copyright 2014 FUJITSU SEMICONDUCTOR LIMITED 2/2