FUJITSU SEMICONDUCTOR FACT SHEET NP501-00024-2v0-E FRAM MB85RS1MT MB85RS1MT is a 1M-bits FRAM LSI with serial interface (SPI) , using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES • Bit configuration • Serial Peripheral Interface • • • • • • • 131,072 words × 8 bits SPI(Serial Peripheral Interface) Correspondent to SPI mode 0 (0,0) and mode 3 (1,1) Operating frequency 1.8V to 2.7V, 25 MHz (Max) 2.7V to 3.6V, 30 MHz (Max) For FSTRD command 2.7V to 3.6V, 40 MHz (Max) High endurance 1013 times/byte Data retention 10 years (+85 ) Operating power supply voltage 1.8V to 3.6V Low power consumption Operating power supply current 9.5mA (Max@30 MHz) Standby current 120μA (Max) Sleep current 10μA (Max) Operation ambient temperature range -40 to +85 Package 8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name Package Shipping form MB85RS1MTPNF-G-JNE1 Plastic SOP,8-pins (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube MB85RS1MTPNF-G-JNERE1 Plastic SOP,8-pins (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Embossed Carrier tape PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) August 2013 1/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RS1MT PIN ASSIGNMENT (TOP VIEW ) Pin No. Pin name Description Chip Select pin 1 /CS 3 /WP 7 /HOLD 6 SCK 5 SI 2 SO 8 4 VDD VSS This is an input pin to make chips select. When /CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When /CS is “L” level, device is in select (active) status. /CS has to be “L” level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register is protected in related with /WP and WPEN. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When /HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. While the hold operation, /CS has to be retained “L” level. Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. Supply Voltage pin Ground pin BLOCK DIAGRAM NP501-00024-2v0-E August 2013 2/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved