FUJITSU SEMICONDUCTOR FACT SHEET NP501-00029-1v0-E FRAM MB85RC1MT The MB85RC1MT is a 1M bits FRAM LSI with serial interface (I2C), using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Since the FRAM is able to write with high-speed operation even though it is a nonvolatile memory, the MB85RC1MT is suitable for the log management and the storage of the resume data, etc. FEATURES • Bit configuration • Two-wire serial interface • Operating frequency • • • • Read/write endurance Data retention Operating power supply voltage Low power consumption • Operation ambient temperature range • Package : 131,072 words×8 bits : Fully controllable by two ports: serial clock (SCL) and serial data (SDA). : 3.4 MHz (Max @HIGH SPEED MODE) 1 MHz (Max @FAST MODE PLUS) : 1013 times / byte : 10 years (+85 °C) : 1.8V to 3.6V : Operating power supply current 0.71 mA (Typ @3.4 MHz) 1.2 mA (Max @3.4 MHz) Standby current 15 μA (Typ) Sleep current 4 μA (Typ) : -40 °C to +85 °C : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name MB85RC1MTPNF-G-JNE1 MB85RC1MTPNF-G-JNERE1 Package Shipping form 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm, 1.27mm pitch Tube *: Please contact our sales office about minimum shipping quantity. OUTLINE OF PACKAGE 8-pin plastic SOP (FPT-8P-M02) September 2014 1/2 Copyright 2014 FUJITSU SEMICONDUCTOR LIMITED Embossed Carrier tape Minimum shipping quantity ―* 1500 MB85RC1MT PIN ASSIGNMENT Pin Number 1 Pin Name NC Functional Description No Connect pin Device Address pins The MB85RC1MT can be connected to the same data bus up to 4 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A1and A2 pins are internally pulled-down and recognized as the "L" level. Ground pin Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the external circuit. Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When the Write Protect pin is the “H” level, the writing operation is disabled. When the Write Protect pin is the “L” level, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The write protect pin is internally pulled down to VSS pin, and that is recognized as the “L” level (write enabled) when the pin is the open state. Supply Voltage pin TOP VIEW 2,3 A1,A2 WP 4 VSS 6 SCL 5 SDA 5 SDA 6 SCL 7 WP 8 VDD NC 1 8 VDD A1 2 7 A2 3 VSS 4 BLOCK DIAGRAM SDA WP Address Counter Control Circuit SCL Row Decoder Serial/Parallel Converter FRAM Array 131,072×8 Column Decoder/Sense Amp/ Write Amp A1, A2 I2C The MB85RC1MT has the two-wire serial interface; the I2C bus, and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, the I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. VDD Pull-up Resistors SCL SDA I2C Bus Master I2C Bus MB85RC1MT A2 0 A1 0 I2C Bus MB85RC1MT A2 0 A1 1 I2C Bus MB85RC1MT A2 1 ... A1 0 Device address NP501-00029-1v0-E September 2014 Copyright 2014 FUJITSU SEMICONDUCTOR LIMITED 2/2