GA10JT12-263 Normally – OFF Silicon Carbide Junction Transistor Features Package RoHS Compliant 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode = 1200 V RDS(ON) = 100 mΩ ID (@ 25°C) = 25 A ID (@ 150°C) = 10 A hFE (@ 25°C) = 80 Drain (TAB) TAB Drain Gate (Pin 1) 7 6 5 S 4 S 3 S 2 S 1 S GR G Gate Return Source (Pin 2) (Pin 3, 4, 5, 6, 7) 7L D2PAK (TO-263-7L) Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth VDS Please note: The Source and Gate Return pins are not exchangeable. Their exchange might lead to malfunction. Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings ...........................................................................................................1 Section II: Static Electrical Characteristics ....................................................................................................2 Section III: Dynamic Electrical Characteristics .............................................................................................2 Section IV: Figures ...........................................................................................................................................3 Section V: Driving the GA10JT12-263.............................................................................................................7 Section VI: Package Dimensions ................................................................................................................. 11 Section VII: SPICE Model Parameters ......................................................................................................... 12 Section I: Absolute Maximum Ratings Parameter Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Continuous Gate Return Current Symbol VDS ID ID IG IGR Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Storage Temperature VSG VSD Ptot Tstg Jun 2015 Conditions VGS = 0 V TC = 25°C TC = 150°C TVJ = 175 oC, Clamped Inductive Load TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 150 °C, tp > 100 ms Value 1200 25 10 1.3 1.3 ID,max = 10 @ VDS ≤ VDSmax Unit V A A A A Fig. 15 Fig. 15 A Fig. 17 >20 µs 30 25 170 / 22 -55 to 175 V V W °C http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Notes Fig. 14 Pg 1 of 11 GA10JT12-263 Section II: Static Electrical Characteristics Parameter Symbol Conditions Drain – Source On Resistance RDS(ON) ID = 10 A, Tj = 25 °C ID = 10 A, Tj = 150 °C ID = 10 A, Tj = 175 °C Gate – Source Saturation Voltage VGS,SAT ID = 10 A, ID/IG = 40, Tj = 25 °C ID = 10 A, ID/IG = 30, Tj = 175 °C hFE VDS = 8 V, ID = 10 A, Tj = 25 °C VDS = 8 V, ID = 10 A, Tj = 125 °C VDS = 8 V, ID = 10 A, Tj = 175 °C Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 150 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C Min. Value Typical Max. Unit Notes mΩ Fig. 4 V Fig. 5 A: On State DC Current Gain 100 160 180 3.50 3.27 80 55 48 – B: Off State 0.1 0.1 0.1 20 μA Fig. 6 nA C: Thermal Thermal resistance, junction - case 0.88 RthJC °C/W Fig. 18 Unit Notes Fig. 7 Fig. 7 Fig. 8 Section III: Dynamic Electrical Characteristics Parameter Value Typical Symbol Conditions Ciss Crss/Coss EOSS VGS = 0 V, VDS = 800 V, f = 1 MHz VDS = 800 V, f = 1 MHz VGS = 0 V, VDS = 800 V, f = 1 MHz 1403 30 13 pF pF µJ Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V 55 pF Coss,er VGS = 0 V, VDS = 0…800 V 40 pF QGS QGD QG VGS = -5…3 V VGS = 0 V, VDS = 0…800 V 11 44 55 nC nC nC 2.6 Ω 0.19 10 9 22 9 9 8 35 9 142 7 149 142 6 148 Ω ns ns ns ns ns ns ns ns µJ µJ µJ µJ µJ µJ Min. Max. A: Capacitance and Gate Charge Input Capacitance Reverse Transfer/Output Capacitance Output Capacitance Stored Energy Effective Output Capacitance, time related Effective Output Capacitance, energy related Gate-Source Charge Gate-Drain Charge Gate Charge - Total B: Switching 1 Internal Gate Resistance – zero bias Internal Gate Resistance – ON Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 RG(INT-ZERO) RG(INT-ON) td(on) tf td(off) tr td(on) tf td(off) tr Eon Eoff Etot Eon Eoff Etot f = 1 MHz, VAC = 50 mV, VDS = 0 V, VGS = 0 V, Tj = 175 ºC VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC Tj = 25 ºC, VDS = 800 V, ID = 10 A, Resistive Load Refer to Section V for additional driving information. Tj = 175 ºC, VDS = 800 V, ID = 10 A, Resistive Load Tj = 25 ºC, VDS = 800 V, ID = 10 A, Inductive Load Refer to Section V. Tj = 175 ºC, VDS = 800 V, ID = 10 A, Inductive Load Fig. 9, 11 Fig. 10, 12 Fig. 9 Fig. 10 Fig. 9, 11 Fig. 10, 12 Fig. 9 Fig. 10 – All times are relative to the Drain-Source Voltage VDS Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 11 GA10JT12-263 Section IV: Figures A: Static Characteristics Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: On-Resistance vs. Gate Current Figure 5: Typical Gate – Source Saturation Voltage Figure 6: Typical Blocking Characteristics Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 11 GA10JT12-263 B: Dynamic Characteristics Figure 7: Input, Output, and Reverse Transfer Capacitance Figure 8: Energy Stored in Output Capacitance Figure 9: Typical Switching Times and Turn On Energy Losses vs. Temperature Figure 10: Typical Switching Times and Turn Off Energy Losses vs. Temperature Figure 11: Typical Switching Times and Turn On Energy Losses vs. Drain Current Figure 12: Typical Switching Times and Turn Off Energy Losses vs. Drain Current Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 11 GA10JT12-263 C: Current and Power Derating 2 Figure 13: Typical Hard Switched Device Power Loss vs. Switching Frequency 2 Figure 14: Power Derating Curve Figure 15: Drain Current Derating vs. Temperature Figure 16: Forward Bias Safe Operating Area at Tc= 25 oC Figure 17: Turn-Off Safe Operating Area Figure 18: Transient Thermal Impedance – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 11 GA10JT12-263 Figure 19: Drain Current Derating vs. Pulse Width Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 11 GA10JT12-263 Section V: Driving the GA10JT12-263 Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA10JT12-263 may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (IG,steady) required to operate the GA10JT12-263. The power level of the supply can be estimated from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. 5V SiC SJT TTL Gate Signal D G 5/0V TTL i/p IG,steady S Figure 20: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 21 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 21: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 11 GA10JT12-263 Ideally, IG,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 5) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA10JT12-263 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology. C2 +12 V GA03IDDJT30-FR4 Gate Driver Board VGL VCC High U3 C5 VCC High RTN CG1 VGL VGH Signal R1 R2 U1 CG2 U5 R4 C9 VEE C6 Gate Signal VEE C10 VGL R3 U2 VEE VCC Low RTN G SiC SJT RG2 S C8 VGH VCC Low C1 VEE IG RG1 U6 D1 Signal RTN +12 V D Gate VGL U4 C3 C4 Source VEE Voltage Isolation Barrier Figure 22: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance3 of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA10JT12-263. The steady state current supplied to the gate pin of the GA10JT12-263 with on-board RG = 3.75 Ω, is shown in Figure 23. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 24. For the GA10JT12-263, RG must be reduced for ID ≥ ~10 A for safe operation with the GA03IDDJT30-FR4. For operation at ID ≥ ~10 A, RG may be calculated from the following equation, which contains the DC current gain hFE and the gate-source saturation voltage VGS,sat (Figure 5). Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 11 GA10JT12-263 Figure 23: Typical steady state gate current supplied by the GA03IDDJT30-FR4 board for the GA10JT12-263 with the on board resistance of 3.75 Ω Figure 24: Maximum gate resistance for safe operation of the GA10JT12-263 at different drain currents using the GA03IDDJT30-FR4 board. B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA10JT12-263 at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified I G,on current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 25. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this driving topology.4 VCC S1 VCC S2 L VEE S3 SiC SJT D G RG S4 S VEE Figure 25: Simplified Inductive Pulsed Drive Topology 3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω 4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 11 GA10JT12-263 C: Proportional Gate Current Driving For applications in which the GA10JT12-263 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA10JT12-263 C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA10JT12-263 drain-source voltage VDS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA10JT12-263 are in off-state. A simplified version of this topology is shown in Figure 27, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ HV Diode Sense Gate Signal Proportional Gate Current Driver Signal D G Output IG,steady SiC SJT S Figure 26: Simplified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA10JT12263 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA10JT12-263 is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 27, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 SiC SJT Gate Signal D G S N3 N1 N2 Figure 27: Simplified Current Controlled Proportional Driver Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 11 GA10JT12-263 Section VI: Package Dimensions TO-263-7L PACKAGE OUTLINE 0.400 (10.160) 0.420 (10.668) 0.171 (4.343) 0.181 (4.597) 0.055 (1.397) REF. 0.075 (1.905) 18°- 22° REF. SEATING PLANE 0.000 (0.000) <D> 0.012 (0.305) 0.045 (1.143) 0.055 (1.397) 0.045 (1.143) 0.055 (1.397) 0.400 (10.160) 0.300 (7.620) 0.065 (1.651) 0.125 (3.175) 0.256 (6.502) 0.304 (7.722) GA10JT12-263 XXXXXX 0.575 (14.605) 0.625 (15.875) 0.351 (8.915) 0.361 (9.169) Lot code 0.013 (0.330) 0.017 (0.432) 0.090 (2.286) 0.110 (2.794) GATE PLANE 0.010 (0.254) 0.050 (1.27) 0.024 (0.60) 0°- 8° NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date Revision Comments 2015/06/05 0 Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 11 of 11 GA10JT12-263 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA10JT12-263_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA10JT12-263. * MODEL OF GeneSiC Semiconductor Inc. * * $Revision: 1.0 $ * $Date: 05-JUN-2015 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * .model GA10JT12 NPN + IS 9.833E-48 + ISE 1.073E-26 + EG 3.23 + BF 80 + BR 0.55 + IKF 5000 + NF 1 + NE 2 + RB 4.67 + IRB 0.001 + RBM 0.16 + RE 0.005 + RC 0.083 + CJC 427.39E-12 + VJC 3.1004 + MJC 0.4752 + CJE 1373E-12 + VJE 10.6442 + MJE 0.21376 + XTI 3 + XTB -1.35 + TRC1 7E-3 + VCEO 1200 + ICRATING 10 + MFG GeneSiC_Semiconductor * * End of GA10JT12 SPICE Model Jun 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1