ASAHI KASEI [AK4555] AK4555 Low Power & Small Package 20bit ∆Σ CODEC AK4555 20bit A/D,D/A S/N (SCF) DC-offset HPF (fc=3.4Hz) ADC - S/(N+D): 80dB@VDD=2.5V - Dynamic Range, S/N: 89dB@VDD=2.5V DAC (32kHz, 44.1kHz, 48kHz ) - S/(N+D): 85dB@VDD=2.5V - Dynamic Range, S/N: 92dB@VDD=2.5V I/F : MSB First, 2’s Compliment - ADC, DAC: I2S : 0.6 x VDD (=1.5Vpp@VDD=2.5V) : 8kHz ∼ 50kHz : 256fs/384fs/512fs/768fs (fs=8kHz∼50kHz) 1024fs (fs=8kHz∼25kHz) : 1.6 ∼ 3.6V : 8mA@VDD=2.5V Ta = −40 85 : 16pin TSSOP VDD AINL AINR VCOM VSS ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter Clock Divider MCLK LRCK SCLK Serial I/O Interface Common Voltage SDTO SDTI DEM0 AOUTL AOUTR LPF ∆Σ Modulator LPF ∆Σ Modulator 8X DEM1 Interpolator 8X Interpolator MS0363-J-01 PWDAN PWADN 2005/08 -1- ASAHI KASEI [AK4555] AK4555VT AKD4555 −40 ∼ +85°C AK4555 16pin TSSOP (0.65mm pitch) VCOM 1 16 AOUTR AINR 2 15 AOUTL AINL 3 14 PWDAN VSS 4 13 PWADN VDD 5 12 SCLK DEM0 6 11 MCLK DEM1 7 10 LRCK SDTO 8 9 SDTI Top View AK4550, AK4554 AK4554 1.6 ∼ 3.6V ADC: 16bit DAC: 16bit 0.5 x VDD 80dB 70kΩ AK4555 Å VCOM pin ADC S/(N+D) (typ) ADC Input Resistance (typ) (typ) AD+DA AD DA DAC Stopband Attenuation (min) Passband Ripple (max) Group Delay AK4550 2.3 ∼ 3.6V ADC: 16bit DAC: 16bit 0.45 x VDD 82dB 100kΩ 10mA 5.6mA 5.6mA 8mA 4mA 4.4mA Å Å Å 43dB ±0.06dB 14.8/fs Å Å Å MCLK 256fs/384fs/512fs 54dB ±0.02dB 19.0/fs 256fs/384fs/512fs/768fs (fs=8∼50kHz) 1024fs (fs=8∼25kHz) I/F VCOM pin AINL, AINR pins 4.7µF + 0.1µF RC 0.1µF RC MS0363-J-01 I2S Å Å Å ( Å ) Å Å 2005/08 -2- ASAHI KASEI No. [AK4555] I/O 1 2 3 4 5 6 7 8 9 10 11 12 VCOM AINR AINL VSS VDD DEM0 DEM1 SDTO SDTI LRCK MCLK SCLK O I I I I O I I I I 13 PWADN I 14 PWDAN I 15 16 AOUTL AOUTR O O , 0.5 x VDD Rch Lch 0 1 L/R ADC “L”: DAC “L”: Lch Rch & ON & ON : Analog Digital AINR, AINL, AOUTL, AOUTR SDTO SDTI VSS MS0363-J-01 2005/08 -3- ASAHI KASEI (VSS=0V; [AK4555] 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Temperature (power applied) Storage Temperature Symbol VDD IIN VIN Ta Tstg min −0.3 −0.3 −40 −65 max 4.6 ±10 VDD+0.3 85 150 Units V mA V °C °C 1. : (VSS=0V; Power Supply 1) Parameter Symbol VDD min 1.6 typ 2.5 max 3.6 Units V 1. : MS0363-J-01 2005/08 -4- ASAHI KASEI [AK4555] ( Ta=25°C; VDD=2.5V; fs=44.1kHz; Signal Frequency =1kHz; SCLK=64fs; Measurement frequency=20Hz ∼ 20kHz) Parameter min typ ADC Analog Input Characteristics: ( 2) Resolution S/(N+D) 70 80 (−0.5dB Input) D-Range 82 89 (−60dB Input, A-weighted) S/N (A-weighted) 82 89 Interchannel Isolation 80 95 Interchannel Gain Mismatch 0.2 Input Voltage 1.35 1.50 ( 3) Input Resistance 40 70 Power Supply Rejection 45 ( 4) DAC Analog Output Characteristics: Resolution S/(N+D) 75 85 D-Range 86 92 (−60dB Output, A-weighted) S/N (A-weighted) 86 92 Interchannel Isolation 80 95 Interchannel Gain Mismatch 0.2 Output Voltage 1.35 1.50 ( 3) Load Resistance 10 Load Capacitance Power Supply Rejection 50 ( 4) Power Supplies Power Supply Current AD+DA PWADN= “H”, PWDAN= “H” 8 AD PWADN= “H”, PWDAN= “L” 4 DA PWADN= “L”, PWDAN= “H” 4.4 PWADN= “L”, PWDAN= “L” 10 Power down ( 5) Power Consumption AD+DA PWADN= “H”, PWDAN= “H” 20 AD PWADN= “H”, PWDAN= “L” 10 DA PWADN= “L”, PWDAN= “H” 11 PWADN= “L”, PWDAN= “L” 25 Power down ( 5) 2. ADC HPF 3. ADC, DAC Input/Output Voltage VDD 4. VDD 1kHz, 50mVpp AINL/R pin = 5. (MCLK, SCLK, LRCK) VSS PWADN, PWDAN MS0363-J-01 max Units 20 0.5 1.65 - Bits dB dB dB dB dB Vpp kΩ dB 20 0.5 1.65 30 - Bits dB dB dB dB dB Vpp kΩ pF dB 13 50 mA mA mA µA 32.5 125 mW mW mW µW 0.6 x VDD(typ) SDTI= “0” VDD VSS 2005/08 -5- ASAHI KASEI [AK4555] (Ta=25°C; VDD=1.6 ∼ 3.6V; fs=44.1kHz; DEM1 pin = “L”, DEM0 pin = “H”) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband PB 0 ±0.1dB ( 6) −1.0dB −3.0dB Stopband SB 25.7 Passband Ripple PR Stopband Attenuation SA 65 Group Delay GD ( 7) Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response ( 6) FR −3dB −0.5dB −0.1dB DAC Digital Filter: Passband PB 0 ±0.05dB ( 6) −6.0dB Stopband SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay GD ( 7) DAC Digital Filter + Analog Filter: Frequency Response FR 0 ∼ 20.0kHz 6. −1.0dB, DAC: −0.1dB) 7. fs( 0.454 x fs typ max Units 20.0 21.1 17.0 0 17.4 ±0.1 - kHz kHz kHz kHz dB dB 1/fs µs 3.4 10 22 - Hz Hz Hz 22.05 19.0 20.0 ±0.02 - kHz kHz kHz dB dB 1/fs ±0.5 - dB ) PB=20.0kHz(@ADC: ADC 20bit DAC 20bit DC (Ta=25°C; VDD=1.6 ∼ 3.6V) Parameter High-Level Input Voltage 2.2V≤VDD≤3.6V 1.6V≤VDD<2.2V Low-Level Input Voltage 2.2V≤VDD≤3.6V 1.6V≤VDD<2.2V High-Level Output Voltage (Iout= −20µA) Low-Level Output Voltage (Iout= 20µA) Input Leakage Current Symbol VIH VIH VIL VIL VOH VOL Iin MS0363-J-01 min 70%VDD 80%VDD VDD−0.1 - typ - max 30%VDD 20%VDD 0.1 ±10 Units V V V V V V µA 2005/08 -6- ASAHI KASEI [AK4555] (Ta=25°C; VDD=1.6 ∼ 3.6V; CL=20pF) Parameter Master Clock Timing Frequency 256fs/384fs/512fs/768fs 1024fs Duty Cycle LRCK Timing Frequency Duty Cycle Serial Interface Timing SCLK Period (8kHz ≤ fs ≤ 33kHz) (33kHz < fs ≤ 50kHz) SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “↑” ( 8) SCLK “↑” to LRCK Edge ( 8) SCLK “↓” to SDTO SDTI Hold Time SDTI Setup Time Reset Timing PWADN or PWDAN Pulse Width PWADN “↑” to SDTO Valid ( 9) 8. 9. PWADN LRCK SCLK LRCK Symbol min typ max Units fCLK fCLK dCLK 2.048 2.048 40 - 38.4 25.6 60 MHz MHz % fs Duty 8 45 44.1 50 50 55 kHz % tSCK tSCK tSCKL tSCKH tLRS tSLR tDSS tSDH tSDS 1/(96fs) 312.5 130 130 50 50 50 50 - 80 - ns ns ns ns ns ns ns ns ns tPW tPWV 150 - 2081 - ns 1/fs “↑” “↑” MS0363-J-01 2005/08 -7- ASAHI KASEI [AK4555] 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK = tCLKH x fCLK x 100 = tCLKL x fCLK x 100 1/fs VIH LRCK VIL tLRH tLRL Duty = tLRH x fs x 100 = tLRL x fs x 100 tSCK VIH SCLK VIL tSCKH tSCKL 1. VIH LRCK VIL tSLR tLRS VIH SCLK VIL tDSS SDTO 50%VD tSDS tSDH VIH SDTI VIL 2. tPW PWDAN VIL tPW VIH PWADN VIL tPWV 50%VD SDTO 3. & MS0363-J-01 2005/08 -8- ASAHI KASEI [AK4555] AK4555 MCLK=256fs/384fs/512fs/768fs/1024fs 256fs 128fs 256fs 1 (1024fs MCLK=1024fs (fs (PWADN=PWDAN= “L”) fs 8.0kHz 16.0kHz 32.0kHz 44.1kHz 48.0kHz 256fs 2.0480MHz 4.0960MHz 8.1920MHz 11.2896MHz 12.2880MHz 384fs 3.0720MHz 6.1440MHz 12.2880MHz 16.9344MHz 18.4320MHz (MCLK, SCLK, LRCK) MCLK 512fs 4.0960MHz 8.1920MHz 16.3840MHz 22.5792MHz 24.5760MHz 1. 768fs 6.1440MHz 12.2880MHz 24.5760MHz 33.8688MHz 36.8640MHz DAC 1024fs fs=25kHz ) DAC ) MCLK pin (LRCK) MCLK S/N 1024fs 8.1920MHz 16.3840MHz N/A N/A N/A SCLK 32fs 64fs 0.2560MHz 0.512MHz 0.5120MHz 1.024MHz 1.0240MHz 2.048MHz 1.4112MHz 2.822MHz 1.5360MHz 3.072MHz MCLK S/N fs 8kHz ∼ 50kHz 8kHz ∼ 25kHz 2. MCLK 256fs/384fs/512fs/768fs 1024fs , MCLK MS0363-J-01 S/N(fs=8kHz, A-weighted) 84dB 90dB DAC S/N 2005/08 -9- ASAHI KASEI [AK4555] 2’s 2 SCLK LRCK MSB 16bit “0” SDTI/SDTO pin SCLK=64fs SDTI LSB 18bit LSB 4 “0” LRCK 0 1 2 3 16 17 18 19 20 21 30 31 0 1 2 3 16 17 18 19 20 21 30 31 0 1 SCLK(64fs SDTO(o) 19 18 4 SDTI(i) 16bit 15 14 0 SDTI(i) 18bit 17 16 2 1 0 SDTI(i) 20bit 19 18 4 3 2 0 1 2 3 8 3 9 2 10 1 0 1 11 0 12 19 18 4 Don’t Care 15 14 0 Don’t Care 17 16 2 1 0 Don’t Care 19 18 4 3 2 13 14 15 0 1 2 3 8 3 2 1 0 Don’t Care 9 10 Don’t Care 11 Don’t Care 0 1 12 13 14 15 0 1 SCLK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 Lch Data Rch Data 4. DAC IIR 3 (32kHz, 44.1kHz, 48kHz) DEM1, DEM0 pin DEM1 pin = “L”, DEM0 pin = “H” DEM1 pin L L H H 3. HPF ADC DC 20Hz −0.12dB DEM0 pin L H L H (50/15µs ) Mode 44.1kHz OFF 48kHz 32kHz HPF HPF 3.4Hz(@fs=44.1kHz) (fs) MS0363-J-01 2005/08 - 10 - ASAHI KASEI [AK4555] AK4555 ADC DAC (PWADN, PWDAN) ADC SDTO 5 DAC “L” 2081xLRCK ADC DAC PWADN 2081/fs ADC Internal State Normal Operation Power-down Init Cycle Normal Operation PWDAN DAC Internal State Normal Operation Normal Operation Power-down GD GD ADC In (Analog) ADC Out (Digital) “0”data Idle Noise DAC In (Digital) Idle Noise “0”data GD GD DAC Out (Analog) Clock In MCLK,LRCK,SCLK The clocks may be stopped. External Mute Mute ON 5. MS0363-J-01 2005/08 - 11 - ASAHI KASEI [AK4555] 6 (AKD4555) 0.1u Rch In Lch In Analog Supply 1.6 ∼ 3.6V + + 10u + 1 VCOM AOUTR 16 2 AINR AOUTL 15 3 AINL 4 VSS 5 VDD 6 DEM0 MCLK 11 7 DEM1 LRCK 10 8 SDTO 0.1u AK4555 Top View PWDAN 14 Reset PWADN 13 Reset SCLK 12 SDTI Analog Ground Mode Control Controller 9 System Ground 6. : AOUT MS0363-J-01 2005/08 - 12 - ASAHI KASEI [AK4555] 1. VDD VSS pin VDD VSS pin VSS 0.1µF 2. VDD pin VDD VCOM 0.1µF VSS pin VCOM pin LSI VDD, VCOM pin 3. ADC Vpp(typ) AK4555 VCOM 2’s 0.6 x VDD (2 ) 64fs 64fs AK4555 (RC 64fs ) 4. DAC 2’s (2 80000H(@20bit) ( VCOM+ mV VCOM ) 7FFFFH(@20bit) 00000H(@20bit) ) DC 0.6 x VDD Vpp(typ) ∆Σ VCOM DC MS0363-J-01 2005/08 - 13 - ASAHI KASEI [AK4555] AK4555 AKD4555 1. VDD pin AK4555 AK4555 2. VDD pin 3. AK4555 VSS pin MCLK pin 4. VDD pin – VSS pin AK4555 10pF VCOM pin – VSS pin 0.1µF AK4555 0.1u Rch In Lch In + + 1 VCOM AOUTR 16 2 AINR AOUTL 15 3 AINL Analog Supply 1.6 ∼ 3.6V + 10u 0.1u AK4555 PWDAN 14 4 VSS PWADN 13 5 VDD Top View SCLK 12 6 DEM0 MCLK 11 7 DEM1 LRCK 10 8 SDTO SDTI 9 Reset &Power-down 51 51 10P 51 Analog Ground Digital Ground Controller 51 51 Mode Control 7. MS0363-J-01 2005/08 - 14 - ASAHI KASEI [AK4555] 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 6.4±0.2 *4.4±0.1 16 1.05±0.05 8 1 0.22±0.1 0.13 M 0.17±0.05 0.65 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° : : : MS0363-J-01 2005/08 - 15 - ASAHI KASEI [AK4555] AKM 4555VT XXYYY 1) 2) 3) 4) Date (YY/MM/DD) 04/11/24 05/08/08 Revision 00 01 Reason Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4555VT Asahi Kasei Logo Page Contents 7 tSCK(min): 312.5ns Æ 1/(96fs) or 312.5ns 4 VDD: 3.3V(typ) Æ 2.5V(typ) MS0363-J-01 2005/08 - 16 - ASAHI KASEI [AK4555] • • • ( ) • • • MS0363-J-01 2005/08 - 17 -