ASAHI KASEI [AK5384] AK5384 107dB 24-Bit 96kHz 4-Channel ADC AK5384 4 8kHz ∼ 96kHz A/D AK5384 AK5384 ∆Σ TDM o 4-Channel ∆Σ ADC o On-Chip Digital Anti-Alias Filtering o Differential Inputs o Digital HPF for DC-Offset Cancel o S/(N+D): 100dB@5V for 48kHz o DR: 107dB@5V for 48kHz o S/N: 107dB@5V for 48kHz o Sampling Rate Ranging from 8kHz to 96kHz o Master Clock: 256fs/384fs/512fs/768fs (∼ 48kHz) 256fs/384fs (∼ 96kHz) o TTL Digital Input Level o Output format: 24bit MSB justified, I2S or TDM o Cascade TDM Interface o Master & Slave Mode o Overflow Flag o Power Supply: 4.75 to 5.25V o Power Supply for output buffer: 3.0 to 5.25V o Ta = −40 ∼ 85°C o 28pin VSOP AVDD LIN1+ LIN1RIN1+ RIN1LIN2+ LIN2- AVSS DVDD DVSS TVDD ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter LRCK BICK SDTO1 SDTO2 Audio Interface TDMIN M/S DIF RIN2+ RIN2- ∆Σ Modulator VCOM Voltage Reference OVF Decimation Filter TDM0 TDM1 Clock Divider PDN MCLK CKS MS0225-J-00 2003/05 -1- ASAHI KASEI [AK5384] n −40 ∼ +85°C AK5384 AK5384VF AKD5384 28pin VSOP (0.65mm pitch) n LIN2+ 1 28 LIN1+ LIN2- 2 27 LIN1- RIN2+ 3 26 RIN1+ RIN2- 4 25 RIN1- TEST 5 24 M/S VCOM 6 23 CKS AVSS 7 22 PDN AVDD 8 21 DVSS DIF 9 20 DVDD TDM1 10 19 TVDD TDM0 11 18 SDTO1 TDMIN 12 17 SDTO2 MCLK 13 16 BICK OVF 14 15 LRCK Top View MS0225-J-00 2003/05 -2- ASAHI KASEI No. 1 2 3 4 5 Pin Name LIN2+ LIN2− RIN2+ RIN2− TEST [AK5384] I/O I I I I I 6 VCOM O 7 8 AVSS AVDD - 9 DIF I 10 TDM1 I 11 TDM0 I 12 13 TDMIN MCLK I I 14 OVF O 15 LRCK I/O 16 BICK I/O 17 SDTO2 O 18 SDTO1 O 19 20 21 TVDD DVDD DVSS - 22 PDN I 23 CKS I 24 M/S I 25 26 27 28 RIN1− RIN1+ LIN1− LIN1+ I I I I Function ADC2 Lch Positive Analog Input Pin ADC2 Lch Negative Analog Input Pin ADC2 Rch Positive Analog Input Pin ADC2 Rch Negative Analog Input Pin Test Pin (Connected to AVSS) Common Voltage Output Pin, AVDD/2 Normally connected to AVSS with a 0.1µF ceramic capacitor in parallel with an electrolytic capacitor less than 2.2µF. Analog Ground Pin Analog Power Supply Pin, 4.75 ∼ 5.25V Audio Interface Format Pin “L” : 24bit MSB justified, “H” : 24bit I2S Compatible TDM I/F BICK Frequency Select Pin “L” : 256fs, “H” : 128fs TDM I/F Format Enable Pin “L” : Normal Mode, “H” : TDM Mode TDM Data Input Pin Master Clock Input Pin Analog Input Overflow Detect Pin This pin goes to “H” if one of four analog inputs overflows. Output Channel Clock Pin “L” Output in Master Mode at Power-down mode. Audio Serial Data Clock Pin “L” Output in Master Mode at Power-down mode. ADC2 Audio Serial Data Output Pin “L” Output at Power-down mode. ADC1 Audio Serial Data Output Pin “L” Output at Power-down mode. Output Buffer Power Supply Pin, 3.0 ∼ 5.25V Digital Power Supply Pin, 4.75 ∼ 5.25V Digital Ground Pin Power-Down Mode Pin When “L”, the circuit is in power-down mode. The AK5384 should always be reset upon power-up. Master Clock Select Pin “L” : 256fs, “H” : 512fs This pin is enabled in Master Mode. Master / Slave Mode Pin “L” : Slave Mode, “H” : Master Mode ADC1 Rch Negative Analog Input Pin ADC1 Rch Positive Analog Input Pin ADC1 Lch Negative Analog Input Pin ADC1 Lch Positive Analog Input Pin Note: All digital input pins should not be left floating. MS0225-J-00 2003/05 -3- ASAHI KASEI [AK5384] (AVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital Output buffer |AVSS – DVSS| (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage (Except BICK, LRCK pins) (BICK, LRCK pins) Ambient Temperature (Powered applied) Storage Temperature Note 1. Note 2. AVSS Symbol AVDD DVDD TVDD ∆GND IIN VINA min −0.3 −0.3 −0.3 −0.3 max 6.0 6.0 6.0 0.3 ±10 AVDD+0.3 Units V V V V mA V VIND1 VIND2 Ta Tstg −0.3 −0.3 −40 −65 DVDD+0.3 TVDD+0.3 85 150 V V °C °C DVSS : (AVSS, DVSS=0V; Note 1) Parameter Power Supplies (Note 3) Analog Digital Output buffer Symbol AVDD DVDD TVDD min 4.75 4.75 3.0 typ 5.0 5.0 5.0 max 5.25 5.25 5.25 Units V V V Note 1. Note 3. AVDD, DVDD, TVDD : MS0225-J-00 2003/05 -4- ASAHI KASEI [AK5384] (Ta=25°C; AVDD=DVDD=TVDD=5.0V; AVSS=DVSS=0V; fs=48kHz, 96kHz; I/F format=Mode 0; Signal Frequency=1kHz; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max ADC Analog Input Characteristics: Resolution 24 S/(N+D) (−1dBFS) fs=48kHz 88 100 fs=96kHz 82 94 DR (−60dBFS) fs=48kHz, A-weighted 100 107 fs=96kHz 94 102 S/N fs=48kHz, A-weighted 100 107 fs=96kHz 94 102 Interchannel Isolation 90 110 DC Accuracy: Interchannel Gain Mismatch 0.1 0.5 Gain Drift 100 150 Input Voltage (Note 4) ±2.7 ±2.9 ±3.1 Input Resistance fs=48kHz 18 26 fs=96kHz 11 16 Power Supply Rejection (Note 5) 50 - Units Bits dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ kΩ dB Power Supplies Power Supply Current (AVDD+DVDD+TVDD) Normal Operation (PDN pin = “H”, fs=48kHz) Normal Operation (PDN pin = “H”, fs=96kHz) Power-down mode (PDN pin = “L”) (Note 6) (Note 6) (Note 7) 43 55 10 65 83 100 mA mA µA Note 4. (0dB) AVDD Vin = 0.58 × AVDD (Vpp) Note 5. AVDD, DVDD 1kHz, 50mVpp Note 6. AVDD=28mA; DVDD=15mA@48kHz&5V, DVDD=26mA@96kHz&5V(typ) Note 7. DVDD DVSS MS0225-J-00 2003/05 -5- ASAHI KASEI [AK5384] (fs=48kHz) (Ta=25°C; AVDD, DVDD=4.75 ∼ 5.25V; TVDD=3.0 ∼ 5.25V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 8) −0.005dB PB 0 −0.02dB −0.06dB −6.0dB Stopband (Note 8) SB 26.5 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 9) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 8) −3dB FR −0.5dB −0.1dB typ max Units 21.768 22.0 24.0 21.5 - 27.6 0 kHz kHz kHz kHz kHz dB dB 1/fs µs 1.0 2.9 6.5 Hz Hz Hz ±0.005 (fs=96kHz) (Ta=25°C; AVDD, DVDD=4.75 ∼ 5.25V; TVDD=3.0 ∼ 5.25V; fs=96kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 8) −0.005dB PB 0 −0.02dB −0.06dB −6.0dB Stopband (Note 8) SB 53.0 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 9) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 8) −3dB FR −0.5dB −0.1dB Note 8. Note 9. fs ( 24 typ max Units 43.536 44.0 48.0 43.0 - 27.6 0 kHz kHz kHz kHz kHz dB dB 1/fs µs 2.0 5.8 13.0 Hz Hz Hz ±0.005 ) ADC DC (Ta=25°C; AVDD, DVDD=4.75 ∼ 5.25V; TVDD=3.0 ∼ 5.25V) Parameter Symbol High-Level Input Voltage (TVDD=3.0 ∼ 3.6V) VIH Low-Level Input Voltage (TVDD=3.0 ∼ 3.6V) VIL High-Level Input Voltage (TVDD=3.6 ∼ 5.25V) VIH Low-Level Input Voltage (TVDD=3.6 ∼ 5.25V) VIL High-Level Output Voltage (Iout=−100µA) VOH Low-Level Output Voltage (Iout=100µA) VOL Input Leakage Current Iin MS0225-J-00 min 2.2 2.7 TVDD-0.5 - typ - max 0.8 0.5 0.5 ±10 Units V V V V V V µA 2003/05 -6- ASAHI KASEI [AK5384] (Ta=25°C; AVDD, DVDD=4.75 ∼ 5.25V; TVDD=3.0 ∼ 5.25V; CL=20pF) Parameter Symbol min Master Clock Timing Master Clock 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High 512fs: Pulse Width Low Pulse Width High 768fs: Pulse Width Low Pulse Width High LRCK Timing (Slave Mode) Normal mode (TDM1=“L”, TDM0=“L”) LRCK Frequency Duty Cycle TDM256 MODE (TDM1=“L”, TDM0=“H”) LRCK Frequency “H” time “L” time TDM128 MODE (TDM1=“H”, TDM0=“H”) LRCK Frequency “H” time “L” time LRCK Timing (Master Mode) Normal mode (TDM1=“L”, TDM0=“L”) LRCK Frequency Duty Cycle TDM256 MODE (TDM1=“L”, TDM0=“H”) LRCK Frequency “H” time (Note 10) TDM128 MODE (TDM1=“H”, TDM0=“H”) LRCK Frequency “H” time (Note 10) Note 10. I2S typ max Units 12.288 24.576 18.432 36.864 24.576 24.576 36.864 36.864 MHz ns ns MHz ns ns MHz ns ns MHz ns ns fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 2.048 16 16 3.072 11 11 4.096 16 16 6.144 11 11 fs Duty 8 45 96 55 kHz % fs tLRH tLRL 8 1/256fs 1/256fs 48 kHz ns ns fs tLRH tLRL 8 1/128fs 1/128fs 96 kHz ns ns fs Duty 8 96 kHz % fs tLRH 8 48 kHz ns fs tLRH 8 96 kHz ns 50 1/8fs 1/4fs “L” time MS0225-J-00 2003/05 -7- ASAHI KASEI [AK5384] Parameter Audio Interface Timing (Slave mode) Normal mode (TDM1=“L”, TDM0=“L”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO1/2 (MSB) (Except I2S mode) BICK “↓” to SDTO1/2 TDM256 mode (TDM1=“L”, TDM0=“H”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) BICK “↓” to SDTO1/2 TDM128 mode (TDM1=“H”, TDM0=“H”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) BICK “↓” to SDTO1 (Note 12) Audio Interface Timing (Master mode) Normal mode (TDM1=“L”, TDM0=“L”) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO1/2 TDM256 mode (TDM1=“L”, TDM0=“H”) BICK Frequency BICK Duty (Note 13) BICK “↓” to LRCK BICK “↓” to SDTO1/2 TDM128 mode (TDM1=“H”, TDM0=“H”) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO1 (Note 12) Power-Down & Reset Timing PDN Pulse Width (Note 14) PDN “↑” to SDTO1/2 valid (Note 15) Note 11. Note 12. SDTO2 Note 13. Note 14. AK5384 Note 15. PDN LRCK “L” MCLK=512fs PDN pin = “L” BICK Symbol min tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 160 65 65 30 30 tBCK tBCKL tBCKH tLRB tBLR tBSD 81 32 32 20 20 tBCK tBCKL tBCKH tLRB tBLR tBSD 81 32 32 20 20 fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD tPD tPDV typ max Units 35 35 ns ns ns ns ns ns ns 20 ns ns ns ns ns ns 20 ns ns ns ns ns ns 20 40 Hz % ns ns 12 20 Hz % ns ns 12 20 Hz % ns ns 64fs 50 −20 −40 256fs 50 −12 −20 128fs 50 −12 −20 150 516 ns 1/fs “↑” MCLK=256fs/384fs LRCK “↑” MS0225-J-00 2003/05 -8- ASAHI KASEI [AK5384] n 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing (TDM0 pin = “L”) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRH tLRL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing (TDM0 pin = “H”) MS0225-J-00 2003/05 -9- ASAHI KASEI [AK5384] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%TVDD Audio Interface Timing (Slave mode, TDM0 pin = “L”) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD SDTO 50%TVDD Audio Interface Timing (Slave mode, TDM0 pin = “H”) Note: SDTO shows SDTO1 and SDTO2. MS0225-J-00 2003/05 - 10 - ASAHI KASEI [AK5384] LRCK 50%TVDD tMBLR dBCK BICK 50%TVDD tBSD SDTO 50%TVDD Audio Interface Timing (Master mode) VIH PDN VIL tPDV SDTO 50%TVDD tPD PDN VIL Power Down & Reset Timing Note: SDTO shows SDTO1 and SDTO2. MS0225-J-00 2003/05 - 11 - ASAHI KASEI [AK5384] n (M/S pin = “L”) AK5384 BICK(48fs∼), LRCK(1fs) MCLK LRCK AK5384 AK5384 AK5384 (Table 2) MCLK(256fs/384fs/512fs/768fs), Table 1 (M/S pin = “H”) MCLK=384fs/768fs MCLK CKS fs=96kHz MCLK=512fs (PDN pin = “H”) (MCLK, BICK, LRCK) (PDN pin = “L”) (MCLK) fs 32.0kHz 44.1kHz 48.0kHz 96.0kHz MCLK 384fs 512fs 768fs 12.2880MHz 16.3840MHz 24.576MHz 16.9344MHz 22.5792MHz 33.8688MHz 18.4320MHz 24.5760MHz 36.8640MHz 36.8640MHz N/A N/A Table 1. System clock example (Slave mode) 256fs 8.1920MHz 11.2896MHz 12.2880MHz 24.5760MHz BICK 64fs 128fs 2.0480MHz 4.0960MHz 2.8224MHz 5.6448MHz 3.0720MHz 6.1440MHz 6.1440MHz N/A MCLK 8kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz L 256fs 256fs H 512fs N/A Table 2. Master clock frequency select (Master mode) CKS n 12 TDM1-0 DIF SDTO1/2 BICK Normal TDM128 fs=48kHz ADC(4 (I2S “L” ) ) LRCK “H” TDM256 1/8fs(typ) ADC(4 BICK 128fs LRCK “H” (I2S DIF (Table 3) MSB Mode 0-1 BICK 64fs TDM256 “H” M/S ) “L” ) “L” BICK 2’s 128fs SDTO1/2 1/256fs(min) fs=96kHz SDTO1 LRCK “H” 1/4fs(typ) TDM128 MS0225-J-00 Mode 2-3 BICK 256fs LRCK “L” SDTO2 1/128fs(min) fs=96kHz “L” 2003/05 - 12 - ASAHI KASEI [AK5384] Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 TDM1 TDM0 M/S DIF LRCK I/O H/L I L/H I H/L O L/H O I ↑ I ↓ O ↑ O ↓ I ↑ I ↓ O ↑ O ↓ N/A N/A SDTO L 24bit, MSB justified H 24bit, I2S Compatible L 24bit, MSB justified H H 24bit, I2S Compatible L 24bit, MSB justified L H 24bit, I2S Compatible L 24bit, MSB justified H H 24bit, I2S Compatible L 24bit, MSB justified L H 24bit, I2S Compatible L 24bit, MSB justified H H 24bit, I2S Compatible N/A N/A N/A Table 3. Audio Interface Formats L Normal L L TDM256 L H TDM128 H H N/A H L BICK I/O I I O O I I O O I I O O N/A 48-128fs 48-128fs 64fs 64fs 256fs 256fs 256fs 256fs 128fs 128fs 128fs 128fs N/A LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO1/2(o) 23 22 12 11 10 23:MSB, 0:LSB 0 23 22 12 11 10 Lch Data 0 23 Rch Data Figure 1. Mode 0, 2 Timing (Normal mode, MSB justified) LRCK 0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1 BICK(64fs) SDTO1/2(o) 23 22 2 1 23:MSB, 0:LSB 0 23 22 Lch Data 2 1 0 Rch Data Figure 2. Mode 1, 3 Timing (Normal mode, I2S Compatible) 256 BICK LRCK (Mode 6) LRCK (Mode 4) BICK (256fs) SDTO1 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 Figure 3. Mode 4, 6 Timing (TDM256 mode, MSB justified) MS0225-J-00 2003/05 - 13 - ASAHI KASEI [AK5384] 256 BICK LRCK (Mode 7) LRCK (Mode5) BICK (256fs) SDTO1 23 0 23 0 23 0 23 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 4. Mode 5, 7 Timing (TDM256 mode, I2S Compatible) 128 BICK LRCK (Mode 10) LRCK (Mode 8) BICK (128fs) SDTO1 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 Figure 5. Mode 8, 10 Timing (TDM128 mode, MSB justified) 128 BICK LRCK (Mode 11) LRCK (Mode 9) BICK (128fs) SDTO1 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 2 Figure 6. Mode 9, 11 Timing (TDM128 mode, I S Compatible) n M/S AK5384 MCLK MCLK, BICK, LRCK AK5384 AK5384 M/S pin L H “H” “L” BICK, LRCK Mode BICK, LRCK BICK = Input Slave Mode LRCK = Input BICK = Output Master Mode LRCK = Output Table 4. Master mode/Slave mode MS0225-J-00 2003/05 - 14 - ASAHI KASEI n [AK5384] HPF ADC DC HPF HPF fc fs=48kHz 1.0Hz fs n AK5384 “H”) 4 1 (−0.3dBFS ) OVF “H” ADC (GD = 27.6/fs = 575µs@fs=48kHz) 516/fs(=10.75ms@fs=48kHz) OVF “L” OVF (PDN pin = “L” → n AK5384 PDN “L” VCOM AVSS SDTO1/2 “0” 516 × LRCK ADC 2’s ADC ) ( 516/fs(10.75ms@fs=48kHz) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (1) GD A/D In (Analog) A/D Out (Digital) Clock In “0”data Idle Noise (3) MCLK,LRCK,BICK Notes: (1) (2) (3) (2) “0”data Idle Noise (GD) ADC “0” (MCLK, BICK, LRCK) Figure 7. Power-down/up sequence example n PDN MCLK “L” PDN LRCK ( “H” I2S ) MS0225-J-00 2003/05 - 15 - ASAHI KASEI [AK5384] n TDM AK5384 #1 4 TDM256 #1 SDTO2 TDM Figure 8 2 #2 TDMIN #2 4 AK5384 #1 #2 8 TDM SDTO1 TDM MCLK 256fs or 512fs LRCK 48kHz BICK 256fs TDMIN GND SDTO1 SDTO2 MCLK AK5384 #2 LRCK BICK TDMIN 8ch TDM SDTO1 SDTO2 Figure 8. Cascade TDM Connection Diagram 256 BICK LRCK BICK(256fs) #1 SDTO1(o) #1 SDTO2(o) #2 TDMIN(i) #2 SDTO1(o) 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L1-#1 R1-#1 L2-#1 R2-#1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 Figure 9. Cascade TDM Timing MS0225-J-00 2003/05 - 16 - ASAHI KASEI [AK5384] Figure 10 (AKD5384) 1 LIN2+ LIN1+ 28 2 LIN2- LIN1- 27 3 RIN2+ RIN1+ 26 4 RIN2- RIN1- 25 5 TEST M/S 24 6 VCOM CKS 23 0.1µ 2.2µ 0.1µ 7 AVSS Analog Supply 4.75 ~ 5.25V 10µ AK5384 PDN 22 Reset 0.1µ 8 AVDD DVSS 21 9 DIF DVDD 20 10 TDM1 TVDD 19 11 TDM0 SDTO1 18 12 TDMIN SDTO2 17 10µ 13 MCLK 0.1µ Digital Supply 4.75 ~ 5.25V Digital Supply 3.0 ~ 5.25V BICK 16 DSP and uP 14 OVF : - AK5384 - LRCK 15 AVSS, DVSS Figure 10. Typical Connection Diagram (Normal mode) MS0225-J-00 2003/05 - 17 - ASAHI KASEI [AK5384] 1. AVDD, DVDD AVDD, DVDD AVSS, DVSS PC 2. AVDD AVSS VCOM 2.2µF 0.1µF AVSS VCOM VCOM 3. AK5384 AVSS−0.3V +5V 10mA (LIN+/−, RIN+/−) AVDD+0.3V IC ±15V LIN(RIN)+ AVDD 26kΩ (typ) VCOM(AVDD/2) AVDD (±0.58 × AVDD) LIN(RIN)− 2’s DC (ADC AK5384 DC AVSS ) HPF AK5384 64fs 64fs MS0225-J-00 2003/05 - 18 - ASAHI KASEI [AK5384] 4. Figure 11 5.7Vpp (AK5384: typ. ±2.9Vpp) 1 5.1kΩ 4.7kΩ Analog In 5.7Vpp VP+ 4.7kΩ 22µ 10kΩ 2.9Vpp AIN+ VA 10k 330Ω Bias VPNJM5532 NJM5532 0.1µ 10µ 330Ω AIN- VA = +5V VP+ = +15V VP- = -15V Bias 10k AK5384 1.5n Bias 2.9Vpp Figure 11. Input buffer circuit example 1 (DC coupled single-end input) Figure 12 5.7Vpp (AK5384: typ. ±2.9Vpp) 2 5.1kΩ 4.7kΩ Analog In 5.7Vpp VP+ 4.7kΩ 22µ 10kΩ 330Ω 2.9Vpp AIN+ VP+ = +15V VP- = -15V 10µ VPNJM5532 NJM5532 1.5n AK5384 330Ω AIN2.9Vpp 10µ Figure 12. Input buffer circuit example 2 (AC coupled single-end input) Figure 13 3 2.9Vpp (AK5384: typ. 2.9Vpp) Analog In 2.9Vpp AIN+ 10µ 330Ω 1.5n Analog In 2.9Vpp AK5384 AIN- 10µ 330Ω Figure 13. Input buffer circuit example 3 (Differential input) MS0225-J-00 2003/05 - 19 - ASAHI KASEI [AK5384] 28pin VSOP (Unit: mm ) *9.8±0.2 1.25±0.2 0.675 28 A 7.6±0.2 *5.6±0.2 15 14 1 0.65 0.22±0.1 +0.1 0.15-0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane | 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° n Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0225-J-00 2003/05 - 20 - ASAHI KASEI [AK5384] AKM AK5384VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB : Lot number (X : Digit number, B : Alpha character) YYYYC : Assembly date (Y : Digit number, C : Alpha character) • • • • • • MS0225-J-00 2003/05 - 21 -