ASAHI KASEI [AK2301] AK2301 3.3V Single channel PCM CODEC LSI FEATURE GENERAL DESCRIPTION ♦Single PCM CODEC and filtering system ♦Selectable functions • Mute • A-law / μ-law ♦Long Frame / Short Frame are selected automatically ♦PCM data rate (64k*N)Hz (N=1~32) (64 ~ 2048kHz) ♦ Op-amp for differential 600Ω power drives with external gain adjust ♦Power down function (BCLK=”L”) ♦ Single power supply voltage +3.0~+3.6V ♦Low power consumption • Power on : 8mA(typ) • Power down : 5uA(typ) The AK2301 is a single channel PCM CODEC for various applications for example, AFE. It includes the selectable A/μ-law function, mute and power down. All of these functions are controlled by the pin. Ω Ω It includes Band limiting filter, A/D and D/A converter, and A-law/μ-law converter. All functions are provided in small 16pin TSSOP package and it is good for reducing the mounting space. PACKAGE ♦ 16pin TSSOP Pin to pin 5.0*6.4mm Pin pitch 0.65mm BLOCK DIAGRAM GST VFTN VFTP AAF A/D AMPT CODEC Core 600 ohm Drive GSR D/A SMF VR VFR PCM I/F DX DR FS BCLK ALAWN MUTEN AMPR 600 ohm Drive VREF Internal Main Clock PLL PLLC BGREF Power Down VDD VSS AK2301 <MS0416-E-02> 1 2010/05 ASAHI KASEI [AK2301] CONTENT ITEMS PAGE BLOCK DIAGRAM…………………………………… 1 PIN CONDITION……………………………………… 3 PIN FUNCTION………………………………………. 4 ABSOLUTE MAXIMUM RATINGS………………… 5 RECOMMENDED OPERATING CONDITON…….. 5 ELECTRICAL CHARACTERESTICS…………….… 5 PACKAGE INFORMATION……………………….… 11 PIN ASSIGNMENT…………………………………… 12 MARKINGS…………………………………….…….. 12 CIRCUIT DESCRIPTIONS………………………...… 13 FUNCTIONAL DESCLIPTIONS………………..…… 14 PCM CODEC………………………...……………….. 14 PCM INTERFACE………………………..…………... 15 LongFrame/ShortFrame…....………….…………… 15 MUTE ▪ POWER DOWN…………………………….. 17 POWER UP SEQUENCE………………..………...... 18 APPLICATION CIRCUIT EXAMPLE …….………… <MS0416-E-02> 2 19 2013/05 ASAHI KASEI [AK2301] PIN CONDITIONS Pin# Name I/O Pin type AC load (MAX.) DC load (MIN.) Output Power Down status Output Status 10 11 VFTN VFTP I I Analog Analog 9 GST O Analog 50pF 6 GSR O Analog 40pF 7 VFR I Analog 8 VR O Analog 5 13 VDD VSS - 4 FS I CMOS 2 BCLK I CMOS 1 DX O CMOS 3 DR I CMOS 16 MUTEN I CMOS 15 ALAWN I CMOS 12 VREF O Analog VSS 14 PLLC O Analog VSS 40pF AC load(*1) 10kΩ(*2) AC load 600Ω(*2, *3) AC load 600Ω(*2, *3) Remarks (mute) Hi-Z Hi-Z Analog ground Hi-Z Must not be left open Must not be left open 50pF Hi-Z Hi-Z Must not be left open Must not be left open Must not be left open - External capacitance 1.0uF or more - External capacitance 0.33uF±40% (Includes temperature characteristic) *1) AC load is a load against AGND. *2) This value includes a feedback resistance of input/output op-amps. *3) In differential mode, this is the AC load between GSR and AC. <MS0416-E-02> 3 2013/05 ASAHI KASEI [AK2301] PIN FUNCTION Pin types DIN: Digital input AIN: Analog input Pin# Name 10 VFTN TOUT: Tri-state output AOUT: Analog output Type AIN 11 VFTP AIN 9 GST AOUT 6 GSR AOUT 7 VFR AIN 8 VR AOUT 5 13 4 VDD VSS FS PWR PWR DIN 2 BCLK DIN 1 DX TOUT 3 DR DIN 16 MUTEN DIN 15 ALAWN DIN 12 VREF AOUT 14 PLLC AOUT <MS0416-E-02> PWR: Power / Ground Function Negative analog input of transmit OP amp. Differential or single-ended input amplifier is composed with the VFTP pin and an external resistor for gain adjustment. Positive analog input of the transmit OP amp. Differential or single-ended input amplifier is composed with the VFTN pin and an external resistor for gain adjustment. Output of the transmit OP amp. An inverting amplifier is composed with an external resistor for gain adjustment. Output of the receive OP amp. An inverting amplifier is composed with an external resistor for gain adjustment. Differential output can be composed with the VR output. Negative analog input of the receive OP amp. An inverting amplifier is composed with an external resistor for gain adjustment. However, when the input gain op-amp is used as a differential amp, this inverting amp is used as an analog ground buffer for the differential amp. In this case, output gain adjustment or differential drive circuit composition by this inverting amp is not available. Analog output of the D/A converter Differential output composition is possible with GSR outputs. Positive supply voltage Ground (0V) Frame sync input It controls In/Output timing of PCM data. FS must be 8kHz clock which synchronized with BCLK and do not stop feeding without power down mode. Bit clock of PCM data interface The frequency of BCLK should be 64kHz × N (N=1~32) and duty should be 40~60%. When this pin taken low, power down the device. Serial output of PCM data A/D converted PCM data is output in synchronization with BCLK. This output remains in high impedance except for the period in which PCM data is transmitted. Serial input of PCM data The PCM data is synchronized with BCLK. Mute setting pin “L” level forces both A/D and D/A outputs to mute state. A/u-law select pin ”L”=A-law, ”H”=μ-law Please tie to H or L. Analog ground output External capacitance (1.0μF or more) should be connected between this pin and VSS. Please do not connect external load to this pin. PLL loop filter output External capacitance (0.33μF±40%: Includes temperature characteristic) should be connected between this pin and VSS. 4 2013/05 ASAHI KASEI [AK2301] ABSOLUTE MAXIMUM RATINGS Parameter Symbol min Power supply voltage Analog/Digital power supply VDD -0.3 Digital input voltage VTD -0.3 Analog input voltage VTA -0.3 Input current (except power supply pins) IIN -10 Storage temperature Tstg -55 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. max Units 4.6 VDD+0.3 VDD+0.3 10 125 V V V mA °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol min typ Power supply voltage VDD 3.0 3.3 Analog/Digital power supply Ambient operating temperature Ta -40 Frame sync frequency *) FS -1.0% 8 Note) All voltages with respect to ground: VSS = 0V *) All characteristics of the CODEC are defined in the condition that FS= 8kHz. max Units 3.6 V 85 +1.0% °C kHz ELECTRICAL CHARACTERISTICS Measurement conditions are: VDD = +3.3V±0.3V, Ta = -40~+85°C, FS=8kHz, VSS=0V, unless otherwise noted. DC Characteristics Parameter Power Consumption All output unloaded Symbol IDD1*1) Conditions *1) BCLK=2.048MHz Power down (BCLK= “L”) Output high voltage IDD2 VOH Output low voltage VOL IOL =1.6mA Input high voltage Input low voltage IOH =-1.6mA VIH min typ 8 Max 13 Unit mA 5 100 uA 0.8VDD V 0.4 0.7VDD V VIL Input leakage current ILL -10 Analog ground output VRG 1.4 1.5 Output leakage current ILT Tri-state mode -10 *1) Measurement conditions: BCLK=2.048MHz, All output pins have no load. VFTP, VFTN (Differential)=1020Hz@0dBm0 input, DR=1020Hz@0dBm0 Code input <MS0416-E-02> 5 V 0.3VDD V +10 uA 1.6 V +10 uA 2013/05 ASAHI KASEI [AK2301] PCM INTERFACE (Long Frame, Short Frame) Measurement conditions are: Ta=-40 to +85°C, VDD = 3.0~3.6V, VSS = 0V, FS=8kHz, unless otherwise noted. All timing parameters of the output pins are measured at VOH = 0.8VDD and VOL = 0.4V. Input pins are measured at VIH = 0.7VDD and VIL = 0.3VDD. AC Characteristics Parameter Symbol Min Typ FS Frequency fPF -1.0% 8 BCLK Frequency fPB - (N=1~32) BCLK Duty Cycle tWB 40 Rising/Falling Time: (BCLK,FS, DX,DR) tRB tFB Hold Time: BCLK Low to FS High tHBF 60 ns Setup Time: FS High to BCLK Low tSFB 60 ns Setup Time: DR to BCLK Low tSDB 60 ns Hold Time: BCLK Low to DR tHBD 60 ns Note1) tDBD 0 60 ns Delay Time: (A) BCLK Low to DX High-Z or (B) FS Low to DX High-Z or (C) BCLK High to DX High-Z Note1) tDZC 0 60 ns Hold Time: 2nd period of BCLK Low to FS Low tHBFL 60 Delay Time: FS or BCLK High, whichever is later, to DX valid Note1) tDZFL FS Pulse Width Low tWFSL 1 BCLK Hold Time: BCLK Low to FS Low tHBFS 60 ns Setup Time: FS Low to BCLK Low tSFBS 60 ns Delay Time: BCLK High to DX valid fPF×8N Max Unit Ref Fig +1.0% kHz - kHz 60 % 40 ns Fig1,2 Long Frame ns 60 Fig1 ns Short Frame Fig2 Note1) Measured with 50pF load capacitance and 0.2mA drive. <MS0416-E-02> 6 2013/05 ASAHI KASEI [AK2301] Interface Timing tFB tRB tBD tBD 1/fPB BCLK tSFB FS tHBF tHBFL tDZFL DX 2 3 4 MSB 2 tDZC 5 6 7 8 5 6 7 8 tDZC tHBD tSDB DR (C) tDZC tDBD MSB (B) (A) 3 4 FS 1/fPF tWFSL Figure 1. Long Frame tFB tWB tRB 1/fPB BCLK tSFB FS tHBF DX tHBFS tSFBS tDBD MSB tDBD 2 3 4 tSDB DR MSB 2 3 tDZC 5 6 7 8 5 6 7 8 tHBD 4 Figure 2. Short Frame <MS0416-E-02> 7 2013/05 ASAHI KASEI [AK2301] CODEC * The receive and transmit op-amp’s characteristics are measured at the 0dB gain. The frequency specifications when FS deviation from 8kHz are as follows: UsedFS × noted frequency specification = Effective frequency specification 8k[Hz] Absolute Gain Parameter Conditions Analog input level VFTP,VFTN (Differential)→ Absolute transmit gain DX (*1) Maximum overload level Analog output level DR → Absolute receive gain VR Maximum overload level (*1) In differential mode, 0dBm0= 0.531Vrms Frequency response Parameter Transmit frequency response (A →D) VFTP,VFTN (Differential) →DX Receive frequency response (D → A) DR → VR 0dBm0@1020Hz input min -0.6 3.14dBm0 0dBm0@1020Hz input -0.6 3.14dBm0 Relative to: -10dBm0 1020Hz Tone Relative to: -10dBm0 1020Hz Tone Conditions -55dBm0~ -50dBm0 -50dBm0~ -40dBm0 -40dBm0~ 3dBm0 -55dBm0~ -50dBm0 -50dBm0~ -40dBm0 -40dBm0~ 3dBm0 Frequency response Parameter Transmit Frequency response (A → D) Conditions Relative to: 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz VFTP,VFTN (Differential) →DX 0.3~3.0kHz 3.4kHz 4.0kHz Receive Frequency response Relative to: 0~3.0kHz (D → A) 0dBm0@1020Hz 3.4kHz DR → VR 4.0kHz typ 0.531 – 0.762 0.531 – 0.762 max 0.6 0.6 min -1.2 -0.4 -0.2 -1.2 -0.4 -0.2 typ – – – – – – max 1.2 0.4 0.2 1.2 0.4 0.2 min – – -1.8 -0.15 -0.8 – -0.15 -0.8 – typ – – – – – – – – – max -30 -26 0 0.15 0 -14 0.15 0 -14 min 25 30 36 25 30 36 typ – – – – – – max – – – – – – Unit Vrms dB Vrms Vrms dB Vrms Unit dB dB Unit dB dB Distortion Parameter Conditions Transmit signal to Distortion 1020Hz Tone -40dBm0 ~ -45dBm0 (A → D) -30dBm0 ~ -40dBm0 VFTP,VFTN (Differential) →DX 0dBm0 ~ -30dBm0 Receive signal to Distortion 1020Hz Tone -40dBm0 ~ -45dBm0 (D → A) -30dBm0 ~ -40dBm0 DR → VR 0dBm0 ~ -30dBm0 Note) C-message Weighted for μ-Law, Psophometric Weighted for A-Law <MS0416-E-02> 8 Unit dB dB 2013/05 ASAHI KASEI [AK2301] Noise Parameter Conditions Idle channel noise A→D (*1) u-law, C-message VFTP,VFTN (Differential) →DX A-law, Psophometric Idle channel noise D→A(*2) u-law, C-message DR → VR A-law, Psophometric PSRR VDD=3.3V/±66mVop Transmit path f=0~10kHz PSRR VDD=3.3V/±66mVop Receiver path F=0~10kHz (*1) Analog input is set to the analog ground level (*2) Digital input is set to the +0 CODE min – – – – typ 8 -85 5 -85 max 13 -80 10 -80 Units dBrnC0 dBm0p dBrnC0 dBm0p dB – 55 – – 55 – min typ – – -75 dB – – -75 dB min 10 – typ – – max – 50 Units kΩ pF -12 – 6 dB min typ max Units – 1.5 – V 600 – – – – 40 Ω pF min 600 – typ – – max – 40 Units Ω pF 50 70 – dB Crosstalk Parameter Transmit to receive VFTP → VR,GSR(Differential) Receive to transmit DR → DX Conditions VFTP 0dBm0@1020Hz DR = PCM 0-Code DR=0dBm0@1020Hz code level VFTP,VFTN = 0 Vrms Transmit op-amp characteristics :AMPT Parameter Conditions Load resistance AC load, Including feedback resistance Load capacitance Inverting amplifiers Gain (Feedback capacitance = 100pF, fc= 80kHz) Receive signal output characteristics: VR Parameter Conditions Output voltage (AGND level) PCM +0 code input Load resistance Load capacitance AC load Receive op-amp characteristics: AMPR Parameter Conditions Load resistance AC load, Including feedback resistance Load capacitance 0dB setting, 1020Hz@0dBm0 input VR,GSR differential output (600Ω load) With C-message SINAD 0dB setting, 1020Hz@0dBm0 input VR,GSR differential output (5kΩ load) With C-message Inverting amplifier Gain (Feedback capacitance = 100pF, fc= 40kHz) Output voltage swing DR = 3.14dBm0 digital code input <MS0416-E-02> 9 max Units dB 80 -12 – 6 dB – 2.15 – Vp-p 2013/05 ASAHI KASEI [AK2301] PACKAGE INFORMATION 9 1 8 0°~10° 4.4 ± 0.1 6.4 ± 0.2 16 0.17±0.05 5.00±0.08 0.13 0°~10° M 0.22±0.08 0.07+0.03 -0.04 1.07+0.03 -0.07 1.00±0.05 0.65 0.10 <MS0416-E-02> 0.5±0.2 16pin TSSOP 10 2013/05 ASAHI KASEI [AK2301] PIN ASSIGNMENT 16pin TSSOP DX BCLK DR FS VDD GSR VFR VR 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MUTEN ALAWN PLLC VSS VREF VFTP VFTN GST MARKING (1) 1pin sign (2) Date Code: 5digit YWWXX Y: Date Code (year) WW: Date Code (week) XX: Control Code (3) Marketing Code: AK2301 (4) AKM logo (4) (3) AKM AK2301 YWWXX (2) (1) <MS0416-E-02> 11 2013/05 ASAHI KASEI [AK2301] CIRCUIT DESCRIPTION BLOCK AMPT AMPR AAF CODEC A/D CODEC D/A SMF BGREF PCM I/F <MS0416-E-02> FUNCTION Op-amp for input gain adjustment. A differential or single-ended input amplifier is composed with an external resistor. The feedback resistor should be larger than 10kΩ. Each pin definition is shown below. VFTN: Negative op-amp input. VFTP: Positive op-amp input. GST: Op-amp output. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. A differential or single-ended amplifier is composed with an external resistor. Each pin definition is shown below. VFR: Negative op-amp input. GSR: Op-amp output. VR and GSR can be used as the differential output. In this case, more than 600Ω AC load should be composed with external and feedback resistors. Integrated anti-aliasing filter (AAF) It prevents signal noise around the sampling rate from folding back into the voice band. AAF is a 2nd order RC active low-pass filter. Converts analog signal to 8bit PCM data according to the compounding schemes of ITU recommendation G.711; A-law or u-law. Even bits are inverted in A-Law conversion. The compounding schemes is set by the ALAWN pin as follows: "H": u-Law "L": A-Law The band limiting filter is also integrated. Expands and playbacks the 8bit PCM data from the DR pin according to the compounding schemes of ITU recommendation G.711; A-law or u-law. Even bits are inverted in A-Law converting. The compounding schemes is set by the ALAWN pin as follows: "H": u-Law "L": A-Law Extracts the inband signal from D/A output. It also corrects the sinx/x effect of the D/A output. Provide the stable analog ground voltage using an on-chip band-gap reference circuit which is temperature compensated. The output voltage is typ. 1.5V. An external capacitor of 1.0uF or larger should be connected between VREF and VSS to stabilize analog ground (VREF). Please do not connect external load to this pin. Characteristics are not guaranteed when connecting an external load. The output should be buffered if using this voltage externally. PCM data transferring rate is dependent on BCLK. Two kinds of data format (Long Frame/Short Frame) are available. Each data format is automatically detected by the AK2301. PCM data is input to the DR pin and output from the DX pin. 12 2013/05 ASAHI KASEI [AK2301] FUNCTIONAL DESCRIPTIONS PCM CODEC - A/D Analog input signal is converted to 8bit PCM data. The analog signal is fed to the anti-aliasing filter (AAF) before converting to PCM data to prevent signals around the sampling rate from folding back into the voice band. The converted PCM data passes through the band limiting filter which Frequency response is designated in page8, and output from the DX pin in MSB first format. It is synchronized with rising edge of the BCLK. This PCM data is A/u-law and full scale is defined as 3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0. - D/A Input PCM data from the DR pin is through the digital filter, which Frequency response is designated in page8, and converted to analog signal. This analog signal is removed the high frequency element with SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is A/u-law data and full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output signal becomes 0.762Vrms. PCM Data Interface The AK2301 supports the following 2 PCM data formats - Long Frame Sync (LF) - Short Frame Sync (SF) PCM data is interfaced through a pin. (DX, DR). In each case, PCM data is interfaced in MSB first format. Selection of the interface format The AK2301 automatically selects the Long Frame/Short frame by means of detecting the length frame signal. LONG FRAME (LF) / SHORT FRAME (SF) -Automatic LF/SF detection The AK2301 monitors the duration of the “H” level of FS and automatically selects LF or SF interface format. Period of FS=”H” Frame type More than 2 BCLK cycles LF 1 BCLK cycle SF Timing of the interface 8bit PCM data is accommodated in 1 flame (125μs) defined by 8kHz frame sync signal. Although there are 32 time-slots at maximum in 8kHz frame (when BCLK = 2.048MHz), PCM data for the AK2301 occupies the first time-slot. <MS0416-E-02> 13 2013/05 ASAHI KASEI [AK2301] - Frame sync signal (FS) 8kHz reference signal. 8bit PCM data is transferred in every 1 frame (125us). This signal must be synchronized with BCLK. WARNING! The AK2301 must be in power down mode by BCLK = “L” when stopping FS. - BCLK (Bit clock) BCLK defines the PCM data rate. BCLK rate is 64kHz × N (N=1~32). LongFrame FS BCLK DX DR Don’t care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Don’t care ShortFrame FS BCLK DX DR Don’t care <MS0416-E-02> 14 Don’t care 2013/05 ASAHI KASEI [AK2301] MUTE The output of the PCM CODEC can be muted by a pin control. MUTEN pin MUTEN pin Operation DX pin VR pin L Mute High-Impedance CODEC analog ground H Normal PCM data output CODEC analog output [DX pin] When the MUTEN pin turns to “L” during the data output, the mute function becomes available at the beginning of the next FS after all bits are output. [VR pin] When the MUTEN pin turns to “L”, 0 code is fed to the D/A converter and VR becomes at analog ground level. POWER DOWN MODE To hold the BCLK pin “L”, the AK2301 is powered down. Power up/down sequence 1)Power down 40usec(typ) passed after the BCLK pin hold “L”, the internal PDN signal turn to “L” and the AK2301 enters power-down mode. In power-down mode, the GST, DX, GSR and VR pins are Hi-z. The VREF and PLLC pins output VSS. 2)Power up Power-down mode is released when FS and BCLK are input. Outputs are muted (DX=High-Z, VR=AGND) for 50msec (typ) after the power-down is released to avoid noises. Power down Power up MUTE release BCLK stop 40usec BCLK input BCLK Internal PD signal Internal MUTE signal <MS0416-E-02> 50msec 15 2013/05 ASAHI KASEI [AK2301] Power Up Sequence The following start up process is recommended when power up the AK2301. Power up (in 50ms) - FS=”L” - BCLK=”L” - MUTEN=”L” Supply FS and BCLK Wait 200ms - CODEC Initialization starts. Wait 60ms - CODEC Initialization completes. - MUTEN=”H” CODEC starts normal operation <MS0416-E-02> 16 2013/05 ASAHI KASEI [AK2301] APPLICATION CIRCUIT EXAMPLES Analog input circuit (differential) Analog output circuit (differential) GST 20kohm 1uF 4.7uF VR 100pF 1uF 10kohm VFTN 40kohm 1uF 600ohm load VFTP 10kohm 100pF 40kohm 20kohm VFR 4.7uF VFR 100pF GSR GSR Analog Output Circuit (Single) Analog input circuit (single) GST 20kohm 1uF 10uF VR 100pF 10kohm 600ohm VFTN VFTP VREF Power supply, PLL loop filter capacitor and analog ground stabillization capacitor 1uF VREF VREF PLLC PLL VSS 1uF VSS 0.33uF +/-40% VSS VDD 10uF 0.1uF VSS <MS0416-E-02> 17 2013/05 ASAHI KASEI [AK2301] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. <MS0416-E-02> 18 2013/05