AK2300

[AK2300]
AK2300
3.3V Single channel PCM CODEC LSI
GENERAL DESCRIPTION
FEATURE
The AK2300 is a single channel PCM CODEC for
various applications for example, AFE. It includes the
selectable linear PCM interface, A/m-law function,
mute and power down. All of these functions are
controlled by the pin.
¨Single PCM CODEC and filtering system
¨Selectable functions
· Mute
· Power down (PDN=’L’ or BCLK=’L’)
· A-law / m-law / linear PCM
¨Long Frame / Short Frame are selected by pin
¨PCM data rate
(64k*N)Hz (N=1~32)
¨ Op-amp for the external gain adjustment
¨ Single power supply voltage: +2.6~+3.6V(VDD)
¨ Digital I/F power supply voltage: +1.7~3.6V(LVDD)
¨Low power consumption
· Power on
: 5.3mA(typ)
· Power down : 0.1uA(typ)
It includes Band limiting filter, A/D and D/A converter,
and A-law/m-law converter. All functions are provided
in very small QFN(16pins) package and it is good for
reducing the mounting space.
PACKAGE
¨ 16pin QFN
Body 3.0*3.0mm
Pin pitch 0.5mm
BLOCK DIAGRAM
GST
VFTN
AAF
A/D
AMPT
VR
CODEC
Core
D/A
SMF
5KΩDrive
Internal
Main Clock
VREF
PLL
PLLC
BGREF
Power Down
VDD
VSS
LVDD
<MS0998-E-00>
PCM I/F
LNSEL
ALAWN
MUTEN
DX
DR
FS
BCLK
PDN
AK2300
1
2008/9
[AK2300]
CONTENT
ITEMS
<MS0998-E-00>
PAGE
-
BLOCK DIAGRAM……………………………………
1
-
PIN CONDITION………………………………………
3
-
PIN FUNCTION……………………………………..
4
-
ABSOLUTE MAXIMUM RATINGS…………………
5
-
RECOMMENDED OPERATING CONDITION……..
5
-
ELECTRICAL CHARACTERESTICS…………….…
5
-
PACKAGE INFORMATION……………………….…
11
-
PIN ASSIGNMENT…………………………………
12
-
MARKINGS…………………………………….……
12
-
CIRCUIT DESCRIPTIONS………………………..…
13
-
FUNCTIONAL DESCLIPTIONS………………..……
14
-
PCM CODEC………………………...…………
14
-
PCM INTERFACE………………………..……
14
-
MUTE, Power Down……………………………
16
-
START UP PROCEDURE……………………
17
-
APPLICATION CIRCUIT EXAMPLE …….………
18
2
2008/9
[AK2300]
PIN CONDITIONS
AC load
(MAX.)
DC load
(MIN.)
Output
status
(mute)
Output
status
(PD)
Pin#
Name
I/O
Pin type
7
VFTN
I
Analog
6
GST
O
Analog
50pF
4
VR
O
Analog
40pF
14
FS
I
CMOS
15
BCLK
I
CMOS
11
DX
O
CMOS
16
DR
I
CMOS
1
2
13
5
3
12
10
MUTEN
PDN
DIF0
DIF1
VDD
LVDD
VSS
I
I
I
I
-
CMOS
CMOS
CMOS
CMOS
PWR
PWR
GND
8
VREF
O
Analog
VSS
9
PLLC
O
Analog
VSS
AC load(*1)
10kΩ(*2)
AC load(*1)
5kΩ
Remarks
Hi-Z
Analog
ground
Hi-Z
Pull down
100K±50Kohm
Pull down
100K±50Kohm
50pF
0 code
VSS
Pull down
100K±50Kohm
Do not open
Do not open
Do not open
Do not open(*3)
- External
capacitance
0.1uF
- External
capacitance
0.056uF±30％
( Includes
temperature
characteristic)
*1) AC load is feedback resistance to VFTN.
*2) This value includes a feedback resistance of input/output op-amps.
*3) Please connect it with VDD when DIF1 is “H”.
<MS0998-E-00>
3
2008/9
[AK2300]
PIN FUNCTION
Pin types
DIN:
Digital input
AIN:
Analog input
Pin#
Name
DOUT: Digital output
AOUT: Analog output
Type
7
VFTN
AIN
6
GST
AOUT
4
VR
AOUT
14
FS
DIN
5
BCLK
DIN
11
DX
DOUT
16
DR
DIN
1
MUTEN
DIN
2
PDN
DIN
13
DIF0
DIN
5
DIF1
DIN
3
12
10
VDD
LVDD
VSS
PWR
PWR
PWR
8
VREF
AOUT
9
PLLC
AOUT
Exposed
Pad
-
<MS0998-E-00>
PWR: Power / Ground
Function
Negative analog onput of analog input OP amp.
Signgle-end amplifire is composed the exernal registers. Transmit gain is
defined by the ratio of the external registers.
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTN.
Analog output of the D/A converter equivalent to the received PCM
code.
Frame sync input
This clock is input for the internal PLL which generates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK.
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 64kHz ´ N (N=1~32) and duty should be
40~60%. When this pin is taken low, power down the device.
*Please don’t stop BCLK at “H” level.
Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the low
level except for the period in which PCM data is transmitted.
Serial input of PCM data
The PCM data is synchronized with BCLK.
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
Power down setting pin
“L” level forces power down mode.
Audio data interface select pin
”L”=A-law,”H”=m-law,“FS”=Linear PCM
(Please connect DIF0 with FS(#14) at a Linear PCM mode.)
Audio data interface timing select pin
“H” : MSB of DX/DR are input/output by rising edge of FS.(Connect to VDD)
“L” : MSB of DX/DR are input/output by next rising edge of BCLK after the
rising edge of FS.
(Please connect it with VDD when DIF1 is “H”.)
Positive supply voltage
Positive supply voltage for digital interface
Ground (0V)
Analog reference voltage output
External capacitance (0.1mF) should be connected between this pin and
VSS. Please do not connect external load to this pin.
PLL loop filter output
External capacitance (0.056mF±30%: Includes temperature characteristic)
should be connected between this pin and VSS.
Flip side PAD
VSS or Open
4
2008/9
[AK2300]
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
min
Power supply voltage
Analog/Digital power supply
VDD
-0.3
Digital interface power supply
LVDD
-0.3
Digital input voltage
VTD
-0.3
Analog input voltage
VTA
-0.3
Input current (except power supply pins)
IIN
-10
Storage temperature
Tstg
-55
Warning: Exceeding absolute maximum ratings may cause permanent damage.
Normal operation is not guaranteed at these extremes.
max
4.6
4.6
LVDD+0.3
VDD+0.3
10
125
Units
V
V
V
V
uA
℃
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
min
Power supply voltage
Analog/Digital power supply
VDD
2.6
Digital interface power supply *1)
LVDD
1.7
Ambient operating temperature
Ta
-30
Frame sync frequency *2)
FS
-1.0%
Note) All voltages reference to ground: VSS = 0V
*1)VDD≧LVDD
*2) All the characteristics of the CODEC are defined by 8kHz FS.
typ
max
Units
3.3
3.3
3.6
3.6
85
+1.0%
V
V
℃
kHz
8
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed for VDD = +2.6V~3.6V, LVDD=+1.7V~+3.6V (VDD≧LVDD),
Ta = -30~+85℃, FS=8kHz, VSS=0V
DC Characteristics
Parameter
Symbol
Conditions
typ
Max
Unit
*1)BCLK=2.048
5.3
9.0
mA
Power down
0.1
5.0
uA
Power Consumption
(All output unloaded)
PDD1*1)
Output high voltage
VOH
IOH＝-200uA
Output low voltage
VOL
IOL＝200uA
Input high voltage1
VIH1
FS,BCLK,DR,MUTEN,
PDN,DIF0
Input low voltage1
VIL1
FS,BCLK,DR,MUTEN,
PDN,DIF0
Input high voltage2
VIH2
DIF1
Input low voltage2
VIL2
DIF1
PDD2
Input leakage current
ILL
Analog ground output
VRG
min
0.8VDD
V
0.4
0.7LVDD
V
0.3LVDD
0.7VDD
Except pull down pins
-10
VREF pin
1.2
V
V
V
1.3
0.3VDD
V
+10
uA
1.4
V
*1) VFTN=1020Hz@0dBm0 input, DR=1020Hz@0dBm0 Code input.
<MS0998-E-00>
5
2008/9
[AK2300]
PCM INTERFACE (Long Frame, Short Frame)
All timing parameters of the output pins are measured at VOH = 0.8LVDD and VOL = 0.4V. Input pins
are measured at VIH = 0.7LVDD and VIL = 0.3LVDD.
AC Characteristics
Parameter
Symbol
Min
Typ
FS Frequency
fPF
-1.0%
8
BCLK Frequency
fPB
-
BCLK Duty Cycle
tWB
40
Rising/Falling Time: (BCLK,FS, DX,DR)
tRB
tFB
Hold Time: BCLK Low to FS High
tHBF
60
ns
Setup Time: FS High to BCLK Low
tSFB
20
ns
Setup Time: DR to BCLK Low
tSDB
20
ns
Hold Time: BCLK Low to DR
tHBD
60
ns
FS Pulse Width Low
tWFSL
1
BCLK
Delay time: FS or BCLK High, whichever is later,to DX valid
Note1)
TDZFL
Hold time: BCLK Low to FS Low
THBFS
60
ns
Setup time: FS Low to BCLK Low
TSFBS
20
ns
tDBD
0
Delay Time: BCLK High to DX valid
Note1)
fPF×8N
(N=1~32)
Max
Unit Ref Fig
+1.0% kHz
-
kHz
60
%
40
ns
60
60
Fig1,2,
3,4
ns
ns
Note1) Measured with 50pF load capacitance and 0.2mA drive.
<MS0998-E-00>
6
2008/9
[AK2300]
Interface Timing
tFB
tRB tWB
tWB
1/fPB
BCLK
tSFB
FS
tHBF
tDZFL
DX
tDBD
MSB
2
3
4
MSB
2
6
7
8
5
6
7
8
tHBD
tSDB
DR
5
3
4
FS
1/fPF
tWFSL
Fig1. DIF0=”L” or “H” , DIF1=”H”
tFB
tRB
tWB
tWB
1/fPB
BCLK
tSFB
FS
tHBF
DX
tHBFS
tSFBS
tDBD
MSB
tDBD
2
3
4
tSDB
DR
MSB
2
3
5
6
7
8
5
6
7
8
tHBD
4
Fig2. DIF0=”L” or “H” , DIF1=”L”
<MS0998-E-00>
7
2008/9
[AK2300]
tFB
tRB tWB
tWB
1/fPB
BCLK
FS/
DIF0
tSFB
tHBF
tDZFL
DX
MS
B
DR
MS
B
tDBD
2
3
4
6
7
14
5
6
7
14
tHBD
tSDB
2
5
3
4
FS
1/fPF
tWFSL
Fig3. DIF0=”FS”, DIF1=”H”
tFB
tRB
tWB
tWB
1/fPB
BCLK
tSFB
FS/
DIF0
tHBF
DX
tHBFS
tSFBS
tDBD
MSB
tDBD
2
3
4
tSDB
DR
MSB
2
3
5
6
7
14
5
6
7
14
tHBD
4
Fig4. DIF0=”FS”, DIF1=”L”
<MS0998-E-00>
8
2008/9
[AK2300]
CODEC
* The AMPT characteristics is measured at the 0dB gain.
The frequency specifications when FS deviation from 8kHz are as follows:
UsedFS
´ noted frequency specification = Effective frequency specification
8k[Hz]
Absolute Gain
Parameter
Analog input level
Absolute transmit gain
Maximum overload level
Analog output level
Absolute receive gain
Maximum overload level
Frequency response
Parameter
Transmit frequency response
（Ａ→Ｄ）
VFTN → DX
Receive frequency response
（Ｄ→Ａ）
DR → VR
Frequency response
Parameter
Transmit Frequency response
（Ａ→Ｄ）
VFTN
→
DX
DR
→
VR
Conditions
0dBm0@1020Hz input
min
-0.6
3.14dBm0
0dBm0@1020Hz input
-0.6
3.14dBm0
Relative to:
-10dBm0
1020Hz Tone
Relative to:
-10dBm0
1020Hz Tone
Conditions
-55dBm0～-50dBm0
-50dBm0～-40dBm0
-40dBm0～ 3dBm0
-55dBm0～-50dBm0
-50dBm0～-40dBm0
-40dBm0～ 3dBm0
Receive Frequency response
（Ｄ→Ａ）
DR → VR
Conditions
Relative to:
0.05kHz
0dBm0@1020Hz
0.06kHz
0.2kHz
0.3～3.0kHz
3.4kHz
4.0kHz
Relative to:
0～3.0kHz
0dBm0@1020Hz
3.4kHz
4.0kHz
Distortion (A-law, m-law)
Parameter
Transmit signal to Distortion
（Ａ→Ｄ）
VFTN → DX
Receive signal to Distortion
（Ｄ→Ａ）
DR → VR
Conditions
-40dBm0～-45dBm0
-30dBm0～-40dBm0
0dBm0～-30dBm0
1020Hz Tone
-40dBm0～-45dBm0
-30dBm0～-40dBm0
0dBm0～-30dBm0
VFTN
→
DX
Distortion (Liear PCM)
Parameter
Transmit signal to Distortion
（Ａ→Ｄ） VFTN → DX
Receive signal to Distortion
（Ｄ→Ａ） DR → VR
<MS0998-E-00>
1020Hz Tone
Conditions
typ
0.460
－
0.660
0.460
－
0.660
max
0.6
0.6
Unit
Vrms
dB
Vrms
Vrms
dB
Vrms
min
-1.2
-0.4
-0.2
-1.2
-0.4
-0.2
Typ
－
－
－
－
－
－
max
1.2
0.4
0.2
1.2
0.4
0.2
Unit
min
－
－
-1.8
-0.15
-0.8
－
-0.15
-0.8
－
typ
－
－
－
－
－
－
－
－
－
max
-30
-26
0
0.15
0
-14
0.15
0
-14
Unit
min
25
30
36
25
30
36
typ
－
－
－
－
－
－
max
－
－
－
－
－
－
Unit
min
typ
max
Unit
dB
dB
dB
dB
dB
dB
1020Hz Tone
0dBm0 (C-massage)
78
dB
1020Hz Tone
0dBm0 (C-massage)
81
dB
9
2008/9
[AK2300]
Noise
Parameter
Idle channel noise A→D (*1)
VFTN → DX
Conditions
u-law, C-message
A-law, Psophometric
Linear, C-message
Idle channel noise D→A(*2)
u-law, C-message
DR → VR
A-law, Psophometric
Linear, C-message
PSRR
VDD=3.3V/±66mVop
Transmit path
f=0～10kHz
PSRR
VDD=3.3V/±66mVop
Receiver path
f=0～10kHz
(*1) Analog input is set to the analog ground level
(*2) Digital input is set to the +0 CODE
min
－
－
－
－
－
typ
12
-78
12
9
-81
9
max
17
-73
17
14
-76
14
Units
dBrnC0
dBm0p
dBrnC0
dBrnC0
dBm0p
dBrnC0
－
55
－
dB
－
55
－
dB
min
Typ
max
Units
－
－
-75
dB
－
－
-75
dB
min
10
－
Typ
－
－
max
－
50
Units
kΩ
pF
-6
－
20
dB
min
typ
max
Units
Output voltage(AGND level) PCM +0 code input
－
1.3
－
V
Load resistance
Load capacitance
5
－
－
－
－
40
kΩ
pF
Crosstalk
Parameter
Transmit to receive
VFTN → VR
Receive to transmit
DR → DX
Conditions
VFTN 0dBm0@1020Hz
DR = 0-Code
DR=0dBm0@1020Hz code level
VFTN = 0 Vrms
Analog input op-amp characteristics :AMPT
Parameter
Conditions
Load resistance
AC load, Including feedback resistance
Load capacitance
Gain
Inverting amplifiers
Receive signal output characteristics :VR
Parameter
<MS0998-E-00>
Conditions
AC load
10
2008/9
[AK2300]
PACKAGE INFORMATION
16pin QFN (3mm x 3mm)
1.50±0.10
3.0±0.1
B
3.0±0.1
0.5
1.50±0.10
0.75
16
1
A
0.22±0.05
0.22±0.05
0.05
M
S A B
0.45±0.10
<MS0998-E-00>
0.00MIN
0.05MAX
0.65MAX
S
0.05
S
11
2008/9
[AK2300]
PIN ASSIGNMENT
16pin QFN
Top View
BCLK
15
DR
16
9
14
PLLC
FS
10
13
VSS
12
DX 11
LVDD
DIF0
Bottom View
300
XXX
PLLC
9
8 VREF
VREF
8
7 VFTN
VFTN
7
6 GST
GST
6
5 DIF1
DIF1
5
VSS DX
LVDD
10 11 12
Exposed
PAD
4 VR
3 VDD
2 PDN
1 MUTEN
4
VR
3
2
13
DIF0
14
FS
15
BCLK
16
DR
1
MUTEN
VDD PDN
MARKING
(1) 1pin sign
(2) Marketing Code: 300
(3) Date Code: 3digit XXX
9
13
300
(2)
XXX
(3)
(1)
<MS0998-E-00>
5
1
12
2008/9
[AK2300]
CIRCUIT DESCRIPTION
BLOCK
AMPT
AAF
CODEC
A/D
CODEC
D/A
SMF
BGREF
PCM I/F
FUNCTION
Op-amp for input gain adjustment. This op-amp is used as an inverting amplifier.
Adjusting the gain with external resistors. The resistor should be larger than
10kohm for the feedback resistor.
VFTN: Negative op-amp input.
GST: Op-amp output.
Integrated anti-aliasing filter which prevents signals around the sampling rate
from folding back into the voice band. AAF is a 2nd order RC active low-pass filter.
Converting the analog signal to 14bits linear data. And it is PCM data according to
the companding schemes of ITU recommendation G.711; A-law or u-law. The
band limiting filter is also integrated.
The selection of companding schemes(A-law/ and interface timing are set by
DIF0/1pins.
Converting the 14bits linear PCM data or 8bits PCM data accroding to A-law /
u-law.
The selection of expanding schemes and interface timing are set by DIF0/1pins.
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of the
D/A output.
Provide the stable analog reference voltage using an on-chip band-gap reference
circuit which is temperature compensated. The output voltage is 1.3V for 3.3V
An external capacitor of 0.1uF should be connected between VREF and
VSS to stabilize analog ground (VREF).
Please do not connect external load to this pin.
For the PCM data rate, 64kHz ´ N (N=1~32) are available.
The 8bit PCM data is input/output by A/u-law data.
The 14bit PCM data is input/output by the 2’s compliment 16bit serial data format.
PCM data is input to DR pin and output from DX pin.
The selection of interface timing is selected by DIF0/1 pins.
DIF0
“L” : A-law
“H” : u-law
“FS” : Linear
<MS0998-E-00>
DIF1
“H” : MSB of DX/DR are input/output by rising edge of FS
“L” : MSB of DX/DR are input/output by next rising edge
of BCLK after the rising edge of FS.
13
2008/9
[AK2300]
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin with MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is 8bit A/u-law or 14bit linear. And full scale is defined
as 3.14dBm0. The analog input of 0.660Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter which Frequency response is designated in
page8, and converted analog signal. This analog signal is removed the high frequency element with
SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is 8bit A/u-law data or 14bit linear.
And full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output
signal becomes 0.660Vrms.
- 14bit linear PCM digital code
The relation ship between the analog signal and the 14bit linear code.
Signal level
+Full code
Peak value of the PCM 0dBm0 CODEC
PCM 0-CODE
-Full scale
14bit linear CODE (MSB First)
01 1111 1111 1111
01 0110 0100 1010
00 0000 0000 0000
10 0000 0000 0000
PCM Data Interface
AK2300 supports the following PCM data formats
- DIF0=”L” : A-Law
- DIF0=”H”: u-Law
- DIF0=”FS”: Linear PCM
- DIF1=”H” : MSB of DX/DR are input/output by rising edge of FS
- DIF1=”L” : MSB of DX/DR are input/output by next rising edge of BCLK after the rising edge of FS.
PCM data is interfaced through the pin (DX, DR).
In each case, PCM data is interfaced by A/u-law data with 8bit format and 2’s compliment 2digit data with
16bit MSB first format. However, internal CODEC is 14bit format operation, then the lowest 2bits output
become to “L” level. For the input, the lowest 2bits are ignored.
- Frame sync signal （FS）
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
All the internal clock of the LSI is generated based on this FS signal.
-Bit clock （BCLK）
BCLK defines the PCM data rate. BCLK rate is 64kHz ´ N (N=1~32). This clock must be synchronized with
FS.
<MS0998-E-00>
14
2008/9
[AK2300]
DIF0=”L or H”, DIF1=”H”
FS
BCLK
DX
DR
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Don’t care
DIF0=”FS”, DIF1=”H”
FS
BCLK
DX
DR
Don’t
care
1
2
3
4
5
6
7
8
９
10
11
12
13
14
L
L
1
2
3
4
5
6
7
8
９
10
11
12
13
14
Don’t care
DIF0=”L or H”, DIF1=”L”
FS
BCLK
DX
DR
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
９
10
11
12
13
14
L
1
2
3
4
5
6
7
8
９
10
11
12
13
14
Don’t care
Don’t care
DIF0=”FS”, DIF1=”L”
FS
BCLK
DX
DR
Don’t
care
<MS0998-E-00>
15
L
2008/9
[AK2300]
MUTE
The output of the PCM CODEC can be muted by pin control.
MUTEN pin
MUTEN pin
Operation
DX pin
VR pin
L
Mute
0 Code
VREF level(1.3V)
H
Normal
PCM data output
CODEC analog output
[DX pin]
When the MUTEN pin turns to “L” during the data output, the mute function becomes available at the top of
the next FS.
[VR pin]
When the MUTEN pin turns to “L”, 0 code is fed to the D/A converter and VR becomes at analog reference
level (VREF level=1.3V).
POWER DOWN MODE
PDN pin “L” or to hold the BCLK pin “L”, the AK2300 is powered down.
(*Please don’t stop BCLK at “H” level.)
Power up/down sequence
1) Power down
60usec(typ) passed after the PDN pin turns “L” or the BCLK pin hold “L”, internal PDN signal turn to L and the
AK2300 is powered down.
When power down mode the output pins are as follows.
PIN Name
GST
VR
DX
VREF
PLLC
Output state
Hi-Z
Hi-Z
VSS
VSS
VSS
2) Power up
FS and BCLK pins are clocked and PDN pin =”H”, internal PDN signal is turn to “H” and power down mode is
released.
During power down mode and 20msec (typ) after the power up, the voice path is muted for not to output
abnormal noise.
Power down
MUTE
release
Power up
Power down
MUTE
release
Power up
BCLK stop
60usec
BCLK input
BCLK
BCLK
PDN
PDN
Internal PD
signal
Internal PD
signal
Internal
MUTE signal
Internal
MUTE signal
20msec
Power Down by BCLK=”L”
<MS0998-E-00>
20msec
Power Down by PDN=”L”
16
2008/9
[AK2300]
Recommended start up procedure
The following start up procedure is recommended when AK2300 is going to power up.
Power up is 5ms or less, internal Power On Reset is working, because ( ) in the following sequence can be
omitted.
Power up
- FS=”L”
-BCLK=”L”
(-PDN=”L”)
-Supply BCLK and FS
Wait 20ms
Wait 20ms
- CODEC Initialization starts.
(- PDN=”H”)
- CODEC Initialization complete.
Internal MUTE=”H”
CODEC starts working
<MS0998-E-00>
17
2008/9
[AK2300]
APPLICATION CIRCUIT EXAMPLES
Analog input circuit (single)
Analog output circuit
GST
20kohm
1uF
100pF
1uF
10kohm
VR
VFTN
5Kohm
Power supply, PLL loop filter
capacitor and analog ground
stabillization capacitor
VREF
VREF
PLLC
PLL
0.1uF
VSS
0.056uF
±30%
VSS
LVDD
VDD
1uF
0.1uF
VSS
<MS0998-E-00>
18
2008/9
[AK2300]
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of
Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
l AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the
application or use of any information contained herein.
l Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
l AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such
use, except for the use approved with the express written consent by Representative Director of AKEMD.
As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure
to function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
l It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such
notification.
<MS0998-E-00>
19
2008/9