[AK4384] AK4384 106dB 192kHz 24-Bit 2ch ΔΣ DAC AK4384 24 ΔΣ DAC (SCF) 192kHz DVD, AC-3 AK4384 16pin TSSOP : 8kHz ∼ 192kHz 128 64 32 24 2 2 4 8 FIR SCF LPF (32kHz, 44.1kHz, 48kHz ) ATT ( 256 ) I/F : 24 , 24/20/16 : 256fs, 384fs, 512fs, 768fs or 1152fs 128fs, 192fs, 256fs or 384fs 2 128fs or 192fs 4 THD+N: -94dB Dynamic Range: 106dB : 4.5 ∼ 5.5V : 16pin TSSOP (6.4mm x 5.0mm) , I2S MCLK P/S VDD SMUTE/CSN ACKS/CCLK De-emphasis Control µP Interface VSS Clock Divider VCOM DIF0/CDTI DZFL DZFR LRCK BICK SDTI Audio Data Interface ATT 8X Interpolator ΔΣ Modulator SCF LPF AOUTL ATT 8X Interpolator ΔΣ Modulator SCF LPF AOUTR PDN MS0176-J-02 2010/09 -1- [AK4384] ■ -20 ∼ +85°C -40 ∼ +85°C AK4384 AK4384ET AK4384VT AKD4384 16pin TSSOP (0.65mm pitch) 16pin TSSOP (0.65mm pitch) ■ No. 1 Pin Name MCLK MCLK 1 16 DZFL BICK 2 15 DZFR SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 VCOM SMUTE/CSN 6 11 AOUTL ACKS/CCLK 7 10 AOUTR DIF0/CDTI 8 9 P/S Top View I/O I Function Master Clock Input Pin An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin When at “L”, the AK4384 is in the power-down mode and is held in reset. The The AK4384 must be reset once upon power-up. 6 SMUTE I Soft Mute Pin in parallel mode “H”: Enable, “L”: Disable CSN I Chip Select Pin in serial mode 7 ACKS I Auto Setting Mode Pin in parallel mode “L”: Manual Setting Mode, “H”: Auto Setting Mode CCLK I Control Data Clock Pin in serial mode 8 DIF0 I Audio Data Interface Format Pin in parallel mode CDTI I Control Data Input Pin in serial mode 9 P/S I Parallel/Serial Select Pin (Internal pull-up pin) “L”: Serial mode, “H”: Parallel mode 10 AOUTR O Rch Analog Output Pin 11 AOUTL O Lch Analog Output Pin 12 VCOM O Common Voltage Pin, VDD/2 Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. 13 VSS Ground Pin 14 VDD Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note: All input pins except pull-up pin should not be left floating. MS0176-J-02 2010/09 -2- [AK4384] (VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature AK4384ET (Powered applied) AK4384VT Storage Temperature Note: 1. Symbol VDD IIN VIND Ta Ta Tstg min -0.3 -0.3 -20 -40 -65 max 6.0 ±10 VDD+0.3 85 85 150 Units V mA V °C °C °C : (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.5 typ 5.0 max 5.5 Units V : MS0176-J-02 2010/09 -3- [AK4384] ( Ta = 25°C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS -94 -84 BW=20kHz -60dBFS -42 fs=96kHz 0dBFS -92 BW=40kHz -60dBFS -39 fs=192kHz 0dBFS -92 BW=40kHz -60dBFS -39 Dynamic Range (-60dBFS with A-weighted) (Note 4) 100 106 S/N (A-weighted) (Note 5) 100 106 Interchannel Isolation (1kHz) 90 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 Output Voltage (Note 6) 3.15 3.40 3.65 Load Resistance (Note 7) 5 Power Supplies Power Supply Current (VDD) 17 27 Normal Operation (PDN = “H”, fs≤96kHz) 20 32 Normal Operation (PDN = “H”, fs=192kHz) 10 100 Power-Down Mode (PDN = “L”) (Note 8) Notes: 3. Audio Precision (System Two) 4. 100dB at 16bit data. 5. S/N 6. (0dB) VDD AOUT (typ.@0dB) = 3.4Vpp × VDD/5 7. AC 8. (MCLK, BICK, LRCK) VDD VSS MS0176-J-02 Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ mA mA µA 2010/09 -4- [AK4384] (Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min Digital filter PB 0 Passband ±0.05dB (Note 9) -6.0dB Stopband (Note 9) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 10) GD Digital Filter + LPF Frequency Response 20.0kHz fs=44.1kHz FR 40.0kHz fs=96kHz FR 80.0kHz fs=192kHz FR Notes: 9. fs ( PB=0.4535×fs(@±0.05dB) SB=0.546×fs 10. 16/24 typ max Units 22.05 20.0 - 19.3 - kHz kHz kHz dB dB 1/fs ± 0.03 ± 0.03 ± 0.03 - dB dB dB ± 0.02 ) (Ta = 25°C; VDD = 4.5 ~ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units PB 0 39.2 18.2 8.1 - Digital Filter Passband ±0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 11) (Note 11) SB PR SA GD (Note 10) 19.3 - kHz kHz kHz dB dB 1/fs +0.02/-5 +0.02/-4 +0.02/-5 - dB dB dB typ - max 0.8 0.4 ± 10 Units V V V V µA ± 0.005 72 - Digital Filter + LPF Frequency Response Note: 11. 20.0kHz 40.0kHz 80.0kHz FR FR FR fs=44.kHz fs=96kHz fs=192kHz ) fs ( PB = 0.185×fs (@±0.04dB), SB = 0.888×fs DC (Ta = 25°C; VDD = 4.5 ∼ 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout = -80µA) Low-Level Output Voltage (Iout = 80µA) Input Leakage Current (Note 12) Note: 12. P/S Symbol VIH VIL VOH VOL Iin min 2.2 VDD-0.4 - - (typ. 100kΩ) MS0176-J-02 2010/09 -5- [AK4384] (Ta = 25°C; VDD = 4.5 ∼ 5.5V) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 13) LRCK Edge to BICK “↑” (Note 13) SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width (Note 14) Notes: 13. LRCK BICK 14. PDN “L” “H” Symbol fCLK dCLK min 2.048 40 typ 11.2896 max 36.864 60 Units MHz % fsn fsd fsq Duty 8 60 120 45 48 96 192 55 kHz kHz kHz % tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns tPD 150 ns “↑” MS0176-J-02 2010/09 -6- [AK4384] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Serial Interface Timing MS0176-J-02 2010/09 -7- [AK4384] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPD PDN VIL Power-down Timing MS0176-J-02 2010/09 -8- [AK4384] ■ MCLK, LRCK, BICK (MCLK) (LRCK) ΔΣ MCLK (Manual Setting Mode) (Auto Setting Mode) Manual Setting Mode (ACKS = “0”: Register 00H) DFS0/1 (Table 1) MCLK (Table 2~4) (PDN = “↑”) Auto Setting Mode Auto Setting Mode (ACKS = “1”: Default) MCLK (Table 5) (Table 6) DFS0/1 MCLK ACKS pin ACKS pin “H” ACKS pin “L” Normal Speed Mode Double Speed Mode 128fs Auto Setting Mode 192fs (PDN= “H”) (MCLK, BICK, LRCK) (PDN= “L”) ON (PDN = “↑”) MCLK, LRCK DFS1 DFS0 Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~48kHz 0 1 Double Speed Mode 60kHz~96kHz 1 0 Quad Speed Mode Table 1. LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz LRCK fs 88.2kHz 96.0kHz 128fs 11.2896MHz 12.2880MHz Table 3. 120kHz~192kHz (Manual Setting Mode) 384fs 12.2880MHz 16.9344MHz 18.4320MHz Table 2. Default MCLK 512fs 16.3840MHz 22.5792MHz 24.5760MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz (Normal Speed Mode MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz (Double Speed Mode MS0176-J-02 1152fs 36.8640MHz N/A N/A BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Manual Setting Mode) 384fs 33.8688MHz 36.8640MHz BICK 64fs 5.6448MHz 6.1440MHz Manual Setting Mode) 2010/09 -9- [AK4384] LRCK fs 176.4kHz 192.0kHz MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz Table 4. (Quad Speed Mode MCLK 512fs 768fs 256fs 384fs 128fs 192fs Table 5. LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 BICK 64fs 11.2896MHz 12.2880MHz Manual Setting Mode) Sampling Speed Normal Double Quad (Auto Setting Mode: Default at Serial mode) 192fs 33.8688 36.8640 256fs 22.5792 24.5760 - MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 33.8688 36.8640 - Table 6. 768fs 24.5760 33.8688 36.8640 - 1152fs 36.8640 - Sampling Speed Normal Double Quad (Auto Setting Mode) ■ BICK LRCK (Table 7) DIF0 DIF1 MSB 2’s complement LSB Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 SDTI DIF0 0 1 Mode 2 16/20 “0” DIF0 0 1 0 1 0 SDTI Format 16bit 20bit 24bit 24bit I2S 24bit Table 7. Mode 2 3 5 (Table 8) 2 BICK BICK ≥32fs ≥40fs ≥48fs ≥48fs ≥48fs ( SDTI Format 24bit 24bit I2S BICK ≥48fs ≥48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Default ) Figure Figure 3 Figure 4 Table 8. MS0176-J-02 2010/09 - 10 - [AK4384] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 2 16 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 Don’t care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don’t care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1,4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing MS0176-J-02 2010/09 - 11 - [AK4384] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 0 1 23 22 Don’t care 23 22 0 1 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing ■ IIR 3 (32kHz, 44.1kHz, 48kHz) Double Speed Mode, Quad Speed Mode (50/15μs ) OFF DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz Table 9. Default (Normal Speed Mode) ■ AK4384 MUTE DAC 256 ATT 0dB -48dB 1 256 Table 10 Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode 1 Level 4LRCK 8LRCK 16LRCK 255 to 0 1020LRCK 2040LRCK 4080LRCK Table 10. ATT MS0176-J-02 2010/09 - 12 - [AK4384] ■ AK4384 DZF DZF “L” 8192 “H” RSTN “0” DZF “0” DZFM “1” 8192 “H” DZFE “0” “0” “H” RSTN “1” DZF 4~5LRCK “L” “0” DZF DZF “L” DZF DZFB ■ ×ATT (Table 10) -∞ ATT SMUTE -∞ (“0”) ATT ×ATT “1” ATT SMUTE ATT ”0” -∞ -∞ ATT SMUTE bit (1) ATT Level (1) (3) Attenuation -∞ GD GD (2) AOUT (4) 8192/fs DZF pin : (1) ATT ×ATT 1020LRCK (2) (3) 0dB (4) (Table 10) Normal Speed Mode ATT “255” (GD) -∞ 8192 ”0” ”0” DZF DZF ”L” ”H” Figure 5. MS0176-J-02 2010/09 - 13 - [AK4384] ■ ON PDN LRCK “↑” “L” MCLK LRCK ■ PDN L” (Hi-Z) Figure5 PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD (1) D/A Out (Analog) GD (2) (3) (3) (1) (4) Clock In Don’t care MCLK, LRCK, BICK DZF (6) External MUTE (5) (1) (2) (3) PDN (4) (5) (6) Mute ON (GD) Hi-Z (“↑ ↓”) “0” (PDN = “L”) (MCLK, BICK, LRCK) (3) (PDN = “L”) Figure 6. DZF “L” / MS0176-J-02 2010/09 - 14 - [AK4384] ■ RSTN VCOM “0” DAC DZFL/DZFR “H” Figure 7 RSTN RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation Normal Operation Digital Block Power-down D/A In (Digital) “0” data (1) GD GD (2) (3) D/A Out (Analog) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK 2/fs(5) DZF (1) (2) RSTN = “0” (3) RSTN (4) (5) DZF “L” (6) RSTN VCOM (“↓ ↑”) (RSTN = “0”) RSTN (GD) (VDD/2) “0” (MCLK, BICK, LRCK) “H” LSI RSTN LSI RSTN 2/fs 3 ~4/fs 2 ~ 3/fs Figure 7. MS0176-J-02 2010/09 - 15 - [AK4384] ■ AK4384 P/S “L” CDTI I/F only), Register address (MSB first, 5bit) “↑” 5MHz (max) 3 Function Parallel mode Serial contorl mode X X O X X O O O O O Double sampling mode at 128/192fs De-emphasis SMUTE Zero Detection 24bit LSB justified format Table 11. PDN I/F : CSN, CCLK, ), Read/Write (1bit, “1” , Write CCLK “↓” “↑” CCLK Chip address (2bit, C1/0, “01” Control data (MSB first, 8bit) CSN (O: , X: “L” ) RSTN “L” CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 8. Control I/F Timing *AK4384 *PDN = “L” C1/0, R/W (“011”) ■ Register Map Addr 00H 01H 02H 03H 04H Notes: Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 D6 D5 D4 D3 D2 D1 D0 ACKS DZFE 0 ATT7 ATT7 0 DZFM 0 ATT6 ATT6 0 SLOW 0 ATT5 ATT5 DIF2 DFS1 INVL ATT4 ATT4 DIF1 DFS0 INVR ATT3 ATT3 DIF0 DEM1 DZFB ATT2 ATT2 PW DEM0 0 ATT1 ATT1 RSTN SMUTE 0 ATT0 ATT0 For addresses from 05H to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is “0”. MS0176-J-02 2010/09 - 16 - [AK4384] ■ Register Definitions Addr 00H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN default 1 0 0 0 1 0 1 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 7) Initial: “010”, Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode. Addr 01H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default 0 0 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (see Table 9) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal Speed Mode 01: Double Speed Mode 10: Quad Speed Mode When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS0176-J-02 2010/09 - 17 - [AK4384] DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Addr 02H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 3 0 0 0 INVL INVR DZFB 0 0 default 0 0 0 0 0 0 0 0 D5 ATT5 ATT5 1 D4 ATT4 ATT4 1 D3 ATT3 ATT3 1 D2 ATT2 ATT2 1 D1 ATT1 ATT1 1 D0 ATT0 ATT0 1 DZFB: Inverting Enable of DZF 0: DZF goes “H” at Zero Detection 1: DZF goes “L” at Zero Detection INVR: Inverting Lch Output Polarity 0: Normal Output 1: Inverted Output INVL: Inverting Rch Output Polarity 0: Normal Output 1: Inverted Output Addr 03H 04H Register Name Lch ATT Rch ATT default D7 ATT7 ATT7 1 D6 ATT6 ATT6 1 ATT = 20 log10 (ATT_DATA / 255) [dB] 00H: Mute MS0176-J-02 2010/09 - 18 - [AK4384] Figure 9 Figure 10 (AKD4384) Master Clock 1 MCLK DZFL 16 64fs 2 BICK DZFR 15 24bit Audio Data 3 SDTI VDD 14 0.1u fs Reset & Power down Mode Setting Digital Ground VSS 13 VCOM 12 SMUTE AOUTL 11 7 ACKS AOUTR 10 8 DIF0 P/S 9 4 LRCK 5 PDN 6 AK4384 10u + Analog Supply 5V 10u + Lch MUTE Lch Out Rch MUTE Rch Out Analog Ground Figure 9. Typical Connection Diagram (Parallel mode) Master Clock 1 MCLK DZFL 16 64fs 2 BICK DZFR 15 24bit Audio Data 3 SDTI VDD 14 0.1u fs Reset & Power down Microcontroller Digital Ground 4 LRCK 5 VSS 13 PDN VCOM 12 6 CSN AOUTL 11 7 CCLK AOUTR 10 8 CDTI P/S 9 AK4384 10u + + Analog Supply 5V 10u Lch MUTE Lch Out Rch MUTE Rch Out Analog Ground Figure 10. Typical Connection Diagram (Serial mode) Notes: - LRCK = fs, BICK=64fs. - AOUT - MS0176-J-02 2010/09 - 19 - [AK4384] 1. VDD VSS VDD VDD VSS 2. VCOM INVL/INVR L/R ) (SCF) 2’s complement (2 ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT ( 800000H(@24bit) VCOM + Figure 11 2Vrms mV 3.40Vpp(typ@VDD=5V) ΔΣ (CTF) VCOM DC DC LPF 820p 3.3k 2.2k +Vop 22u 1.5k Analog Out 1.8k AOUT 10k 820p -Vop fc=111.8kHz, Q=0.714, g=-0.04dB at 40kHz Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) MS0176-J-02 2010/09 - 20 - [AK4384] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 M 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : MS0176-J-02 2010/09 - 21 - [AK4384] (AK4384VT) AKM 4384VT XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4384VT Asahi Kasei Logo MS0176-J-02 2010/09 - 22 - [AK4384] (AK4384ET) AKM 4384ET XXYYY 5) 6) 7) 8) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4384ET Asahi Kasei Logo MS0176-J-02 2010/09 - 23 - [AK4384] Date (YY/MM/DD) 02/09/11 06/01/11 Revision 00 01 Reason Page Contents 2 AK4384ET 23 AK4384ET 10/09/28 02 21 z z z z z z MS0176-J-02 2010/09 - 24 -