[AK4388A] AK4388A 192kHz 24-Bit 2ch ΔΣ DAC AK4388A 24 DAC ΔΣ (SCF) 192kHz DVD, AC-3 AK4388A 16pin TSSOP : 8kHz ∼ 192kHz 128 64 32 24 2 4 8 FIR SCF I/F : 24bit , 24bit/16bit : 256fs, 384fs, 512fs, 768fs, 1152fs 256fs, 384fs 2 128fs or 192fs 4 , I2S THD+N: -90dB S/N: 106dB : 4.5 ∼ 5.5V : 16pin TSSOP (6.4mm x 5.0mm) AK4384 MCLK VDD DEM SMUTE ACKS DIF0 DIF1 LRCK BICK SDTI Control Port De-emphasis Control VSS Clock Divider VCOM DZF Audio Data Interface 8X Interpolator ΔΣ Modulator SCF LPF AOUTL 8X Interpolator ΔΣ Modulator SCF LPF AOUTR RSTN MS1008-J-02 2010/09 -1- [AK4388A] ■ -20°C ∼ +85°C AK4388A AK4388AET AKD4388A 16pin TSSOP (0.65mm pitch) ■ MCLK 1 16 DZF BICK 2 15 DEM SDTI 3 14 VDD LRCK 4 13 VSS RSTN 5 12 VCOM SMUTE 6 11 AOUTL ACKS 7 10 AOUTR DIF0 8 9 DIF1 Top View ■ Compatibility with AK4384, AK4388 1. Function Functions THD+N Output Voltage Slow Roll-Off Filter Mode Setting DEM in Parallel control Audio Format in Parallel control Zero Data Detect Pin MCLK, LRCK, BICK Clock Stop (RSTN pin= “H”) 2. Pin Configuration AK4388/A AK4384 MCLK MCLK BICK BICK SDTI SDTI LRCK LRCK RSTN PDN SMUTE SMUTE/CSN ACKS ACKS/CCLK DIF0 DIF0/CDTI AK4384 -94dB 3.4Vpp Available Serial/Parallel Not Available AK4388A Å Å Å Å Å Å 2 pins AK4388 -90dB 3.2Vpp Not Available Parallel Available 24/16-Bit I2S 24-Bit MSB justified 24/16-Bit LSB justified 1 pin Not Available Not Available Available 24-Bit I2S 24-Bit MSB justified Pin# 1 2 3 4 5 6 7 8 Pin# 16 15 14 13 12 11 10 9 AK4384 DZFL DZFR VDD VSS VCOM AOUTL AOUTR P/S (pu) Å AK4388/A DZF DEM (pd) VDD VSS VCOM AOUTL AOUTR DIF1 (pu) : AK4384 * pu: Pull-up, pd: Pull-down MS1008-J-02 2010/09 -2- [AK4388A] No. 1 Pin Name MCLK I/O I 2 3 4 5 BICK SDTI LRCK RSTN I I I I 6 SMUTE I 7 ACKS I 8 9 10 11 12 DIF0 DIF1 AOUTR AOUTL VCOM I I O O O 13 14 VSS VDD - 15 DEM I Function Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Reset Mode Pin When at “L”, the AK4388A is in the power-down mode and is held in reset. The AK4388A should always be reset upon power-up. Soft Mute Pin “H”: Enable, “L”: Disable Auto Setting Mode Pin “L”: Manual Setting Mode, “H”: Auto Setting Mode Audio Data Interface Format Pin Audio Data Interface Format Pin (Internal pull-up pin) Rch Analog Output Pin Lch Analog Output Pin Common Voltage Pin, VDD/2 Normally connected to VSS with a 10μF electrolytic cap. Ground Pin Power Supply Pin 4.5V~5.5V De-emphasis Mode Pin (Internal pull-down pin) When at “H”, the de-emphasis filter is available. 16 DZF O Zero Input Detect Pin Note: All input pins except pull-up and pull-down pins should not be left floating. (VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 1. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -20 -65 max 6.0 ±10 VDD+0.3 85 150 Units V mA V °C °C : (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.5 typ 5.0 max 5.5 Units V : MS1008-J-02 2010/09 -3- [AK4388A] ( Ta = 25°C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 2) THD+N fs=44.1kHz 0dBFS –90 –80 BW=20kHz –60dBFS –42 fs=96kHz 0dBFS –90 BW=40kHz –60dBFS –39 fs=192kHz 0dBFS –85 BW=40kHz –60dBFS –39 Dynamic Range (-60dBFS with A-weighted) (Note 3) 98 106 S/N (A-weighted) (Note 4) 98 106 Interchannel Isolation (1kHz) 90 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 Output Voltage (Note 5) 2.95 3.20 3.45 Load Resistance (Note 6) 5 Load Capacitance 25 Power Supplies Power Supply Current (VDD) 16 Normal Operation (RSTN pin = “H”, fs ≤ 96kHz) 18 27 Normal Operation (RSTN pin = “H”, fs = 192kHz) 60 160 Power-Down Mode (RSTN pin = “L”) (Note 7) Note 2. Audio Precision (System Two) Note 3. 100dB at 16bit data. Note 4. S/N Note 5. (0dB) VDD AOUT (typ.@0dB) = 3.20Vpp × VDD/5 Note 6. AC Note 7. DIF1 pin VDD (MCLK, BICK, LRCK) VSS MS1008-J-02 Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ pF mA mA µA 2010/09 -4- [AK4388A] (Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz) Parameter Digital filter (DEM = OFF) Passband ±0.05dB (Note 8) –6.0dB Stopband (Note 8) Passband Ripple Stopband Attenuation Group Delay (Note 9) De-emphasis Filter (DEM = ON) De-emphasis Error fs = 32kHz fs = 44.1kHz (DC ) fs = 48kHz Digital Filter + LPF (DEM = OFF) Frequency Response 20.0kHz fs=44.1kHz 40.0kHz fs=96kHz 80.0kHz fs=192kHz Note 8. Symbol min typ max Units PB 0 24.1 22.05 20.0 - SB PR SA GD FR FR FR fs ( 54 - 19.3 - kHz kHz kHz dB dB 1/fs - - –1.5/0 –0.2/+0.2 0/+0.6 dB dB dB ± 0.02 ) dB ±0.2 dB ±0.3 dB +0.1/-0.6 PB=0.4535×fs(@±0.05dB) SB=0.546×fs Note 9. 16/24 MS1008-J-02 2010/09 -5- [AK4388A] DC (Ta = 25°C; VDD = 4.5 ∼ 5.5V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout = –80µA) VOH Low-Level Output Voltage (Iout = 80µA) VOL Input Leakage Current (Note 10) Iin Note 10. DIF1 pin DEM pin DIF1 pin (typ. 100kΩ) (Ta = 25°C; VDD = 4.5 ∼ 5.5V; CL = 20pF) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 11) LRCK Edge to BICK “↑” (Note 11) SDTI Hold Time SDTI Setup Time Reset Timing RSTN Pulse Width (Note 12) Note 11. LRCK BICK Note 12. RSTN pin “L” “H” min 2.2 VDD-0.4 - typ - max 0.8 0.4 ± 10 Units V V V V µA DEM pin Symbol fCLK dCLK min 2.048 40 fsn fsd fsq Duty 8 32 120 45 tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns tRST “↑” 150 ns MS1008-J-02 typ 11.2896 max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % 2010/09 -6- [AK4388A] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Serial Interface Timing tRST RSTN VIL Figure 3. Power-down Timing MS1008-J-02 2010/09 -7- [AK4388A] ■ MCLK, LRCK, BICK (MCLK) (LRCK) MCLK ΔΣ MCLK (Manual Setting Mode) (Auto Setting Mode) Manual Setting Mode (ACKS pin = “L”, Normal Speed mode) MCLK (Table 1) Auto Setting Mode (ACKS pin = “H”) MCLK (Table 2) (Table 3) LRCK fs 256fs 32.0kHz 8.1920MHz 44.1kHz 11.2896MHz 48.0kHz 12.2880MHz Table 1. MCLK BICK 384fs 512fs 768fs 1152fs 64fs 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz (Manual Setting Mode, ACKS pin = “L”, Normal Speed Mode) MCLK 1152fs 512fs 256fs 128fs Table 2. LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK= 256fs/384fs 32kHz~48kHz 3dB 768fs 384fs 192fs 128fs 192fs 22.5792 33.8688 24.5760 36.8640 Table 3. Mode Sampling Rate Normal 8kHz~32kHz Normal 8kHz~48kHz Double 32kHz~96kHz Quad 120kHz~192kHz (Auto Setting Mode, ACKS pin = “H”) MCLK (MHz) 256fs 384fs 512fs 768fs 8.1920 12.2880 16.3840 24.5760 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 22.5792 33.8688 24.5760 36.8640 (Auto Setting Mode, ACKS pin = “H”) Auto Setting Mode 32kHz~96kHz MCLK= 256fs/384fs DR, S/N 1152fs 36.8640 - (Table 2) MCLK= 512fs/768fs ACKS pin MCLK DR,S/N L 256fs/384fs/512fs/768fs 106dB H 256fs/384fs 103dB H 512fs/768fs 106dB Table 4. MCLK DR, S/N (fs = 44.1kHz) MS1008-J-02 2010/09 -8- [AK4388A] ■ BICK LRCK DIF1 pin BICK (Table 5) SDTI Mode 0 DIF1 L DIF0 L 1 L 2 H 3 H DIF1-0 pin 4 MSB 2’s SDTI Format 16bit BICK ≥32fs Figure Figure 4 H 24bit ≥48fs Figure 5 L 24bit ≥48fs Figure 6 ≥48fs or 32fs Figure 7 2 H 16/24bit I S Table 5. LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 0 14 6 1 5 14 4 15 3 2 16 17 1 0 31 15 0 14 6 1 5 14 4 15 3 16 2 17 1 0 31 15 14 0 1 0 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don’t care 23 22 21 20 19 0 Don’t care 23 22 21 20 19 0 23:MSB, 0:LSB Lch Data Rch Data Figure 5. Mode 1 Timing MS1008-J-02 2010/09 -9- [AK4388A] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI Mode 2 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 6. Mode 2 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI Mode 3 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 7. Mode 3 Timing ■ IIR (50/15μs ) DEM pin = “H” ON Mode (MCLK=256fs/384fs), Quad Speed Mode (MCLK=128fs/192fs) DEM pin De-emphasis Filter 1 0 ON OFF Table 6. DEM pin Double Speed OFF (default) (Normal Speed Mode) MS1008-J-02 2010/09 - 10 - [AK4388A] ■ 8192 DZF pin “L” “0” (Figure 8) DZF pin “H” “0” ■ SMUTE pin “H” SMUTE pin “L” -∞ 1024LRCK 1024LRCK -∞ 1024LRCK -∞ (“0”) 0dB 0dB SMUTE pin 1024/fs 1024/fs (1) 0dB (3) Attenuation -∞ GD GD (2) AOUT (4) 8192/fs DZF pin : (1) 1024LRCK (2) (3) (1024/fs) -∞(“0”) (GD) 1024LRCK (4) 0dB 8192 “0” “0” DZF pin DZF pin “H” “L” Figure 8. MS1008-J-02 2010/09 - 11 - [AK4388A] ■ ON RSTN pin “L” MCLK LRCK “↑” ■ LRCK ON/OFF AK4388A RSTN pin VCOM(VDD/2) “L” DAC RSTN Power RSTN pin Internal State DAC In (Digital) Normal Operation (2) “0”data (3) (1) (2) (3) RSTN (4) (5) (1) GD (3) (5) DZF External Mute (2) “0”data GD DAC Out (Analog) Reset (4) Mute ON Mute ON (GD) VCOM (VDD/2) (“↑ ↓”) “0” (3) (RSTN pin= “L”) Figure 9. DZF pin “L” / MS1008-J-02 2010/09 - 12 - [AK4388A] ■ MCLK LRCK BICK (RSTN pin = “H”) MCLK LRCK MCLK LRCK BICK BICK AK4388A RSTN pin Internal State Power-down D/A In (Digital) Power-down Normal Operation Normal Operation (2) GD D/A Out (Analog) Digital Circuit Power-down (1) GD (4) (3) VCOM (1) (3) (3) <Case1:MCLK Stop> Clock In MCLK Stop MCLK, BICK, LRCK External MUTE (5) (5) <Case2:LRCK Stop> Clock In LRCK Stop MCLK, BICK, LRCK External MUTE (5) (5) (5) <Case3:BICK Stop> Clock In BICK Stop MCLK, BICK, LRCK External MUTE (5) (5) Notes. (1) (2) (5) (GD) “0” BICK (3) RSTN pin (“↑”) MCLK MCLK, LRCK 20usec BICK (4) MCLK MCLK MCLK LRCK 20usec (3 4LRCK) MCLK, LRCK BICK LRCK 20usec BICK VCOM (5) (3) Figure 10. Clock MS1008-J-02 2010/09 - 13 - [AK4388A] Figure 11 (AKD4388A) Master Clock 1 MCLK DZF 16 64fs 2 BICK DEM 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Optional External Mute Circuits 0.1u 4 LRCK 5 RSTN 6 VSS 13 VCOM 12 SMUTE AOUTL 11 7 ACKS AOUTR 10 8 DIF0 DIF1 9 AK4388A + + 10u Analog Supply 5V 10u Lch Out Mode Setting Digital Ground Rch Out Analog Ground Figure 11. Typical Connection Diagram Notes: - LRCK = fs, BICK=64fs. - AOUT - (DIF1 DEM pin MS1008-J-02 ) 2010/09 - 14 - [AK4388A] 1. VDD VSS VDD VDD pin VSS pin 2. ΔΣ (CTF) VCOM 3.20Vpp ( typ@VDD=5V) ) (SCF) 2’s complement (2 ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT ( 800000H(@24bit) VCOM 2 VCOM + Figure 12 1 LPF LPF mV DC DC Figure 13 2Vrms 3.20Vpp (1.13Vrms) AK4388A 10u 220 Analog Out AOUT 3.2Vpp (1.13Vrms) 2.2nF 22k fc=328.8kHz, g=-0.064dB at 40kHz st Figure 12. External 1 order LPF Circuit Example (simple) 390p 3.9k 3.3k +Vop AK4388A 10u 2.7k Analog Out 3.9k AOUT 22k 390p -Vop 5.93Vpp (2.09Vrms) fc=125.8kHz, Q=0.752, g=0.058dB at 40kHz Figure 13. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) MS1008-J-02 2010/09 - 15 - [AK4388A] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 M 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : MS1008-J-02 2010/09 - 16 - [AK4388A] (AK4388AET) AKM 4388AET XXYYY 1) 2) 3) 4) Date (YY/MM/DD) 08/09/19 08/10/17 Revision 00 01 Reason Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4388AET Asahi Kasei Logo Page Contents 10 ■ “Double Speed Mode, Quad Speed Mode OFF ” 10/09/28 02 16 MS1008-J-02 2010/09 - 17 - [AK4388A] z z z z z z MS1008-J-02 2010/09 - 18 -