[AK4392] AK4392 High Performance 120dB Premium 32-Bit DAC AK4392 Filter DVD-Audio 32-bit DAC 32bit Digital 216kHz PCM (SCF) DSD Blu-Ray, DVD-Audio, SACD • 128 • : 30kHz ∼ 216kHz • 32 8 - Ripple: ±0.005dB, Attenuation: 100dB , GD=7/fs • • • DSD • 32, 44.1, 48kHz • • ATT(255 levels and 0.5dB step) • Mono Mode • • THD+N: -103dB • DR, S/N: 120dB • I/F : 24/32 • 30kHz ~ 32kHz: 1152fs 30kHz ~ 54kHz: 512fs or 768fs 30kHz ~ 108kHz: 256fs or 384fs 108kHz ~ 216kHz: 128fs or 192fs • : 4.75 ∼ 5.25V • : TTL • : 44 LQFP MS1045-J-02 , 16/20/24/32 , I2S, DSD 2009/04 -1- [AK4392] ■ DVDD BICK/DCLK LRCK/DSDR/WCK SDATA/DSDL VSS3 PDN DINL VSS4 VSS2 VDDL PCM Data Interface 8X Interpolator SCF AOUTLP AOUTLN DSD Data Interface BCK AVDD DATT Soft Mute Bias Vref ΔΣ Modulator External DF Interface SCF VCML VREFHL VREFLL VREFLR VREFLL VCMR AOUTRP AOUTRN DINR CSN/SMUTE CCLK/DEM0 Control Register VDDR Clock Divider CDTI/DEM1 VSS1 CAD0 CAD1/DIF0 PSN DZFL/DIF1 DIF2 MCLK DZFR Block Diagram MS1045-J-02 2009/04 -2- [AK4392] ■ −10 ∼ +70°C AK4392 AK4392EQ AKD4392 44pin LQFP (0.8mm pitch) AOUTLN VSS2 VDDL VREFHL VREFLL NC VREFLR VREFHR VDDR V SS1 AOUTRN 33 32 31 30 29 28 27 26 25 24 23 ■ AOUTLP 34 22 A OUTRP VCML 35 21 V CMR NC 36 20 NC 19 DINL 18 DINR 17 NC 16 B CK 15 TST2/DZFR NC 37 NC 38 NC 39 AK4392 VSS3 40 AVDD 41 MCLK 42 14 P SN VSS4 43 13 NC NC 44 12 DIF2 7 8 9 10 11 TST1 /CA D0 DEM0/CCLK DEM1/CDTI DIF0/CA D1 DIF1/DZFL 5 LRCK/DSDR/WCK 6 4 S MUTE/CSN 3 BICK/DCLK 2 PDN SDATA/DSDL 1 DVDD Top View MS1045-J-02 2009/04 -3- [AK4392] No. Pin Name I/O Function Digital Power Supply Pin, 4.75 ∼ 5.25V Power-Down Mode Pin When at “L”, the AK4392 is in power-down mode and is held in reset. The AK4392 must always be reset upon power-up. Audio Serial Data Clock Pin in PCM Mode DSD Clock Pin in DSD Mode Audio Serial Data Input Pin in PCM Mode DSD Lch Data Input Pin in DSD Mode L/R Clock Pin in PCM Mode DSD Rch Data Input Pin in DSD Mode Word Clock input pin Soft Mute Pin in Parallel Control Mode When this pin is changed to “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. Chip Select Pin in Serial Control Mode Test Pin in Parallel Control Mode (Internal pull-down pin) Chip Address 0 Pin in Serial Control Mode (Internal pull-down pin) De-emphasis Enable 0 Pin in Parallel Control Mode Control Data Clock Pin in Serial Control Mode De-emphasis Enable 1 Pin in Parallel Control Mode Control Data Input Pin in Serial Control Mode Digital Input Format 0 Pin in PCM Mode Chip Address 1 Pin in Serial Control Mode Digital Input Format 1 Pin in PCM Mode Lch Zero Input Detect Pin in Serial Control Mode 1 DVDD - 2 PDN I BICK DCLK SDATA DSDL LRCK DSDR WCK I I I I I I I SMUTE I CSN TST1 CAD0 DEM0 CCLK DEM1 CDTI DIF0 CAD1 DIF1 DZFL I I I I I I I I I I O 12 DIF2 I 13 NC - 3 4 5 6 7 8 9 10 11 Digital Input Format 2 Pin in PCM Mode No internal bonding. Connect to GND. Note: All input pins except internal pull-up/down pins must not be left floating. MS1045-J-02 2009/04 -4- [AK4392] 14 PSN I TST2 I DZFR O 16 BCK I 17 NC - 18 19 DINR DINL I I 20 NC - 21 VCMR - 22 23 24 25 26 27 AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR O O I I 28 NC - 29 30 31 32 33 34 VREFLL VREFHL VDDL VSS2 AOUTLN AOUTLP I I O O 35 VCML - 36 NC - 37 NC - 38 NC - 39 NC - 40 41 42 43 VSS3 AVDD MCLK VSS4 I - 44 NC - 15 Parallel or Serial Select Pin (Internal pull-up pin) “L”: Serial Control Mode, “H”: Parallel Control Mode Test pin in Parallel Control Mode. Connect to GND. Rch Zero Input Detect Pin in Serial Control Mode Audio Serial Data Clock Pin (Internal pull-down pin) No internal bonding. Connect to GND. Rch Audio Serial Data Input Pin (Internal pull-down pin) Lch Audio Serial Data Input Pin (Internal pull-down pin) No internal bonding. Connect to GND. Right channel Common Voltage Pin, Normally connected to VSS with a 10uF electrolytic cap. Rch Positive Analog Output Pin Rch Negative Analog Output Pin Ground Pin Rch Analog Power Supply Pin, 4.75 ∼ 5.25V Rch High Level Voltage Reference Input Pin Rch Low Level Voltage Reference Input Pin No internal bonding. Connect to GND. Lch Low Level Voltage Reference Input Pin Lch High Level Voltage Reference Input Pin Lch Analog Power Supply Pin, 4.75 ∼ 5.25V Ground Pin Lch Negative Analog Output Pin Lch Positive Analog Output Pin Left channel Common Voltage Pin, Normally connected to VSS with a 10uF electrolytic cap. No internal bonding. Connect to GND. No internal bonding. Connect to GND. No internal bonding. Connect to GND. No internal bonding. Connect to GND. Ground Pin Analog Power Supply Pin, 4.75 ∼ 5.25V Master Clock Input Pin Ground Pin No internal bonding. Connect to GND. Note: All input pins except internal pull-up/down pins must not be left floating. MS1045-J-02 2009/04 -5- [AK4392] ■ (1) (PCM mode Analog Digital ) AOUTLP, AOUTLN AOUTRP, AOUTRN SMUTE TST1 TST2 VSS4 VSS4 (2) 1. PCM Mode Analog Digital AOUTLP, AOUTLN AOUTRP, AOUTRN DIF2 DZFL, DZFR VSS4 2. DSD Mode Analog AOUTLP, AOUTLN AOUTRP, AOUTRN DZFL, DZFR MS1045-J-02 2009/04 -6- [AK4392] (VSS1-4 =0V; Note 1) Parameter Power Supplies: Analog Analog Digital Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature Symbol AVDD VDDL/R DVDD IIN VIND Ta Tstg min −0.3 −0.3 −0.3 −0.3 −10 −65 max 6.0 6.0 6.0 ±10 DVDD+0.3 70 150 Units max 5.25 5.25 5.25 AVDD AVDD Units V V V V V V V V V mA V °C °C Note 1. Note 2. VSS1-4 : (VSS1-4 =0V; Note 1) Parameter Analog Power Supplies Analog (Note 3) Digital “H” voltage reference Voltage “L” voltage reference Reference VREFH − VREFL (Note 4) Symbol AVDD VDDL/R DVDD VREFHL/R VREFLL/R ΔVREF min 4.75 4.75 4.75 AVDD−0.5 VSS 3.0 typ 5.0 5.0 5.0 - Note 1. Note 3. AVDD, VDDL/R, DVDD Note 4. (VREFH − VREFL) AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5. : MS1045-J-02 2009/04 -7- [AK4392] (Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 5) 0dBFS -103 93 fs=44.1kHz THD+N BW=20kHz −60dBFS -57 0dBFS 100 fs=96kHz BW=40kHz −60dBFS -54 0dBFS 100 fs=192kHz BW=40kHz −60dBFS -54 BW=80kHz -51 −60dBFS Dynamic Range (−60dBFS with A-weighted) (Note 6) 114 120 S/N (A-weighted) (Note 7) 114 120 Interchannel Isolation (1kHz) 110 120 DC Accuracy Interchannel Gain Mismatch 0.15 0.3 Gain Drift (Note 8) 20 Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Load Capacitance 25 Load Resistance (Note 10) 1 Power Supplies Power Supply Current Normal operation (PDN pin = “H”) AVDD + VDDL/R DVDD (fs ≤ 96kHz) DVDD (fs = 192kHz) Power down (PDN pin = “L”) AVDD+VDDL/R+DVDD Units Bits dB dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp pF kΩ - 60 43 46 90 70 mA mA mA - 10 100 μA (Note 11) Note 5. Audio Precision System Two Note 6. Figure 20 ( 2) 101dB at 16bit data and 118dB at 20bit data. Note 7. Figure 20 ( 2) S/N Note 8. (VREFH − VREFL) +5V Note 9. (0dB) (VREFHL/R − VREFLL/R) AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5. Note 10. Load Resistance AC (DC ) 1k ohm (min) Figure 20 DC (DC ) 1.5k ohm (min) Figure 19 Load Resistance Note 11. P/S pin = DVDD VSS4 (MCLK, BICK, LRCK) MS1045-J-02 2009/04 -8- [AK4392] (fs = 44.1kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 20.0 kHz −6.0dB 22.05 kHz Stopband (Note 12) SB 24.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 13) GD 36 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz ±0.2 dB (fs = 96kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 43.5 kHz −6.0dB 48.0 kHz Stopband (Note 12) SB 52.5 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 95 dB Group Delay (Note 13) GD 36 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz ±0.3 dB (fs = 192kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 87.0 kHz −6.0dB 96.0 kHz Stopband (Note 12) SB 105 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 90 dB Group Delay (Note 13) GD 36 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz +0/−1 dB Note 12. fs( ) PB = 0.4535 × fs(@±0.01dB) SB = 0.546 × fs Note 13. 16/20/24 MS1045-J-02 2009/04 -9- [AK4392] (fs = 44.1kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“1”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 20.0 kHz −6.0dB 22.05 kHz Stopband (Note 12) SB 24.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 13) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 20.0kHz ±0.2 dB (fs = 96kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“1”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 43.5 kHz −6.0dB 48.0 kHz Stopband (Note 12) SB 52.5 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 95 dB Group Delay (Note 13) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 40.0kHz ±0.3 dB (fs = 192kHz) (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“1”) Parameter Symbol min typ max Units Digital Filter Passband (Note 12) ±0.01dB PB 0 87.0 kHz −6.0dB 96.0 kHz Stopband (Note 12) SB 105 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 90 dB Group Delay (Note 13) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 80.0kHz +0/−1 dB MS1045-J-02 2009/04 - 10 - [AK4392] DC (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.4 Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−100μA) VOH DVDD−0.5 Low-Level Output Voltage (Iout=100μA) VOL Input Leakage Current (Note 14) Iin Note 14. TST1/CAD0 pin TST1/CAD0 pin, PSN pin , PSN pin MS1045-J-02 typ - max 0.8 0.5 ±10 Units V V V V μA (typ. 100kΩ) 2009/04 - 11 - [AK4392] (Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V) Parameter Symbol min Master Clock Timing Frequency fCLK 7.7 Duty Cycle dCLK 40 LRCK Frequency (Note 15) 1152fs, 512fs or 768fs fsn 30 256fs or 384fs fsd 54 128fs or 192fs fsq 108 Duty Cycle Duty 45 PCM Audio Interface Timing BICK Period 1/128fsn tBCK 1152fs, 512fs or 768fs 1/64fsd tBCK 256fs or 384fs 1/64fsq tBCK 128fs or 192fs 30 tBCKL BICK Pulse Width Low 30 tBCKH BICK Pulse Width High 20 tBLR BICK “↑” to LRCK Edge (Note 16) 20 tLRB LRCK Edge to BICK “↑” (Note 16) 20 tSDH SDATA Hold Time 20 tSDS SDATA Setup Time External Digital Filter Mode BICK Period BCK Pulse Width Low BCK Pulse Width High BCK “↑” to WCK Edge WCK Edge to BCK “↑” WCK Pulse Width Low WCK Pulse Width High DATA Hold Time DATA Setup Time DSD Audio Interface Timing DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDL/R (Note 17) Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width (Note 18) typ max Units 41.472 60 MHz % 54 108 216 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns tB tBL tBH tBW tWB tWCK tWCH tDH tDS 27 10 10 5 5 54 54 5 5 ns ns ns ns ns ns ns ns ns tDCK tDCKL tDCKH tDDD 1/64fs 160 160 −20 ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns tPD 150 ns MS1045-J-02 20 2009/04 - 12 - [AK4392] Note 15. 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs Note 16. Note 17. Note 18. LRCK PDN pin RSTN bit BICK “↑” PDN pin “L” “H” ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL 1/fs VIH WCK VIL tB VIH BCK VIL tBH tBL Clock Timing MS1045-J-02 2009/04 - 13 - [AK4392] VIH LRCK VIL tLRB tBLR VIH BICK VIL tSDH tSDS VIH SDATA VIL Audio Interface Timing (PCM Mode) tDCK tDCKL tDCKH VIH DCLK VIL tDDD VIH DSDL DSDR VIL Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”) tDCK tDCKL tDCKH VIH DCLK VIL tDDD tDDD VIH DSDL DSDR VIL Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) MS1045-J-02 2009/04 - 14 - [AK4392] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing MS1045-J-02 2009/04 - 15 - [AK4392] tPD PDN VIL Power Down & Reset Timing VIH WCK VIL tBW tWB VIH BCK VIL tDS tDH VIH DATA VIL External Digital Filter I/F mode MS1045-J-02 2009/04 - 16 - [AK4392] ■ D/A AK4392 DSDR PCM DSD D/A DSD mode PCM mode BICK, LRCK, SDATA D/P bit D/P bit PCM/DSD mode 2 ~ 3/fs PCM DSD DCLK, DSDL, PCM RSTN bit DP bit Interface 0 PCM 1 DSD Table 1. PCM/DSD Mode Control DP bit= “0” Digital Filter Digital Filter I/F I/F (EX DF I/F mode) MCLK, BCK, WCK, DINL, DINR EXDF bit EXDF bit Digital Filter Digital Filter I/F 2 ~ 3/fs Digital Filter RSTN bit Ex DF bit Interface 0 PCM 1 EX DF I/F Table 2. Digital Filter Control (DP bit = “0”) ■ [1] PCM mode AK4392 MCLK, BICK, LRCK MCLK MCLK PDN pin (PDN pin = “H”) RSTN bit MCLK, LRCK (Hi-Z) ON MCLK MCLK LRCK ΔΣ AK4392 MCLK LRCK (PDN pin = “L” → “H”) MCLK LRCK Table 4 MCLK 1152fs 512fs 256fs 128fs Mode Normal 768fs Normal 384fs Double 192fs Quad Table 3. Sampling Speed MS1045-J-02 Sampling Rate 30kHz~32kHz 30kHz~54kHz 30kHz~108kHz 108kHz~216kHz 2009/04 - 17 - [AK4392] LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK= 256fs/384fs MCLK (MHz) 128fs 192fs 256fs 384fs 512fs 768fs N/A N/A 8.1920 12.2880 16.3840 24.5760 N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A N/A N/A Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available) 30kHz~108kHz MCLK= 256fs/384fs DR,S/N MCLK 256fs/384fs 512fs/768fs Table 5. MCLK 30kHz~54kHz 3dB MCLK= 512fs/768fs DR,S/N 117dB 120dB DR, S/N 1152fs 36.8640 N/A N/A N/A N/A N/A N/A (fs = 44.1kHz) [2] DSD mode MCLK, DCLK MCLK DCKS bit (PDN pin = “H”) MCLK (Hi-Z) DCKS bit 0 1 MCLK DCLK AK4392 (PDN pin = “L” → “H”) ON MCLK Frequency DCLK Frequency 512fs 64fs 768fs 64fs Table 6. System Clock (DSD Mode) MS1045-J-02 MCLK (default) 2009/04 - 18 - [AK4392] ■ [1] PCM mode BICK LRCK SDATA DIF2-0 bit DIF2-0 pin 2’s 20 BICK “0” LSB pin (Table 7) MSB Mode 2 16 DIF2-0 8 DIF2-0 bit Mode 0 1 2 3 4 5 6 7 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 Input Format BICK 0 16bit ≥ 32fs 1 20bit ≥ 48fs 0 24bit ≥ 48fs 2 1 24bit I S ≥ 48fs 0 24bit ≥ 48fs 1 32bit ≥ 64fs 0 32bit ≥64fs 1 32bit I2S ≥ 64fs Table 7. Audio Interface Format Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6 Figure 7 (default) LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDATA Mode 0 15 0 14 6 1 5 14 4 15 3 16 2 17 1 0 31 15 0 14 6 5 14 1 4 15 3 16 2 17 1 0 31 15 14 0 1 0 1 BICK (64fs) SDATA Mode 0 Don’t care 15 14 Don’t care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDATA Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDATA Mode 4 Don’t care 23 22 21 20 23 22 21 20 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1/4 Timing MS1045-J-02 2009/04 - 19 - [AK4392] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDATA 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDATA 1 23 22 0 Don’t care 23 22 0 1 23 Don’t care 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing LRCK 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 BICK(128fs) SDATA 31 0 1 2 12 13 14 23 1 24 0 31 31 0 1 2 12 13 14 23 1 24 0 31 0 1 BICK(64fs) SDATA 31 30 20 19 18 9 8 1 0 31 30 Lch Data 20 19 18 9 8 1 0 31 Rch Data 31: MSB, 0:LSB Figure 5. Mode 5 Timing MS1045-J-02 2009/04 - 20 - [AK4392] LRCK 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 BICK(128fs) SDATA 31 30 0 1 12 11 10 2 12 13 0 14 31 30 23 24 31 0 1 12 2 11 10 12 13 0 14 31 23 24 31 0 1 BICK(64fs) SDATA 31 30 20 19 18 8 9 0 1 31 30 20 19 18 Lch Data 8 9 0 1 31 Rch Data 31: MSB, 0:LSB Figure 6. Mode 6 Timing LRCK 0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 24 25 31 0 1 BICK(128fs) SDATA 31 0 1 13 12 11 2 12 0 13 14 31 24 25 31 0 1 13 2 12 11 12 0 13 14 0 1 BICK(64fs) SDATA 0 31 21 20 19 8 9 1 2 0 31 21 20 19 Lch Data 9 8 2 1 0 Rch Data 31: MSB, 0:LSB Figure 7. Mode 7 Timing [2] DSD mode DSD DIF2-0 pin DIF2-0 bit DCLK 64fs DCLK DCKB bit DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal D0 DSDL,DSDR Phase Modulation D0 D1 D1 D2 D1 D2 D3 D2 D3 Figure 8. DSD Mode Timing MS1045-J-02 2009/04 - 21 - [AK4392] [3] (EX DF I/F mode) DW WCK1 BCK MCLK, BCK WCK (Table 9) DIF2-0bit BCK, MCLK MCLK BCK Table 8 (PDN pin = “H”) MCLK, WCK (Hi-Z) ON Sampling Speed[kHz] 44.1(30 54) 44.1(30 54) 96(54 108) 96(54 108) 192(108 216) 192(108 216) DINL, DINR BCK 3 BCK AK4392 MCLK, WCK (PDN pin = “L” → “H”) MCLK, WCK MCLK&BCK [MHz] 128fs N/A 512fs 768fs 22.5792 33.8688 48 11.2896 32 16.9344 32 N/A 33.8688 N/A 24.576 36.864 N/A 96 N/A 48 12.288 32 18.432 32 N/A 36.864 N/A N/A 24.576 36.864 N/A 96 N/A N/A N/A 32 N/A 48 N/A N/A 256fs N/A WCK 384fs N/A N/A 192fs N/A MCLK 48 48 N/A N/A N/A N/A 96 Table 8 System Clock Example (EX DF I/F mode) (N/A: Not available) 36.864 16fs DW 8fs DW 8fs DW 4fs DW 4fs DW 2fs DW ECS 0 1 0 1 0 1 Mode DIF2 DIF1 DIF0 Input Format 0 0 0 0 16bit 1 0 0 1 N/A 2 0 1 0 N/A 3 0 1 1 N/A 4 1 0 0 24bit 5 1 0 1 32bit 6 1 1 0 N/A 7 1 1 1 N/A Table 9 Audio Interface Format (EX DF I/F mode) (N/A: Not available) MS1045-J-02 2009/04 - 22 - [AK4392] 1/16fs or 1/8fs or 1/4fs or 1/2fs WCK 0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1 BCK DINL or DINR 31 0 30 1 24 23 5 22 6 21 7 20 8 17 16 47 15 48 14 6 5 65 49 4 3 92 2 93 1 94 0 95 0 1 BCK DINL or DINR Don’t care 0 1 Don’t care 5 6 7 Don’t care 8 23 24 31 17 25 44 1 2 3 45 46 0 Don’t care 47 0 1 BCK DINL or DINR Don’t care Don’t care Don’t care 31 3 2 1 0 Don’t care Figure 9 EX DF I/F Mode Timing MS1045-J-02 2009/04 - 23 - [AK4392] ■ D/A RSTN bit ≥4/fs D/A Mode PCM Mode DSD Mode ≥0 D/A Data PCM Data DSD Data Figure 10. D/A Mode Switching Timing (PCM to DSD) RSTN bit D/A Mode DSD Mode PCM Mode ≥4/fs D/A Data DSD Data PCM Data Figure 11. D/A Mode Switching Timing (DSD to PCM) Note. DSD mode DSD 25% 75% SACD (Scarlet Book) ■ IIR 3 (32kHz, 44.1kHz, 48kHz) 256fs/384fs 128fs/192fs PCM mode DSD mode DEM1 0 0 1 1 OFF (50/15μs DSD mode ) DEM1-0 bit DEM0 Mode 0 44.1kHz 1 OFF (default) 0 48kHz 1 32kHz Table 10. De-emphasis Control ■ AK4392 MUTE DAC 255 (ATT) 0dB −127dB MS1045-J-02 2009/04 - 24 - [AK4392] ■ (PCM mode, DSD mode) AK4392 DZF pin DZF pin “L” “1” “L” pin “H” DZFM bit DZF pin “H” “L” DZF pin RSTN bit “0” “0” “1” DZFE bit 8192 “0” “0” DZF pin “H” RSTN bit DZF pin 4 ∼ 5LRCK 8192 “0” DZF DZFB bit ■ AK4392 MONO bit SELLR bit MONO bit 0 0 1 1 SELLR bit 0 1 0 1 Lch Out Lch In Rch In Lch In Rch In Rch Out Rch In Lch In Lch In Rch In Table 11 MONO Mode Output Select MS1045-J-02 2009/04 - 25 - [AK4392] ■ ATT × ATT SMUTE bit “0” ATT “L” SMUTE pin “H” −∞ (“0”) −∞ ATT −∞ SMUTE bit “1” SMUTE pin ATT × ATT −∞ ATT S M U T E pin or S M U T E bit (1) (1) AT T _Level (3) A ttenuation -∞ GD (2) GD (2) AOUT (4) 8192/fs D ZF pin (1) ATT × ATT (2) (3) Normal Speed Mode ATT “255” 1020LRCK (GD) −∞ ATT (4) 8192 “0” “0” DZF pin “H” DZF pin “L” Figure 12. Soft Mute Function ■ ON MCLK, LRCK PDN pin “L” PDN pin “H” MCLK 4/fs MS1045-J-02 2009/04 - 26 - [AK4392] ■ ON/OFF AK4392 PDN pin “L” (Hi-Z) RSTN bit “0” DAC VCML/R PDN RSTN Power PDN pin (1) Internal State Normal Operation DAC In (Digital) “0”data “0”data GD DAC Out (Analog) Reset (3) (2) GD (4) (4) (3) (5) Clock In MCLK,LRCK,BICK Don’t care Don’t care (7) DZFL/DZFR External Mute Notes: (1) (2) (3) (4) PDN (5) (6) (7) (6) Mute ON Mute ON PDN pin “L” 150ns PDN pin “L” (GD) Hi-Z (“↓ ↑”) “0” (PDN pin = “L”) (MCLK, BICK, LRCK) (3) (PDN pin = “L”) DZFL/R pin “L” Figure 13. Power-down/up Sequence Example MS1045-J-02 2009/04 - 27 - [AK4392] ■ (1) RSRN bit RSTN bit “0” VCML/R DAC DZFL/DZFR pin “H” Figure 14 RSTN bit RSTN bit 3~4/fs (5) 2~3/fs (5) Internal RSTN bit Internal State Normal Operation Normal O peration D igital Block P D/A In (Digital) d “0 ” data (1) GD GD (3) D/A Out (Analog) (2) (3) (1) 2/ fs(4) DZF (6) (1) (2) RSTN bit = “0” (3) RSTN (GD) VCOM (“↓ ↑”) (4) DZF pin RSTN bit “L” (5) RSTN bit (6) “0” “H” LSI RSTN bit 2 ~ 3/fs (3) Hi-Z (2) LSI RSTN bit 2/fs 3 ~4/fs Figure 14. MS1045-J-02 2009/04 - 28 - [AK4392] (2) MCLK LRCK/WCK PCM mode (RSTN pin = “H”) MCLK MCLK DSD mode MCLK WCK LRCK (Hi-Z) LRCK AK4392 LRCK MCLK MCLK AVDD pin DVDD pin RSTB pin (1) Internal State Power-down D/A In (Digital) Power-down Normal O peration Normal Operation (3) GD D/A Out (Analog) Digital Circuit P ower-down (2) GD (4) Hi-Z (2) (4) (5) (4) (5) Clock In MCLK, BICK, LRCK Stop MCLK, BICK, LRCK External MUTE Notes: (1) (2) (3) (6) PDN pin (6) “L” (6) 150ns PDN pin “L” (GD) 0 MCLK, BICK, LRCK (4) PDN pin (“↑”) MCLK “0” (5) (MCLK LRCK ) (6) 3~4LRCK (MCLK, BICK, LRCK) (4) Figure 15 Figure 15. MS1045-J-02 2009/04 - 29 - [AK4392] ■ AK4392 ( ) ( ) P/S pin P/S pin “L” 3 I/F pin: CSN, CCLK, CDTI I/F Chip address (2bit, C1/0), Read/Write (1bit, “1” , Write only), Register address (MSB first, 5bit) Control data (MSB first, 8bit) CCLK “↓” “↑” CSN “↑” CCLK 5MHz (max) PDN pin AK4392 Function Parallel Control Mode Serial Control Mode Audio Format Y Y De-emphasis Y Y SMUTE Y Y DSD Mode Y EX DF I/F Y Minimum delay Filter Y Digital Attenuator Y Table 12. Function List1 (Y: Available, -: Not available) PDN pin “L” RSTN bit “0” CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin) R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 16. Control I/F Timing *AK4392 *PDN pin = “L” *CSN “L” CCLK “↑” 15 17 MS1045-J-02 2009/04 - 30 - [AK4392] PCM Attenuation Level 0dB 03H 04H 00H 00H 00H 01H 01H 01H 01H 01H 02H 02H ATT7-0 External Digital Filter I/F Mode Disable EXDF Ex DF I/F mode clock setting 16fs(fs=44.1kHz) ESC Audio Data Interface Modes 24bit DIF2-0 Data Zero Detect Enable Disable DZFE Data Zero Detect Mode Separated DZFM Minimum delay Filter Enable Sharp roll-off filter SD De-emphasis Response OFF DEM1-0 Soft Mute Enable Normal Operation SMUTE DSD/PCM Mode Select PCM mode DP Master Clock Frequency Select at 512fs DCKS DSD mode MONO mode Stereo mode select Stereo 02H MONO Inverting Enable of DZF “H” active 02H DZFB The data selection of L channel and R channel 02H SELLR R channel Table 13. Function List2 (Y: Available, -: Not available) MS1045-J-02 DSD Ex DF I/F Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - - Y - Y Y Y Y Y - Y Y Y Y - 2009/04 - 31 - [AK4392] ■ Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 0 DZFE DP ATT7 ATT7 D6 EXDF DZFM 0 ATT6 ATT6 D5 ECS SD DCKS ATT5 ATT5 D4 0 0 DCKB ATT4 ATT4 D3 DIF2 0 MONO ATT3 ATT3 D2 DIF1 DEM1 DZFB ATT2 ATT2 D1 DIF0 DEM0 SELLR ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0 Note: 05H ∼ 1FH PDN pin “L” RSTN bit “0” PSN pin PDN pin AK4392 ■ Addr Register Name 00H Control 1 Default D7 0 0 D6 EXDF 0 D5 ECS 0 D4 0 0 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1 RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) “0” DIF2-0: Audio Data Interface Modes (Table 7) “010” (Mode2: 24bit ) ECS: Ex DF I/F mode clock setting (Table 8) 0: Disable: Internal Digital Filter mode (default) 1: Enable: External Digital Filter mode EXDF: External Digital Filter I/F Mode (Serial mode only) 0: Disable: Internal Digital Filter mode (default) 1: Enable: External Digital Filter mode MS1045-J-02 2009/04 - 32 - [AK4392] Addr Register Name 01H Control 2 Default D7 DZFE 0 D6 DZFM 0 D5 SD 0 D4 0 0 D3 0 0 D2 DEM1 0 D1 DEM0 1 D0 SMUTE 0 SMUTE: Soft Mute Enable 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM1-0: De-emphasis Response (Table 10) “01” (OFF) SD: Minimum delay Filter Enable 0: Sharp roll-off filter (default) 1: Minimum delay filter DZFM: Data Zero Detect Mode 0: Channel Separated Mode (default) 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. DZFE: Data Zero Detect Enable 0: Disable (default) 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS1045-J-02 2009/04 - 33 - [AK4392] Addr Register Name 02H Control 3 Default D7 DP 0 D6 0 0 D5 DCKS 0 D4 DCKB 0 D3 MONO 0 SELLR: The data selection of L channel and R channel, when MONO mode 0: All channel output R channel data, when MONO mode. (default) 1: All channel output L channel data, when MONO mode. MONO bit “1” “0” R ch “1” D2 DZFB 0 D1 SELLR 0 D0 0 0 D2 ATT2 ATT2 1 D1 ATT1 ATT1 1 D0 ATT0 ATT0 1 L ch DZFB: Inverting Enable of DZF 0: DZF pin goes “H” at Zero Detection (default) 1: DZF pin goes “L” at Zero Detection MONO: MONO mode Stereo mode select 0: Stereo mode (default) 1: MONO mode MONO bit “1” Mono mode DCKB: Polarity of DCLK (DSD Only) 0: DSD data is output from DCLK falling edge. (default) 1: DSD data is output from DCLK rising edge. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs (default) 1: 768fs DP: DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode D/P bit Addr Register Name 03H Lch ATT 04H Rch ATT Default RSTN bit AK4392 D7 ATT7 ATT7 1 D6 ATT6 ATT6 1 D5 ATT5 ATT5 1 D4 ATT4 ATT4 1 D3 ATT3 ATT3 1 ATT7-0: Attenuation Level 256 levels, 0.5dB step Data FFH FEH FDH : : 02H 01H 00H Attenuation 0dB -0.5dB -1.0dB : : -126.5dB -127.0dB MUTE (-∞) 7425 (168ms@fs=44.1kHz) RSTN bit = “0” FFH (0dB) ATT 7424/fs 00H (MUTE) FFH ATT FFH MS1045-J-02 RSTN bit “1” ATT 2009/04 - 34 - [AK4392] Figure 17 Figure 19, Figure 20 Figure 21 (AKD4392) Master clock Analog5.0V Digital 5.0V + 10u 10u + + 34 VCML 35 Lch LPF 1 DVDD Reset & PD 64fs 2 PDN VSS2 32 3 BICK VDDL 31 Audio D ata 4 SDATA 5 LRCK 6 CSN 7 CAD0 8 CCLK 9 CDTI fs MicroC ontroller 0.1u VRE FLL 29 10u + + VREFHL 30 AK4392EQ 0.1u 10u NC 28 VREFLR 27 VRE FHR 26 Top View 0.1u VSS1 24 10u + + V DDR 25 0.1u 10u 21 VCMR 20 NC 19 DINL 18 DINR 17 NC 16 B CK 15 DZFR 14 PSN 13 NC 12 DIF2 22 AOUTRP AOUTRN 23 DZFL + 10u Digital Lch Out AO UTLN 33 10 CAD1 11 Lch Mute AOUTLP NC 36 NC 37 NC 38 NC 39 VSS3 40 AVDD 41 VSS4 43 0.1u 10u + MCLK 42 NC 44 0.1u Rc h LPF R ch Mute R ch Out Analog G + d Electrolytic C apac itor C eramic Capacitor : - Chip Address = “00”. BICK = 64fs, LRCK = fs - AVDD DVDD - VSS1-4 - AOUT / Figure 17. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode) MS1045-J-02 2009/04 - 35 - [AK4392] AOUTLP 34 NC 36 VCML 35 NC 37 NC 38 NC 39 VSS 3 40 AOUTLN 33 1 DVDD 2 PDN VSS2 32 3 BICK/DCLK VDDL 31 4 SDATA/DSDL AK4392EQ VRE FHL 30 VRE FLL 29 NC 28 5 LRCK/DSDR/WCK 6 SMUTE/CSN 7 DFS0/CAD0 8 DEM0/CCLK VRE FHR 26 9 DEM1/CDTI VDDR 25 10 DIF0/CAD1 VSS1 24 VRE FLR 27 22 AOUTRP 21 VCMR 20 NC 19 DINL 18 DINR 17 NC AOUTRN 23 16 BCK 14 PSN 12 DIF2 13 NC 11 DIF1/DZFL 15 ACKS/DZFR Controller AVDD 41 NC 44 System MCLK 42 Analog Ground VS S4 4 3 Digital Ground Figure 18. Ground Layout AK4392 AVDD, VDDL/R AVDD, VDDL/R DVDD AVDD, VDDL/R AVDD, VDDL/R DVDD DVDD DVDD VSS1-4 AK4392 VREFHL/R pin VREFLL/R pin VREFHL/R pin AVDD 0.1µF VREFLL/R pin VSS VCML/R 10µF VSS VCML/R pin VREFHL/R, VREFLL/R pin 0.1µF AK4392 AVDD/2 2.8Vpp (typ, VREFHL/R − AOUTL/R +, AOUTL/R − VAOUT = 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V) 2’s compliment (2 ) 800000H(@24bit) VREFLL/R = 5V) (AOUT+)−(AOUT−) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT 0V ΔΣ Figure 19 VREFHL/R pin VREFLL/R pin ( 1 ) (SCF) LPF Figure 20 3 LPF MS1045-J-02 2009/04 - 36 - [AK4392] AK4392 1.5k AOUT- 1.5k 390 1n +Vop 2.2n 1.5k AOUT+ 1.5k Analog Out 390 1n -Vop Figure 19. External LPF Circuit Example 1 for PCM (fc = 99.2kHz, Q=0.704) Frequency Response Gain 20kHz −0.011dB 40kHz −0.127dB 80kHz −1.571dB Table 14. Frequency Response of External LPF Circuit Example 1 for PCM +15 3.3n + AOUTL- + 10k 330 180 0.1u 7 3 2 + 4 3.9n -15 10u 6 NJM5534D + 10u 0.1u 620 620 3.3n + 100u 3.9n 100 6 Lch 1.0n NJM5534D 10u 6 NJM5534D 1.2k 330 2 - 4 + 3 7 0.1u 7 3 + 2 4 + 10k AOUTL+ 180 +10u 1.0n 1.2k 680 0.1u 560 560 100u 680 + 0.1u 10u + 10u 0.1u Figure 20. External LPF Circuit Example 2 for PCM 1st Stage 2nd Stage Total Cut-off Frequency 182kHz 284kHz Q 0.637 Gain +3.9dB -0.88dB +3.02dB 20kHz -0.025 -0.021 -0.046dB Frequency 40kHz -0.106 -0.085 -0.191dB Response 80kHz -0.517 -0.331 -0.848dB Table 15. Frequency Response of External LPF Circuit Example 2 for PCM MS1045-J-02 2009/04 - 37 - [AK4392] SACD (Scarlet Book) SACD 50kHz −30dB/oct (Figure 21) AK4392 (Table 16) Frequency Gain 20kHz −0.4dB 50kHz −2.8dB 100kHz −15.5dB Table 16. Internal Filter Response at DSD Mode 2.0k 1.8k 4.3k AOUT1.0k 270p 2.8Vpp 2200p +Vop 3300p 2.0k 1.8k 1.0k AOUT+ + 2.8Vpp 4.3k 270p Analog Out 6.34Vpp -Vop Figure 21. External 3rd Order LPF Circuit Example for DSD Frequency Gain 20kHz −0.05dB 50kHz −0.51dB 100kHz −16.8dB DC gain = 1.07dB Table 17. 3rd Order LPF (Figure 21) Response MS1045-J-02 2009/04 - 38 - [AK4392] 44pin LQFP (Unit: mm) 1.60max 12.0 1.40 ±0.05 0.10±0.05 10.0 23 33 1.00 0.80 12.0 22 10.0 34 12 44 1 11 0.37 +0.08 –0.07 0.20 M 0.145±0.055 0°∼7° S 0.6±0.15 0.10 S ■ Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate MS1045-J-02 2009/04 - 39 - [AK4392] AK4392EQ XXXXXXX AKM 1 1) Pin #1 indication 2) AKM Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK4392 5) Audio 4 pro Logo Date (YY/MM/DD) 09/01/09 09/02/25 Revision 00 01 09/04/27 02 Reason Page Contents 37 Figure 19 Table 14 → MS1045-J-02 2009/04 - 40 - [AK4392] • • • • • • MS1045-J-02 2009/04 - 41 -