データシート

[AK4650]
AK4650
16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC
AK4650
16bit
CODEC
(PDA)
ALC(Auto Level Control)
AK4650 AC’97
57pin BGA
2∼3
1.
2.
(CPU) AC-Link
: 16bits
•
•2
•
•
• ALC
• ADC
•
(
)
(
2
)
(
)
(+20dB or 0dB)
IPGA
(+27.5dB ∼ −8dB, 0.5dB Step)
(@MIC-Amp=+20dB, Single-ended input): S/(N+D): 79dB, DR, S/N: 83dB
3.
•
•
•
•
(tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
(0dB ∼ −63dB, 0.5dB Step, Mute)
-
: S/(N+D): 85dB, S/N: 95dB
: +6dB ∼ −15dB, 3dB Step
-
: 40mW@16Ω (HVDD=3.3V)
: S/(N+D): 60dB@10mW, S/N: 90dB
•
•
•
: 300mW@8Ω (HVDD=3.3V, ALC2=OFF)
: S/(N+D): 55dB@110mW, S/N: 90dB
- BTL
- ALC(Auto Level Control)
•
• AUX
-
: +12dB ∼ −34.5dB, 1.5dB Step, Mute
-
: +12dB ∼ −34.5dB, 1.5dB Step, Mute
•
MS0502-J-01
2007/04
-1-
[AK4650]
4.
•2
•
•
•
•
(2.5V)
12Bit ADC
: 24.576MHz, 12MHz, 3.6864MHz
: 48kHz, 44.1kHz, 32kHz, 24kHz, 22.05kHz, 16kHz, 11.025kHz, 8kHz
5.
6.
7.
8.
,
&
9. Ta = −30 ∼ 85°C
10.
: 2.7V ∼ 3.6V (typ. 3.3V)
11.
: 57pin BGA (5mm x 5mm)
MS0502-J-01
I/F : AC-Link I/F
2007/04
-2-
[AK4650]
■
(
)
MICOUT
AIN
MVREF
DVDD1
DVSS1 DVDD2
DVSS2
PMMIC
MPE
MPI
MIC Power
Supply
PR6-0
MIC Power
Supply
ALC1
(IPGA)
INT
HPF
ADC
MIC-AMP
0dB or 20dB
EXT
RESETN
MDT
SYNC
Audio
Interface
0.075 x AVDD
PMMO
BITCLK
ATT
MOUT+
MOUT-
CPU
SDATAIN
Control
Register
ATT
SDATAOUT
PMHPL or PMHPR or PMSPK
ATT
PR6-0
DAC
DATT
SMUTE
PLL1
HVDD
HVSS
VRA
PR5
PMHPL
HPL
HP-AMP
MIX
MIX
PR5
XTO/PLL0
PLL
XTI/MCKI
HDT
PMHPR
HPR
HP-AMP
MIX
MIX
VCOC1
MUTET
PMLIN
PMAUX
VCOC2
PMSPK
SPP
Volume
SPKAMP
MIX
ALC2
Volume
Volume
MIX
SPN
PMBP
MDT/RIN
VCOM
BEEP
MIN
MOUT2
MPE/LIN
AUXIN+
AUXIN-
AVSS AVDD
Figure 1.
(
MS0502-J-01
)
2007/04
-3-
[AK4650]
■
(
)
SYNC
XP
BITCLK
YP
SDATAIN
Control
Logic
XN
SDATAOUT
YN
IN1
Internal
VREF(2.5V)
IN2
VREF
VBAT
VREF+
VREF-
AIN+
R1
AIN-
12bit
ADC
(SAR type)
R2
INTN
Pen
Interrupt
ADEXE
Figure 2.
TSVDD
TSVSS
(TSC )
MS0502-J-01
2007/04
-4-
[AK4650]
■
−30 ∼ +85°C
AK4650
AK4650VG
AKD4650
57pin BGA (0.5mm pitch)
■
9
8
7
6
AK4650
5
Top View
4
3
2
1
A
B
C
D
E
F
G
H
J
9
NC
BEEP/IN2
AVDD
VCOM
AUXIN+
MPI
EXT/MIC+
MPE/LIN
NC
8
VCOC1
VCOC2
AVSS
MVREF
AUXIN−
INT/MIC−
MDT/RIN
AIN
MICOUT
7
XP
TSVDD
MOUT−
MOUT+
6
YP
XN
HPL
HPR
5
YN
TSVSS
HVSS
HVDD
4
IN1
VBAT
SPP
SPN
3
VREF
TEST2
NC
MUTET
HDT
2
ADEXE
INTN
XTO/PLL0
SDATA
OUT
DVSS2
SDATAIN
SYNC
MOUT2
MIN
1
NC
DVDD1
XTI/MCKI
DVSS1
BITCLK
DVDD2
RESETN
PLL1
TEST1
A
B
C
D
E
F
G
H
J
Top View
MS0502-J-01
2007/04
-5-
[AK4650]
No.
I/O
A1
NC
-
B1
DVDD1
XTI
MCKI
XTO
I
I
O
PLL0
I
D1
D2
E1
E2
F2
F1
G2
G1
DVSS1
SDATAOUT
BITCLK
DVSS2
SDATAIN
DVDD2
SYNC
RESETN
I
O
O
I
I
H1
PLL1
I
J1
TEST1
-
J2
H2
MIN
MOUT2
I
O
H3
MUTET
O
J3
H4
J4
H5
J5
J6
H6
H7
J7
H8
HDT
SPP
SPN
HVSS
HVDD
HPR
HPL
MOUT−
MOUT+
AIN
I
O
O
O
O
O
O
I
J9
NC
-
C1
C2
No Connect
1
(PLL1 pin = “L”)
PLL
0
(PLL1 pin = “H”)
“L”: 3.6864MHz, “H”: 12MHz
1
256bit AC’97
, 12.288MHz(256fs)
2
256bit AC’97
2
AC’97
, 48kHz(1fs)
AC’97
PLL
1
“L”: 24.576MHz (PLL0 pin = “L”)
“H”: 3.6864MHz (PLL0 pin = “L”) or 12MHz (PLL0 pin = “H”)
PLL1 pin = “H”
1
ALC2
HVSS
(
100kΩ)
&
&
Rch
Lch
ALC1
No Connect
MS0502-J-01
2007/04
-6-
[AK4650]
No.
J8
I/O
O
I
I
O
I
I
I
I
I
O
I
I
O
F9
E8
E9
D8
MICOUT
MDT
RIN
MPE
LIN
EXT
MIC+
INT
MIC−
MPI
AUXIN−
AUXIN+
MVREF
D9
VCOM
O
C8
C9
AVSS
AVDD
BEEP
IN2
I
I
A9
NC
-
A8
VCOC1
O
PLL
DVSS
(10kΩ)
B8
VCOC2
O
PLL
DVSS
(10kΩ)
G8
H9
G9
F8
B9
Note:
(
Rch
Lch
500kΩ) (RNMD bit = “0”)
(RNMD bit = “1”)
(LNMP bit = “0”)
(LNMP bit = “1”)
(
: MDIF bit = “0”)
(
: MDIF bit = “1”)
(
: MDIF bit = “0”)
(
: MDIF bit = “1”)
AUX
AUX
, 0.45 x AVDD
ADC
DAC
(INBP bit = “0”)
2
(INBP bit = “1”)
12bit ADC
No Connect
1
(4.7nF)
2
(4.7nF)
(XTI/MCKI, PLL0, SDATAOUT, SYNC, RESETN, PLL1,
ADEXE)
MS0502-J-01
2007/04
-7-
[AK4650]
No.
B7
TSVDD
I/O
X+
„X
„Y
A7
XP
I/O
:
: ADC
„
Z1
„
„
„
: OPEN
X+
ADC
:
: OPEN
50kΩ
(PDN pin = “L”
50kΩ
)
Y+
„Y
„X
A6
YP
I/O
:
: ADC
„
„
„
„
:
: OPEN
Y+
Y+
: OPEN
: OPEN
X−
B6
XN
I/O
„X
„Y
„
„
„
„
:
: OPEN
X−
:
: OPEN
X−
: OPEN
: OPEN
Y−
A5
YN
I/O
„Y
„X
„
: Z2
„
„
„
B5
B4
A4
TSVSS
VBAT
IN1
TEST2
-
A3
VREF
I/O
B2
INTN
O
A2
ADEXE
I
C3
NC
-
Y−
: OPEN
: GND
: OPEN
I
I
B3
:
: OPEN
ADC
1
2
PMVREF bit = “1”
2.5V
100kΩ
ADC
No Connect
MS0502-J-01
2007/04
-8-
[AK4650]
■
Analog
Digital
MIN, MOUT2, MUTET, HDT, SPP, SPN, HPR, HPL,
MOUT−, MOUT+, AIN, MICOUT, MDT/RIN,
MPE/LIN, EXT/MIC+, INT/MIC−, MPI, AUXIN−,
AUXIN+, BEEP/IN2, XP, YP, XN, YN, VBAT, IN1,
INTN
XTO
MS0502-J-01
2007/04
-9-
[AK4650]
(AVSS, DVSS, HVSS, TSVSS=0V; Note 1, Note 2)
Parameter
Power Supplies:
Analog
Digital (Note 3)
Headphone-Amp / Speaker-Amp
Touch Screen Controller
|AVSS – DVSS| (Note 4)
|AVSS – HVSS| (Note 4)
|AVSS – TSVSS| (Note 4)
Input Current, Any Pin Except Supplies
Analog Input Voltage
(Note 5)
(Note 6)
Digital Input Voltage
(Note 7)
Touch Screen Controller Input Voltage
(Note 8)
Touch Screen Drive Current
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
HVDD
TSVDD
ΔGND1
ΔGND2
ΔGND3
IIN
VINA1
VINA2
VIND
VINTS
IOUTDRV
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
max
6.0
6.0
6.0
6.0
0.3
0.3
0.3
±10
AVDD+0.3
HVDD+0.3
DVDD+0.3
TSVDD+0.3
50
85
150
Units
V
V
V
V
V
V
V
mA
V
V
V
V
mA
°C
°C
Note 1.
Note 2. DVSS DVSS1 DVSS2
Note 3. DVDD DVDD1 DVDD2
Note 4. AVSS DVSS, HVSS, TSVSS
Note 5. MIN, AIN, MDT/RIN, MPE/LIN, EXT/MIC+, INT/MIC−, AUXIN−, AUXIN+, BEEP/IN2 pins
Note 6. HDT pin
Note 7. XTI/MCKI, XTO/PLL0, SDATAOUT, SYNC, RESETN, PLL1, ADEXE pins
Note 8. XP, YP, XN, YN, IN1, IOUT, VREF pins
:
(AVSS, DVSS, HVSS, TSVSS=0V; Note 1, Note 2)
Parameter
Symbol
Power Supplies: Analog
AVDD
(Note 9)
Digital (Note 3)
DVDD
HP / SPK-Amp
HVDD
Touch Screen Controller
TSVDD
Note 1.
Note 2. DVSS DVSS1 DVSS2
Note 3. DVDD DVDD1 DVDD2
Note 9. AVDD, DVDD, HVDD, TSVDD
DVDD, HVDD, TSVDD
OFF
DVDD2
0.3V
ON
min
2.7
2.7
2.7
2.7
PDN pin = “L”
typ
3.3
3.3
3.3
3.3
max
3.6
AVDD
3.6
3.6
Units
V
V
V
V
AVDD,
(Note 28
)
DVDD1
:
MS0502-J-01
2007/04
- 10 -
[AK4650]
(
)
(Ta=25°C; AVDD, DVDD, HVDD, TSVDD=3.3V; AVSS=DVSS=HVSS=TSVSS=0V; fs=48kHz; Signal
Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier: INT, EXT pins, MDIF bit = “0” (Single-ended input)
Input Resistance
20
30
40
kΩ
Gain
MGAIN bit = “0”
0
dB
MGAIN bit = “1”
+20
dB
MIC Amplifier: MIC+, MIC− pins, MDIF bit = “1” (Full-differential input), MGAIN bit = “1” (+20dB)
Maximum Input Voltage (Note 10)
0.099
Vpp
MIC Power Supply: MPI, MPE pins
Output Voltage
1.98
2.2
2.42
V
Load Resistance
2
kΩ
Load Capacitance
30
pF
MIC Detection: MDT pin
Comparator Voltage Level
0.15
0.20
0.23
V
Internal pull down Resistance
250
500
750
kΩ
Input PGA Characteristics: AIN pin
Input Resistance (Note 11)
5
10
15
kΩ
Step Size
0.1
0.5
0.9
dB
Gain Control Range (ALC1 bit = “0”)
max: IPGA6-0 bits = “3FH”
+27.5
dB
min: IPGA6-0 bits = “00H”
dB
−8
ADC Analog Input Characteristics: MIC Gain=+20dB, IPGA=0dB, ALC1=OFF, MIC (Single) → IPGA → ADC
Resolution
16
Bits
Input Voltage (Note 12)
0.168
0.198
0.228
Vpp
S/(N+D)
71
79
dB
(−1dBFS)
D-Range
75
83
dB
(−60dBFS, A-weighted)
S/N
(A-weighted)
75
83
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: RL=20kΩ, DAC → MOUT+/MOUT− pins, MOGN2-0 bits = +6dB
Output Voltage (Note 13)
3.56
3.96
4.36
Vpp
S/(N+D)
75
85
dB
(−3dBFS)
S/N
(A-weighted)
85
95
dB
Load Resistance
20
kΩ
Load Capacitance
30
pF
Step Size
2
3
4
dB
Gain Control Range
max: MOGN2-0 bits = “111”
+6
dB
min: MOGN2-0 bits = “000”
dB
−15
Note 10. MIC+ pin, MIC− pin
AVDD
Vin = 0.03 x AVDD(typ).
| (MIC+) − (MIC−) | ≤ 0.06 x AVDD(typ).
Note 11. IPGA
ALC1
typ. 8kΩ ∼ 11kΩ
Note 12.
AVDD
Vin = 0.06 x AVDD(typ).
Note 13.
AVDD
Full-differential
Vout = 1.2 x AVDD(typ)@MOGN2-0 bits =
“111”
Single-end
Vout = 0.6 x AVDD(typ)@MOGN2-0 bits = “111”
MS0502-J-01
2007/04
- 11 -
[AK4650]
Parameter
min
typ
max
Units
Headphone-Amp Characteristics: RL=16Ω, DAC → HPL/HPR pins, DATT=0dB
Output Voltage (Note 14)
0dBFS Input
0.82
Vrms
0.32
0.41
0.50
Vrms
−6dBFS Input
S/(N+D)
0dBFS Input
35
dB
50
60
dB
−6dBFS Input
S/N
(A-weighted)
80
90
dB
60
85
dB
Interchannel Isolation (−6dBFS Input)
0.1
dB
Interchannel Gain Mismatch (−6dBFS Input)
Load Resistance
16
Ω
Load Capacitance (Note 15)
300
pF
Headphone Detection: HDT pin
Comparator Voltage Level (Note 16)
0.99
2.31
V
Internal pull up Resistance
50
100
150
kΩ
Speaker-Amp Characteristics: RL=8Ω, BTL, DAC → MOUT2 pin → MIN pin → SPP/SPN pins, ALC2=OFF
Output Voltage (Note 17)
1.55
Vrms
−2.5dBFS Input
0.75
0.94
1.13
Vrms
−7.5dBFS Input
S/(N+D)
20
dB
−2.5dBFS Input
40
55
dB
−7.5dBFS Input
S/N
(A-weighted)
80
90
dB
Load Resistance
8
Ω
Load Capacitance (Note 15)
30
pF
Mono Output: DAC → MIX → MOUT2 pin
Output Voltage (Note 18)
1.98
Vpp
Load Resistance (Note 19)
30
kΩ
Load Capacitance (Note 15, Note 19)
20
pF
Mono Input: MIN pin
Maximum Input Voltage (Note 20)
1.98
Vpp
Input Resistance (Note 21)
12
24
36
kΩ
BEEP Input: BEEP pin, External input resistance = 20kΩ
Maximum Input Voltage (Note 22)
1.98
Vpp
Feedback Resistance
20
kΩ
Output Voltage (0.8Vpp input)
0.045
0.09
0.135
Vpp
BEEP pin → HPL/HPR pins
1.26
2.53
3.80
Vpp
BEEP pin → SPP/SPN pins, ALC2 bit = “0”
Note 14.
AVDD
Vout = 0.12 x AVDD Vrms(typ)@−6dBFS.
Note 15.
Note 16.
HVDD
Vth = 0.3 x HVDD(min), 0.7 x HVDD(max).
Note 17.
AVDD
Full-differential
Vout = 0.28 x AVDD Vrms(typ)@−6dBFS.
Note 18.
AVDD
Vout = 0.6 x AVDD(typ).
Note 19. MIN
Note 20.
AVDD
Vin = 0.6 x AVDD(typ).
Note 21. Mono Input
ALC2
typ. 22kΩ ∼ 26kΩ
Note 22.
AVDD
(Ri)
(Rf)
Vin =
0.6 x AVDD x Ri / Rf (typ).
MS0502-J-01
2007/04
- 12 -
[AK4650]
Parameter
Line Input: LIN, RIN pins
Maximum Input Voltage (Note 23)
Input Resistance
Step Size
Gain Control Range
max: GL4-0 bits = “00H”
min: GL4-0 bits = “1FH”
AUX Input: AUXIN+, AUXIN− pins
Maximum Input Voltage (Note 24)
Input Resistance
AUXIN+ pin
AUXIN− pin
Step Size
Gain Control Range
max: GN4-0 bits = “00H”
min: GN4-0 bits = “1FH”
Power Supplies:
Power Up (RESETN pin = “H”)
All Circuit Power-up:
AVDD+DVDD (Note 25)
HVDD: HP-AMP Normal Operation
No Output (Note 26)
HVDD: SPK-AMP Normal Operation
No Output (Note 27)
TSVDD
Internal VREF=OFF
Internal VREF=ON
Power Down (RESETN pin = “L”) (Note 28)
AVDD+DVDD+HVDD+TSVDD
min
typ
max
Units
25
0.5
1.98
40
1.5
55
2.5
Vpp
kΩ
dB
-
+12
−34.5
-
dB
dB
-
1.98
-
Vpp
25
50
0.5
40
80
1.5
55
110
2.5
kΩ
kΩ
dB
-
+12
−34.5
-
dB
dB
-
15
23
mA
-
2.5
5
mA
-
7
21
mA
-
0.16
0.23
0.4
0.4
mA
mA
-
1
100
μA
Note 23.
AVDD
Vin = 0.6 x AVDD(typ).
Note 24.
AVDD
Vin = (AUXIN+) − (AUXIN−) = 0.6 x AVDD(typ).
Note 25. PR0-6 bits = all “0”, PMMIC=PMMO=PMSPK=PMHPL=PMHPR=PMBPM=PMAUX=PMLIN= “1”.
AVDD=10mA (typ.), DVDD=5mA (typ.).
Note 26. PR0-6 bits = all “0”, PMMIC=PMMO=PMHPL=PMHPR=PMBPM=PMAUX=PMLIN= “1”, PMSPK= “0”.
Note 27. PR0-6 bits = all “0”, PMMIC=PMMO=PMSPK=PMBPM=PMAUX=PMLIN= “1”, PMHPL=PMHPR= “0”.
Note 28.
DVDD
DVSS
AVDD, DVDD, HVDD,
TSVDD
0.3V
MS0502-J-01
2007/04
- 13 -
[AK4650]
(
)
(Ta=25°C; AVDD, DVDD, HVDD, TSVDD=3.3V; AVSS=DVSS=HVSS=TSVSS=0V; External Vref=2.5V, unless
otherwise specified) fs=96kHz
Parameter
min
typ
max
Units
ADC for Touch Screen
Resolution
12
Bits
No Missing Codes
10
12
Bits
Integral Linearity Error
LSB
±5
DNL
LSB
±2
Analog Input Voltage Range
0
VREF
V
Offset Error
LSB
±6
Gain Error
LSB
±4
Touch Panel Driver
5
X+, Y+, RL=300Ω
Ω
5
X−, Y−, RL=300Ω
Ω
PSRR (10KHz 100mVpp)
70
dB
Reference Output
Internal Reference
2.425
2.50
2.575
V
Drift
30
ppm/°C
Load Capacitance
0.1
μF
Reference Input
Input Voltage Range
TSVDD
V
Battery Monitor
Input Voltage Range
5.0
V
Input Impedance (Battery Measure Mode)
5
10
kΩ
Accuracy (Note 29)
External VREF
%
±2
Internal VREF
%
±4
Note 29. 5V
VBAT pin
1.25V
MS0502-J-01
2007/04
- 14 -
[AK4650]
(Ta=25°C; AVDD, HVDD, DVDD, TSVDD=2.7 ∼ 3.6V; fs=48kHz; DEM=OFF)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband (Note 30)
PB
0
±0.1dB
−1.0dB
21.8
−3.0dB
23.0
Stopband
SB
29.4
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay (Note 31)
GD
17.0
Group Delay Distortion
0
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 30) −3.0dB
FR
1.0
6.5
−0.1dB
DAC Digital Filter:
Passband (Note 30)
PB
0
±0.1dB
24.0
−6.0dB
Stopband
SB
25.2
Passband Ripple
PR
Stopband Attenuation
SA
59
Group Delay (Note 31)
GD
16.8
DAC Digital Filter + SCF:
FR
Frequency Response: 0 ∼ 20.0kHz
±1.0
BOOST Filter: (Note 32)
Frequency Response
MIN
20Hz
FR
5.80
100Hz
3.17
1kHz
0.03
MID
FR
20Hz
10.85
100Hz
7.23
1kHz
0.18
MAX 20Hz
FR
16.14
100Hz
11.05
1kHz
0.47
Note 30.
Note 31.
fs (
ADC PB=21.8kHz(@−1.0dB)
max
Units
18.9
±0.1
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
-
Hz
Hz
21.3
±0.01
-
kHz
kHz
kHz
dB
dB
1/fs
-
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
)
0.454 × fs
ADC
1kHz
16bit
DAC
16 bit
Note 32.
MS0502-J-01
2007/04
- 15 -
[AK4650]
DC
(Ta=25°C; AVDD, HVDD, DVDD, TSVDD=2.7 ∼ 3.6V)
Parameter
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Input Voltage at AC Coupling (Note 33)
VAC
High-Level Output Voltage
VOH
(Iout=−400μA)
Low-Level Output Voltage
VOL
(Iout=400μA)
Input Leakage Current
Iin
Tri-state Leakage Current (TSC block)
All pins except for XP, YP, XN, YN pins
IOLK
XP, YP, XN, YN pins
IOLK
VOLP
INTN “L” level output voltage (100kΩ Pull-Up)
Note 33.
min
70%DVDD
50%DVDD
DVDD−0.4
-
typ
-
max
30%DVDD
0.4
±10
Units
V
V
V
V
V
μA
−10
−50
-
-
+10
+50
0.8
μA
μA
V
MCKI pin
MS0502-J-01
2007/04
- 16 -
[AK4650]
(Ta=25°C; AVDD, HVDD, DVDD, TSVDD=2.7 ∼ 3.6V; CL=25pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
PLL1 pin = “L”, PLL0 pin = “L”
Fmclk
PLL1 pin = “H”, PLL0 pin = “L”
Fmclk
PLL1 pin = “H”, PLL0 pin = “H”
Fmclk
Duty Cycle
Dmclk
40
AC link Interface Timing
BITCLK frequency
Fbclk
BITCLK clock Period (Tbclk=1/Fbclk)
Tbclk
BIT_BLK low pulse width
Tclk_low
36
BIT_BLK low pulse width
Tclk_high
36
BITCLK rise time
Trise_clk
BITCLK fall time
Tfall_clk
SYNC frequency
Fsync
SYNC low pulse width
Tsync_low
SYNC high pulse width
SYNC rise time
SYNC fall time
Setup time (SYNC, SDATAOUT)
Hold time (SYNC, SDATAOUT)
SDATAIN delay time from BITCLK rising
edge
SDATAIN rise time
SDATAIN fall time
SDATAOUT rise time
SDATAOUT fall time
Cold Reset (SDATAOUT = “L”, SYNC = “L”)
RESETN active low pulse width
RESETN inactive to BITCLK delay
PLL1 pin = “L” (External clock)
PLL1 pin = “L” (X’tal oscillator)
PLL1 pin = “H”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin = “H”
Warm Reset Timing
SYNC active high pulse width
SYNC inactive to BITCLK delay
PLL1 pin = “L” (External clock)
PLL1 pin = “L” (X’tal oscillator)
PLL1 pin = “H”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin = “H”
AC-link Low Power Mode Timing
End of Slot 2 to BITCLK, SDATAIN Low
Activate Test Mode Timing
Setup to trailing edge of RESETN
Hold from RESETN rising edge
Rising edge of RESETN to Hi-Z
Falling edge of RESETN to “L”
typ
max
Units
24.576
3.6864
12
-
60
MHz
MHz
MHz
%
45
45
6
6
-
6
6
15
MHz
ns
ns
ns
ns
ns
kHz
μs
(Tbclk)
μs
(Tbclk)
ns
ns
ns
ns
ns
Tsync_high
-
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
14
25
-
12.288
81.38
40.7
40.7
48
19.5
(240 cycle)
1.3
(16 cycle)
-
Trise_din
Tfall_din
Trise_dout
Tfall_dout
-
-
6
6
6
6
ns
ns
ns
ns
Trst_low
1.0
-
-
μs
Trst2clk
Trst2clk
Trst2clk
Trst2clk
-
42
0.5
9.5
3.2
-
μs
ms
ms
ms
Tsync_high
1.0
1.3
(16 cycle)
-
μs
(Tbclk)
Trst2clk
Tsync2clk
Tsync2clk
Tsync2clk
-
42
0.5
9.5
3.2
-
μs
ms
ms
ms
Ts2_pdwn
-
-
1.0
μs
Tsetup2rst
Thold2rst
Toff
Tlow
15.0
100
-
-
50
50
ns
ns
ns
MS0502-J-01
-
ns
2007/04
- 17 -
[AK4650]
■
1/Fmclk
VIH
MCKI
VIL
Tmclkh
Tmclkl
Dmclk = Tmclkh x Fmclk x 100
= Tmclkl x Fmclk x 100
Figure 3. Master Clock Timing
Tbclk = 1/Fbclk
Tclk_high
Tclk_low
BITCLK
50%DVDD
Figure 4. BITCLK Timing
Tsync_high
Tsync_low
SYNC
VIH
VIL
1/Fsync
Figure 5. SYNC Timing
Tdelay
Tsetup
VIH
BITCLK
VIL
VIH
SDATAIN
VIL
Thold
VIH
SDATAOUT,
SYNC
VIL
Figure 6. Setup and Hold Timing
Trise_clk
Tfall_clk
90%DVDD
10%DVDD
BITCLK
Trise_sync
SYNC
Trise_din
90%DVDD
10%DVDD
SDATAIN
Tfall_sync
Trise_dout
90%DVDD
10%DVDD
Tfall_din
Tfall_dout
SDATAOUT
90%DVDD
10%DVDD
Figure 7. Signal Rise and Fall Times
(25pF external load; between 10%DVDD and 90%DVDD)
MS0502-J-01
2007/04
- 18 -
[AK4650]
Trst_low
Trst2clk
RESETN
VIL
SDATAOUT= “L”
SYNC= “L”
BITCLK
Figure 8. Cold Reset Timing
Tsync_high
Tsync2clk
SYNC
VIH
BITCLK
Figure 9. Warm Reset Timing
Slot
Slot
Ts2_pdwn
BITCLK
SDATAOUT
Write to 0x26
Data PR4=1
Don’t care
SDATAIN
Figure 10. AC-link Low Power Mode Timing
RESETN
VIH
VIL
SDATAOUT
VIH
Tsetup2rst Thold2rst
SDATAIN
BITCLK
HI-Z
VIL
Toff
Tlow
Figure 11. Activate Test Mode Timing
MS0502-J-01
2007/04
- 19 -
[AK4650]
■
(MCLK)
3
(1) XTI pin XTO pin
X’tal
(2) XTI pin
CMOS
(3) 50%DVDD
AC
X’tal
(XTI/XTO
Master Clock
X’tal Oscillator
(PLL1 pin = “L”)
External Clock Direct Input
(PLL1 pin = “L”)
)
(Figure 12)
Status
(Figure 12)
X’tal
X’tal
(Figure 13)
MCKI pin
MCKI pin
MCKI pin
MCKI pin
External Clock Direct Input (Figure 14)
MCKI pin
(PLL1 pin = “H”)
MCKI pin
MCKI pin
MCKI pin
AC Coupling Input
(Figure 15)
MCKI pin
(PLL1 pin = “L”)
MCKI pin
Table 1. PR5, MCKPD bit
(1) X’tal
DVSS
PR5 bit
0
1
0
1
1
1
0
0
0
0
0
1
ON
OFF
“L”
“H”
Hi-Z
“L”
“H”
Hi-Z
MCKPD bit
0
1
0
0/1
0
1
0
0/1
0
1
0
1
(PLL1 pin = “L”)
XTI
MCKPD = "0"
C
PR5 = "0"
25kΩ (typ)
C
PLL1 = "L"
XTO
PLL1 = "L"
AK4650
Figure 12. X’tal
(typ. 10 ∼ 30pF)
Note 34.
MS0502-J-01
2007/04
- 20 -
[AK4650]
(2)
(2-1)
PLL1 pin = “L”
MCKI
External
Clock
MCKPD = "0"
PR5 = "0"
25kΩ (typ)
PLL1 = "L"
PLL1 = "L"
XTO
AK4650
Figure 13.
Note 35. DVDD
(2-2)
(PLL1 pin = “L”,
: CMOS
)
PLL1 pin = “H”
MCKI
External
Clock
MCKPD = "0"
PR5 = "0"
25kΩ (typ)
PLL1 = "H"
PLL1 = "H"
PLL0
AK4650
Figure 14.
Note 36. DVDD
(3) AC
(PLL1 pin = “H”,
: CMOS
)
(PLL1 pin = “L”)
C
MCKI
External
Clock
MCKPD = "0"
PR5 = "0"
25kΩ (typ)
PLL1 = "L"
PLL1 = "L"
XTO
AK4650
Figure 15.
Note 37. DVDD
(
MS0502-J-01
: ≥ 50%DVDD)
2007/04
- 21 -
[AK4650]
■
PLL PLL1-0 pin (Table 2)
PLL
PR5 bit = “0”
PLL
PLL
AC-Link
(
ADC
MHz)
DAC
X’tal
0.5ms(typ)
(VRA bit = “0” → “1”)
9ms
(PR4 = PR5 bits = “0”) MCKI pin
BITCLK “L”
(Table 3)
(PR0 = PR1 = PR3 = PR4 = PR5 bits = “0”) MCLK
PR0-6 bit
PLL1 pin
L
H
MCKI pin
BITCLK pin
SYNC pin
X’tal
PLL0 pin
L
H
L
H
Table 2. MCKI
Power up
PLL1-0 pin
(Table 2)
12.288MHz Output
SYNC
ADC
DAC
MCKI
24.576MHz
N/A
3.6864MHz
12MHz
Power down
Table 1
“L”
Input
PLL
“L” or “H”
PLL Unlock
PLL1-0 pin
(Table 2)
“L”
Input
or
“L” or “H”
Table 3.
MS0502-J-01
2007/04
- 22 -
[AK4650]
■
2CH
32H
D15(MSB) ∼ D0
(2AH)
DAC
0 ∼ 65535
16bit
ADC
(
: Hz)
Extended Audio Status and Control Register
VRA bit = “1”
Sample Rate (kHz)
Data in D15 – D0
8.0
1F40H
11.025
2B11H
16.0
3E80H
22.05
5622H
24.0
5DC0H
32.0
7D00H
44.1
AC44H
48.0
BB80H
Table 4. Audio Sample Rate
AK4650
Table 4
D15-12
D15-12 = 5H
24kHz
4bit
D11
Table 4
D11= “0”
22.05kHz D11= “1”
(Table 5)
D15 – D12
0H,1H
2H
3H
4H
D11
Sample Rate (kHz)
x
8.0
x
11.025
x
16.0
x
22.05
0
22.05
5H
1
24.0
6H
x
24.0
7H,8H
x
32.0
9H,AH
x
44.1
BH-FH
x
48.0
Table 5. Audio Sample Rate (x: Don’t care)
VRA bit = “0”
2CH
32H
2CH
32H
“BB80H”
“BB80H”
VRA bit = “0”
MS0502-J-01
2007/04
- 23 -
[AK4650]
■
26H
ADC
DAC
VCM
XTL
PLL
AC-Link
HP
SPK
MIC
Line In
AUXIN
Mono Out
BEEP
TSC
PR0 = “1”
PD
PU
PU
PU
VRA
PU
PMHPL/R
PMSPK
PMMIC
PMLIN
PMAUX
PMMO
PMBPM
PM12AD
PR1 = “1”
PU
PD
PU
PU
VRA
PU
PMHPL/R
PMSPK
PMMIC
PMLIN
PMAUX
PMMO
PMBPM
PM12AD
60H
PR2 = “1”
PR3 = “1”
PU
PD
PU
PD
PU
PD
PU
PU
VRA
PD
PU
PU(Note 38)
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PM12AD
PD
Table 6. Power Management
PR4 = “1”
PD
PD
PU
PU
VRA
PD
PMHPL/R
PMSPK
PMMIC
PMLIN
PMAUX
PMMO
PMBPM
PM12AD
PR5 = “1”
PD
PD
PU
PD
PD
PD
PMHPL/R
PMSPK
PMMIC
PMLIN
PMAUX
PMMO
PMBPM
PM12AD
PR6 = “1”
PU
PU
PU
PU
VRA
PU
PD
PMSPK
PMMIC
PMLIN
PMAUX
PMMO
PMBPM
PM12AD
PD: Power Down
PU: Power Up
PM*: PM bit
VRA
VRA bit = “1”: PLL Power Up
VRA bit = “0”: PLL Power Down
Note 38. PLL1 pin = “H”(MCKI=3.6864MHz or 12MHz)
■
PR3 bit = “1”
AC-Link
HPF
ADC DC
HPF
HPF
1.0Hz@fs=48kHz
(fs)
MS0502-J-01
2007/04
- 24 -
[AK4650]
■ MIC
ATTM bit
AK4650
MICM bit
MOUT+/−
ATT
INT pin
ALC1 bit
IPGA5-0 bits
MDIF bit MGAIN bit
MSEL bit
+20dB/0dB IPGA with ALC
ATTS2-0 bits MICL bit
ATT
HP, SP
MICAD bit
ADC
EXT pin
MICOUT pin
AIN pin
Figure 16.
AK4650
(1) 2
(2) +20dB
(3) ALC
(4)
(5)
: MDIF, MSEL bit
(Table 9)
: MGAIN bit
ON/OFF
(Table 10)
IPGA : IPGA5-0 bit
(Table 14)
: ATTS2-0 bit
(Table 7)
:
4dB
ATTM bit
(Table 8)
ATTS2-0
Attenuation
STEP
0H
−6dB
1H
−9dB
Default
2H
−12dB
3H
−15dB
3dB
4H
−18dB
5H
−21dB
6H
−24dB
7H
−27dB
Table 7. Attenuator Table (IPGA → Stereo Mixer)
ATTM
Attenuation
0
0dB
Default
1
−4dB
Table 8. Attenuator Table (IPGA → Mono Mixer)
MS0502-J-01
2007/04
- 25 -
[AK4650]
■
AK4650
(Figure 17)
(Figure 18)
MDIF bit = “1”
MDIF bit
0
1
Table 9.
MSEL bit
INT, EXT pin
MSEL bit
0
1
x
/
MIC−, MIC+ pin
Selector
INT
Default
EXT
Differential
(x: Don’t care)
AK4650
MPE pin
MPI pin
INT pin
MIC-Amp
EXT pin
MDT pin
DTMIC bit
500k
Figure 17.
0.2V(typ)
(MDIF bit = “0”:
)
AK4650
MPI pin
MIC-Amp
MIC− pin
MIC+ pin
Figure 18.
Note 39.
(MDIF bit = “1”:
)
MGAIN bit = “1”
| (MIC+) − (MIC−) | = 0.198Vpp(typ)@AVDD=3.3V
MS0502-J-01
2007/04
- 26 -
[AK4650]
■
AK4650
MGAIN bit
0dB
+20dB
typ. 30kΩ
MGAIN bit
0
1
Table 10.
Input Gain
0dB
+20dB
Default
■
MPI, MPE pin
MPWRI bit
LNMP bit = “1”
2.2V(typ)
MPWRE bit
MPI pin
MPE pin LIN pin
min. 2kΩ
MPE pin
PMMIC bit
0
MPWRI bit
x
0
1
1
Table 11.
MPI pin
Hi-Z
Default
Hi-Z
Output
(x: Don’t care)
PMMIC bit
0
MPE pin
Hi-Z
Default
Hi-Z
Output
(x: Don’t care)
MPWRE bit
X
0
1
1
Table 12.
■
AK4650
(1) MPWRE bit = “1”.
(2) MPE pin
(3) DTMIC bit
(Table 13
Input Level of MDT
> 0.247V
< 0.165V
RNMD bit = “1”
MDT pin
DTMIC bit
1
0
Table 13.
)
External microphone
Connect
Disconnect
RIN pin
MS0502-J-01
2007/04
- 27 -
[AK4650]
■
AK4650
ALC1 bit = “0”
(1)
(2)
ALC1
ZTM1-0, LMTH
ALC1
(3) IPGA
IPGA5-0 bit
MICMT
0
1
IPGA5-0
GAIN (dB)
STEP
3FH
+27.5
3EH
+27.0
0.5dB
:
:
09H
+0.5
08H
+0.0
07H
−1.0
06H
−2.0
1.0dB
:
:
01H
−7.0
00H
−8.0
x
MUTE
Table 14. IPGA Volume (x: Don’t care)
MS0502-J-01
Default
2007/04
- 28 -
[AK4650]
■ MIC – ALC
ALC1 bit = “1”
ALC1
ALC
(1) ALC1
ALC1
ALC1
IPGA
ATT
ZELMN bit = “1”
ALC1
(LMAT1-0 bit: Table 16)
(LMTH bit: Table 15)
IPGA
LTM1-0 bit
(Table 17)
IPGA
ALC1 bit “0”
LMTH
IPGA
LMTH
ZELMN bit = “0”
IPGA
LMTH
0
1
ALC1
ZTM1-0 bit
ALC1
ADC Input ≥ −6.0dBFS
ADC Input ≥ −4.0dBFS
Table 15. ALC1
0
0
1
1
Table 17.
ALC1
−6.0dBFS > ADC Input ≥ −8.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
/
LMAT1
LMAT0
ATT STEP
0
0
0.5 B
0
1
1.0dB
1
0
1.5dB
1
1
2.0dB
Table 16. ALC1
ATT
0dB
LMAT1-0 bits
Note: IPGA
LTM1
(Table 18)
LTM0
0
1
0
1
0.5/fs
1/fs
2/fs
4/fs
ZTM1
ZTM0
0
0
1
1
0
1
0
1
128/fs
256/fs
512/fs
1024/fs
Table 18. ALC1
ALC1
8kHz
16kHz
63μs
31μs
125μs
63μs
250μs
125μs
500μs
250μs
(ZELMN bit = “1”) ALC1
8kHz
16ms
32ms
64ms
128ms
MS0502-J-01
16kHz
8ms
16ms
32ms
64ms
Default
Default
1 step
44.1kHz
11μs
23μs
45μs
91μs
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
Default
2007/04
- 29 -
[AK4650]
(2) ALC1
ALC1
WTM1-0 bit
ALC1
(Table 18)
ALC1
ALC1
ALC1
IPGA
ALC1
(
(
ALC1
(Table 19)
IPGA
(LMTH: Table 15)
ALC1
(REF5-0 bit: Table 21)
ZTM1-0 bit
RGAIN bit
(Table 20)
IPGA
WTM1-0 bit
WTM1-0 bit
WTM1-0 bit
ALC1
(LMTH)
) ≤ (IPGA
)<(
) > (IPGA
)
)
ALC
WTM1
WTM0
0
0
1
1
0
1
0
1
ALC1
8kHz
128/fs
16ms
256/fs
32ms
512/fs
64ms
1024/fs
128ms
Table 19. ALC1
RGAIN
GAIN STEP
0
0.5dB
1
1.0dB
Table 20. ALC1
REF5-0
GAIN (dB)
3DH
+26.5
3CH
+26.0
:
:
2DH
+19.0
:
:
05H
+0.5
04H
+0.0
03H
−1.0
02H
−2.0
:
:
01H
−7.0
00H
−8.0
Table 21. ALC1
MS0502-J-01
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
Default
STEP
0.5dB
Default
1.0dB
2007/04
- 30 -
[AK4650]
(3) ALC1
Table 22
Register
Name
LMTH
LTM1-0
ZELMN
ZTM1-0
WTM1-0
REF5-0
IPGA5-0
LMAT1-0
RGAIN
ALC1
ALC1
ALC1
Comment
Data
1
00
0dB
fs=8kHz
Operation
−4dBFS
Don’t use
Limiter detection Level
Limiter operation period at ZELMN
bit = “1”
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
00
16ms
Recovery waiting period
*WTM1-0 bits should be the same
00
16ms
data as ZTM1-0 bits
Maximum gain at recovery operation
3DH
+26.5dB
Gain of IPGA at ALC1 operation start 37H
0dB
Limiter ATT Step
00
0.5dB
Recovery GAIN Step
0
0.5dB
ALC1 Enable bit
1
Enable
Table 22. ALC1
ALC1
ALC1 bit = “0”
Data
1
00
fs=16kHz
Operation
−4dBFS
Don’t use
fs=44.1kHz
Data
Operation
1
−4dBFS
00
Don’t use
0
01
Enable
16ms
0
10
Enable
11.6ms
01
16ms
10
11.6ms
3DH
37H
00
0
1
+26.5dB
0dB
0.5dB
0.5dB
Enable
3DH
37H
00
0
1
+26.5dB
0dB
0.5dB
0.5dB
Enable
ALC1
PMMIC bit = “0”
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN, REF5-0, ZELMN
ALC1
ALC1 bit = “1” → “0”
PMMIC bit = “1”
IPGA
ALC1 bit = “0”
ALC1
IPGA5-0 bit
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 0.5dB
Maximum Gain = +26.5dB
Limiter Detection Level = −4dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM1-0, LTM1-0)
(1) Addr=66H, Data=4100H
WR (REF5-0)
(2) Addr=64H, Data=3D31H
WR (IPGA5-0)
* The value of IPGA should be
(3) Addr=0EH, Data=0077H
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RGAIN, LMTH, ZELMN)
(4) Addr=66H, Data=6100H
ALC1 Operation
Note : WR : Write
Figure 19. ALC1
MS0502-J-01
2007/04
- 31 -
[AK4650]
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bit
(tc=50/15μs
)
(Table 23)
DEM1
DEM0
0
0
0
1
1
0
1
1
Table 23.
Mode
44.1kHz
OFF
48kHz
32kHz
Default
■
BST1-0 bit
24)
BST1-0 bit = “10”(MID)
DAC
(Table
47μF
DC
DAC
Boost Filter (fs=48kHz)
20
MAX
15
Gain [dB]
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 20.
(fs=48kHz)
BST1
BST0
0
0
0
1
1
0
1
1
Table 24.
Mode
OFF
MIN
MID
MAX
MS0502-J-01
Default
2007/04
- 32 -
[AK4650]
■
AK4650
MUTE
DATTC bit
“0”
0.5dB
128
DAC
“1”
ATTL6-0 bit Lch, Rch
Lch, Rch
ATTL/R6-0
00H
01H
02H
:
7DH
7EH
7FH
ATT
ATT
@fs=48kHz)
(DATT)
−63dB
0dB
DATTC bit
Attenuation
0dB
−0.5dB
−1.0dB
:
−62.5dB
−63.0dB
MUTE (−∞)
Table 25. DATT
STEP
Default
0.5dB
-
ATS bit 531/fs 128/fs
531
00H(0dB)
ATS
0
1
Table 26.
ATT speed
0dB to MUTE
1 step
531/fs
4/fs
128/fs
1/fs
ATT
MS0502-J-01
(Table 26)
7FH(MUTE)
ATS bit = “0”
531/fs (11ms
Default
2007/04
- 33 -
[AK4650]
■
DAC
SMUTE bit
“1”
SMUTE bit
0dB
TM1-0 bit
“0”
−∞
TM1-0 bit
0dB
(Figure 21)
SMUTE bit
(Table 27)
−∞(“0”)
−∞
TM1-0 bit
S M U T E bit
TM 1-0 bit
0dB
TM 1-0 bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 21.
−∞(“0”)
(GD)
(1) TM1-0 bit
(2)
(3)
0dB(
TM1-0 bit
)
TM1
0
0
1
1
TM0
Cycle
0
1024/fs
Default
1
512/fs
0
256/fs
1
128/fs
Table 27. Soft Mute Time Setting
MS0502-J-01
2007/04
- 34 -
[AK4650]
■ AUX
AK4650
ADC
AUXIN+ pin
AUXIN− pin
AUXAD bit
AUXMT, GN4-0 bits
Volume
HP, SP
AUXL bit
Figure 22. AUX
AUX
AK4650 AUX
(Table 28.
AUXMT
0
1
GN4-0
00H
01H
02H
:
08H
:
1EH
1FH
x
Table 28. AUX
GN4-0 bit
)
GAIN (dB)
+12.0
+10.5
+9.0
:
+0.0
:
−33.0
−34.5
MUTE
STEP
1.5dB
Default
(x: Don’t care)
MS0502-J-01
2007/04
- 35 -
[AK4650]
■
AK4650
LIN pin
HP Lch, SP
LNMT, GL4-0 bits
Volume
RIN pin
HP Rch, SP
LNMT, GR4-0 bits
Volume
Figure 23.
LNMP bit = “1”
LIN/RIN
GR4-0 bit
MPE pin
LIN pin
AK4650
RNMD bit = “1”
MDT pin
GL4-0,
(Table 28.
LNMT
0
1
GL/GR4-0
00H
01H
02H
:
08H
:
1EH
1FH
x
Table 29.
RIN pin
GAIN (dB)
+12.0
+10.5
+9.0
:
+0.0
:
−33.0
−34.5
MUTE
MS0502-J-01
)
STEP
1.5dB
Default
2007/04
- 36 -
[AK4650]
■
BEEP
BEEP
PMBPM bit
“1”
BPMHP bit “1”
BPMSP bit
BEEP pin
BEEP pin
BEEP
Ri
“1”
BEEP pin
−20dB
20kΩ ± 30%
0dB
BPMT bit = “1”
BEEP
BEEP
OFF
INBP bit = “1”
BEEP pin
IN2 pin
AK4650
HP Lch
BPMHP bit
-20dB
HP Rch
Rf
Ri
SP
BEEP pin
BPMSP bit
Figure 24. BEEP pin
(Rf = 20kΩ ± 30%)
MS0502-J-01
2007/04
- 37 -
[AK4650]
■
(MOUT+/MOUT− pin)
MICOUT pin
AIN pin
AK4650
MIC In
ATT
+20dB/0dB
IPGA5-0 bits
ATTM bit
DAMO bit
MICM bit
1/2
MOUT+ pin
ATT+DAC
MOUT− pin
1/2
MOGN2-0 bits
+6dB to –15dB
Figure 25.
DAMO bit
“1”
DAC Lch, Rch
MICM bit “1”
IPGA
MOUT− pin
PMMO bit “0”
PMMO
0
1
MOMT
x
1
0
Lch
Mode
[(L+R)/2]
MOUT+/MOUT− pin
MOUT+/MOUT− pin
MOUT+ pin
min. 20kΩ
Hi-Z
MOUT+/MOUT− pin
Hi-Z
VCOM
Default
Table 30.
DAC
ATTL7-0, ATTR7-0 bits(Table 25)
ATTM bit(Table 8)
(Table 31)
MOGN2-0
0H
1H
2H
3H
4H
5H
6H
7H
Table 31.
GAIN (dB)
+6.0
+3.0
+0.0
−3.0
−6.0
−9.0
−12.0
−15.0
MS0502-J-01
IPGA
MOGN2-0 bit +6dB ∼ −15dB
STEP
Default
3dB
2007/04
- 38 -
[AK4650]
■
16Ω
HPMT bit
HVDD
PMHPL=PMHPR= “1” HPMT bit
MUTET pin
0.44 x AVDD
“0”
“1”
HVSS
MUTET pin
ESR(
)
ESR
tr:
tf:
(0.44 x AVDD
(0V
)
)
100k x C (typ)
200k x C (typ)
Table 32.
: MUTET pin
C=1μF
(0.22 x AVDD
(0V
):
): tr = 100k x 1μ = 100ms(typ)
tf = 200k x 1μ = 200ms(typ)
PMHPL, PMHPR bit “0”
HPL, HPR pin HVSS
PMHPL/R bit
HPMT bit
0.44 x AVDD
HPL/R pin 0.22 x AVDD
tf
tr
(1) (2)
(3)
(4)
Figure 26.
(1)
(2)
(3)
(4)
(PMHPL, PMHPR bit = “1”)
HVSS
(HPMT bit = “0”) MUTET
MUTET pin
“C”
(tr) 100k x C(typ)
(HPMT bit = “1”) MUTET
HVSS
MUTET pin
(tf) 200k x C(typ)
(PMHPL, PMHPR bit = “0”)
HVSS
MS0502-J-01
0.44 x AVDD
“C”
0V
2007/04
- 39 -
[AK4650]
(fc)
Table 33
(fc)
HVDD=2.7, 3.0, 3.3V
HP-AMP
RL 16Ω
0.6 x AVDD (Vpp)
R
C
Headphone
16Ω
AK4650
Figure 27.
R [Ω]
0
6.8
16
C [μF]
220
100
100
47
100
47
fc [Hz]
BOOST=OFF
45.2
99.5
69.8
148.5
49.7
105.8
Table 33.
fc [Hz]
BOOST=MIN
17
42
28
74
19
46
,
MS0502-J-01
2.7V
Output Power [mW]
3.0V
3.3V
27.9
34.5
41.7
13.7
17.0
20.5
7.0
8.6
10.4
f
2007/04
- 40 -
[AK4650]
■
AK4650
HVDD
Headphone Jack
Not inserted
Inserted
100k
Pins 1 and 2
Short
Open
HDT pin
“L” (pulled-down by external 2.2k)
“H” (pulled-up by internal 100k)
HPDT bit
HDT pin
DTHPJ bit
HPL pin
47u
6.8
1
2
3
4
5
2.2k
HPR pin
Headphone Out
47u
6.8
2.2k
Figure 28.
(1) HPDT bit = “1”.
(2) HDT pin 100kΩ HVDD
(3) DTHPJ bit
DTHPJ bit
INTN pin
(Table 34)
HPINT bit = “1”
“L”
Input Level of HDT
< 0.3 x HVDD
> 0.7 x HVDD
Table 34.
DTHPJ bit
0
1
PMHPL=PMHPR=PMSPK= “1”, HPMT=SPPS= “0”
Headphone Jack
Not inserted
Inserted
ATSW bit
“1”
(Table 35, Table 36)
DTHPJ
0
1
PMHPL
PMHPR
x
0
1
HPMT
x
1
0
Table 35.
DTHPJ
0
PMSPK
0
Power Down
Power Down
Power UP
(ATSW bit = “1”)
SPPS
SPK-Amp
x
Power Down
1
Power Save
0
Power UP
x
Power Down
x
Power Save
(ATSW bit = “1”)
1
0
1
1
HP-Amp
Table 36.
MS0502-J-01
2007/04
- 41 -
[AK4650]
■
DAC
[(L+R)/2]
BTL
DAC
8Ω
ALC2
, HVDD=3.3V
BEEP
300mW(typ)@ALC2 bit = “0”, 190mW(typ)
@ALC2 bit = “1”
ALC2
0
1
Table 37.
PMSPK bit
bit “0”
300mW
190mW
(MOUT2, ALC2, Speaker-amp)
MOUT2, SPP, SPN pin Hi-Z
Default
Power ON/OFF
PMSPK
SPPS bit “1”
HVDD/2
SPP pin
RESETN pin
PMSPK
0
“L”
SPPS
x
1
0
1
“H”
SPP, SPN pin
PMSPK bit “1”
HVDD/2
Power OFF
Mode
Hi-Z SPN pin
SPP, SPN pin
(PMSPK bit = “0”)
SPP pin
Hi-Z
Hi-Z
SPN pin
Hi-Z
HVDD/2
Default
Table 38.
PMSPK bit
SPPS bit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
Hi-Z
Figure 29.
■
DAC Lch, Rch
OFF
PMSPK bit
(MOUT2 pin)
[(L+R)/2]
MOUT2 pin
“0”
MO2 bit
VCOM
“0”
MOUT2
min. 10kΩ
Hi-Z
MS0502-J-01
2007/04
- 42 -
[AK4650]
■ ALC2
ALC2
(MIN pin)
Figure 30
ALC2
typ. 24kΩ VCOM
0dBV=1Vrms=2.828Vpp
HVDD
+1.8dBV@HVDD=3.3V
ALC2
ALC2
ROTM bit
ALC2
+1.8dBV
ALC2
0.5dB
(Table 39)
−0.2dBV@HVDD=3.3V
ALC2
−0.2dBV
ALC2
1dB
ALC2
(Table 39)
ROTM bit
+18dB
+1.8dBV ∼ −0.2dBV
PMSPK bit “0”
ROTM bit = “1”
(Addr=32H)
ALC2
ALC2
“1”
512/fs=11.6ms@fs=44.1kHz)
ALC2
(ROTM bit = “0”
fs
ALC2
+1.8dBV
2/fs = 45μs@fs=44.1kHz
2/fs = 181μs@fs=11.025kHz
ROTM bit = “0”
ROTM bit = “1”
0.5dB step
ATT/GAIN
Table 39. ALC2
2048/fs=46.4ms@fs=44.1kHz
ADC
ALC2
ALC2
−0.2dBV
2048/fs = 46.4ms@fs=44.1kHz
512/fs = 46.4ms@fs=11.025kHz
(Timeout = 2048/fs)
1dB step
(HVDD=3.3V)
SPK Out
+3.8dBV
(Limitter)
+1.8dBV
−0.2dBV
(Recovery)
(ALC2=OFF)
Figure 30. DAC
-
0dBFS
−2dBFS
−23.2dBFS
−25.2dBFS
−18.2dBV
DAC In
(HVDD=3.3V, ALC2 bit = “1”)
MS0502-J-01
2007/04
- 43 -
[AK4650]
■
Microphone
Audio CODEC
AK4650
ADC
Mic In
CPU
HP Out
Headphone
RF
Module
HP
Amp
DAC
Aux In
Mono Out
Figure 31.
&
Microphone
Audio CODEC
AK4650
Mic In
ADC
Side Tone ATT
CPU
Headphone
RF
Module
HP Out
HP
Amp
DAC
Aux In
Mono Out
Figure 32.
Microphone
Audio CODEC
AK4650
Mic In
ADC
Side Tone ATT
CPU
Headphone
RF
Module
HP Out
HP
Amp
DAC
Aux In
Mono Out
Figure 33.
MS0502-J-01
&
2007/04
- 44 -
[AK4650]
■
A/D
12bit
A/D
A/D
12bit A/D
Table 40
~ ΔVREF
~ (ΔVREF−1.5LSB)
:
0.5LSB ~ 1.5LSB
0 ~ 0.5LSB
ΔVREF: (VREF+) – (VREF−)
Table 40.
FFFH
FFEH
:
001H
000H
(ΔVREF−1.5LSB)
(ΔVREF−2.5LSB)
ΔVREF
A/D
(
)
■
A2-0, SER bit
SER bit “0”
(ΔVREF)
(ΔAIN)
(ΔVREF)
SER bit
“1”
(XP, YP)
(
(X
(X
)
XP–XN)
YP–XN)
(
VREF
GND
SER bit = “0”
IN2
SER bit
0
1
A/D
) A/D
GND
GND
(ΔAIN)
Differential
Single-ended
Table 41.
A/D
VBAT, IN1
ΔVREF
X
: XP−XN
Y
: YP−YN
VREF−TSVSS
ΔVREF, ΔAIN
MS0502-J-01
A/D
IN2 pin
VREF
ΔAIN
X
: YP−XN
Y
: XP−YN
AIN−TSVSS
2007/04
- 45 -
[AK4650]
■
(
XP, XN )
X ,Y
YP)
2
A/D
ON
ON
XP
VREF+
XP
AIN+
VREF+
YP
ADC
VREF-
(
AIN+
YP
ADC
AIN-
VREF-
AIN-
XN
XN
ON
YN
YN
ON
a)
X-Position Measurement
b)
Differential Mode
Y-Position Measurement
Differential Mode
Figure 34.
A/D
MS0502-J-01
ON
2007/04
- 46 -
[AK4650]
■
YP
VREF+ XN
VREF−
XP, YN
2
1) X
(Rxplate)
Z1
Xposition
Rtouch = Rxplate ×
×
4096
2) X
Y
Xposition
4096
)
–1
Z1
(Rxplate, Ryplate)
Y
Z1
X
Rtouch = Rxplate ×
(
Z2
Z2
×
(
4096
)
–1
Z1
– Ryplate ×
AK4650
(
Yposition
1–
4096
)
AK4650
ON
ON
YP
XP
VREF+
YP
touch
XP
AIN+
ADC
VREF+
AIN+
VREF-
AIN-
touch
ADC
VREF-
AIN-
XN
XN
ON
ON
YN
YN
a) Z1-Position Measurement
b) Z2-Position Measurement
Differential Mode
Differential Mode
Figure 35.
■
(VREF)
AK4650
2.5V
VREF
PMVREF bit
“1”
“0”
PMVREF bit
VREF
VREF pin
VREF
400µs
PMVREF bit
0.1µF
0.1µF
“1”
A/D
“0”
MS0502-J-01
2007/04
- 47 -
[AK4650]
■
AK4650
2.7~3.6V
Figure 36
5V
R1, R2(7.5k, 2.5k)
VBAT
ADEXE pin
(Table 53)
VBAT pin
ADEXE pin
ADEXE pin
VREF
AK4650
PD1
Internal
VREF
VBAT
AIN+
R0
VREF+
ADC
R1=7.5K
AIN-
VREF-
R2=2.5K
Enable
Figure 36.
MS0502-J-01
2007/04
- 48 -
[AK4650]
■
A/D
YN pin
(Ri:
GND
(100kΩ
50kΩ)
XP pin
INTN pin
2
XP pin
)
(TSVDD)---(Ri)---(X+)---(Y−)
INTN pin “L”
100Ω
INTN pin
“H”
PM12AD bit = “1”
= “H”
INTN pin
PINTE bit
Y
INTN pin
“0”
“L”
A2-0, PINTE bit
PINTE bit
INTN pin = “L”
12bit ADC
INTN pin
VBAT, IN1, IN2
“1”
INTN pin
X
INTN pin
“H”
PM12AD bit = “0”
PINTE bit = “0”
XP, YP, XN
pin
Hi-Z
INTN pin
PINTE bit = “1”
INTN pin
PM12AD bit
0
0
1
PINTE bit
0
1
0
Disable
Enable
Disable
1
1
Auto
“H”
“L”
INTN pin
“H”
“L”
XY
“H”
“L”
XY
“H”
“L”
“H”
“L”
(x: Don’t care)
Table 42. INTN pin
“H”
100kΩ
AK4650
INTN pin
EN2
50kΩ
Driver OFF
XP pin
EN1
YN pin
Driver ON
Figure 37.
MS0502-J-01
2007/04
- 49 -
[AK4650]
■ AC-Link
T S C To u c h
IN T N
S D A TA IN
SY NC
C ry s t a l O c ila t o r
M in : 2 0 m s
B I TC L K
T im e r m in : 2 5 m s
V R A b it (P L L )
P LL
m in : 2 0 m s
P R 1 b it ( D A C )
V R A b it (P L L )
P R 6 b it ( H P )
Ty p . 5 0 m s
H P L/R
(N o t e )
Note 40. PR2 = PR3 = PR6 = “0”
PMHPL bit = “1”, PMHPR bit = “1”, HPMT bit = “0”
(ATPU bit = “1”)
Figure 38. AC-Link
MS0502-J-01
2007/04
- 50 -
[AK4650]
■ Waking up AC-Link
1. AC-Link
AK4650
AC’97 CODEC
26H PR4 bit
PR5 bit
PR4 bit = “1”
BITCLK
SDATAIN
PR5 bit = “1”
BITCLK
SDATAIN
Up/Down
VRA bit
AC-Link
Power Up/Down
PLL Power
PLL
Power Down
Power Down
Power Down
BITCLK/SDATAIN
PR4 bit = “1”
PR5 bit = “1”
VRAbit = “0”
Table 43. AC-Link
2. AC-Link
AC-Link
WARM RESET
AC-Link
SDATAIN
WARM RESET
Power Down
AC’97 CODEC COLD RESET
SYNC
CODEC
Sleep State
New Audio
Wake Event
SYNC
BITCLK
SDATAOUT
Slot 12
TAG
SDATAIN
Slot 12
TAG
WR
26H
Data
PR4
Figure 39. SDATAIN
TAG
Slot 1
Slot 2
TAG
Slot 1
Slot 2
AC-Link Wake Up
3. SDATAIN
AK4650
SDATAIN pin
“L”
Enable
“H”
AK4650
AC-Link
STATAIN
SYNC
“L”
SYNC
WARM RESET
MS0502-J-01
2007/04
- 51 -
[AK4650]
4. Wake Up Time
AK4650
Power Down
50ms
(1) PR4 bit = “1”, PR5 bit = “1”
Touch Screen
AK4650
BITCLK
Touch Screen
(12bit ADC
)
Wake Up
T5, T7
T7
AK4650
1µs
CPU
T5
20ms
T1 : Touch Screen
SDATAIN
T2 : SDATAIN
CPU SYNC
T3 : SYNC
=> CPU
1µs
T4 : SYNC Falling
T5 :
BITCLK
T6 : CPU BITCLK
SYNC
T7 : AK4650 SYNC
CODEC Ready
T8 : CPU
CODEC Ready
ADC
=> Touch Screen
=> CPU
=> CPU
Read
=>
=> CPU
=> 162.8ns
=> CPU
T S C To u c h
IN T N
S D A TA IN
SY NC
C ry s t a l O c ila t o r
B I TC L K
1 2 b it A D C
T2
T1
T3
T4
T5
T6
T7
T8
Figure 40. AC-Link Wake Up Timing (PR5 bit = “1”)
5.
AK4650
Enable
(1) PENINT bit “1”
(2) AC-Link
(3) PINTR bit “1”
(2)
(3)
Interrupt
INTN pin
Interrupt
GINT bit = “1”
SLOT bit = “1”
DTPEN bit (Addr=6AH: D2) “1”
SDATAIN
Slot 12
Bit 0
“1”
GPIO pin
MS0502-J-01
2007/04
- 52 -
[AK4650]
■ 12bit ADC
1.
12bit ADC
AK4650
2
SLOT bit
0
AK4650
12bit ADC
Register (74H, 76H, 78H)
1
AK4650
SDATAIN
SLOT bit
Write
Slot 5, Slot 6
Register
Slot 12
Read
Default
CPU
Table 44. 12bit ADC
2.
A2-0, SER bit
PM12AD bit = “1”
(Table 45)
DLY3-0 bit
4
(Table 47)
(Table 48)
A2-0, SER bit
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PM12AD, PMVREF bit
12bit ADC
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SER
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
ADC
(ΔAIN)
AIN+
AIN−
SLOT bit = “0”
ADFLT bit
12bit ADC
(ΔVREF)
VREF+ VREF−
XP
OFF
OFF
OFF
OFF
OFF
ON
OFF
XN
OFF
OFF
OFF
ON
ON
ON
OFF
YP
OFF
ON
OFF
ON
ON
OFF
OFF
YN
OFF
ON
OFF
OFF
OFF
OFF
OFF
XP
VBAT
XP(Z1)
YN(Z2)
YP
IN1
GND
GND
GND
GND
GND
GND
VREF
VREF
VREF
VREF
VREF
VREF
GND
GND
GND
GND
GND
GND
OFF
OFF
ON
ON
XP
YN
YP
YN
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
XP(Z1)
YN(Z2)
YP
IN2
XN
XN
XN
GND
YP
YP
XP
VREF
XN
XN
XN
GND
N/A (Default)
Y
(Z1)
(Z2)
X
IN1
N/A
N/A
Y
N/A
(Z1)
(Z2)
X
IN2
N/A
Table 45. 12bit ADC
MS0502-J-01
2007/04
- 53 -
[AK4650]
PM12AD
PMVREF
PINTE
VREF
0
x
0
Disable
x
0
x
1
Enable
x
ADC
OPEN
1
1
x
x
0
1
x
x
0
1
x
x
Disable
Auto
x
x
x
OFF
x
ON
Table 46.
ADC
OPEN
XP pin TSVDD YN pin TSVSS)
ADC
XY
XYZ
ADC
PMVREF bit VREF ON/OFF
(x: Don’t care)
DLY3-0 bit
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
ADC
Table 47.
ADFLT bit
0
1
(
1TS
Default
2TS
4TS
8TS
12TS
16TS
24TS
32TS
48TS
64TS
96TS
128TS
160TS
192TS
224TS
256TS
(1TS=1SYNC
=20.83μs@fs=48kHz)
Filter
Default
4
Table 48. 12bit ADC
(SLOT bit = “0”
MS0502-J-01
)
2007/04
- 54 -
[AK4650]
3. Register Read
3
ADMODE1-0 bits
(1) 74H Register Read
(2) XY
(3) XYZ
ADMODE 1-0 bits
00
74H Register Read
01
XY
10
XYZ
11
N/A
Table 49. 12bit ADC
Default
3-1. 74H Register Read
A2-0, SER bit
Read
74H
74H
: 0:
1: D11-0
D14-12(A2-0) :
D11-0
:
CPU
PM12AD bit = “0”
74H
74H
D15(ADE)
(A2-0 bit)
(12bit)
3-1-1.ADFLT bit = “0” : 4
(1) 70H(ADFLT, DLY3-0, ADEXE1-0)
= “1” 12bit ADC Power Up
(2) DLY3-0 bit
(3) 74H Read
ADC
A2-0, SER bit
74H
PM12AD bit
SYNC
SYN C
PM 12AD ,
P IN T E b it s
A 2 - 0 , S E R , b it
11
01
1010
0010
R ead C om m and
74h
74h
74h
S e n d A D C D a ta
ADC M ode
1 2 b it A D C
X M e a s u re
DELAY
W a it
Y M e a s u re
X -M e a s u re
W a it
X -M e a s u re
DELAY
W a it
W a it
Y -M e a s u re
W a it
P e n W a it
A D E b it
D 1 1 - D 0 b its
XXX
X -P o s
X -P o s
Y -P o s
DLY3-0 bits = “0H” (1TS)
Figure 41. X,Y
(ADFLT bit = “0”)
MS0502-J-01
2007/04
- 55 -
[AK4650]
3-1-2.ADFLT bit = “1” : 4
(1) 70H(ADFLT, DLY3-0, ADEXE1-0)
= “1” 12bit ADC Power Up
(2) DLY3-0 bit
(3) 74H Read
74H
A2-0, SER bit
ADC 4
PM12AD bit
74H
SYN C
PM 12AD ,
P IN T E b it s
A 2 - 0 , S E R , b it
11
1010
0010
R ead C om m and
74h
74h
S e n d A D C D a ta
ADC M ode
1 2 b it A D C
X M e a s u re
DELAY
Y M e a s u re
X -M e a s u re
DELAY
W a it
Y -M e a s u re
W a it
A D E b it
D 1 1 - D 0 b its
XXX
X -P o s
Y -P o s
DLY3-0 bits = “1H” (2TS)
Figure 42. X, Y
(ADFLT bit = “1”)
3-2. X-Y
A2-0, SER bit
2
Y
PM12AD bit = “0”
X
ADMODE1-0 bit = “01”
PM12AD bit = “1”
Register 74H
Y
Register 76H
(1) 70H(ADFLT, DLY3-0, ADEXE1-0)
“1” 12bit ADC Power Up
(2) DLY3-0 bit
X
4
74H
(3) X
DLY3-0 bit
ADFLT bit = “1”
4
(4)
ADMODE1-0 bit “00”
(5) PINTE bit = “1”
ADC
ADMODE1-0 bit
1
74H, 76H
“01”
74H
X
PM12AD bit
ADFLT bit = “1”
Y
76H
76H
SYN C
PM 12AD ,
P IN T E b it s
10
A D M O D E 1 - 0 b its
01
ADC M ode
X M e a s u re
1 2 b it A D C
DELAY
00
Y M e a s u re
X M e a s u re
y M e a s u re
DELAY
P E N - W a it
7 4 H : A D E b it
7 4 H :D 1 1 - D 0 b its
XXX
X - P o s itio n
7 6 H : A D E b it
7 6 H :D 1 1 - D 0 b its
Y - P o s itio n
XXX
DLY3-0 bits = “2H” (4TS)
Figure 43. X, Y
ADMODE1-0 bit
“01”
ADE bit
MS0502-J-01
“0”
2007/04
- 56 -
[AK4650]
3-3. XYZ
ADMODE1-0 bit = “10”
PM12AD bit = “1”
X
Register 74H
PM12AD bit = “0”
74H, 76H, 78H
(1) 70H(ADFLT, DLY3-0, ADEXE1-0)
bit
“10”
PM12AD bit = “1”
(2) (1)
X
4
74H
(3) X
DLY3-0 bit
ADFLT bit = “1”
4
(4) Y
DLY3-0 bit
78H
ADFLT bit = “1”
(5)
ADMODE1-0 bit “00”
(6) PINTE bit = “1”
1
X
2
Register 76H
Y
A2-0, SER bit
12bit ADC Power Up
74H
Y
3
3
ADMODE1-0
ADFLT bit = “1”
Y
76H
A2-0, SER bit
4
A2-0, SER bit
78H
76H
78H
SYN C
PM 12AD ,
P IN T E b it s
11
A D M O D E 1 - 0 b its
10
ADC M ode
X M e a s u re
1 2 b it A D C
DELAY
00
Y M e a s u re
X M e a s u re
DELAY
Z 1 M e a s u re
y M e a s u re
DELAY
Z 1 M e a s u re
P E N - W a it
7 4 H : A D E b it
7 4 H :D 1 1 - D 0 b its
X - P o s itio n
XXX
7 6 H : A D E b it
7 6 H :D 1 1 - D 0 b its
Y - P o s it io n
XXX
7 8 H : A D E b it
7 8 H :D 1 1 - D 0 b its
Z 1 - P o s it io n
XXX
Figure 44. X, Y, Z
ADMODE1-0 bit
“10”
DLY3-0 bits = “1H” (2TS)
(ADFLT bit = “1”, A2-0 bits = “011”, SER bit = “0”)
ADE bit
MS0502-J-01
“0”
2007/04
- 57 -
[AK4650]
4. SDATAIN
Slot
SLOT bit “1”
SDATAIN Slot 5, Slot 6
= “00”
Slot 5
“01”
Slot 6
“10”
ADC
Tag bit(Bit 10, Bit 9
Bit 3) “1”
“0”
Slot 5, Slot 6
Slot 12
Slot 12
Slot 12
ADC
“0”
SLOT bit
0
1
Bit 19
:
==>
Bit 18-16 :
Bit 15-4 : ADC
ADFLT bit
SLOTNO1-0 bit
16bit
Slot 0 Slot 5, Slot 6
Slot 12
Tag bit(Bit 10, Bit 9
Bit 3)
SLOTNO1-0 bits
x
00
01
10
11
Table 50. 12bit ADC
Slot
Default
Slot 5
Slot 6
Slot 12
N/A
“1”
Slot 0 Tag bit “1”
(A2-0 bit)
ADFLT bit = “1”
4
3
(1)
(2) XY
(3) XYZ
ADMODE1-0 bits
00
01
XY
10
XYZ
11
N/A
Table 51. 12bit ADC
Default
4-1.
A2-0, SER bit
Bit 19 “0”
Slot
(1) SLOT bit = “1”
(2) PEN Interrupt
(3) PM12AD bit
1SYNC
(PM12AD bit = “0” PINTE bit = “1”)
CPU PM12AD bit = “1”
Slot
“1”
A2-0, SER bit
DLY3-0 bit
Bit 19(ADE)
MS0502-J-01
“0”
2007/04
- 58 -
[AK4650]
4-2. X-Y
A2-0, SER bit
PM12AD bit = “1”
MSR1-0 bit
X
ADMODE1-0 bit
Y
“01”
MSR1-0 bit
Slot
(1) SLOT bit = “1”
(2) PEN Interrupt
ADMODE1-0 bit
(3) DLY3-0 bit
(4) X
(PM12AD bit = “0” PINTE bit = “1”)
CPU PM12AD bit = “1”
12bit ADC Power Up
Slot
X
MSR1-0 bit
Slot
“01”
DLY3-0 bit
Y
MSR1-0 bit
Slot
(5) Y
SYN C
S lo t b it
PM 12AD ,
P IN T E b it s
A D M O D E 1 - 0 b its
00
10
01
00
ADC M ode
1 2 b it A D C
X M e a s u re
P E N - W a it
DELAY
Y M e a s u re
X M e a s u re
X M e a s u re
X M e a s u re
X M e a s u re
DELAY
y M e a s u re
y M e a s u re
y M e a s u re
y M e a s u re
P E N - W a it
S lo t B IT 1 9
S lo t B IT 1 8 - 1 6
S lo t B IT 1 5 - 4
000
0
101
X pos
X P os
000
X pos
X pos
0
001
y pos
000
y pos
DLY3-0 bits = “0H” (1TS), MSR1-0 bits = “0H” (4
Figure 45. X, Y
MSR1-0 bit
00
01
10
11
Table 52.
4
8
16
32
(SLOT bit = “1”
MS0502-J-01
y pos
y pos
0
)
Default
)
2007/04
- 59 -
[AK4650]
4-3. X-Y-Z
PM12AD bit = “1”
ADMODE1-0 bit “10”
DLY3-0 bit
X
Y
MSR1-0 bit
A2-0, SER bit
Slot
(1) SLOT bit = “1”
(2) PEN Interrupt
ADMODE1-0 bit
(3) DLY3-0 bit
(4) X
(PM12AD bit = “1” PINTE bit “1”)
CPU PM12AD bit = “1”
12bit ADC Power Up
Slot
X
MSR1-0 bit
Slot
“10”
DLY3-0 bit
Y
DLY3-0 bit
Slot
A2-0, SER bit
MSR1-0 bit
Slot
(5) Y
MSR1-0 bit
(6)
5. ADEXE pin
LCD
AK4650
LCD
AK4650
LCD
ADEXE pin
ADC
ADEXE1-0 bit
00
01
10
11
ADEXE pin
ADC
ADEXE pin = “↑” ADC
ADEXE pin = “↓” ADC
N/A
Table 53. ADEXE
■
SDATAIN
SLOT bit
“1”
SDATAIN
Default
Slot 12
Slot 12
Bit 1:
Bit 0:
MS0502-J-01
2007/04
- 60 -
[AK4650]
■ AC ’97
AC-Link
AK4650
5
AC’97
Controller
AK4650
SYNC
BITCLK
SDATAOUT
SDATAIN
RESETN
Figure 46. AC ’97
RESETN
BITCLK
SYNC
SDATAIN
SDATAOUT
(Input)
(Output)
(Input)
(Output)
(Input)
: AK4650
: AK4650
: AK4650
:
:
12.288MHz
(AK4650
(AK4650
)
)
■
AK4650 AC’97
(48kHz)
5
AC-Link
12bit ADC
PCM
(TDM)
20bit
16bit
12
AK4650
ADC
DAC
AC’97
z PCM Playback
2 output slots
2ch PCM
z PCM Record data 2 input slots
1ch PCM
z Control
2 output slots
z Status
2 input slots
z 12bit ADC data
12bit ADC
3 input slots
48kHz
AC-Link
AC-Link
SYNC
AK4650
BITCLK
1
16bit
BITCLK
AC’97
BITCLK
(Slot 0)
12
20bit
Slot 0
“1”
“0”
MS0502-J-01
2007/04
- 61 -
[AK4650]
SYNC
Phase”
SYNC
AC’97
SDATAOUT
16BITCLK
“Data Phase”
“L”
“H”
SYNC
BITCLK
1BITCLK
SDATAIN
AC’97
“H”
“Tag
SYNC
AK4650
AK4650
AC’97
■ AC-Link
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
12bit ADC
Data
SYNC
SDATA
OUT
TAG
SDATA
IN
TAG
Command Command PCM(dac) PCM(dac)
Address
Data
Left
Right
Status
Address
Status
Data
PCM(adc)
Left
Tag Phase
All
”0”
12bit ADC 12bit ADC
Data
Data
Data Phase
48kHz
Figure 47. AC-Link
AC-Link
Tag Phase Slot 0
13
16bit
SYNC
48kHz
20bit
MS0502-J-01
2007/04
- 62 -
[AK4650]
1) AC-Link
(SDATAOUT)
[Slot 0]
SY NC
BITCLK
Valid
Frame
SDATAIN
Slot1 Slot2 Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10 Slot11 Slot12
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
“1/0” “1/0” “1/0” “1/0” “1/0” “0”
Bit9
“0”
Bit8
“0”
Bit7
“0”
Bit6
“0”
Bit5
“0”
Bit4
“0”
Bit3
“0”
Bit2
“0”
Bit1
“0”
Bit0
“0”
Slot 1
Slot 0
1 BITCLK delay
Figure 48. Slot 0
Slot 0 16bit (Bit 15-0)
(
)
AK4650
Bit 15-11
“1”=valid (
) “0”=invalid
1
Bit 15 (Valid Frame bit):
“1” = Slot 1-4
Valid
1
Slot 0
Bit 10-0
“0” =
slot invalid (
)
Bit 14 (Slot 1 valid bit): Slot 1 (
)
Valid
Bit 13 (Slot 2 valid bit): Slot 2 (
)
Valid
Bit 12 (Slot 3 valid bit): Slot 3 (DAC Left)
Valid
Bit 11 (Slot 4 valid bit): Slot 4 (DAC Right)
Valid
AC’97
AK4650
“1” =
“0” =
(
Loop back
all “0”
(LOOP bit = “1”)
AK4650
AC’97
valid bit
SYNC
BITCLK
SYNC BITCLK
SYNC
SDATAOUT Slot 0
BITCLK
SDATAOUT
MSB
)
AC-Link
BITCLK
(Valid Frame bit)
AK4650
AK4650
MS0502-J-01
2007/04
- 63 -
[AK4650]
Bit 14&13
Read/Write
Table 54
Bit 15
Valid Frame
1
1
1
Bit 14: Slot1 Valid Bit
(Command Address)
1
0
1
1
Bit 13: Slot 2 Valid Bit
(Command Data)
1
1
0
Read/Write Operation
Read/Write (Normal Operation)
Ignore
Read: Normal Operation
Write: Ignore
Ignore
0
0
Table 54. AK4650 Addressing: Slot 0 Tag Bits
[Slot 1]:
Slot 1 Slot 2
AK4650
30
16bit
BITCLK
SDATAOUT
Bit19 Bit18
Bit17 Bit16
“1/0” “1/0”
“1/0”
Bit15 Bit14
“1/0” “1/0”
“1/0”
Bit13 Bit12
Bit11
Bit10
Bit9
Bit2
Bit1
Bit0
“1/0” “1/0”
“0”
“0”
“0”
“0”
“0”
“0”
Slot 0
Bit19 Bit18
Bit17
Bit1
6
Slot 2
Slot 1
Command Address Port
Figure 49. Slot 1
Bit 19:
Bit 18-12:
Bit 11-0:
Read/Write
(1bit; “1”=read, “0”=write)
(7bit; “Mixer Registers”
)
Reserved (12bit; “0”)
Slot 1 Bit 18
Bit 11-0
MSB
AC’97
“0”
[Slot 2]:
BITCLK
SDATAOUT
Bit19 Bit18
Bit17 Bit16
“1/0” “1/0”
“1/0”
Bit15 Bit14
“1/0” “1/0”
“1/0”
Slot 1
Bit13 Bit12
Bit6
“1/0” “1/0”
Bit5
Bit4
Bit3
“1/0”
“1/0” “0”
Bit2
Bit1
Bit0
“0”
“0”
“0”
Bit19 Bit18
Bit17
Bit16
Slot 3
Slot 2
Command Data Port
Figure 50. Slot 2
Bit19-4:
Bit3-0:
Slot 1
Slot 2
(Slot1 Bit19(R/W)
Reserved (4bit; “0”)
Bit 19(R/W) “0”(Write)
Slot 1 Bit 19(R/W)
Bit 19
(16bit)
Slot2 Bit19-4
“1”(Read)
AC’97
“1”(Read)
“0”
)
Slot 2
Slot 2
D15
MS0502-J-01
2007/04
- 64 -
[AK4650]
[Slot 3]: PCM
Lch (16bit)
DAC
Lch
, MSB
4bit(Bit 3-0)
Slot 3 20bit
“0”
Bit 19-4:
(16bit)
Bit 3-0: “0” (4bit)
[Slot 4]: PCM
Rch (16bit)
DAC
Rch
, MSB
4bit(Bit 3-0)
Slot 3 20bit
“0”
Bit 19-4:
(16bit)
Bit 3-0: “0” (4bit)
Slot 0
16bit, 2’s complement,
Valid bit (Slot 3) Invalid (“0”)
Slot 0
16bit, 2’s complement,
Valid bit (Slot 3) Invalid (“0”)
[Slot 5-12]:
MS0502-J-01
2007/04
- 65 -
[AK4650]
2) AC-Link
(SDATAIN)
1
16bit Tag Phase
[Slot 0]
Slot 0 16bit
“1” Valid (
Ready”) Valid
Invalid
Slot 0
&
Tag Phase
) “0” Invalid (
)
AK4650
“0”
SDATAIN
“
12
AK4650 Bit 15-9
Not Ready
Slot 0
AC’97
ADC
Bit 12 Bit 11 (
20bit
Bit 3
Slot 0
(Bit 15 = “Codec
“Codec Ready”
Slot 0
48kHz
Slot 3
Slot 4
)
“1”
”
CODEC
SDATAOUT(
CODEC
SDATAIN(CODEC→
)
→ CODEC)
CODEC SLOTREQ bit
AK4650
Bit 14 Slot 1(Status Address)
(“0”)
Bit 14, 13
Bit 15
(Codec
Ready)
1
Bit 14
(Status
Address)
1
(“1”) or
AK4650
Bit 13
(Status
Data)
1
(“0”)
Bit 13
Bit 14, 13
1
0
0
(“1”) or
Status
Slot 1(address), Slot 2(data)
AK4650
1
1
1
Slot 2(Status Data)
Table 55
(
Slot2
“1”
)
all “0”
0
1
0
Slot 1 Bit 19-12, 9-0
Table 55. SDATAIN Slot0
“0”
Slot 2
all “0”
Note 41.
SLOTREQ
2=all “0”
Note 42. Slot 0 Bit 14
13
AK4650
Bit 14= “0”, Bit 13= “0”, Slot 1=all “0”, Slot
Slot 1
SLOTREQ bit (Bit 11, 10)
Bit 12, 10, 9, 3
Slot 3(PCM(ADC)Lch), Slot 5, Slot 6, Slot12
(“1”) or
(“0”)
Bit 11
Bit 12
Bit 11
Slot 4 all “0”
ADEXE1-0 bits = “00”
SLOT bit = “1”
SLOTNO1-0 bits
Slot
Tag bit (Slot 5=Bit 10, Slot 6=Bit 9, Slot 12=Bit 3)
“1”(Valid)
Bit 8-4, 2-0
“0”
MS0502-J-01
2007/04
- 66 -
[AK4650]
SYNC
BITCLK
AK4650
AK4650
SDATAIN
SYNC BITCLK
SYNC
Slot 0
AC-Link
BITCLK
(Codec Ready bit)
AC’97
BITCLK
SY NC
BITCLK
Codec
Ready
SDATAIN
Slot1 Slot2 Slot3
Slot4
Slot5
“1/0” “1/0” “1/0” “1/0” “1/0” “1/0”
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Slot7
Slot8
Slot11 Slot12
“1/0” “0”
Bit9 Bit8
“0”
Bit7
“0”
Bit4
Slot6
“1/0”
Bit3
“0”
Bit2
“0”
Bit1
“0”
Bit0
Slot 1
Slot 0
Figure 51. Slot 0
[Slot 1]:
Slot 1
(Slot 0
Slot 1 Valid bit
Slot 2 Valid bit
“Valid”
)
BITCLK
SDATAIN
Bit19 Bit18
Bit17 Bit16 Bit15 Bit14
“0”
“1/0”
“1/0”
Bit13 Bit12 Bit11
“1/0” “1/0” “1/0” “1/0” “1/0”
Slot 0
Bit10
“1/0” “1/0”
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
“0”
“0”
“0”
“0”
“0”
“0”
“0”
Bit2
Bit1
Bit0
“0”
“0”
“0”
Bit19
Slot 2
Slot 1
Status Address Port
Figure 52. Slot 1
Slot 2
SDATAOUT
SDATAIN
AC’97
“
”
SLOTREQ bit 11
Slot 1
DAC
10
48kHz
AK4650
Slot 1
“0”
SLOTREQ bit
VRA bit
SLOTREQ bit
AC’97
“0”
SLOTREQ bit
“1”
SDATAIN
SDATAOUT
“0”
48kHz
SLOTREQ Bit
19
18-12
11
10
9-0
Description
Reserved (Set to “0”)
Control Register Index (7bit; Invalid
“0”)
Slot 3 Request: PCM Lch
“0”: send data request, “1”: do not send
Slot 4 Request: PCM Rch
“0”: send data request, “1”: do not send
Reserved (10bit; Set to “0”)
Table 56. SLOTREQ bit
MS0502-J-01
2007/04
- 67 -
[AK4650]
[Slot 2]:
SDATAIN pin
Bit 19-4
Bit 3-0
(16bit; Slot 1
)
“0” (4bit)
:
Slot 1
AC’97
N
N+1
SDATAIN
1
[Slot 3]: PCM
ADC
Lch
ADC
“0”
Bit 19-4: ADC Lch
Bit 3-0: “0” (4bit)
[Slot 4]:
Bit 19-0
16bit, 2’s complement,
Slot 0
4bit(Bit 3-0) “0”
Invalid (“0”)
Slot 3 20bit
(16bit)
“0”
[Slot 5]: TSC 12bit ADC
SLOT bit = “1”, SLOTNO1-0 bit = “00”
Bit 19:
ADE (1bit; “0”=
, “1”=
Bit 18-16: A2-0 (3bit;
)
Bit 15-4: D11-0 (12bit; 12bit ADC
Bit 3-0:
“0” (4bit)
[Slot 6]: TSC 12bit ADC
SLOT bit = “1”, SLOTNO1-0 bit = “01”
Bit 19:
ADE (1bit; “0”=
, “1”=
Bit 18-16: A2-0 (3bit;
)
Bit 15-4: D11-0 (12bit; 12bit ADC
Bit 3-0:
“0” (4bit)
[Slot 7-11]:
Bit 19-0
, MSB
Valid bit (Slot 3)
12bit ADC
)
)
12bit ADC
)
)
“0”
[Slot 12]: TSC 12bit ADC
SLOT bit = “1”, SLOTNO1-0 bit = “10”
12bit ADC
SLOT bit = “1”
Bit 19:
ADE (1bit; “0”=
, “1”=
)
Bit 18-16: A2-0 (3bit;
)
Bit 15-4: D11-0 (12bit; 12bit ADC
)
Bit 3-2:
“0” (2bit)
Bit 1:
DTHPJ (1bit; “0”=
, “1”=
)
Bit 0:
DTPEN (1bit; “0”=
, “1”=
MS0502-J-01
SLOTNO1-0 bit
)
2007/04
- 68 -
[AK4650]
■
“Cold Reset”
RESETN pin = “L”
“Cold Reset”
Vdd
RESETN
SDATAOUT=”L”
SYNC=”L”
BITCLK
Initialize Registers
start up crystal oscillation
Trst2clk
Figure 53. Power On Timing
■ Cold Reset
SDATAOUT pin = “L”, SYNC pin = “L”
RESETN pin = “L”
RESETN pin
RESETN
:
“Cold Rest”
VREF
Hi-Z
“↑” : BITCLK
ADC, DAC
Cold Reset
SYNC
(1028Ts)
CODEC-Ready
Ready
28H VRA “0”
Ts=1/fs=20.83µs@fs=48kHz
Ts
Status Register, Tag Slot(SDATAIN Slot_0)
RESETN pin = “L”
: “1” (Ready)
Status Bit
: “0” (not Ready)
Trst_low
Trst2clk
RESETN
VIL
SDATAOUT= “L”
SYNC= “L”
BITCLK
Figure 54. Cold Reset Timing
MS0502-J-01
2007/04
- 69 -
[AK4650]
■ Warm Reset
SYNC
“H”
AC-Link
PR4 bit = “0”, PR5 bit = “0”
Note 43. Warm Reset
Note 44.
(PR4 bit = “1”, PR5 bit = “1”)
PR0-3, PR6-7
(Warm Reset)
SYNC
BITCLK
Warm Reset
SYNC
Tsync_high
Tsync2clk
SYNC
VIH
BITCLK
Figure 55. Warm Reset Timing
■ Active Test Mode
RESETN
VIH
VIH
SDATAOUT
Tsetup2rst
HI-Z
SDATAIN
BITCLK
Toff
Figure 56. Activate Test Mode Timing
Note 45. RESETN pin = “L”
RESETN “H”
BITCLK
SYNC
H/L
Note 46.
“H”
“Cold Reset”
AC-Link
“L”
SDATAOUT
SDATAIN Hi-Z
ATE
AK4650 ATE
SYNC pin = “L”, SDATAOUT pin = “L” RESETN pin = “L”→
MS0502-J-01
2007/04
- 70 -
[AK4650]
■
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
18H
1AH
20H
26H
28H
2AH
2CH
32H
60H
62H
64H
66H
68H
6AH
Reset
Speaker Output
Headphone Output
Mono Output
Boost Control
PC_BEEP Volume
Phone Volume
Mic Volume
Line In Volume
PCM Out Volume
Record Select
General Purpose
Powerdown Ctrl/Stat
Extended Audio ID
Ext’d audio Stat/Ctrl
PCM Front DAC Rate
PCM LR ADC Rate
Power Management
Signal Select
ALC/DAC Control
ALC Mode Control
Volume Cotrol
Detect Result
0
SPPS
HPMT
MOMT
0
BPMT
AUXMT
MICMT
LNMT
SMUTE
0
0
0
0
0
SR15
SR15
MPWRE
HPM
0
0
0
0
0
0
0
0
0
0
0
0
0
ATTL6
0
0
PR6
0
0
SR14
SR14
MPWRI
0
HPINT
ALC2
0
0
0
0
0
0
0
0
0
0
0
ATTL5
0
0
PR5
0
0
SR13
SR13
0
0
REF5
ALC1
0
0
0
0
0
0
0
0
0
0
GL4
ATTL4
0
0
PR4
0
0
SR12
SR12
0
0
REF4
ZELMN
0
0
0
0
0
0
BST1
0
0
0
GL3
ATTL3
0
0
PR3
0
0
SR11
SR11
0
INBP
REF3
LMAT1
0
0
0
0
0
0
BST0
0
0
0
GL2
ATTL2
0
0
PR2
0
0
SR10
SR10
0
RNMD
REF2
LMAT0
0
0
0
0
0
0
0
0
0
0
GL1
ATTL1
MICAD
MDIF
PR1
0
0
SR9
SR9
0
LNMP
REF1
RGAIN
0
0
0
0
0
0
0
0
0
0
GL0
ATTL0
AUXAD
MSEL
PR0
0
0
SR8
SR8
MCKPD
DAHS
REF0
LMTH
0
0
0
0
0
MOGN0
0
0
GN0
IPGA0
GR0
ATTR0
0
0
ADC
1
VRA
SR0
SR0
PMMIC
MO2
DEM0
LTM0
ATTS0
DTMIC
0030H
8000H
8000H
8000H
0000H
8000H
8008H
8008H
8808H
0000H
0200H
0000H
0300H
0001H
0000H
BB80H
BB80H
0000H
0103H
2D21H
0000H
0002H
X
ADFLT
MSR1
MSR0
DLY3
DLY2
DLY1
DLY0
1
0
0
0
0
0
GN4
IPGA4
GR4
ATTR4
0
0
0
0
0
SR4
SR4
PMBPM
DAMO
HPDT
ZTM0
ATS
0
ADMO
DE0
0
0
0
MOGN1
0
0
GN1
IPGA1
GR1
ATTR1
0
0
DAC
0
0
SR1
SR1
PMAUX
ALCS
DEM1
LTM1
ATTS1
DTHPJ
PM12AD
1
0
0
0
0
0
0
IPGA5
0
ATTR5
0
0
0
0
0
SR5
SR5
PMHPL
MICM
ATSW
ZTM1
0
0
ADMO
DE1
0
0
0
MOGN2
0
0
GN2
IPGA2
GR2
ATTR2
0
0
ANL
0
0
SR2
SR2
PMMO
BPMSP
TM0
WTM0
ATTS2
DTPEN
12bit ADC Control 1
0
0
0
0
0
0
0
MGAIN
0
ATTR6
0
0
0
0
0
SR6
SR6
PMHPR
MICL
ATPU
ROTM
0
0
ADEXE
0
0
0
0
0
0
0
GN3
IPGA3
GR3
ATTR3
0
0
0
0
0
SR3
SR3
PMLIN
BPMHP
TM1
WTM1
ATTM
0
70H
0
0
0
0
0
0
0
0
0
0
0
LOOP
0
0
0
SR7
SR7
PMSPK
AUXL
DATTC
0
0
0
ADEXE
1
A1
A0
SER
0001H
SLOTN
O1
D2
D2
D2
0
0
SLOTN
O0
D1
D1
D1
1
0
SLOT
9400H
D0
D0
D0
1
0
x
x
x
414BH
4D10H
72H
12bit ADC Control 2
74H
76H
78H
7CH
7EH
ADC Data 1
ADC Data 2
ADC Data 3
Vendor ID1
Vendor ID2
1
GINT
PENINT
PINTR
ADE
ADE
ADE
0
0
A2
A2
A2
1
1
A1
A1
A1
0
0
A0
A0
A0
0
0
PMVRE
F
D11
D11
D11
0
1
A2
PINTE
0
0
0
0
0
0
0
D10
D10
D10
0
1
D9
D9
D9
0
0
D8
D8
D8
1
1
D7
D7
D7
0
0
D6
D6
D6
1
0
D5
D5
D5
0
0
D4
D4
D4
0
1
D3
D3
D3
1
0
Table 57.
MS0502-J-01
2007/04
- 71 -
[AK4650]
■ Speaker Output (02H)
SPPS: Speaker Output
ON/OFF
0: Normal Operation
1: Power Save Mode (Default)
“1”
PMSPK bit = “1”
PMSPK bit = “0”
(Table 38)
SPP pin
Hi-Z SPN pin HVDD/2
RESETN pin = “↑”
■ Headphone Output (04H)
HPMT: Headphone Output
0: Mute OFF
1: Mute ON (Default)
ON/OFF
(Figure 26)
■ Mono Output (06H)
MOMT: Mono Output
0: Mute OFF
1: Mute ON (Default)
ON/OFF
MOGN2-0: MOUT Volume
Default: “000” (+6dB)
(Table 30)
(Table 31)
■ Boost Control (08H)
BST1-0:
Default: “00” (OFF)
(Table 24)
■ BEEP Volume (0AH)
BPMT: BEEP Input
0: Mute OFF
1: Mute ON (Default)
ON/OFF
■ Phone Volume (0CH)
AUXMT: AUX Input
0: Mute OFF
1: Mute ON (Default)
ON/OFF
GN4-0: AUX Input Volume
Default: “08H” (0dB)
(Table 28)
(Table 28)
■ MIC Volume (0EH)
MICMT: Mic Input
0: Mute OFF
1: Mute ON (Default)
MGAIN:
0: 0dB (Default)
1: +20dB
IPGA5-0: IPGA
Volume
ON/OFF
(Table 14)
(Table 10)
(Table 14)
MS0502-J-01
2007/04
- 72 -
[AK4650]
Default: “08H” (0dB)
MS0502-J-01
2007/04
- 73 -
[AK4650]
■ Line In Volume (10H)
LNMT: Line Input
0: Mute OFF
1: Mute ON (Default)
ON/OFF
(Table 29)
GL4-0: Lch Line Input Volume
Default: “08H” (0dB)
(Table 29)
GR4-0: Rch Line Input Volume
Default: “08H” (0dB)
(Table 29)
■ PCM Volume (18H)
SMUTE:
0: Normal Operation (Default)
1: DAC outputs soft-muted
ATT
(Figure 21)
ATTL/R6-0:
Default: “00H” (0dB)
(Table 25)
■ Record Select Control Register (1AH)
AUXAD: ADC
0: OFF (Default)
1: ON
AUX
MICAD: ADC
0: OFF
1: ON (Default)
ALC1
■ General Purpose (20H)
LOOP:
0: OFF (Default)
1: ON
LOOP bit = “1”
MSEL:
/
0: Internal MIC (Default)
1: External MIC
MDIF:
0:
1:
VRA bit = “0”
(Table 9 at MDIF bit = “0”)
(Table 9)
(Default)
MS0502-J-01
2007/04
- 74 -
[AK4650]
■ Power Management (26H)
PR6-0:
(Table 6)
Default: “0000011” (ADC, DAC Power down)
ANL:
0: NOT Ready
1: Ready
(Read only)
DAC: DAC
0: NOT Ready
1: Ready
(Read only)
ADC: ADC
0: NOT Ready
1: Ready
(Read only)
■ Extended Audio Status & Control (2AH)
VRA: Variable Sampling Rate
0: OFF (Default) PLL
1: ON
ON/OFF
■ Audio Sample Rate control Registers (2CH, 32H)
SR15-0: DAC(2CH), ADC(32H)
Default: “BB80H” (48kHz)
VRA bit = “1”
(Table 4, Table 5)
MS0502-J-01
2007/04
- 75 -
[AK4650]
■ Power Management (60H)
PMMIC:
(MIC-Amp, ALC1)
0: Power down (Default)
1: Power up
PMAUX: AUX Input
0: Power down (Default)
1: Power up
PMMO:
0: Power down (Default)
1: Power up
PMLIN:
0: Power down (Default)
1: Power up
PMBPM:
0: Power down (Default)
1: Power up
PMBPM bit = “0”
BEEP pin
HP-Amp
SPK-Amp
BPMHP bit = “0”, BPMSP bit = “0”
PMHPR: Rch
0: Power down (Default)
1: Power up
PMHPL: Lch
0: Power down (Default)
1: Power up
PMSPK:
0: Power down (Default)
1: Power up
MCKPD: XTI pin
0: Master Clock input enable (Default)
1: XTI pin is internally pulled-down
MPWRI: Internal MIC
0: OFF (Default)
1: Internal MIC
PMMIC bit = “1”
(Table 11)
MPWRE: External MIC
0: OFF (Default)
1: External MIC
PMMIC bit = “1”
(Table 12)
MS0502-J-01
2007/04
- 76 -
[AK4650]
■ Signal Select (62H)
MO2:
(MOUT2 pin)
0: OFF
1: ON (Default)
“0” VCOM
PMSPK bit = “0”
ALCS:
0: OFF
1: ON (Default)
“1”
Hi-Z
PMSPK bit = “1”
ALC2
BPMSP: BEEP pin
0: OFF (Default)
1: ON
BPMHP: BEEP pin
0: OFF (Default)
1: ON
DAMO: DAC
0: OFF (Default)
1: ON
MICM: IPGA
0: OFF (Default)
1: ON
MICL: IPGA
0: OFF (Default)
1: ON
AUXL: AUXIN
0: OFF (Default)
1: ON
DAHS: DAC
0: OFF
1: ON (Default)
LNMP: LIN/MPE pin
0: MPE pin (Default)
1: LIN pin
RNMD: RIN/MDT pin
0: MDT pin (Default)
1: RIN pin
INBP: IN2/BEEP pin
0: BEEP pin (Default)
1: IN2 pin
HPM:
0: Stereo (Default)
1: Mono [(L+R)/2]
Lch
Rch
(L+R)/2
MS0502-J-01
2007/04
- 77 -
[AK4650]
■ ALC/DAC Control (64H)
DEM1-0:
Default: “01” (OFF)
(Table 23)
TM1-0:
Default: “00” (1024/fs)
(Table 27)
HPDT:
0: OFF (Default)
1: ON
ON/OFF
ATSW:
(Table 35, Table 36)
0:
1:
OFF
ON (Default)
ATPU:
0:
1:
(Figure 38)
OFF (Default)
ON
DATTC:
0: Independent (Default)
1: Dependent
“0” Lch, Rch
“1”
ATTR6-0 bit
DATTC bit = “1”
REF5-0: ALC1
Default: “2DH” (+19dB)
ALC1
HPINT:
Default: “0” (OFF)
HPINT bit “1”
Lch ATT
ATTL6-0 bit
Rch
ATT
(Table 21)
IPGA
REF5-0 bit
INTN pin
INTN pin
Interrupt
■ ALC Control (66H)
LTM1-0: ALC1
Default: “00” (0.5/fs)
ALC1
(Table 17)
(ZELMN bit = “1”)
IPGA
WTM1-0: ALC1
Default: “00” (128/fs)
ALC1
ALC1
LTM1-0 bit
IPGA
(Table 19)
ZTM1-0: ALC1
Default: “00” (128/fs)
(Table 18)
ALC1
MS0502-J-01
2007/04
- 78 -
[AK4650]
ROTM: ALC2
0: 2048/fs (Default)
1: 512/fs
(Table 39)
LMTH: ALC1
Default: “0” (−6dB/−8dB)
ALC1
(
±2dB)
/
(Table 15)
RGAIN: ALC1
(Table 20)
Default: “0” (0.5dB)
ALC1
IPGA
IPGA
30H
RGAIN bit = “1”
1dB(=0.5dB x 2)
IPGA
(REF5-0 bit)
ALC1
32H
IPGA
LMAT1-0: ALC1
ATT
(Table 16)
Default: “00” (0.5dB)
ALC1
ALC1
IPGA
LMAT1-0 bit = “11”
ALC1
2dB(=0.5dB x4)
ALC1
LTM1-0 bit ZELMN bit
IPGA = “00H”(-8dB)
“00H”
ZELMN: ALC1
0: Enable (Default)
1: Disable
“0”
ALC1
IPGA
(LMTH)
IPGA
47H
IPGA
43H
IPGA
“1”
ALC1
IPGA
ALC1
ALC1: ALC1
0: ALC1 Disable (Default)
1: ALC1 Enable
ALC2: ALC2
0: ALC2 Disable (Default)
1: ALC2 Enable
(2048/fs=46.4ms@fs=44.1kHz)
PMSPK bit “0”
“1”
ALC2
■ Volume Control (68H)
ATTS2-0: IPGA
Stereo Mixer
Default: “2H” (−12dB)
(Table 7)
ATTM: IPGA
Mono Mixer
0: 0dB (Default)
1: −4dB
ATS:
Default: “0” (531/fs)
(Table 8)
(Table 26)
MS0502-J-01
2007/04
- 79 -
[AK4650]
■ Detect Result (6AH)
DTMIC:
MIC
0: Microphone isn’t detected.
1: Microphone is detected
(Read only, Table 13)
DTHPJ: Headphone
0:
1:
(Read only, Table 34)
Headset Jack
DTPEN: PM12AD bit = “0”, PENINT bit = “1”
(Read only)
0:
1:
PINTR bit = “1”
MS0502-J-01
PEN
2007/04
- 80 -
[AK4650]
■ 12bit ADC Control 1 (70H: Write Only)
A2-0, SER: 12bit ADC
Default: “0001” (N/A)
(Table 45)
ADMODE1-0: 12bit ADC
Default: “00” (74H Register Read)
ADEXE1-0: ADEXE
Default: “00” (Mode 0)
(Table 49, Table 51)
(Table 53)
DLY3-0:
ADC
Default: “0000” (1TS)
MSR1-0:
Default: “00” (4
(Table 47)
(Table 52)
)
ADFLT: 12bit ADC
0:
(Default)
1: 4
PM12AD:
0: Power Down (Default)
1: Power Up
(Table 48)
12bit ADC
MS0502-J-01
(Table 6)
2007/04
- 81 -
[AK4650]
■ 12bit ADC Control 2 (72H)
SLOT: 12bit ADC
0: Register (Default)
1: Slot
(Table 44)
SLOTNO1-0: 12bit ADC
Default: “00” (Slot 5)
(Table 50)
PINTE:
0: Power Down
1: Power Up (Default)
12bit ADC
(Table 46)
PMVREF:
0: Power Down (Default)
1: Power Up
PINTR:
Default: “1” (ON)
PINTR bit “1”
PENINT:
Default: “0” (OFF)
PENINT bit “1”
GINT:
Default: “0” (OFF)
AC-Link
(Table 46)
DTPEN bit
DTPEN bit
INTN pin
INTN pin
Interrupt
Slot
GINT bit
“1”
SDATAIN
Slot 12
Bit 0
■ 12bit ADC Data (74H, 76H, 78H)
ADE:
0:
1:
A2-0:
(Read only)
(Read only, Table 45)
D11-0: 12bit ADC
(Read only)
■ Vendor ID (7CH, 7EH)
“A(41H), K(4BH), M(4DH), 16(10H)” (Read only)
MS0502-J-01
2007/04
- 82 -
[AK4650]
AK4650
(AKD4650)
0.1u
2.2k
0.1u
2.2u
MIC Jack
0.1u
+
0.1u
10k
4.7n
10k
10u 0.1u
NC
IN2
AVDD
VCOM
AUXIN+
MPI
EXT
MPE
NC
VCOC1
VCOC2
AVSS
MVREF AUXIN−
INT
MDT
AIN
MICOUT
XP
TSVDD
YP
XN
YN
TSVSS
0.1u
MOUT− MOUT+
+
Touch
Screen
+
AK4650VG
HPL
HPR
HVSS
HVDD
47u
+ 47u
2.2k
4.7n
+
2.2k
Regulator
4.7u
2.7 ∼ 3.6V
10u
∼ 5V
Battery
0.1u
Internal MIC
2.2k
Figure 57
Headphone
Jack
0.1u 10u
IN1
VBAT
VREF
TEST2
NC
ADEXE
INTN
XTO
SDATA
OUT
DVSS2 SDATAIN SYNC
NC
DVDD1
XTI
DVSS1
BITCLK
SPP
SPN
MUTET
HDT
MOUT2
MIN
PLL1
TEST1
0.1u
+
4.7u
LCD
Driver
100k
DVDD2 RESETN
1u
8ohm
Speaker
0.1u
10
+
10u 0.1u
0.1u
24.576MHz
Controller
Note 47. AK4650
Note 48.
Digital Ground
Analog Ground
AVSS, DVSS, HVSS, TSVSS
Figure 57.
MS0502-J-01
2007/04
- 83 -
[AK4650]
1.
AVDD, DVDD, HVDD, TSVDD
AVDD, DVDD, HVDD, TSVDD
AVSS, DVSS, HVSS, TSVSS
PC
2.
VCOM
2.2μF
0.1μF
AVSS
VCOM pin
VREF pin
VCOM pin
3.
BEEP
AUX
(0.45 x AVDD)
0.6 x AVDD Vpp(typ)
fc=1/(2πRC)
AK4650
AUX
0.06 x AVDD Vpp(typ)
AVSS
BEEP,
DC
AVDD
4.
DAC
8000H(@16bit)
2’s
7FFFH(@16bit)
0.45 x AVDD
0.44 x AVDD
HVDD/2
MS0502-J-01
2007/04
- 84 -
[AK4650]
57pin BGA (Unit: mm)
5.0 ± 0.1
φ 0.05
A
57 - φ 0.3 ± 0.05
M S AB
9 8 7 65
4 3 2 1
4.0
5.0 ± 0.1
A
B
C
D
E
B
F
G
H
J
0.5
0.5
1.0MAX
0.25 ± 0.05
S
0.08 S
■
:
: BT
: SnAgCu
MS0502-J-01
2007/04
- 85 -
[AK4650]
4650
XXXX
XXXX: Date code (4 digit)
Pin #1 indication
Date (YY/MM/DD)
06/04/24
07/04/18
Revision
00
01
Reason
Page
Contents
29
MIC-ALC
Table 16. ALC1
ATT
ATT STEP: 1 Æ 0.5dB, 2 Æ 1.0dB, 3 Æ 1.5dB,
4 Æ 2.0dB
38
Table 30.
Mode:
45
Æ
A/D
Æ
47
(VREF)
Æ
49
Æ
76
80
MS0502-J-01
, VBAT, IN1, IN2
VBAT, IN1, IN2
Signal Select (62H)
HPM: “1:Mono” Æ “1:Mono [(L+R)/2]”
(Addr=70H)
A2-0, SER Default: “TEMP0
”
Æ “N/A”
2007/04
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[AK4650]
•
•
•
•
•
•
MS0502-J-01
2007/04
- 87 -