AKM AKD4534

ASAHI KASEI
[AK4534]
AK4534
16Bit ∆Σ CODEC with MIC/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4534 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo
CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4534 is available in a
52-QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution : 16bits
2. Recording Function
• 1ch Mono Input
• 1st MIC Amplifier : +20dB or 0dB
• 2nd Amplifier with ALC : +27.5dB ∼ -8dB, 0.5dB Step
• ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB
3. Playback Function
• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
• Digital Volume (0dB ∼ -127dB, 0.5dB Step, Mute)
• Headphone-Amp
- S/(N+D) : 70dB, S/N : 90dB
- Output Power : 15mW@16Ω (HVDD=3.3V)
• Mono Speaker-Amp with ALC
- S/(N+D) : 64dB@250mW, 20dB@300mW, S/N : 90dB
- BTL Output
- Output Power : 300mW@8Ω (THD=10%, HVDD=3.3V)
• Mono and Stereo Beep Inputs
• Mono Line Output
4. Power Management
5. Master Clock
(1) PLL Mode
• Frequencies : 11.2896MHz, 12MHz and 12.288MHz
• Input Level : CMOS
(2) External Clock Mode
• Frequencies : 2.048MHz ∼ 12.288MHz
6. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs
7. Sampling Rate
(1) PLL Mode
• 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
(2) External Clock Mode
• 8kHz ∼ 48kHz
8. Control mode: 4-wire Serial / I2C Bus
9. Master/Slave mode
10. Audio Interface Format : MSB First, 2’s compliment
• ADC : I2S, 16bit MSB justified
• DAC : I2S, 16bit MSB justified, 16bit LSB justified
11. Ta = -10 ∼ 70°C
MS0133-E-03
2003/5
-1-
ASAHI KASEI
[AK4534]
12. Power Supply: 2.4V ∼ 3.6V (typ. 3.3V)
13. Power Supply Current
• AVDD+DVDD : 16mA
• PVDD : 1.2mA
• HVDD (HP-AMP=ON, SPK-AMP=OFF) : 6.5mA
• HVDD (HP-AMP=OFF, SPK-AMP=ON) : 9mA
14. Package : 52pin QFN
n Block Diagram
M/S
MICOUT
AVSS AVDD
AIN
PMMIC
MPE
MIC Pow er
Supply
CAD0
MPI
MIC Pow er
Supply
PMADC
ALC1
(IPGA)
INT
ADC
HPF
MIC-AMP
0dB or 20dB
EXT
PDN
Audio
Interface
PMDAC
PMMO
LRCK
BICK
MOUT+
MIX
DAC
MOUT-
DATT
SMUTE
SDTO
SDTI
I2C
DSP
and
uP
CSN/CAD1
HVDD
HVSS
Control
Register
PMHPL
HPL
HP-AMP
MIX
CCLK/SCL
CDTI/SDA
CDTO
PMHPR
PMPLL
HPR
HP-AMP
PMXTL
XTO
MIX
PLL
XTI/MCKI
PMSPK
SPP
SPKAMP
ALC2
PVDD
PVSS
MIX
MIX
MCKO
SPN
PMBPS
VCOC
PMBPM
VCOM
MUTET
DVSS DVDD
MIN
BEEPL
BEEPR
BEEPM
MOUT2
Block Diagram
MS0133-E-03
2003/5
-2-
ASAHI KASEI
[AK4534]
n Ordering Guide
−10 ∼ +70°C
52pin QFN (0.4mm pitch)
Evaluation board for AK4534
AK4534VN
AKD4534
MIN
MOUT2
TST2
TST3
MOUT-
MOUT+
TST4
TST5
BEEPM
BEEPR
BEEPL
AIN
NC
n Pin Layout
52 51 50 49 48 47 46 45 44 43 42 41 40
MICOUT
1
39
MUTET
TST1
2
38
HPL
EXT
3
37
HPR
MPE
4
36
HVSS
MPI
5
35
HVDD
INT
6
34
SPN
VCOM
7
33
SPP
AVSS
8
32
M/S
AVDD
9
31
XTI/MCKI
PVDD
10
30
XTO
PVSS
11
29
DVSS
VCOC
12
28
DVDD
NC
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
AK4534VN
MS0133-E-03
NC
NC
MCKO
BICK
LRCK
SDTO
SDTI
I2C
CDTO
CDTI/SDA
CCLK/SCL
CSN/CAD1
PDN
CAD0
Top View
2003/5
-3-
ASAHI KASEI
[AK4534]
PIN/FUNCTION
No.
Pin Name
I/O
1
2
3
4
5
6
MICOUT
TST1
EXT
MPE
MPI
INT
O
I
O
O
I
7
VCOM
O
8
9
10
11
AVSS
AVDD
PVDD
PVSS
-
12
VCOC
O
13
14
NC
CAD0
I
15
PDN
I
19
CSN
CAD1
CCLK
SCL
CDTI
SDA
CDTO
20
I2C
21
22
23
24
25
26
SDTI
SDTO
LRCK
BICK
MCKO
NC
16
17
18
I
I
I
I
I
I/O
O
I
I
O
I/O
I/O
O
-
Function
Microphone Analog Output Pin
Test Pin. This pin should be open.
External Microphone Input Pin (Mono Input)
MIC Power Supply Pin for External Microphone
MIC Power Supply Pin for Internal Microphone
Internal Microphone Input Pin (Mono Input)
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Analog Ground Pin
Analog Power Supply Pin
PLL Power Supply Pin
PLL Ground Pin
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to PVSS with one resistor and capacitor in series.
No Connect. No internal bonding.
Chip Address 0 Select Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Chip Select Pin (I2C = “L”)
Chip Address 1 Select Pin (I2C = “H”)
Control Data Clock Pin (I2C = “L”)
Control Data Clock Pin (I2C = “H”)
Control Data Input Pin (I2C = “L”)
Control Data Input Pin (I2C = “H”)
Control Data Output Pin (I2C = “L”)
Control Mode Select Pin
“H”: I2C Bus, “L”: 4-wire Serial
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Input / Output Channel Clock Pin
Audio Serial Data Clock Pin
Master Clock Output Pin
No Connect. No internal bonding.
MS0133-E-03
2003/5
-4-
ASAHI KASEI
27
28
29
30
[AK4534]
NC
DVDD
DVSS
XTO
XTI
MCKI
O
I
I
32
M/S
I
33
34
35
36
37
38
SPP
SPN
HVDD
HVSS
HPR
HPL
O
O
O
O
39
MUTET
O
40
41
42
43
44
45
46
47
48
49
50
51
52
MIN
MOUT2
TST2
TST3
MOUT−
MOUT+
TST4
TST5
BEEPM
BEEPR
BEEPL
AIN
NC
I
O
O
O
I
I
I
I
-
31
No Connect. No internal bonding.
Digital Power Supply Pin
Digital Ground Pin
X’tal Output Pin
X’tal Input Pin
External Master Clock Input Pin
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Speaker Amp Positive Output Pin
Speaker Amp Negative Output Pin
Headphone Amp Power Supply Pin
Headphone Amp Ground Pin
Rch Headphone Amp Output Pin
Lch Headphone Amp Output Pin
Mute Time Constant Control Pin
Connected to HVSS pin with a capacitor for mute time constant.
ALC Input Pin
Analog Mixing Output Pin
Test Pin. This pin should be open.
Test Pin. This pin should be open.
Mono Line Negative Output Pin
Mono Line Positive Output Pin
Test Pin. This pin should be open.
Test Pin. This pin should be open.
Mono Beep Signal Input Pin
Rch Stereo Beep Signal Input Pin
Lch Stereo Beep Signal Input Pin
Analog Input Pin
No Connect. No internal bonding.
Note: All input pins except analog input pins (INT, EXT, AIN, MIN, BEEPM, BEEPL, and BEEPR) should not be left
floating.
MS0133-E-03
2003/5
-5-
ASAHI KASEI
[AK4534]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS, HVSS=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
PLL
Headphone-Amp / Speaker-Amp
|AVSS – PVSS|
(Note 2)
|AVSS – DVSS|
(Note 2)
|AVSS – HVSS|
(Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
PVDD
HVDD
∆GND1
∆GND2
∆GND3
IIN
VINA
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−10
−65
max
4.6
4.6
4.6
4.6
0.3
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
70
150
Units
V
V
V
V
V
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS, PVSS and HVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS, HVSS=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
PLL
HP / SPK-Amp
Symbol
AVDD
DVDD
PVDD
HVDD
min
2.4
2.4
2.4
2.4
typ
3.3
3.3
3.3
3.3
max
3.6
AVDD
AVDD
AVDD
Units
V
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, DVDD, HVDD and PVDD is not critical.
It is recommended that DVDD and PVDD are the same voltage as AVDD in order to reduce the current at power
down mode.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0133-E-03
2003/5
-6-
ASAHI KASEI
[AK4534]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=PVDD=HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier
Input Resistance
20
30
40
kΩ
Gain
(MGAIN bit = “0”)
0
dB
(MGAIN bit = “1”)
20
dB
MIC Power Supply
Output Voltage
(Note 4)
2.22
2.47
2.72
V
Output Current
1.25
mA
Input PGA Characteristics:
Input Resistance (Note 5)
5
10
15
kΩ
Step Size
0.1
0.5
0.9
dB
Gain Control Range
+27.5
dB
−8
ADC Analog Input Characteristics: MIC Gain=20dB, IPGA=0dB, ALC1=OFF, MIC → IPGA → ADC
Resolution
16
Bits
Input Voltage (MIC Gain=20dB, Note 6)
0.168
0.198
0.228
Vpp
71
79
dB
S/(N+D)
(−1dBFS)
75
83
dB
D-Range
(−60dBFS, A-weighted)
S/N
(A-weighted)
75
83
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: RL=20kΩ, DAC → MOUT+/MOUT3.56
3.96
4.36
Vpp
Output Voltage (Note 7)
79
89
dBFS
S/(N+D)
(−3dBFS)
85
95
dB
S/N
(A-weighted)
20
Load Resistance
kΩ
30
pF
Load Capacitance
Headphone-Amp Characteristics: RL=22.8Ω, DAC → HPL/HPR, DATT=0dB
1.54
1.92
2.30
Vpp
Output Voltage (Note 8)
60
70
dB
S/(N+D)
(−3dBFS)
S/N
(A-weighted)
80
90
dB
70
85
dB
Interchannel Isolation
0.1
0.5
dB
Interchannel Gain Mismatch
Load Resistance
20
Ω
Load Capacitance
(C1 of Figure 1)
30
pF
300
pF
(C2 of Figure 1)
Speaker-Amp Characteristics: RL=8Ω, BTL, DAC → MOUT2 → MIN → SPP/SPN, ALC2=OFF
Output Voltage
(Note 9)
2.37
2.96
3.55
Vpp
S/(N+D)
50
64
dB
82
90
dB
S/N
(A-weighted)
Load Resistance
8
Ω
Load Capacitance
30
pF
BEEP Input: BEEPL, BEEPR, BEEPM pin
1.98
Vpp
Maximum Input Voltage (Note 10)
14
20
26
Feedback Resistance
kΩ
Mono Input: MIN pin
1.98
Vpp
Maximum Input Voltage (Note 11)
Input Resistance
(Note 12)
12
24
36
kΩ
MS0133-E-03
2003/5
-7-
ASAHI KASEI
[AK4534]
Parameter
Mono Output: RL=10kΩ, DAC → MIX → MOUT2
Output Voltage
(Note 13)
Load Resistance
Load Capacitance (Note 14)
Power Supplies
Power Up (PDN = “H”)
AVDD+DVDD
(Note 15)
PVDD
HVDD: HP-AMP Normal Operation
No Output
(Note 16)
HVDD: SPK-AMP Normal Operation
No Output
(Note 17)
Power Down (PDN = “L”) (Note 18)
AVDD+DVDD
PVDD
HVDD
min
typ
max
Units
30
Vpp
kΩ
pF
16
1.2
26
2
mA
mA
6.5
10
mA
9
18
mA
10
10
10
100
100
100
µA
µA
µA
1.94
10
Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD.
Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.
Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD.
Note 7. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD at Full-differential output.
Vout = 0.6 x AVDD at Single-end Output
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.582 x AVDD.
Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.897 x AVDD at Full-differential output.
Note 10. BEEP-AMP can’t output more than this maximum voltage.
Note 11. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD.
Note 12. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.
Note 13. Output Voltage is proportional to AVDD voltage. Vout = 0.588 x AVDD.
Note 14. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and
capacitive load.
Note 15. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM
=PMBPS=“1”,MCKO=”1” and Master Mode. AVDD : 10mA (typ.), DVDD : 6mA (typ.)
AVDD : 10mA (typ.), DVDD : 4mA (typ.) at MCKO= “0” in Slave Mode
Note 16. PMMIC=PMADC=PMDAC=PMMO=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM
=PMBPS=“1”, PMSPK=“0”.
Note 17. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMVCM=PMPLL=PMXTL=PMBPM=PMBPS=“1”
PMHPL=PMHPR=“0”.
Note 18. All digital input pins are fixed to DVDD or DVSS.
HP-Amp
HPL/HPR pin
47µF
> 6.8Ω
C1
C2
16Ω
Figure 1. Headphone-amp output circuit
MS0133-E-03
2003/5
-8-
ASAHI KASEI
[AK4534]
FILTER CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 19) ±0.1dB
PB
0
−1.0dB
20.0
−3.0dB
21.1
Stopband
SB
27.0
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay
(Note 20)
GD
17.0
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response
−3.0dB
FR
3.4
(Note 19)
−0.5dB
10
−0.1dB
22
DAC Digital Filter:
Passband
(Note 19) ±0.1dB
PB
0
−6.0dB
22.05
Stopband
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
43
Group Delay
(Note 20)
GD
16.8
DAC Digital Filter + SCF:
Frequency Response: 0 ∼ 20.0kHz
FR
±0.5
BOOST Filter:
(Note 21)
5.74
FR
Frequency Response
MIN
20Hz
2.92
100Hz
0.0
1kHz
5.94
FR
MID
20Hz
4.71
100Hz
0.14
1kHz
16.04
FR
MAX 20Hz
10.55
100Hz
0.3
1kHz
max
Units
17.4
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.1
Hz
Hz
Hz
20.0
±0.06
kHz
kHz
kHz
dB
dB
1/fs
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 19. The passband and stopband frequencies scale with fs (system sampling rate).
For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.01dB).
Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of both channels from the input register to the output register of the ADC. This time includes the
group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input
register to the output of analog signal.
Note 21. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips
to the full-scale.
MS0133-E-03
2003/5
-9-
ASAHI KASEI
[AK4534]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V)
Parameter
Symbol
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
VAC
Input Voltage at AC Coupling
(Note 22)
VOH
High-Level Output Voltage
(Iout=−200µA)
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200µA)
VOL
(
SDA pin: Iout= 3mA)
Input Leakage Current
Iin
min
70%DVDD
50%DVDD
DVDD−0.2
typ
-
Max
30%DVDD
-
Units
V
V
V
V
-
-
0.2
0.4
±10
V
V
µA
Note 22. When AC coupled capacitor is connected to MCKI pin.
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator
External Clock
MCKO Output
LRCK Frequency
Frequency
Duty Cycle
Frequency
Frequency
Pulse Width Low
Pulse Width High
AC Pulse Width (Note23)
Frequency
Duty Cycle : except fs=32kHz
fs=32kHz at 256fs (Note 24)
Slave mode
Master mode
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 25)
BICK “↑” to LRCK Edge
(Note 25)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fCLK
tCLKL
tCLKH
tACW
fMCK
dMCK
dMCK
11.2896
2.048
0.4/fCLK
0.4/fCLK
0.4/fCLK
0.256
40
fs
Duty
Duty
8
45
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
312.5
130
130
50
50
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
typ
max
Units
-
12.288
12.288
MHz
MHz
ns
ns
ns
MHz
%
%
50
33
12.288
60
48
55
50
80
80
50
50
−80
−80
50
50
64fs
50
80
80
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 2)
Note 24. PMPLL bit = “1”.
Note 25. BICK rising edge must not occur at the same time as LRCK edge.
MS0133-E-03
2003/5
- 10 -
ASAHI KASEI
[AK4534]
Parameter
Control Interface Timing (4-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 26)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
PMADC “↑” to SDTO valid
(Note 27)
(Note 28)
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
tPD
tPDV
150
typ
2081
max
Units
50
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
1/fs
Note 26. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 27. The AK4534 can be reset by the PDN pin = “L”.
Note 28. This is the count of LRCK “↑” from the PMADC bit = “1”.
2
2
Purchase of Asahi Kasei Microsystems Co., Ltd I C components conveys a license under the Philips I C
2
2
patent to use the components in the I C system, provided the system conform to the I C specifications
defined by Philips.
MS0133-E-03
2003/5
- 11 -
ASAHI KASEI
[AK4534]
n Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
dMCK
dMCK
Clock Timing
1/fCLK
tACW
1000pF
MCKI Input
tACW
Measurement Point
100kΩ
AGND
VAC
AGND
Figure 2. MCKI AC Coupling Timing
MS0133-E-03
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ASAHI KASEI
[AK4534]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (Slave mode)
VIH
LRCK
VIL
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (Master mode)
MS0133-E-03
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ASAHI KASEI
[AK4534]
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Hi-Z
CDTO
WRITE/READ Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
CDTO
Hi-Z
WRITE Data Input Timing
MS0133-E-03
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ASAHI KASEI
[AK4534]
VIH
CSN
VIL
VIH
CCLK
VIL
VIH
CDTI
A1
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
50%DVDD
READ Data Output Timing 1
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%DVDD
READ Data Output Timing 2
MS0133-E-03
2003/5
- 15 -
ASAHI KASEI
[AK4534]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Start
Stop
2
I C Bus Mode Timing
VIH
CSN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Power Down & Reset Timing
MS0133-E-03
2003/5
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ASAHI KASEI
[AK4534]
OPERATION OVERVIEW
n Master Clock Source
The AK4534 requires a master clock (MCLK). This master clock is input to the AK4534 by connecting a X’tal oscillator
to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is
greater than 50% of the DVDD level to the XTI pin through a capacitor.
When using a X’tal oscillator, there should be capacitors between XTI/XTO pins and DVSS. When using an external
clock, there are two choices: direct, where an external clock is input directly to the XTI pin and indirect, where the external
clock is input through a capacitor.
Master Clock
X’tal Oscillator
Status
PMXTL bit
(Figure 3)
Oscillator ON
1
Oscillator OFF
0
External Clock Direct Input (Figure 4)
Clock is input to MCKI pin.
0
MCKI pin is fixed to “L”.
0
MCKI pin is fixed to “H”.
0
MCKI pin is Hi-Z
0
AC Coupling Input
(Figure 5)
Clock is input to MCKI pin.
1
Clock isn’t input to MCKI pin.
0
Table 1. Master Clock Status by PMXTL bit and MCKPD bit
MCKPD bit
0
1
0
0/1
0
1
0
1
(1) X’tal Oscillator
XTI
MCKPD = "0"
C
25kΩ
PMXTL = "1"
C
XTO
AK4534
Figure 3. X’tal mode
- Note: The capacitor values depend on the X’tal oscillator used. (C : typ. 10 ∼ 30pF)
MS0133-E-03
2003/5
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ASAHI KASEI
[AK4534]
(2) External Clock Direct Input
XTI
External
Clock
MCKPD = "0"
25kΩ
PMXTL = "0"
XTO
AK4534
Figure 4. External Clock mode (Input : CMOS Level)
- Note: This clock level must not exceed DVDD level.
(3) AC Coupling Input
C
XTI
External
Clock
MCKPD = "0"
25kΩ
PMXTL = "1"
XTO
AK4534
Figure 5. External Clock mode (Input : ≥ 50%DVDD)
- Note: This clock level must not exceed DVDD level. (C : 0.1µF)
MS0133-E-03
2003/5
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ASAHI KASEI
[AK4534]
n System Clock
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table.2 and Table.3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table.4
and the MCKO output enable is controlled by the MCKO bit. If PS1-0 bits are changed before LRCK is input,
MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted. If X'tal and
PLL are powered-up at the same time or PLL is powered-up before external master clock is inputted,
the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. The PLL needs 40ms
lock time, whenever the sampling frequency changes or the PLL is powered-up (PMPLL bit=“0” → “1”).
If the sampling frequency is changed and the PLL goes to unlock state when the DAC is operated(PMDAC bit=“1”), the
DAC data should be soft-muted or “0”. In case of the ADC(PMADC bit = “1”), the ADC data acquired during the
frequency change may be erroneous and therefore should not be used.
LRCK and BICK are output from the AK4534 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to “L”
(see Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present whenever
the AK4534 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4534 may draw
excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the
AK4534 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
0
1
2
3
FS2
0
0
0
0
1
1
1
1
PLL1
PLL0
MCKI
0
0
12.288MHz
0
1
11.2896MHz
1
0
12MHz
1
1
N/A
Table 2. MCKI Input Frequency (PLL Mode)
FS1
FS0
Default
Sampling Frequency
0
0
44.1kHz
0
1
22.05kHz
1
0
11.025kHz
1
1
48kHz
0
0
32kHz
0
1
24kHz
1
0
16kHz
1
1
8kHz
Table 3. Sampling Frequency (PLL Mode)
Default
Mode
PS1
PS0
MCKO
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
MS0133-E-03
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ASAHI KASEI
[AK4534]
MCKI pin
MCKO pin
BICK pin
LRCK pin
MCKI pin
MCKO pin
BICK pin
LRCK pin
Master Mode (M/S pin = “H”)
Power up
Power down
PLL Unlock
Frequency set by PLL1-0
Frequency set by PLL1-0 bits
Refer to Table 1
bits (Refer to Table 2)
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “0” : “L”
“L”
MCKO bit = “1” : Output
MCKO bit = “1” : Unsettling
BF bit = “0” : 64fs Output
“L”
“L”
BF bit = “1” : 32fs Output
Output
“L”
“L”
Table 5. Clock Operation at Master Mode (PLL Mode)
Slave Mode (M/S pin = “L”)
Power up
Power down
PLL Unlock
Frequency set by PLL1-0
Frequency set by PLL1-0 bits
Refer to Table 1
bits (Refer to Table 2)
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “0” : “L”
“L”
MCKO bit = “1” : Output
MCKO bit = “1” : Unsettling
Input
Fixed to “L” or “H” externally
Input
Input
Fixed to “L” or “H” externally
Input
Table 6. Clock Operation at Slave Mode (PLL Mode)
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4534 works in external clock mode. The MCKO pin outputs a buffered clock of MCKI
input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 8kHz to 48kHz (Table 7).
The MCKO bit controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined
in Table.8. If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be
changed after LRCK is input in slave mode. The master clock frequency should be changed only when both the
PMADC and PMDAC bits = “0”.
LRCK and BICK are output from the AK4534 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMPLL bit = “1”). If this clock is not provided, the AK4534 may draw excess current due to its use of internal
dynamically refreshed logic. If the external clocks are not present, place the AK4534 in power-down mode (PMADC bit =
PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4534 is in normal operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided,
the AK4534 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4534 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
0
1
2
3
FS1
0
0
1
1
FS0
Sampling Frequency (fs)
0
8kHz ∼ 48kHz
1
8kHz ∼ 24kHz
0
8kHz ∼ 12kHz
1
8kHz ∼ 48kHz
Table 7. Sampling Frequency Select (EXT Mode)
MS0133-E-03
MCKI
256fs
512fs
1024fs
256fs
Default
2003/5
- 20 -
ASAHI KASEI
[AK4534]
Mode
PS1
PS0
MCKO
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 8. MCKO Frequency (EXT Mode, MCKO bit = “1”)
Master Mode (M/S pin = “H”)
Power up
Power down
MCKO bit = “0” : “L”
MCKO pin
“L”
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BICK pin
“L”
BF bit = “1” : 32fs Output
LRCK pin
Output
“L”
Table 9. Clock Operation at Master Mode (EXT Mode)
Slave Mode (M/S pin = “L”)
Power up
Power down
MCKO bit = “0” : “L”
MCKO pin
“L”
MCKO bit = “1” : Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
Fixed to “L” or “H” externally
Table 10. Clock Operation at Slave Mode (EXT Mode)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through Headphone amp at fs=8kHz is shown in Table 11.
MCLK
S/N (fs=8kHz, A-weighted)
256fs
84dB
512fs
88dB
1024fs
88dB
Table 11. Relationship between MCLK and S/N of HP-AMP
n Master Mode/Slave Mode
The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The
AK4534 outputs MCKO, BICK and LRCK in master mode. The AK4534 outputs only MCKO in slave mode, while BICK
and LRCK must be input separately.
MCKO
BICK / LRCK
BICK = Input
Slave Mode
MCKO = Output
LRCK = Input
BICK = Output
Master Mode
MCKO = Output
LRCK = Output
Table 12. Master mode/Slave mode
MS0133-E-03
2003/5
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ASAHI KASEI
[AK4534]
n System Reset
Upon power-up, reset the AK4534 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle
time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are
forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete.
The DAC does not require an initialization cycle.
n Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits. In all modes, the serial data is MSB
first, 2’s complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising
edge. All data formats can be used in both master and slave modes. LRCK and BICK are output from AK4534 in master
mode, but must be input to AK4534 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit data by removing
LSB 8-bit, −1 at 16bit data is converted to −1 at 8-bit data. And when the DAC playbacks this 8-bit data, −1 at 8-bit data
will be converted to −256 at 16-bit data and this is a large offset. This offset can be removed by adding the offset of 128 to
16-bit data before converting to 8-bit data.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
SDTI (DAC)
MSB justified
LSB justified
MSB justified
MSB justified
I2 S
I2 S
N/A
N/A
Table 13. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
N/A
Figure
Figure 6
Figure 7
Figure 8
-
Default
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
15 16 17 18
15
7 6 5 4 3 2 1 0 15
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
15 14 13
1 0
Don't Care
15
15 14
1 0
Don't Care
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 0 Timing
MS0133-E-03
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ASAHI KASEI
[AK4534]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
15 16 17 18
15
31 0 1 2 3
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
15
Don't Care
15 14 13
1 0
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
SDTI(i)
15 14
0 15 14
0 1 2 3
8 7 6 5 4 3 2 1 0
8 7 6 5 4 3 2 1 0 15 14
15 16 17 18
31 0 1 2 3
8 7 6 5 4 3 2 1 0
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. Mode 2 Timing
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.4Hz
(@fs=44.1kHz) and scales with sampling rate (fs).
MS0133-E-03
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ASAHI KASEI
[AK4534]
n MIC Gain Amplifier
AK4534 has a Gain Amplifier for Microphone input. This gain is 0dB or 20dB, selected by the MGAIN bit. The typical
input impedance is 30kΩ.
MGAIN bit
Input Gain
0
0dB
1
+20dB
Table 14. Input Gain
Default
n MIC Power
The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the maximum
output current is 1.25mA.
MS0133-E-03
2003/5
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ASAHI KASEI
[AK4534]
n Manual Mode
The AK4534 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.
1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)
2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.
For example; When the change of the sampling frequency.
3. When IPGA is used as a manual volume.
When writing to the IPGA6-0 bits continually, the control register should be written by an interval more than zero crossing
timeout.
n MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.
[1] ALC1 Limiter Operation
When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is
attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.
When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously
until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after completing the
attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH.
When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation
function so that the IPGA value is attenuated at the zero-detect points of the waveform.
[2] ALC1 Recovery Operation
The ALC1 recovery refers to the amount of time that the AK4534 will allow a signal to exceed a predetermined limiting
value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period
used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting Counter
Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the
reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is
detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation
starts.
During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the
ALC1 recovery operation changes immediately into an ALC1 limiter operation.
In the case of “(Recovery waiting counter reset level) ≤ IPGA Output Level < Limiter detection level” during the ALC1
recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of “(Recovery waiting
counter reset level) > IPGA Output Level”, the wait timer for the ALC1 recovery operation starts.
The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation
becomes faster than a normal recovery operation.
MS0133-E-03
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ASAHI KASEI
[AK4534]
[3] Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
fs=8kHz
Data Operation
1
-4dBFS
00
Don’t use
0
Enable
00
16ms
fs=16kHz
Data Operation
1
-4dBFS
00
Don’t use
0
Enable
01
16ms
Register Name
Comment
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data 00
16ms
01
as ZTM1-0 bits
Maximum gain at recovery operation
47H +27.5dB 47H
Gain of IPGA at ALC1 operation start 10H
0dB
10H
Limiter ATT Step
00
1 step
00
Recovery GAIN Step
0
1 step
0
ALC1 Enable bit
1
Enable
1
Table 15. Example of the ALC1 setting
WTM1-0
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
fs=44.1kHz
Data Operation
1
-4dBFS
00
Don’t use
0
Enable
10
11.6ms
16ms
10
11.6ms
+27.5dB
0dB
1 step
1 step
Enable
47H
10H
00
0
1
+27.5dB
0dB
1 step
1 step
Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
Manual Mode
ALC2 bit = “1” (default)
WR (ZTM1-0, WTM1-0, LTM1-0)
(1) Addr=08H, Data=00H
WR (REF6-0)
(2) Addr=0AH, Data=47H
WR (IPGA6-0)
* The value of IPGA should be
(3) Addr=0BH, Data=10H
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
(4) Addr=09H, Data=61H
ALC1 Operation
Note : WR : Write
Figure 9. Registers set-up sequence at ALC1 operation
MS0133-E-03
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ASAHI KASEI
[AK4534]
n De-emphasis Filter
The AK4534 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter.
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
Default
0
48kHz
1
32kHz
Table 16. De-emphasis Control
n Bass Boost Function
The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal. If the BST1-0 bits are set to
“10” (MID Level), use a 47µF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips
to the full scale. Figure 10 shows the boost frequency response at –20dB signal input.
Boost Frequency (fs=44.1kHz)
Output Level [dB]
0
MAX
-5
-10
MID
-15
-20
MIN
-25
0.01
0.1
1
10
Frequency [kHz]
Figure 10. Boost Frequency (fs=44.1kHz)
BST1
BST0
Mode
0
0
OFF
Default
0
1
MIN
1
0
MID
1
1
MAX
Table 17. Low Frequency Boost Control
MS0133-E-03
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ASAHI KASEI
[AK4534]
n Digital Attenuator
The AK4534 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each
channel can be set by the ATTL/R7-0 bits (Table 18). When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and
Rch attenuation levels. When the DATTC bit = “0”, the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch
level. This attenuator has a soft transition function. It takes 1061/fs from 00H to FFH.
ATTL/R7-0
Attenuation
00H
0dB
Default
01H
−0.5dB
02H
−1.0dB
03H
−1.5dB
:
:
:
:
FDH
−126.5dB
FEH
−127.0dB
FFH
MUTE (−∞)
Table 18. DATT Code Table
n Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to a “1”, the output signal is attenuated
by -∞ (“0”) during the cycle set by the TM1-0 bits. When the SMUTE bit is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to 0dB during the cycle set of the TM1-0 bits. If the soft mute is cancelled within the
cycle set by the TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute
is effective for changing the signal source without stopping the signal transmission.
The soft mute function is independent of output volume and cascade connected between both functions.
SMUTE bit
T M 1-0 bit
0dB
T M 1-0 bit
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 11. Soft Mute Function
NOTE:
(1) The output signal is attenuated until -∞ (“0”) by the cycle set by the TM1-0 bits.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle of setting the TM1-0 bits, the attenuation is discounted and returned to
0dB(the set value).
MS0133-E-03
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ASAHI KASEI
[AK4534]
n BEEP Input
When the PMBPS bit is set to “1”, the stereo beep input is powered up. And when the BPSHP bit is set to “1”, the input
signals from the BEEPL and BEEPR pins are mixed to Headphone outputs. When the BPSSP bit is set to “1”, the signal of
(BEEPL + BEEPR)/2 is input to Speaker-amp. When the PMBPM bit is set to “1”, mono beep input is powered up. And
when the BPMHP bit is set to “1”, the input signal from the BEEPM pin to Headphone-amp. When the BPMSP bit is set to
“1”, the signal from the BEEPM pin is input to Speaker output. The external resisters Ri adjust the signal level of each
BEEP input that are mixed to Headphone and Speaker outputs.
The signal from the BEEPM pin is mixed to the Headphone-amp through a –20dB gain stage. The signal from the BEEPM
pin is mixed to the Speaker-amp without gain. The internal feedback resistance is 20k ± 30%Ω.
Rf = 20kΩ
Ri
BPSHP
BEEPL
HPL
MIX
BPMHP
Rf = 20kΩ
-20dB
Ri
HPR
MIX
BEEPR
BPSHP
BPSSP
Rf = 20kΩ
SPK
MIX
Ri
BEEPM
BPMSP
AK4534
Figure 12. Block Diagram of BEEP pins
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ASAHI KASEI
[AK4534]
n Headphone Output
Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The
Headphone output load resistance is min.20Ω. When the HPL and HPR bits are “1”, output signals are muted and the HPL
and HPR pins output HVDD/2 voltage. When the HPL and HPR bits are “0”, the Headphone-amps are in normal
operation. When the PMHPL and PMHPR bits are “0”, the Headphone-amp is powered down and the outputs (HPL and
HPR pins) go to “L” (HVSS). A capacitor between the MUTET pin and ground reduces pop noise at power-up.
[Example] : A capacitor between the MUTET pin and ground = 1.0µF, a capacitor between the HPL (HPR) pin and
Headphone = 47µF
Time constant of rise time: τr = 100ms, Time constant of fall time: τf = 188ms
PMHPL/R bits
HPL/R pins
(1)
τr
(2)
τf
Figure 13. Power-up/Power-down Timing for Headphone-amp
Note: The HPL and HPR bits should be kept to “0” during power-up.
(1) PMHPL and PMHPR bits = “1”
Headphone-amp is powered up. Common voltage of Headphone-amp is rising. This rise time depends on the capacitor
value connected with the MUTET pin. The time constant is τr = 100k x C when the capacitor value on MUTET pin is
“C”.
(2) PMHPL and PMHPR bits = “0”
Headphone-amp is powered down. Common voltage is falling. This fall time depends on the internal resistor and the
capacitor value of HPL/R pins. The time constant is τf = 2k x (2 x C) when the capacitor value on HPL(HPR) pin is “C”.
If the power supply is powered off or Headphone-Amp is powered-up again before the common voltage goes to GND,
some POP noise occurs. It takes 5times of τf that the common voltage goes to GND.
The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 19 shows the
cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp).
When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF+10Ω) because it has the
possibility that Headphone-amp oscillates.
HP-AMP
AK4534
R
C
0.22µ
Headphone
16Ω
10Ω
Figure 14. External Circuit Example of Headphone
R [Ω]
C [µF]
6.8
16
6.8
16
47
47
100
100
fc [Hz]
BOOST=OFF
fc [Hz]
BOOST=MID
2.7V
148.5
60
10.1
105.8
43
5.1
69.8
26
10.1
49.7
20
5.1
Table 19. External Circuit Example
MS0133-E-03
Output Power [mW]
3.0V
12.5
6.3
12.5
6.3
3.3V
15.0
7.7
15.0
7.7
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ASAHI KASEI
[AK4534]
n Speaker Output
Mono signal [(L+R)/2] converted from stereo DAC output and BEEP input signal can be output via Speaker-amp which is
controlled by BTL. ALC2 circuit is available for DAC output signal. This Speaker-amp can deliver a maximum power of
300mW(typ)@THD=10%, 250mW(typ)@THD=0.1% into 8 ohm load at HVDD=3.3V. Maximum output power is
137mW(typ) when DAC output signal is output via ALC2 circuit as system design example (Figure 31). When BEEP input
is used for DAC output, maximum power becomes 300mW. Figure 16 and Figure 17 indicates connection examples for
300mW output.
Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT2, SPP and SPN pins are placed in a Hi-Z state.
When the SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and
the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this
mode can reduce pop noise at power-up. When the AK4534 is powered down, pop noise can be also reduced by first
entering power-save-mode.
PMSPK bit
SPPS bit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
Hi-Z
Figure 15. Power-up/Power-down Timing for Speaker-amp
[Connection Example for 300mW output]
1)
Using BEEPM pin
20k
± 30%
AK4534
SPK-Amp
SPP
BPMSP
SPN
MOUT2
45%AVDD
0.047u
13k
BEEPM
Figure 16. Connection example for 300mW output using BEEPM pin
MS0133-E-03
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ASAHI KASEI
2)
[AK4534]
Using BEEPL and BEEPR pins
20k
± 30%
AK4534
BPSSP
SPK-Amp
45%AVDD
SPP
20k
± 30%
SPN
BPSSP
45%AVDD
MOUT2
0.1u
15k
BEEPL
BEEPR
15k
Figure 17. Connection example for 300mW output using BEEPL and BEEPR pins
Note)
1. MOUT2 output is recommended to be AC coupled to avoid amplified DC offset of common voltage of MOUT2 and
BEEP-Amp is output via BTL Speaker-Amp (that means stand-by current is increased). Capacitor size affects the
cut-off frequency of 1st order LPF made by this AC coupling capacitor and series resister in front of BEEP input.
2. Internal feedback resister of BEEP-Amp which determines BEEP-Amp gain has 30% sample variation.
n MONO OUTPUT (MOUT2 pin)
The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MOUT2 bit is “0”, this output is OFF and the
MOUT2 pin is forced to VCOM voltage. The load impedance is 10kΩ (min.). When the PMSPK bit is “0”, the
Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state.
n MONO LINE OUTPUT (MOUT+ and MOUT- pins)
The mixed Lch/Rch signal of DAC is output from the MOUT+ and MOUT- pins, creating a differential output. Either the
MOUT+ or MOUT- pins can be also used as single-ended output.
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ASAHI KASEI
[AK4534]
n ALC2 Operation
Input resistance of the ALC2 is 24kΩ (typ) and centered around VCOM voltage, and the input signal level is –3.1dBV. (see
Figure 18. 0dBV=1Vrms=2.828Vpp)
The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the input signal
exceeds –5.2dBV (=FS-1.9dB@HVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to the ALC2
circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery
operation period.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit = “0”,
512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = “1”) starts. The ALC2 is disabled during the initilization cycle and the
ALC2 starts after completing the initilization cycle.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
−5.2dBV
−7.2dBV
Operation Start Level
Period
ROTM bit = “0”
2/fs = 45µs (at 44.1kHz)
2048/fs=46.4ms (at 44.1kHz)
ROTM bit = “1”
2/fs = 180µs (at 11.025kHz)
512/fs=46.4ms (at 11.025kHz)
No
Yes (Timeout = Period Time)
Zero-crossing Detection
ATT/GAIN
0.5dB step
Table 20. Limiter /Recovery of ALC2 at HVDD=3.3V
1dB step
Full-differential
FS-1.9dB = -5.2dBV
0.4dBV
0dBV
-3.3dBV
-3.3dBV
FS
+5.6dB
-1.9dB
Single-ended
-5.6dBV
+4.1dB
-8dB
-1.6dBV
-11.3dBV
-10dBV
-0.4dB
-15.3dBV
+8.1dB
-15.3dBV
FS-3.9dB = -7.2dBV
FS-12dB
+16.1dB
-8dB
-20dBV
-23.3dBV
-30dBV
ATT+DAC
ALC2
SPK-AMP
Figure 18. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=−8.0dB)
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ASAHI KASEI
[AK4534]
n Serial Control Interface
(1) 4-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on this
interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB first,
8bits). The chip address high bit is fixed to “1” and the lower bit is set by the CAD0 pin. Address and data is clocked in on
the rising edge of CCLK and data is clocked out on the falling edge. After a low-to-high transition of CSN, data is latched
for write operations and CDTO bit outputs Hi-Z. The clock speed of CCLK is 5MHz (max). The value of internal registers
is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDTI
Write
Hi-Z
CDTO
CDTI
C1
C0
R/W
A4
A3
A2
A1
A0
Read
CDTO
Hi-Z
Hi-Z
C1 - C0 : Chip Address (C1="1", C0=CAD0)
R/W :
READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 19. Serial Control I/F Timing
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ASAHI KASEI
[AK4534]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4534 supports the standard-mode I2C-bus (max: 100kHz). The AK4534 does not support a fast-mode I2C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 20 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 26). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The
most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address
bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0 pins) set these
device address bits (Figure 21). If the slave address matches that of the AK4534, the AK4534 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 27). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4534. The format is MSB first, and those most significant
3-bits are fixed to zeros (Figure 22). The data after the second byte contains control data. The format is MSB first, 8bits
(Figure 23). The AK4534 generates an acknowledge after each byte has been received. A data transfer is always terminated
by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition (Figure 26).
The AK4534 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4534
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0FH prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. In
order to ensure proper operation, write “00H” to registers 0EH and 0FH test registers.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 28) except for the START and STOP conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Sub
Address(n)
Slave
S Address
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 20. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 21. The First Byte
0
0
0
A4
A3
A2
A1
A0
D2
D1
D0
Figure 22. The Second Byte
D7
D6
D5
D4
D3
Figure 23. Byte Structure after the second byte
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ASAHI KASEI
[AK4534]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4534. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically
taken into the next address. If the address exceeds 0FH prior to generating a stop condition, the address counter will “roll
over” to 00H and the previous data will be overwritten.
The AK4534 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4534 contains an internal address counter that maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access
data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4534 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the
AK4534 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 24. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4534 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4534 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 25. RANDOM ADDRESS READ
MS0133-E-03
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ASAHI KASEI
[AK4534]
SDA
SCL
S
P
start condition
stop condition
Figure 26. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 27. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 28. Bit Transfer on the I2C-Bus
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ASAHI KASEI
[AK4534]
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
DAC Control
MIC Control
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Input PGA Control
Lch Digital ATT Control
Rch Digital ATT Control
D7
PMVCM
MCKPD
0
DAHS
PLL1
FS2
TM1
0
0
0
0
0
ATTL7
ATTR7
D6
PMBPS
PMXTL
PSMO
0
PLL0
FS1
TM0
0
ROTM
ALC2
REF6
IPGA6
ATTL6
ATTR6
D5
PMBPM
PMPLL
DAMO
0
PS1
FS0
SMUTE
0
ZTM1
ALC1
REF5
IPGA5
ATTL5
ATTR5
D4
0
0
0
0
PS0
HPRM
DATTC
MPWRE
ZTM0
ZELM
REF4
IPGA4
ATTL4
ATTR4
D3
PMMO
PMSPK
BPSSP
BPSHP
MCKO
HPLM
BST1
MPWRI
WTM1
LMAT1
REF3
IPGA3
ATTL3
ATTR3
D2
0
PMHPL
BPMSP
BPMHP
BF
0
BST0
MICAD
WTM0
LMAT0
REF2
IPGA2
ATTL2
ATTR2
D1
PMMIC
PMHPR
ALCS
HPL
DIF1
LOOP
DEM1
MSEL
LTM1
RATT
REF1
IPGA1
ATTL1
ATTR1
D0
PMADC
PMDAC
MOUT2
HPR
DIF0
SPPS
DEM0
MGAIN
LTM0
LMTH
REF0
IPGA0
ATTL0
ATTR0
The PDN pin = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Note: Only write to address 00H to 0DH.
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ASAHI KASEI
[AK4534]
n Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMVCM
R/W
0
D6
PMBPS
R/W
0
D5
PMBPM
R/W
0
D4
0
RD
0
D3
PMMO
R/W
0
D2
0
RD
0
D1
PMMIC
R/W
0
D0
PMADC
R/W
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (2081/[email protected]) starts. After
initializing, digital data of the ADC is output.
PMMIC: MIC In Block Power Control
0: Power down (Default)
1: Power up
PMMO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMBPM: Mono BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register
values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=PMSPK=“0” or PDN pin =
“L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.
MS0133-E-03
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ASAHI KASEI
Addr
01H
Register Name
Power Management 2
R/W
Default
[AK4534]
D7
MCKPD
R/W
1
D6
PMXTL
R/W
0
D5
PMPLL
R/W
0
D4
0
RD
0
D3
PMSPK
R/W
0
D2
PMHPL
R/W
0
D1
PMHPR
R/W
0
D0
PMDAC
R/W
0
PMDAC: DAC Block Power Control
0: Power down (Default)
1: Power up
PMHPR: Rch of Headphone-Amp Power Control
0: Power down (Default)
1: Power up
PMHPL: Lch of Headphone-Amp Power Control
0: Power down (Default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (Default)
1: Power up
PMPLL: PLL Block Power Control Select
0: PLL is Power down and External is selected. (Default)
1: PLL is Power up and PLL Mode is selected.
PMXTL: X’tal Oscillation Block Power Control
0: Power down (Default)
1: Power up
MCKPD: MCKI pin pull down control
0: Master Clock input enable
1: Pulled down by 25kΩ (Default)
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ASAHI KASEI
Addr
02H
[AK4534]
Register Name
Signal Select 1
R/W
Default
D7
0
RD
0
D6
PSMO
R/W
0
D5
DAMO
R/W
0
D4
0
RD
0
D3
BPSSP
R/W
0
D2
BPMSP
R/W
0
D1
ALCS
R/W
0
D0
MOUT2
R/W
0
MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2)
0: OFF (Default)
1: ON
When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs signal at the
MOUT2 bit = “1”. This bit is valid at the PMSPK bit = “1”. Hi-Z is output at the PMSPK bit = “0”.
ALCS: ALC2 to Speaker-amp Enable
0: OFF (Default)
1: ON
ALC2 output signal is mixed to Speaker-amp at the ALCS bit = “1”.
BPMSP: BEEPM to Speaker-amp Enable
0: OFF (Default)
1: ON
Mono BEEP signal (BEEPM pin) is mixed to Speaker-amp at the BPMSP bit = “1”.
BPSSP: BEEPL/BEEPR to Speaker-amp Enable
0: OFF (Default)
1: ON
Stereo BEEP signals (BEEPL/BEEPR pins) are mixed to Speaker-amp at the BPSSP bit = “1”.
DAMO: DAC to MOUT+/MOUT- Enable
0: OFF (Default)
1: ON
DAC output signal is output through Mono Line Output (MOUT+/MOUT-pins) at the DAMO bit = “1”.
PSMO: MOUT+/MOUT- Output Enable (Mixing = (L+R)/2)
0: Power Save Mode (Default)
1: ON
When the PSMO bit = “0”, Mono Line Output is in power save mode and the MOUT+ and MOUT- pins output
0.45 x AVDD voltage.
DAHS
MOUT2
DAC
MIX
ALCS
ALC2
SPK
BPMSP
BEEPM
BPSSP
BEEPL
BEEPR
Figure 29. Speaker-amp switch control
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ASAHI KASEI
Addr
03H
Register Name
Signal Select 2
R/W
Default
[AK4534]
D7
DAHS
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
BPSHP
R/W
0
D2
BPMHP
R/W
0
D1
HPL
R/W
1
D0
HPR
R/W
1
HPR: Rch Headphone-amp Disable
0: Normal Operation
1: OFF(Default)
The HPR bit should be always “0” during operation.
HPL: Lch Headphone-amp Disable
0: Normal Operation
1: OFF(Default)
The HPL bit should be always “0” during operation.
BPMHP: BEEPM to Headphone-amp Enable
0: OFF (Default)
1: ON
Mono BEEP signal (BEEPM) is mixed to Headphone-amp at the BPMHP bit = “1”.
BPSHP: BEEPL/BEEPR to Headphone-amp Enable
0: OFF (Default)
1: ON
Stereo BEEP signals (BEEPL/BEEPR) is mixed to Headphone-amp at the BPSHP bit = “1”.
DAHS: DAC to Headphone-amp and MOUT2 Enable
0: OFF (Default)
1: ON
DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = “1”.
DAHS
HPL
DAC
HPL
MUTE
BPMHP
BEEPM
BPSHP
BEEPL
HPR
HPR
MUTE
BEEPR
Figure 30. Headphone-amp switch control
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ASAHI KASEI
Addr
04H
Register Name
Mode Control 1
R/W
Default
[AK4534]
D7
PLL1
R/W
0
D6
PLL0
R/W
0
D5
PS1
R/W
0
D4
PS0
R/W
0
D3
MCKO
R/W
0
D2
BF
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF1-0: Audio Interface Format Select (see Table 13)
Default: “10” (ADC: I2S, DAC: I2S)
BF: BICK frequency Select at Master Mode
0: 64fs (Default)
1: 32fs
This bit is invalid in slave mode.
MCKO: Master Clock Output Enable
0: Disable (Default)
1: Enable
PS1-0: Output Master Clock Select (see Table 4, 8)
Default: “00” (256fs)
PLL1-0: Input Master Clock Select at PLL Mode (see Table 2)
Default: “00” (12.288MHz)
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ASAHI KASEI
Addr
05H
[AK4534]
Register Name
Mode Control 2
R/W
Default
D7
FS2
R/W
0
D6
FS1
R/W
0
D5
FS0
R/W
0
D4
HPRM
R/W
0
D3
HPLM
R/W
0
D2
0
RD
0
D1
LOOP
R/W
0
D0
SPPS
R/W
0
SPPS: Speaker-amp Power-Save-Mode
0: Power Save Mode (Default)
1: Normal Operation
When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is
set to HVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from “L” to “H”,
the PMSPK bit is “0”, which powers down Speaker-amp
LOOP: Loopback ON/OFF
0: OFF (Default)
1: ON
When this bit is “1”, the ADC output is passed to the DAC input internally. The external input data to DAC is
ignored.
HPLM: Lch of HP-Amp output control
0: Enable output from Rch of Headphone-amp (Default)
1: Lch mono output of Headphone-amp. The PMHPR bit can be powered down at this time.
HPRM: Rch of HP-Amp output control
0: Enable output from Lch of Headphone-amp (Default)
1: Rch mono output of Headphone-amp. The PMHPL bit can be powered down at this time.
Output Channel
Register bit
Register : 00H
Register : 05H
PMHPL
PMHPR
HPLM
HPRM
Lch
Rch
ON
ON
OFF
OFF
ON
1
1
0
OFF
1
0
1
ON
0
1
0
OFF
0
0
Don’t Care
Table 21. Output control for Headphone-amp
0
0
1
Don’t Care
FS2-0: Sampling frequency modes (see Table 3, 7)
Default: “000” (fs=44.1kHz)
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ASAHI KASEI
Addr
06H
Register Name
DAC Control
R/W
Default
[AK4534]
D7
TM1
R/W
0
D6
TM0
R/W
0
D5
SMUTE
R/W
0
D4
DATTC
R/W
1
D3
BST1
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DEM1-0: De-emphases response (see Table 16)
Default is “01” (OFF).
BST1-0: Select Low Frequency Boost Function (see Table 17)
Default is “00” (OFF).
DATTC: DAC Digital Attenuator Control Mode Select
0: ATTL7-0 and ATTR7-0 bits control the attenuator level of Lch and Rch respectively.
1: ATTL7-0 bits control both Lch and Rch at same time. (Default)
ATTR7-0 bits are not changed when the ATTL7-0 bits are written.
SMUTE: Soft Mute Control
0: Normal Operation (Default)
1: DAC outputs soft-muted
Soft mute operation is independent of digital attenuator and is performed in the digital domain.
TM1-0: Soft Mute Time Select (see Table 22)
Default: “00” (1024/fs)
TM1
0
0
1
1
TM0
Cycle
0
1024/fs
Default
1
512/fs
0
256/fs
1
128/fs
Table 22. Soft Mute Time Setting
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ASAHI KASEI
Addr
07H
Register Name
MIC/HP Control
R/W
Default
[AK4534]
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
MPWRE
R/W
0
D3
MPWRI
R/W
0
D2
MICAD
R/W
0
D1
MSEL
R/W
0
D0
MGAIN
R/W
1
MGAIN: 1st Mic-amp Gain control
0: 0dB
1: 20dB (Default)
MSEL: Microphone select
0: Internal Mic (Default)
1: External Mic
MICAD: Switch Control from Mic In to ADC.
0: OFF (Default)
1: ON
MPWRI: Power Supply Control for Internal Microphone
0: OFF (Default)
1: ON
MPWRE: Power Supply for External Microphone
0: OFF (Default)
1: ON
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ASAHI KASEI
Addr
08H
[AK4534]
Register Name
Timer Select
R/W
Default
D7
0
RD
0
D6
ROTM
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
LTM1
R/W
0
D0
LTM0
R/W
0
LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (see Table 23)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the
period specified by the LTM1-0 bits. Default is “00” (0.5/fs).
ALC1 Limiter Operation Period
8kHz
16kHz
44.1kHz
Default
0
0.5/fs
63µs
31µs
11µs
1
1/fs
125µs
63µs
23µs
0
2/fs
250µs
125µs
45µs
1
4/fs
500µs
250µs
91µs
Table 23. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = “1”)
LTM1
0
0
1
1
LTM0
WTM1-0: ALC1 Recovery Waiting Period (see Table 24)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “00” (128/fs).
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC1 Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC1 Recovery Operation Waiting Period
Default
ZTM1-0: Zero crossing timeout for the write operation by the µP, ALC1 recovery, and zero crossing enable (ZELM bit
= “0”) of the ALC1 operation. (see Table 25)
When the IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is changed
by the µP WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”).
Default is “00” (128/fs).
ZTM1
ZTM0
0
0
1
1
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 25. Zero Crossing Timeout Period
Default
ROTM: Period time for ALC2 Recovery operation
0: 2048/fs (Default)
1: 512/fs
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ASAHI KASEI
Addr
09H
[AK4534]
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
ALC2
R/W
1
D5
ALC1
R/W
0
D4
ZELM
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RATT
R/W
0
D0
LMTH
R/W
0
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 26)
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.
Default is “0”.
LMTH
0
1
ALC1 Limiter Detection Level
ALC1 Recovery Waiting Counter Reset Level
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −6.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 26. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC1 Recovery GAIN Step (see Table 27)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the ALC1 recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
RATT
GAIN STEP
0
1
Default
1
2
Table 27. ALC1 Recovery Gain Step Setting
LMAT1-0: ALC1 Limiter ATT Step (see Table 28)
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH,
the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is
47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts, resulting
in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = “00”
(−8dB), it clips to “00”.
LMAT1
LMAT0
ATT STEP
0
0
1
Default
0
1
2
1
0
3
1
1
4
Table 28. ALC1 Limiter ATT Step Setting
ZELM: Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and the
IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery
operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
ALC1: ALC1 Enable Flag
0: ALC1 Disable (Default)
1: ALC1 Enable
ALC2: ALC2 Enable Flag
0: ALC2 Disable
1: ALC2 Enable (Default)
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ASAHI KASEI
Addr
0AH
[AK4534]
Register Name
ALC Mode Control 2
R/W
Default
D7
0
RD
0
D6
REF6
R/W
0
D5
REF5
R/W
1
D4
REF4
R/W
1
D3
REF3
R/W
0
D2
REF2
R/W
1
D1
REF1
R/W
1
D0
REF0
R/W
0
REF6-0: Reference value at ALC1 Recovery Operation (see Table 29)
During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then
the IPGA does not become larger than the reference value. For example, when REF7-0 = “30H”, RATT = 2step,
IPGA = 2FH, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”, the
IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”.
DATA (HEX)
GAIN (dB)
STEP
47
+27.5
46
+27.0
45
+26.5
:
:
36
+19.0
Default
:
:
10
+0.0
:
:
0.5dB
06
−5.0
05
−5.5
04
−6.0
03
−6.5
02
−7.0
01
−7.5
00
−8.0
Table 29. Setting Reference Value at ALC1 Recovery Operation
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ASAHI KASEI
Addr
0BH
[AK4534]
Register Name
Input PGA Control
R/W
Default
D7
0
RD
0
D6
IPGA6
R/W
0
D5
IPGA5
R/W
0
D4
IPGA4
R/W
1
D3
IPGA3
R/W
0
D2
IPGA2
R/W
0
D1
IPGA1
R/W
0
D0
IPGA0
R/W
0
IPGA6-0: Input Analog PGA (see Table 30)
Default: “10H” (0dB)
When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. IPGA
gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC is
changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
When IPGA6-0 bits are read, the register values written by the last write operation are read out regardless the
actual gain.
DATA (HEX)
47
46
45
:
36
:
10
:
06
05
04
03
02
01
00
Addr
0CH
0DH
Register Name
Lch Digital ATT Control
Rch Digital ATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
GAIN (dB)
STEP
+27.5
+27.0
+26.5
:
+19.0
:
+0.0
:
0.5dB
−5.0
−5.5
−6.0
−6.5
−7.0
−7.5
−8.0
Table 30. Input Gain Setting
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
Default
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL/R7-0: Digital ATT Output Control (see Table 18)
Default: “00H” (0dB)
MS0133-E-03
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ASAHI KASEI
[AK4534]
SYSTEM DESIGN
Figure 31 shows the system connection diagram. An evaluation board [AKD4534] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
1µ
1µ
1µ
1µ
R
52
51
50
C
R
49
48
47
46
C
45
44
43
42
41
10Ω
40
0.22µ
MIN
MOUT2
TST2
TST3
MOUT-
MOUT+
TST4
TST5
BEEPM
BEEPR
BEEPL
AIN
NC
1µ
R
6.8Ω 47µ
1µ
1 MICOUT
MUTET 39
2 TST1
HPL 38
3 EXT
HPR 37
4 MPE
HVSS 36
5 MPI
HVDD 35
6 INT
SPN 34
16Ω
6.8Ω
0.22µ
1µ
16Ω
10Ω
2.2k
0.1µ
2.2k
10µ
Analog Supply
2.4 ~ 3.6V
1µ
Analog Supply
2.4 ~ 3.6V
2.2µ
0.1µ
10µ
0.1µ
Top View
7 VCOM
8 AVSS
10µ
8Ω
SPP 33
M/S 32
9 AVDD
XTI/MCKI 31
C
10 PVDD
XTO 30
C
11 PVSS
DVSS 29
12 VCOC
DVDD 28
0.1µ
PDN
CSN/CAD1
CCLK/SCL
CDTI/SDA
CDTO
I2C
SDTI
SDTO
LRCK
BICK
MCKO
NC
4.7n
CAD0
0.1µ
10kΩ
14
15
16
17
18
19
20
21
22
23
24
25
26
13 NC
NC 27
10µ
10
Reset
DSP and uP
Notes:
- AVSS, DVSS, PVSS and HVSS of the AK4534 should be distributed separately from the ground of external
controllers.
- Values of R and C in Figure 31 should depend on system.
- All input pins should not be left floating.
Figure 31. Typical Connection Diagram
MS0133-E-03
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ASAHI KASEI
[AK4534]
1. Grounding and Power Supply Decoupling
The AK4534 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD
are usually supplied from the system’s analog supply. If AVDD, DVDD, PVDD and HVDD are supplied separately, the
correct power up sequence should be observed. AVSS, DVSS, PVSS and HVSS of the AK4534 should be connected to the
analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are
brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4534 as possible, with the small
value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to
the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into
the AK4534.
3. Analog Inputs
The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic
input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (0.45 x AVDD). Usually the
input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4534 can accept input
voltages from AVSS to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin and Mono Line Output from the MOUT+ and
MOUT- pins are centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2.
MS0133-E-03
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ASAHI KASEI
[AK4534]
CONTOROL SEQUENCE
n Power up
Upon power-up, bring the PDN pin = “L”. Initialize the internal registers to default values after the PDN pin = “H”. Set the
following registers to establish the initial condition.
E xam p le :
Pow er Supply
A u d i o I / F F o r m a t : I2 S
B ICK frequency at M a s ter M o d e : 64fs
Input M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 . 2 8 9 6 M H z
(2)
PDN pin
(1 )
P o w e r S u p p ly
(3)
PMVCM bit
(2 ) P D N p in = “L ” → “H ”
(Addr:00H, D7)
(4)
MOUT2 bit
(3 ) A d d r:0 0 H , D a t a 8 0 H
(Addr:02H, D0)
ALCS bit
(4 ) A d d r:0 2 H , D a t a 0 3 H
(Addr:02H, D1)
(5)
(5 ) A d d r:0 3 H , D a t a 8 0 H
HPL/R bits
(Addr:03H, D1-0)
DAHS bit
(6 ) A d d r:0 4 H , D a t a 4 2 H
(Addr:03H, D7)
(6)
DIF1-0 bits
(Addr:04H, D1-0)
BF bit
(Addr:04H, D2)
PLL1-0 bits
(Addr:04H, D7-6)
10
XX
0
X
00
XX
Figure 32. Power Up Sequence
<Example>
(1) Power Supply
(2) PDN pin = “L” → “H”
“L” time of 150ns or more is needed to reset the AK4534.
(3) Power up VCOM : PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) Set up register 02H : MOUT2 bit = ALCS bit = “0” → “1”
Set the MOUT2 and ALCS bits to “1” when using the Speaker-amp.
(5) Set up register 03H : HPL bit = HPR bit = “1” → “0”, DAHS bit = “0” → “1”
(6) Set up register 04H
• DIF1-0 bits set the audio interface format.
• BF bit sets BICK output frequency in master mode.
• PLL1-0 bits set MCLK input frequency in PLL mode.
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ASAHI KASEI
[AK4534]
n Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied.
1. When X'tal is used in PLL mode. (Slave mode)
MCKPD bit
E xam p le :
(Addr:01H, D7)
A u d io I/F F o r m a t : I 2 S
B ICK frequency at M a ster M o d e : 64fs
I n p u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s t e r C lo c k F re q ue n c y : 6 4 f s
(1)
PMXTL bit
(Addr:01H, D6)
20ms(typ)
(2)
(1 ) A d d r : 0 1 H , D a t a : 4 0 H
PMPLL bit
(Addr:01H, D5)
40ms(max)
(2 ) A d d r : 0 1 H , D a t a : 6 0 H
MCKO bit
(Addr:04H, D3)
(3)
(3 ) A d d r : 0 4 H , D a t a 4 A H
(4)
MCKO pin
Output
(4 ) M C K O o u t p u t s t a r t s
(5)
BICK, LRCK
Input
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
(5 ) B I C K a n d L R C K i n p u t s t a r t
(6)
00
XX
(6 ) A d d r : 0 4 H , D a t a 6 A H
Figure 33. Clock Set Up Sequence(1)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and power-up the X’tal oscillator: PMXTL bit =
“0” → “1”
(2) Power-up the PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at the
same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. This
time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1”
(4) MCKO is output after PLL becomes stable.
(5) Input BICK and LRCK synchronized with the MCKO output.
(6) Set the MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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[AK4534]
2. When X'tal is used in PLL mode. (Master mode)
E xam p le :
MCKPD bit
A u d io I/F F o r m a t : I 2 S
B ICK frequency at M a ster M o d e : 64fs
I n p u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s t e r C lo c k F re q ue n c y : 6 4 f s
(Addr:01H, D7)
(1)
PMXTL bit
(Addr:01H, D6)
(1 ) A d d r : 0 1 H , D a t a : 4 0 H
20ms(typ) (2)
PMPLL bit
(Addr:01H, D5)
40msec(max)
(2 ) A d d r : 0 1 H , D a t a : 6 0 H
MCKO bit
(3 ) A d d r : 0 4 H , D a t a 6 A H
(Addr:04H, D3)
(3)
PS1-0 bits
(Addr:04H, D5-4)
00
XX
(4 ) M C K O , B I C K a n d L R C K o u t p u t s t a r t s
(4)
MCKO pin
Output
BICK, LRCK
Output
(Master Mode)
Figure 34. Clock Set Up Sequence(2)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and and power-up the X’tal oscillator: PMXTL
bit = “0” → “1”
(2) Power-up PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at the
same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. This
time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(4) MCKO, BICK and LRCK are output after PLL lock time.
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[AK4534]
3. When an external clock is used in PLL mode. (Slave mode)
E xam p le :
MCKPD bit
A u d io I/F F o r m a t : I 2 S
B ICK frequency at Master Mode : 64fs
Inp u t M a s t e r C lo c k S e lect at P L L M o d e : 1 1 . 2 8 9 6 M H z
O utp u t M a s t e r C lo c k F r e q u e n c y : 6 4 f s
(1)
(Addr:01H, D7)
External MCLK
(2)
Input
( 1 ) A d d r :0 1 H , D a t a : 0 0 H
(3)
PMPLL bit
(2) Input external M C L K
(Addr:01H, D5)
40ms(max)
( 3 ) A d d r :0 1 H , Data 2 0 H
MCKO bit
(Addr:04H, D3)
(4)
( 4 ) A d d r :0 4 H , D a t a 4 A H
(5)
MCKO pin
Output
(5) MCKO output starts
BICK, LRCK
(6)
Input
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
( 6 ) B I C K a n d L R C K inp u t s t a r t
(7)
00
XX
( 7 ) A d d r :0 4 H , D a t a 6 A H
Figure 35. Clock Set Up Sequence(3)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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[AK4534]
4. When an external clock is used in PLL mode. (Master mode)
Exam p le :
MCKPD bit
Audio I/F Format : I 2 S
BICK frequency at Master Mode : 64fs
Input Master Clo c k S e lect at PLL Mode : 11.2896MHz
O utput Master Clock Frequency : 64fs
(Addr:01H, D7)
(1)
(2)
External MCLK
Input
(1) Addr:0 1 H , Data:00H
(3)
PMPLL bit
(Addr:01H, D5)
(2) Input external MCLK
40ms(max)
(3) Addr:0 1 H , Data 20H
MCKO bit
(Addr:04H, D3)
(4)
PS1-0 bits
00
(Addr:04H, D5-4)
(4) Addr:0 4 H , Data 6AH
XX
(5) MCKO, BICK and LRCK output starts
(5)
MCKO pin
Output
BICK, LRCK
Output
(Master Mode)
Figure 36. Clock Set Up Sequence(4)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(5) MCKO, BICK and LRCK are output after PLL lock time.
5. External clock mode
Exam p le :
(1)
MCKPD bit
Audio I/F Format : I 2 S
BICK frequency at Master Mode : 64fs
Input Master Clock Frequency : 256fs
O utput Master Clock Frequency : 64fs
(Addr:01H, D7)
(2)
FS1-0 bits
(Addr:05H, D6-5)
External MCLK
BICK, LRCK
00
XX
(1) Addr:01H, Data:00H
(3)
(4)
(Slave Mode)
BICK, LRCK
(Master Mode)
(5)
Input
Input
Output
(2) A d d r:05H, Data 00H
(3) Input external MCLK
(4) Input BICK a n d L R C K ( S lave)
(5) BICK and LRCK output(Master)
Figure 37. Clock Set Up Sequence(5)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Set up MCLK frequency (FS1-0 bits)
(3) Input an external MCLK
(4) In slave mode, input MCLK, BICK and LRCK.
(5) In master mode, while MCLK is input, BICK and LRCK are output.
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[AK4534]
n MIC Input Recording
FS2-0 bits
(Addr:05H, D7-5)
MIC Control
(Addr:07H, D2-0)
ALC1 Control 1
(Addr:08H)
ALC1 Control 2
(Addr:0AH)
ALC1 Control 3
(Addr:09H)
Example :
000
XXX
X’tal and PLL are used.
Sampling Frequency : 8kHz
Mic Select : Internal Mic
Pre Mic AMP : +20dB
MIC Power On
ALC1 setting : Refer to Figure 9
ALC2 bit = “1”(default)
(1)
00001
XX1XX
(2)
XXH
(1) Addr:05H, Data:E0H
00H
(3)
XXH
(2) Addr:07H, Data:0DH
47H
(4)
(3) Addr:08H, Data:00H
XXH
61H or 21H
(5)
ALC1 State
(4) Addr:0AH, Data:47H
ALC1 Disable
ALC1 Enable
ALC1 Disable
(5) Addr:09H, Data:61H
PMADC bit
(Addr:00H, D0)
(6)
PMMIC bit
(6) Addr:00H, Data 83H
2081 / fs
(Addr:00H, D1)
ADC Internal
State
(7)
Recording
Power Down
Initialize Normal State Power Down
(7) Addr:00H, Data 80H
Figure 38. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=8kHz. If the parameter of the ALC1 is changed, please refer to
“Figure 9. Registers set-up sequence at the ALC1 operation.”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits). When the AK4534 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 07H)
(3) Set up Timer Select for ALC1 (Addr: 08H)
(4) Set up REF value for ALC1 (Addr: 0AH)
(5) Set up LMTH, RATT, LMAT1-0, ALC1 bits (Addr: 09H)
(6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0” → “1”
The initialization cycle time of ADC is 2081/fs=47.2ms@fs=44.1kHz.
After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA initial
value (0dB).
(7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1” → “0”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1
operation is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also
changed when the sampling frequency is changed, it should be done after the AK4534 goes to the manual mode
(ALC1 bit = “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC bit is
“0”, and then IPGA operation starts from the default value when PMMIC is changed to “1”.
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[AK4534]
n Headphone-amp Output
E x a m p le :
FS2-0 bits
(Addr:05H, D7-5)
BST1-0 bits
(Addr:06H, D3-2)
ATTL7-0 bits
(Addr:0CH 0DH, D7-0)
000
X ’t a l a n d P L L a r e u s e d .
S a m p ling Frequency : 44.1kH z
D A T T C b it = “ 1 ” ( d e f a u lt)
D igital A ttenuato r L e v e l : -8 d B
B a s s B o o s t L e v e l : M iddle
D e -e m p h a s e s r e s p o n s e : O F F
S o ft M ute Tim e : 1 0 2 4 / f s
XXX
(1)
(1) A d d r:05H, Data:00H
00
XX
00
(2)
(2) A d d r : 0 6 H , D a t a 1 9 H
(8)
0000000
(3 ) A d d r : 0 C H , D a t a 1 0 H
XXXXXXX
(3)
(4) A d d r:01H, Data 67H
PMDAC bit
(Addr:01H, D0)
(4)
(7)
PMHPL/R bits
( 5 ) R e le a s e e x t e r n a l M u t e
P la y b a c k
(Addr:01H, D2-1)
Normal Output
HPL/R pins
(5)
(6)
( 6 ) E n a b le e x t e r n a l M u t e
(7) A d d r : 0 1 H , D a t a 6 0 H
External Mute
(8) A d d r : 0 6 H , D a t a 1 1 H
Figure 39. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used.
(2) Set up the low frequency boost level(BST1-0 bits)
(3) Set up the digital volume(Addr : 0CH and 0DH)
At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level.
(4) Power up DAC and headphone-amp : PMDAC bit = PMHPL bit = PMHPR bit = “0” → “1”
The rising time after power up Headphone-amp depends on the capacitor value connected with the MUTET
pin. When this capacitor value is 1.0µF, the time constant is τr = 100ms.
(5) Release the external mute.
(6) Enable the external mute.
(7) Power down DAC and headphone-amp : PMDAC bit = PMHPL bit = PMHPR bit = “1” → “0”
The falling time of Headphone-amp depends on the capacitor for the AC couple of Headphone-amp output.
When this capacitor value is 47µF, the time constant is τf = 188ms. If the power supply is powered off or
Headphone-Amp is powered-up again before the common voltage goes to GND, some POP noise occurs. It
takes 5times of τf that the common voltage goes to GND.
(8) Off the low frequency boost level (BST1-0 bits = “00”)
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[AK4534]
n Speaker-amp Output
FS2-0 bits
(Addr:05H, D7-5)
ALC2 bit
(Addr:09H, D6
ATTL7-0 bits
(Addr:0CH 0DH, D7-0)
000
XXX
(1)
E x a m p le :
0
X ’t a l a n d P L L a r e u s e d .
S a m p li n g F r e q u e n c y : 4 8 k H z
D A T T C b it = “ 1 ” ( d e f a u lt )
D igita l A t t e n u a t o r L e v e l : 0 d B
A L C 1 : D isable
A L C 2 : D isable
X
(2)
0000000
XXXXXXX
(1 ) A d d r:0 5 H , D a t a 6 0 H
(3)
PMDAC bit
(2 ) A d d r:0 9 H , D a t a 0 0 H
(Addr:01H, D0)
(4)
(7)
(3 ) A d d r:0 C H , D a t a 0 0 H
PMSPK bit
(Addr:01H, D3)
(4 ) A d d r:0 1 H , D a t a 6 9 H
SPPS bit
(5 ) A d d r:0 5 H , D a t a 6 1 H
(Addr:05H, D0)
(5)
SPP pin
Hi-Z
(6)
Normal Output
P layb a c k
Hi-Z
(6 ) A d d r:0 5 H , D a t a 6 0 H
SPN pin
Hi-Z
HVDD/2
Normal Output
HVDD/2
Hi-Z
(7 ) A d d r:0 1 H , D a t a 6 0 H
Figure 40. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used.
(2) Set up the ALC2 Enable/Disable(ALC2 bit)
(3) Set up the digital volume(Addr : 0CH and 0DH)
At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level.
(4) Power up of DAC and Speaker-amp : PMDAC bit = PMSPK bit = “0” → “1”
The initializing time of Speaker-amp is 2048/fs=46.4ms@fs=44.1kHz.
(5) Exit the power-save-mode of Speaker-amp : SPPS bit = “0” → “1”
(6) Enter the power-save-mode of Speaker-amp : SPPS bit = “1” → “0”
(7) Power down DAC and Speaker-amp : PMDAC bit = PMSPK bit = “1” → “0”
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[AK4534]
n Stop of Clock
MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKO bit
E x a m p le :
(1)
A u d io I/F Form at : I 2 S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(Addr:03H, D4)
PMXTL bit
(Addr:01H, D6)
(1) Addr:04H, Data:62H
(2)
PMPLL bit
(2) Addr:01H, Data:80H
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
Figure 41. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1” → “0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
2. When an external clock is used in PLL mode
E x a m p le :
MCKO bit
A u d io I/F : I 2 S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1)
(Addr:03H, D4)
(2)
PMPLL bit
(1) Addr:04H, Data:62H
(Addr:01H, D5)
(2) Addr:01H, Data:80H
MCKPD bit
(Addr:01H, D7)
(3) Stop external clock
(3)
External MCLK
Input
Figure 42. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1” → “0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
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[AK4534]
3. External clock mode
E x a m p le :
M C K P D b it
(Addr:01H, D7)
E xternal M C L K
(1) A d d r : 0 1 H , D a t a : 8 0 H
Input
(2) S t o p e x t e r n a l c l o c k
Figure 43. Stop of Clock Sequence(3)
<Example>
(1) Pull down the XTI pin : MCKPD = “0” → “1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(2) Stop an external MCLK
n Power down
Power down VCOM(PMVCM= “1” → “0”) after all blocks except VCOM are powered down and MCLK stops. The
AK4534 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
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[AK4534]
PACKAGE
52pin QFN (Unit: mm)
7.2 ± 0.20
7.0 ± 0.10
39
1
7.0 ± 0.10
7.2 ± 0.20
39
4 - C0.6
52
45°
13
27
14
10
0.
1
40
40
±
52
0.20 + 0.10
- 0.20
30
0.
0.60 + 0.10
- 0.30
45°
27
26
13
26
14
0.05
0.80 + 0.20
- 0.00
0.18 ± 0.05
0.05
M
0.02 + 0.03
- 0.02
0.21 ± 0.05
0.78 + 0.17
- 0.28
0.40
Note) The part of black at four corners on reverse side must not be soldered and must be open.
n Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate (Pb free)
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[AK4534]
MARKING
n 52pin QFN
AKM
AK4534VN
XXXXXXX
1
XXXXXXX :
Date code identifier (7 digits)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
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