[AK4691] AK4691 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP GENERAL DESCRIPTION The AK4691 is a 16bit, 4ch ADC and 2ch DAC with Microphone-Amplifier, Headphone-Amplifier, and Speaker-Amplifier. The recording block corresponds to supports 4-channel inputs, and also has 3-input selector for Internal/External MIC and LINE, output power for Microphone, Pre-Amp, and ALC (Automatic Level Control) circuit. The playback bock has Lineout-Amplifier, Headphone-Amplifier, and Speaker-Amplifier. The AK4691 is suitable for portable applications such as built-in LCD. The AK4691 is available in a 57pin BGA, utilizing less board space than competitive offerings. FEATURES 1. Recording Function • 4-channel Single-ended Pre-Amp (Pre-Amp Gain: 0dB, +18dB, +20dB, +24dB or +28dB) • 2-channel Line Input • 3-input Selector (Internal MIC, External MIC or LINE) • 4-channel Digital ALC (Automatic Level Control) • ADC Performance: S/(N+D): 82dB, DR, S/N: 90dB (Pre-Amp=+24dB) S/(N+D): 85dB, DR, S/N: 90dB (LINE) • Wind-noise Reduction Filter • Stereo Separation Emphasis • Fade-in/out Function 2. Playback Function • Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz) • Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) • Stereo Separation Emphasis • Stereo Line Output - Performance: S/(N+D): 85dB, S/N: 90dB - Output Level: -3.9dBV @ AVDD=LVDD=3.0V, LVOL=0dB +2dBV @ AVDD=3.0V, LVDD=4.5V, LVOL=+5.9dB • Stereo Headphone-Amp - S/(N+D): 70dB, S/N: 90dB - Output Power: 58mW @ 16Ω (LVDD=3.3V) - Pop Noise Free at Power ON/OFF • Mono Speaker-Amp - S/(N+D): 50dB@240mW, S/N: 90dB - BTL Output - Output Power: 400mW @ 8Ω (SVDD=3.3V) • Analog Mixing 3. Power Management 4. Master Clock: (1) PLL Mode • Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0672-E-00 2007/11 -1- [AK4691] 6. Sampling Rate: • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 48kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. μP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode) 8. Master/Slave mode 9. Audio Interface Format: MSB First, 2’s complement • ADC: 16bit MSB justified, I2S, TDM Mode • DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, TDM Mode 10. Ta = −30 ∼ 85°C 11. Power Supply Voltage: • Analog (AVDD), Digital (DVDD): 2.6 ∼ 3.6V • MIC (MVDD): 2.6 ∼ 5.5V • Lineout & Headphone (LVDD): 2.6 ∼ 5.5V • Speaker (SVDD): 2.6 ∼ 3.6V • Digital I/F (TVDD1, TVDD2): 1.6 ∼ 3.6V 12. Package: 57pin BGA (5mm x 5mm, 0.5mm pitch, height: 1.0mm) MS0672-E-00 2007/11 -2- [AK4691] ■ Block Diagram MRF MVDD RIN LIN AVDD VSS1 VCOM PMMP MPWR MIC Power Supply I2CN PRELN1 PMMICL1 Control Register INTL1 PRERN1 CCLK/SCL CDTI/SDA EXTL1 Internal MIC CSN/CAD0 PMADC1 PMMICR1 PDN SDTI ADC1 PMADC1 or PMADC2 = “1” PMADC1 =PMADC2 = “0” INTR1 EXTR1 PRELN2 BICK PMADC1 or PMDAC PMMICL2 LRCK PMADC2 EXTL2 External MIC PRERN2 SDTO1 HPF1 INTL2 ADC2 PMMICR2 SDTO2 HPF2 INTR2 Wind-Noise Reduction2 Wind-Noise Reduction1 Stereo Separation2 Stereo Separation1 SDTI Audio I/F EXTR2 PMADC1 or PMADC2 or PMDAC PMLO LOUT ALC (IVOL) PMADC1 = “0”: OFF Line Out SDTO1 ROUT PMADC2 = “0”: OFF SDTO2 PMHPL PMDAC D/A HPL Headphone PMADC1=PMADC2=“0” DATT Bass SMUTE Boost PMADC1 or PMADC2 = “1” PMHPR HPR MCKO PMPLL MUTET PLL MCKI VCOC PMSPK SPP Speaker SPN MUTE PMBP BEEP SVDD VSS3 LVDD LVCM VSS4 TVDD1 TVDD2 DVDD VSS2 Figure 1. Block Diagram MS0672-E-00 2007/11 -3- [AK4691] ■ Ordering Guide −30 ∼ +85°C 57pin BGA Evaluation board for AK4691 AK4691EG AKD4691 ■ Pin Layout 9 8 7 6 AK4691 5 Top View 4 3 2 1 A B C D E F G H J 9 NC VCOC VCOM AVDD RIN LOUT LVCM MUTET NC 8 MRF PRELN1 VSS1 LIN BEEP ROUT LVDD HPL VSS4 7 PRERN2 PRELN2 VSS3 HPR 6 PRERN1 MVDD SVDD SPP 5 MPWR INTL1 PDN SPN 4 INTL2 EXTL1 CDTI/SDA MUTE 3 INTR1 EXTL2 NC 2 INTR2 EXTR1 TVDD1 MCKI SDTO2 LRCK MCKO TVDD2 NC 1 NC EXTR2 I2CN SDTI SDTO1 BICK DVDD VSS2 NC A B C D E F G H J Top View CSN/CAD0 CCLK/SCL MS0672-E-00 2007/11 -4- [AK4691] PIN/FUNCTION No. Pin Name Power Supply D9 AVDD C8 VSS1 C9 VCOM I/O O G1 DVDD H1 VSS2 H6 SVDD H7 VSS3 B6 MVDD A5 MPWR O A8 MRF O G8 LVDD G9 LVCM O J8 VSS4 C2 TVDD1 H2 TVDD2 Audio Interface D2 MCKI I G2 MCKO O F2 LRCK I/O F1 BICK I/O D1 SDTI I E1 SDTO1 O E2 SDTO2 O Control Register Interface C1 I2CN CSN CAD0 CCLK J3 SCL CDTI H4 SDA MIC Block B5 INTL1 B4 EXTL1 B8 PRELN1 A3 INTR1 B2 EXTR1 A6 PRERN1 A4 INTL2 B3 EXTL2 B7 PRELN2 A2 INTR2 B1 EXTR2 A7 PRERN2 ADC Block D8 LIN E9 RIN H3 I I I I I I I/O Function Analog Power Supply Pin, 2.6 ∼ 3.6V Ground 1 Pin Common Voltage Output Pin, 0.5 x AVDD Bias voltage of ADC inputs and DAC outputs. Digital Power Supply Pin, 2.6 ∼ 3.6V Ground 2 Pin Speaker-Amp Power Supply Pin, 2.6 ∼ 3.6V Ground 3 Pin MIC Block Power Supply Pin, 2.6 ∼ 5.5V MIC Power Output Pin MIC Power Supply Ripple Filter Pin Headphone & LINEOUT-Amp Power Supply Pin, 2.6 ∼ 5.5V LINEOUT-Amp Common Voltage Output Pin, 0.5 x LVDD Ground 4 Pin Digital I/F(Audio Interface) Power Supply 1 Pin, 1.6 ∼ 3.6V Digital I/F(Control Register Interface) Power Supply 2 Pin, 1.6 ∼ 3.6V External Master Clock Input Pin Master Clock Output Pin Input / Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Audio Serial Data Output 1 Pin Audio Serial Data Output 2 Pin Control Mode Select Pin “L”: I2C Bus, “H”: 3-wire Serial Chip Select Pin (I2CN pin = “H”) Chip Address 0 Select Pin (I2CN pin = “L”) Control Data Clock Pin (I2CN pin = “H”) Control Data Clock Pin (I2CN pin = “L”) Control Data Input Pin (I2CN pin = “H”) Control Data Input/Output Pin (I2CN pin = “L”) I I I I I I I I I I I I Internal MIC Lch Input 1 Pin External MIC Lch Input 1 Pin Lch Pre-Amp Negative Input 1 Pin Internal MIC Rch Input 1 Pin External MIC Rch Input 1 Pin Rch Pre-Amp Negative Input 1 Pin Internal MIC Lch Input 2 Pin External MIC Lch Input 2 Pin Lch Pre-Amp Negative Input 2 Pin Internal MIC Rch Input 2 Pin External MIC Rch Input 2 Pin Rch Pre-Amp Negative Input 2 Pin I I Lch Line Input Pin Rch Line Input Pin MS0672-E-00 2007/11 -5- [AK4691] No. Pin Name DAC Block F9 LOUT F8 ROUT HP-Amp Block H8 HPL J7 HPR H9 I/O MUTET O O Lch Stereo Line Output Pin Rch Stereo Line Output Pin O O Lch Headphone-Amp Output Pin Rch Headphone-Amp Output Pin Mute Time Constant Control Pin Connected to VSS4 pin with a capacitor for mute time constant. O SPK-Amp Block J5 SPN J6 SPP Other Functions Function O O J4 MUTE I B9 VCOC O H5 PDN I E8 A1 A9 C3 J1 J2 J9 BEEP I NC - Speaker Amp Negative Output Pin Speaker Amp Positive Output Pin Mute Pin “L”: Normal Operation, “H”: Mute Output Pin for Loop Filter of PLL Circuit This pin should be connected to VSS1 with one resistor and capacitor in series. Power-Down Mode Pin “H”: Power-up, “L”: Power-down, reset and initialize the control register. BEEP Signal Input Pin No Connection Pin No internal bonding. This pin should be connected to ground. Note 1. All input pins except analog input pins (BEEP, INTL1/2, EXTL1/2, INTR1/2, EXTR1/2, LIN, and RIN) should not be left floating. Note 2.All analog input pins (INTL1/2, EXTL1/2, INTR1/2, EXTR1/2, LIN, and RIN pins ) except the BEEP pin should be supplied signal via AC-coupling capacitor. Note 3. The BEEP pin should be supplied signal via AC-coupling capacitor and resistor. Note 4. Analog output pins (HPL, HPR, LOUT, and ROUT pins) except the SPP and SPN pins should deliver signal via AC-coupling capacitor. ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Other Pin Name MPWR, VCOC, SPN, SPP, HPR, HPL, MUTET, ROUT, LOUT, BEEP INTL1, INTL2, INTR1, INTR2, EXTL1, EXTL2, EXTR1, EXTR2, LIN, RIN MCKO, SDTO1, SDTO2 MCKI, SDTI, MUTE NC MS0672-E-00 Setting These pins should be open. These pins should be open and each path should be switched off. These pins should be open. These pins should be connected to VSS2. This pin should be connected to ground (VSS1, VSS2, VSS3 or VSS4). 2007/11 -6- [AK4691] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4 = 0V; Note 5, Note 6) Parameter Symbol min max Units Power Supplies: Analog AVDD 6.0 V −0.3 Digital DVDD 6.0 V −0.3 MIC-Amp MVDD 6.0 V −0.3 Speaker-Amp SVDD 6.0 V −0.3 Headphone-Amp/LINEOUT-Amp LVDD 6.0 V −0.3 Digital I/F 1 TVDD1 6.0 V −0.3 Digital I/F 2 TVDD2 6.0 V −0.3 Input Current, Any Pin Except Supplies IIN mA ±10 Analog Input Voltage (Note 7) VINA1 AVDD+0.3 V −0.3 (Note 8) VINA2 MVDD+0.3 V −0.3 Digital Input Voltage (Note 9) VIND1 TVDD1+0.3 V −0.3 (Note 10) VIND2 TVDD2+0.3 V −0.3 Ambient Temperature (powered applied) Ta 85 −30 °C Storage Temperature Tstg 150 −65 °C Maximum Power Dissipation (Note 11) Pd 1.1 W Note 5. All voltages with respect to ground. Note 6. VSS1, VSS2, VSS3, and VSS4 must be connected to the same analog ground plane. Note 7. LIN, RIN, BEEP pins Note 8. INTL1/2, INTR1/2, EXTL1/2, EXTR1/2, PRELN1/2, PRERN1/2 pins Note 9. I2CN, MCKI, LRCK, BICK, SDTI pins Note 10. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, MUTE pins Pull-up resistors at the SDA and SCL pins should be connected to (TVDD2+0.3)V or less voltage. Note 11. In case of PCB wiring density is 200% or more. This power is the AK4691 internal dissipation that does not include power dissipation of externally connected speaker and headphone. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. MS0672-E-00 2007/11 -7- [AK4691] RECOMMEND OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4 = 0V; Note 5) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 2.6 3.0 3.6 V (Note 14) LINE/HP (Note 12) LVDD 2.6 3.0 5.5 V MIC (Note 13) MVDD 2.6 or “AVDD – 0.1” 3.0 5.5 V Digital DVDD 2.6 3.0 3.6 V Digital I/F 1 TVDD1 1.6 3.0 DVDD V Digital I/F 2 TVDD2 1.6 3.0 DVDD V SPK SVDD 2.6 3.0 3.6 V Difference AVDD – DVDD -0.3 0 0.3 V Note 5. All voltages with respect to ground. Note 12. When the voltage of LVDD pin is low and a high level signal is output from LINEOUT, the output signal is clipped and the distortion of LINEOUT degrades. LVDD should be more than (0.6 x AVDD + 0.8)[V] at LVOL2-0 bits = “000” and be more than (0.76 x AVDD + 0.8)[V] at LVOL2-0 bits = “001” and be more than (1.19 x AVDD + 0.8)[V] at LVOL2-0 bits = “010” and be more than (1.36 x AVDD + 0.8)[V] at LVOL2-0 bits = “100”in order to avoid clipping. Note 13. The Minimum value is higher value between 2.6V and “AVDD – 0.1”V. Note 14. The power up sequence among AVDD, LVDD, MVDD, DVDD, TVDD1, TVDD2, and SVDD is not critical. The AK4691 supports the following two cases of partial power ON/OFF. In these cases, the PDN pin must be “L”. 1. TVDD1=TVDD2=ON: AVDD=DVDD=LVDD=MVDD=SVDD can be power ON/OFF. 2. TVDD2=ON: TVDD1=AVDD=DVDD=LVDD=MVDD=SVDD can be power ON/OFF. When the power state is changed from OFF to ON in the above cases, the PDN pin should be changed from “L” to “H” after all power supply pins (TVDD1, TVDD2, AVDD, DVDD, MVDD, LVDD, and SVDD pins) are supplied. “L” time of 150ns or more is needed to reset the AK4691. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0672-E-00 2007/11 -8- [AK4691] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=MVDD=LVDD=SVDD=TVDD1=TVDD2=3.0V; VSS1=VSS2=VSS3=VSS4 = 0V; fs=48kHz; Input Frequency =1kHz; Measurement width=20Hz ∼ 20kHz, unless otherwise specified) Parameter min typ max Units Pre-Amp Characteristics: Input Resistance: Positive Input Pin (Note 15) 70 100 130 kΩ Negative Input Pin (Note 16) 1.54 2.2 2.86 kΩ Gain PRG12-10 bits = “000”, FB bit = “1” -0.8 0 +17.2 dB PRG22-20 bits = “000”, FB bit = “1” PRG12-10 bits = “001”, FB bit = “0” +17.2 +18 +18.8 dB PRG22-20 bits = “001”, FB bit = “0” PRG12-10 bits = “010”, FB bit = “0” +19.2 +20 +20.8 dB PRG22-20 bits = “010”, FB bit = “0” PRG12-10 bits = “011”, FB bit = “0” +23.2 +24 +24.8 dB PRG22-20 bits = “011”, FB bit = “0” PRG12-10 bits = “100”, FB bit = “0” +27.2 +28 +28.8 dB PRG22-20 bits = “100”, FB bit = “0” MIC Power Supply Voltage Characteristics: MPWR pin Output Voltage (Output current = 0mA) (Note 17) 1.7 1.9 2.1 V Maximum Output Current 4 mA ADC Analog Input Characteristics: ALC = OFF Resolution 16 bits Input Resistance (LIN, RIN pins) 70 100 130 kΩ Input Voltage (Note 18) (Note 19) -4.5 -3.7 -2.9 dBV (Note 18) (Note 20) -57.9 -57.1 -56.3 dBV S/(N+D) (-1dBFS) (Note 19) 75 85 dB (Note 21) 72 82 dB DR (-60dBFS, A-Weighted) (Note 19) 81 90 dB (Note 20) 54 60 dB S/N (A-Weighted) (Note 19) 81 90 dB (Note 20) 54 60 dB Interchannel Isolation (Note 19) 80 100 dB (Note 20) 50 70 dB Interchannel Gain Mismatch (Note 19) 0.5 dB (Note 20) 0.5 dB Note 15. INTL1/2, INTR1/2, EXTL1/2, EXTR1/2 pins Note 16. PRELN1/2, PRERN1/2 pins. Gain=0dB, +20dB: 3.5kΩ ± 30%; Gain=+18dB: 4.4kΩ ± 30%, Gain=+24dB: 2.2kΩ ± 30%, Gain=+28dB: 1.4kΩ ± 30% Note 17. When the output current is 0mA, the output voltage of MPWR pin is typically (MVDD – 1.1) V at MVDD=3.0V and typically (MVDD-1.4) V at MVDD=4.5V. When the output current is 4mA, the output voltage of MPWR pin is typically (MVDD – 1.3) V at MVDD=3.0V and typically (MVDD-1.5) V at MVDD=4.5V. Note 18. Input voltages are proportional to AVDD voltage. LIN, RIN = typ. (0.62 x AVDD) Vpp INTL1/2, INTR1/2, EXTL1/2, EXTR1/2 = typ. (0.0013 x AVDD) Vpp Note 19. Input from LIN, RIN pins. FB = “1”, IVOL=0dB. Note 20. Input from INTL1/2, INTR1/2, EXTL1/2 or EXTR1/2 pins. Pre-Amp Gain = + 24dB, PRE bit = “1”, FB bit = “0”, IVOL = +29.625dB, MGL12-10 = MGR12-10 = MGL22-20 = MGR22-20 bits = “010” (0dB) Note 21. Input from INTL1/2, INTR1/2, EXTL1/2 or EXTR1/2 pins. Pre-Amp Gain = + 24dB, PRE bit = “1”, FB bit = “0”, IVOL = +0dB, MGL12-10 = MGR12-10 = MGL22-20 = MGR22-20 bits = “010” (0dB) * 0dBV = 1Vrms = 2.83Vpp MS0672-E-00 2007/11 -9- [AK4691] Parameter min typ max Units DAC Analog Output characteristics: DAC Æ LOUT/ROUT, IVOL=DVOL=LVOL=+0dB, ALC=OFF, RL= 10kΩ Resolution 16 bits S/(N+D) (0dBFS) 76 85 dB DR (-60dBFS, A-Weighted) 83 90 dB S/N (A-Weighted) 83 90 dB Output Voltage (Note 23) -4.7 -3.9 -3.1 dBV Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.5 dB Load Resistance 10 kΩ Load Capacitance (Note 22) 30 pF Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=DVOL=0dB Output Voltage (Note 24) -5.8 -3.9 -2 dBV HPG bit = “0”, 0dBFS, LVDD=3.0V, RL=22.8Ω -0.3 dBV HPG bit = “1”, 0dBFS, LVDD=3.3V, RL=16Ω (Po=58mW) S/(N+D) 60 70 dBFS HPG bit = “0”, −3dBFS, LVDD=3.0V, RL=22.8Ω 80 dBFS HPG bit = “1”, 0dBFS, LVDD=5.0V, RL=100Ω 20 dBFS HPG bit = “1”, 0dBFS, LVDD=3.3V, RL=16Ω (Po=58mW) S/N (A-weighted) (Note 25) 82 90 dB Interchannel Isolation (Note 25) 65 75 dB Interchannel Gain Mismatch (Note 25) 0.1 0.8 dB Load Resistance 16 Ω C1 in Figure 2 30 pF Load Capacitance 300 pF C2 in Figure 2 Note 22. When the output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. Note 23. Output voltage is proportional to AVDD voltage. LOUT, ROUT = typ. (0.6 x AVDD) Vpp @LVOL = 0dB. Note 24. Output voltage is proportional to AVDD voltage. HPL, HPR = typ. (0.6 x AVDD) Vpp @ HPG bit = “0”, typ. (0.91 x AVDD) Vpp @ HPG bit = “1”. Note 25. HPG bit = “0”, LVDD=3.0V, RL=22.8Ω. HP-Amp HPL/HPR pin Measurement Point 47μF C1 0.22μF 6.8Ω C2 16Ω 10Ω Figure 2. Headphone-Amp output circuit * 0dBV = 1Vrms = 2.83Vpp MS0672-E-00 2007/11 - 10 - [AK4691] Parameter min typ max Units Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=DVOL=0dB, RL=8Ω, BTL, SVDD=3.0V (Note 27) Output Voltage (Note 26) SPKG1-0 bits = “00”, 0dBFS (Po=140mW) 0.5 dBV 1.4 3 4.6 dBV SPKG1-0 bits = “10”, −3.75dBFS (Po=240mW) SPKG1-0 bits = “11”, −3.75dBFS, SVDD=3.3V, 5 dBV (Po=400mW) S/(N+D) SPKG1-0 bits = “00”, 0dBFS (Po=140mW) 60 dB 20 50 dB SPKG1-0 bits = “10”, −3.75dBFS (Po=240mW) SPKG1-0 bits = “11”, −3.75dBFS, SVDD=3.3V 20 dB (Po=400mW) S/N (A-weighted) 80 90 dB Load Resistance 8 Ω Load Capacitance 30 pF Mono Input: BEEP pin (External Input Resistance=20kΩ) Maximum Input Voltage (Note 28) 1.8 Vpp Gain (Note 29) BEEP Æ LOUT/ROUT LVOL2-0 bits = “000” 0 +4.5 dB −4.5 BEEP Æ HPL/HPR HPG bit = “0” dB −24.5 −20 −15.5 BEEP Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” +4.43 +8.93 dB −0.57 ALC bit = “0”, SPKG1-0 bits = “01” +6.43 dB ALC bit = “0”, SPKG1-0 bits = “10” +10.65 dB ALC bit = “0”, SPKG1-0 bits = “11” +12.65 dB ALC bit = “1”, SPKG1-0 bits = “00” +6.43 dB ALC bit = “1”, SPKG1-0 bits = “01” +8.43 dB ALC bit = “1”, SPKG1-0 bits = “10” +12.65 dB ALC bit = “1”, SPKG1-0 bits = “11” +14.65 dB Note 26. Output voltage is proportional to AVDD voltage. But actual speaker output level is clipped according to the supplied SVDD voltage. Vout = typ. 1.0 x AVDD Vpp @ SPKG1-0 bits = “00” & 0dBFS, typ. 1.26 x AVDDVpp @ SPKG1-0 bits = “01” & 0dBFS, typ. 2.04 x AVDDVpp @ SPKG1-0 bits = “10” & 0dBFS, typ. 2.58 x AVDDVpp @ SPKG1-0 bits = “11” & 0dBFS at Full-differential. Note 27. In case of measuring at the SPP and SPN pins. Note 28. The Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 29. The gain is in inverse proportion to external input resistance. * 0dBV = 1Vrms = 2.83Vpp MS0672-E-00 2007/11 - 11 - [AK4691] Parameter Power Supplies: Power-Up (PDN pin = “H”) All Circuit Power-up: (Note 30) AVDD+DVDD+MVDD+TVDD1+TVDD2 LVDD: HP & LINEOUT-Amp Normal Operation (No Output) SVDD: SPK-Amp Normal Operation (No Output) MIC + ADC (4ch Mode): AVDD+DVDD+TVDD1+TVDD2 (Note 31) MVDD DAC+LINEOUT: AVDD+DVDD+MVDD+SVDD+TVDD1+TVDD2 (Note 32) LVDD: LINEOUT-Amp Normal Operation Power-Down (PDN pin = “L”) (Note 33) AVDD+DVDD+MVDD+LVDD+SVDD+TVDD1+TVDD2 min typ max Units - 28 6.4 8 42 9.6 24 mA mA mA - 15.2 7.5 - mA mA - 9.2 1.8 - mA mA - 10 100 μA Note 30. PLL Master Mode (MCKI=12.288MHz), PMMICL1=PMMICR1=PMMICL2=PMMICR2=PMADC1 = PMADC2 = PMDAC = PMLO = PMHPL = PMHPR = PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S = SPPSN =HPMNT bits = “1” and LOPS bit = “0”. The MPWR pin outputs 0mA. AVDD=14.5mA(typ), DVDD=4.1mA(typ), MVDD=7.5mA (typ.), TVDD1=2mA(typ), TVDD2=0mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=13.5mA(typ), DVDD=4.1mA(typ), TVDD1=TVDD2=0mA(typ) Note 31. PLL Master Mode (MCKI=12.288MHz) and PMMICL1 = PMMICR1 = PMMICL2 = PMMICR2 = PMADC1 = PMADC2 = PMVCM=PMPLL=MCKO=PMMP = M/S bits = “1”. Note 32. PLL Master Mode (MCKI=12.288MHz), PMDAC = PMLO =PMVCM= PMPLL = MCKO = PMBP = M/S bits = “1”, and LOPS bit = “0”. Note 33. All digital input pins are fixed to TVDD1, TVDD2 or VSS2. The PDN pin is held at “VSS2”. MS0672-E-00 2007/11 - 12 - [AK4691] FILTER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=SVDD=2.6 ∼ 3.6V; LVDD=MVDD= 2.6 ∼ 5.5V; TVDD1=TVDD2=1.6 ∼ 3.6V; fs=48kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 34) PB 0 18.8 kHz ±0.16dB 21.1 kHz −0.66dB 21.6 kHz −1.1dB 24.0 kHz −6.9dB Stopband SB 28.4 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 35) GD 19 1/fs Group Delay Distortion 0 ΔGD μs ADC Digital Filter (HPF): (Note 36) Frequency Response (Note 34) −3.0dB FR 1.0 Hz 2.9 Hz −0.5dB 6.5 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 34) PB 0 21.3 kHz ±0.1dB 21.8 kHz −0.7dB 24.0 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 35) GD 26 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 36) Frequency Response (Note 34) −3.0dB FR 1.0 Hz 2.9 Hz −0.5dB 6.5 Hz −0.1dB BOOST Filter: (Note 37) Frequency Response MIN FR 20Hz dB 6.27 100Hz dB 3.18 1kHz dB 0.02 MID FR 20Hz dB 11.6 100Hz dB 7.44 1kHz dB 0.14 MAX 20Hz FR dB 17.48 100Hz dB 11.47 1kHz dB 0.40 Note 34. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.45 x fs (@-1.1dB). Each response refers to that of 1kHz. Note 35. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. DAC group delay is at PMADC1 = PMADC2 bits = “0”. When PMADC1 bit is “1” or PMADC2 bit is “1”, it is typ. 19/fs. Note 36. When PMADC1 bit = “1” or PMADC2 bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADC1 = PMADC2 bits = “0” and PMDAC bit = “1”, the HPF of DAC is enabled (@ HPFN bit = “0”) but the HPF of ADC is disabled. Note 37. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0672-E-00 2007/11 - 13 - [AK4691] DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=SVDD=2.6 ∼ 3.6V; LVDD=MVDD= 2.6 ∼ 5.5V; TVDD1=TVDD2=1.6 ∼ 3.6V) Parameter Symbol min typ max High-Level Input Voltage 2.2V≤TVDD1≤3.6V VIH1 70%TVDD1 (Note 38) 1.6V≤TVDD1<2.2V VIH1 80%TVDD1 Low-Level Input Voltage 2.2V≤TVDD1≤3.6V VIL1 30%TVDD1 (Note 38) 1.6V≤TVDD1<2.2V VIL1 20%TVDD1 High-Level Output Voltage (Note 39) TVDD1−0.2 (Iout=−200μA) VOH1 Low-Level Output Voltage (Note 39) 0.2 (Iout=200μA) VOL1 High-Level Input Voltage 2.2V≤TVDD2≤3.6V VIH2 70%TVDD2 (Note 40) 1.6V≤TVDD2<2.2V VIH2 80%TVDD2 Low-Level Input Voltage 2.2V≤TVDD2≤3.6V VIL2 30%TVDD2 (Note 40) 1.6V≤TVDD2<2.2V VIL2 20%TVDD2 Low-Level Output Voltage (SDA pin) (2.0V≤TVDD2≤3.6V: Iout=3mA) VOL2 0.4 20%TVDD2 (1.6V≤TVDD2<2.0V: Iout=3mA) VOL2 Input Leakage Current Iin ±10 Note 38. I2CN, MCKI, BICK, LRCK, SDTI pins Note 39. MCKO, SDTO1, SDTO2 pins Note 40. MUTE, PDN, CSN/CAD0, CCLK/SCK, CDTI pins Units V V V V V V V V V V V V μA SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=DVDD=SVDD=2.6 ∼ 3.6V; LVDD=MVDD= 2.6 ∼ 5.5V; TVDD1=TVDD2=1.6 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns MCKO Output Timing Frequency fMCK 0.2352 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK 33 % LRCK Output Timing Frequency fs 7.35 48 kHz Duty Cycle Duty 50 % BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) ns BCKO bit = “1” tBCK 1/(64fs) ns Duty Cycle dBCK 50 % MS0672-E-00 2007/11 - 14 - [AK4691] Parameter Symbol PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK Pulse Width Low tCLKL Pulse Width High tCLKH MCKO Output Timing Frequency fMCK Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 256fs at fs=32kHz, 29.4kHz dMCK LRCK Input Timing Frequency fs Duty Cycle (Except TDM mode) Duty “H” time in TDM mode tLRCKH BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs Duty Cycle (Except TDM mode) Duty “H” time in TDM mode tLRCKH BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs Duty Cycle (Except TDM mode) Duty “H” time in TDM mode tLRCKH BICK Input Timing Period PLL3-0 bits = “0010” tBCK PLL3-0 bits = “0011” tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency MCKI = 256fs fCLK MCKI = 512fs fCLK MCKI = 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Input Timing Frequency MCKI = 256fs fs MCKI = 512fs fs MCKI = 1024fs fs Duty Cycle (Except TDM mode) Duty “H” time in TDM mode tLRCKH BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH MS0672-E-00 min typ max Units 11.2896 0.4/fCLK 0.4/fCLK - 27 - MHz ns ns 0.2352 - 12.288 MHz 40 - 50 33 60 - % % 7.35 45 1/(16fs) - 48 55 1/(32fs) kHz % ns 1/(64fs) 0.4 x tBCK 0.4 x tBCK - 1/(32fs) - ns ns ns 7.35 45 1/(16fs) - 48 55 1/(32fs) kHz % ns 1/(64fs) 240 240 - 1/(32fs) - ns ns ns 7.35 45 1/(16fs) - 48 55 1/(32fs) kHz % ns 0.4 x tBCK 0.4 x tBCK 1/(32fs) 1/(64fs) - - ns ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 24.576 13.312 - MHz MHz MHz ns ns 7.35 7.35 7.35 45 1/(16fs) - 48 48 13 55 1/(32fs) kHz kHz kHz % ns 312.5 130 130 - - ns ns ns 2007/11 - 15 - [AK4691] Parameter Symbol min Audio Interface Timing Master Mode tMBLR −40 BICK “↓” to LRCK Edge (Note 42) tLRD LRCK Edge to SDTO (MSB) −70 (Except I2S mode) tBSD BICK “↓” to SDTO −70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 50 LRCK Edge to BICK “↑” (Note 42) tBLR 50 BICK “↑” to LRCK Edge (Note 42) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN Edge to CCLK “↑” (Note 43) tCSH 50 CCLK “↑” to CSN Edge (Note 43) Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 44) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive Load on Bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Power-down & Reset Timing PDN Pulse Width (Note 45) tPD 150 tPDV PMADC1 or PMADC2 “↑” to SDTO valid (Note 46) Note 41. I2C is a registered trademark of Philips Semiconductors. Note 42. BICK rising edge must not occur at the same time as LRCK edge. Note 43. CCLK rising edge must not occur at the same time as CSN edge. Note 44. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 45. The AK4691 can be reset by the PDN pin = “L”. Note 46. This is the count of LRCK “↑” from the PMADC1 or PMADC2 bit = “1”. MS0672-E-00 typ max Units - 40 70 ns ns - 70 - ns ns ns - 80 ns ns ns - 80 - ns ns ns - - ns ns ns ns ns ns ns ns - 400 0.3 0.3 400 50 kHz μs μs μs μs μs μs μs μs μs μs pF ns 1059 - ns 1/fs 2007/11 - 16 - [AK4691] ■ Timing Diagram 1/fCLK VIH1 MCKI VIL1 tCLKH tCLKL tBCK 50%TVDD1 BICK tBCKH tBCKL 1/fs dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100 50%TVDD1 LRCK tLRCKH tLRCKL 1/fMCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 MCKO 50%TVDD1 tMCKL dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL Master mode) 50%TVDD1 LRCK tMBLR BICK 50%TVDD1 tLRD tBSD SDTO 50%TVDD1 tSDS tSDH VIH1 SDTI VIL1 Figure 4. Audio Interface Timing (PLL Master mode) MS0672-E-00 2007/11 - 17 - [AK4691] 1/fCLK VIH1 MCKI VIL1 tCLKH tCLKL 1/fs VIH1 LRCK VIL1 tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH1 BICK VIL1 tBCKH tBCKL fMCK 50%TVDD1 MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 5. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin) 1/fCLK VIH1 MCKI VIL1 tCLKH tCLKL 1/fs VIH1 LRCK VIL1 tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH1 BICK VIL1 tBCKH tBCKL Figure 6. Clock Timing (EXT Slave mode) MS0672-E-00 2007/11 - 18 - [AK4691] VIH1 LRCK VIL1 tBLR tLRB VIH1 BICK VIL1 tLRD tBSD SDTO 50%TVDD1 MSB tSDS tSDH VIH1 SDTI VIL1 Figure 7. Audio Interface Timing (PLL/EXT Slave mode) VIH2 CSN VIL2 tCSH tCCKL tCSS tCCKH VIH2 CCLK VIL2 tCCK tCDH tCDS CDTI C1 A5 R/W VIH2 VIL2 Figure 8. WRITE Command Input Timing MS0672-E-00 2007/11 - 19 - [AK4691] tCSW VIH2 CSN VIL2 tCSH tCSS VIH2 CCLK VIL2 CDTI D2 D1 VIH2 D0 VIL2 Figure 9. WRITE Data Input Timing VIH2 SDA VIL2 tBUF tLOW tHIGH tR tF tSP VIH2 SCL VIL2 tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop 2 Figure 10. I C Bus Mode Timing PMADC1 bit or PMADC2 bit tPDV SDTO 50%TVDD1 Figure 11. Power Down & Reset Timing 1 tPD PDN VIL2 Figure 12. Power Down & Reset Timing 2 MS0672-E-00 2007/11 - 20 - [AK4691] OPERATION OVERVIEW ■ System Clock There are the following four clock modes to interface with external devices (Table 1, Table 2). Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode 1 1 Table 4 Figure 13 PLL Slave Mode 1 Table 4 Figure 14 1 0 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 Table 4 Figure 15 1 0 (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode 0 0 x Figure 16 Don’t Care (Note 47) 0 1 x Note 47. If this mode is selected, the invalid clocks are output from the MCKO pin when MCKO bit is “1”. Table 1. Clock Mode Setting (x: Don’t care) Mode MCKO bit 0 PLL Master Mode 1 0 PLL Slave Mode (PLL Reference Clock: MCKI pin) 1 PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode MCKO pin L Selected by PS1-0 bits L Selected by PS1-0 bits 0 L MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits GND Selected by FS3-0 bits Table 2. Clock pins state in Clock Mode 0 L BICK pin Output (Selected by BCKO bit) LRCK pin Input (≥ 32fs) Input (1fs) Output (Selected by BCKO bit) Input (≥ 32fs) Output (1fs) Input (1fs) Input (1fs) ■ Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4691 is power-down mode (PDN pin = “L”) and exits reset state, the AK4691 is slave mode. After exiting reset state, the AK4691 is set to master mode by changing M/S bit = “1”. When the AK4691 is used by master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The LRCK and BICK pins of the AK4691 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode (default) 1 Master Mode Table 3. Select Master/Slave Mode MS0672-E-00 2007/11 - 21 - [AK4691] ■ PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4691 is supplied stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. 1) Setting of PLL Mode Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit PLL Reference Clock Input Pin Input Frequency 0 1 0 0 0 0 0 0 0 1 LRCK pin N/A 1fs - 2 0 0 1 0 BICK pin 32fs 3 0 0 1 1 BICK pin 64fs 4 5 6 7 12 13 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Others R and C of VCOC pin R[Ω] C[F] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n PLL Lock Time (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms (default) MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz Others N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available) 2) Setting of sampling frequency in PLL Mode When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz (default) 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available) When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and FS1-0 bits (Table 6). FS2 bit is “don’t care”. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 x 0 0 0 (default) 7.35kHz ≤ fs ≤ 8kHz 0 x 1 1 0 8kHz < fs ≤ 12kHz 0 x 0 2 1 12kHz < fs ≤ 16kHz 0 x 1 3 1 16kHz < fs ≤ 24kHz 1 x 0 6 1 24kHz < fs ≤ 32kHz 1 x 1 7 1 32kHz < fs ≤ 48kHz Others Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” (x: Don’t care) MS0672-E-00 2007/11 - 22 - [AK4691] ■ PLL Unlock State 1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) In this mode, the LRCK and BICK pins change to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit is “1” before the PLL sets to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin changes to “L” (Table 7). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but change to “L” by setting PMPLL bit to “0”. MCKO pin BICK pin MCKO bit = “0” MCKO bit = “1” After after PMPLL bit “0” Æ “1” “L” Output Invalid “L” Output PLL Unlock (except above case) “L” Output Invalid Invalid PLL Lock “L” Output Table 9 Table 10 Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State LRCK pin “L” Output Invalid 1fs Output 2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) In this mode, an invalid clock is output from the MCKO pin before the PLL sets to lock state after PMPLL bit = “0” Æ “1”. Then, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL, DACH and DACS bits. MCKO pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid PLL Unlock “L” Output Invalid PLL Lock “L” Output Output Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PLL State MS0672-E-00 2007/11 - 23 - [AK4691] ■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table 10). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or μP AK4691 MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 13. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) BICK Output Frequency 0 32fs (default) 1 64fs Table 10. BICK Output Frequency at Master Mode BCKO bit MS0672-E-00 2007/11 - 24 - [AK4691] ■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4691 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4). a) PLL reference clock: MCKI pin The BICK and LRCK inputs should be synchronized with the MCKO output. The phase between MCKO and LRCK dose not matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (Table 5). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4691 DSP or μP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs ≥ 32fs 1fs MCLK BCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 6). AK4691 DSP or μP MCKO MCKI BICK LRCK 32fs, 64fs 1fs BCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 15. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin) The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADC1 bit = “1”, PMADC2 bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4691 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC1=PMADC2=PMDAC bits = “0”). MS0672-E-00 2007/11 - 25 - [AK4691] ■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4691 becomes EXT mode. Master clock is input directly from MCKI pin without the internal PLL circuit. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (Table 11). MCKI Input Sampling Frequency Frequency Range x 0 0 0 256fs (default) 7.35kHz ∼ 48kHz 1 x 0 1 1024fs 7.35kHz ∼ 13kHz 2 x 1 0 512fs 7.35kHz ∼ 48kHz 3 x 1 1 512fs 7.35kHz ∼ 26kHz Others Others N/A N/A Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”), (N/A: Not available, x: Don’t care) Mode FS3-2 bits FS1 bit FS0 bit The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through the LOUT/ROUT pins at fs=8kHz is shown in Table 12. Mode MCKI S/N (fs=8kHz, 20kHzLPF + A-weighted) 0 256fs 80dB 2 512fs 3 512fs 90dB 1 1024fs 90dB Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADC1 bit = “1”, PMADC2 bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4691 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC1=PMADC2=PMDAC bits = “0”). AK4691 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK ≥ 32fs BICK 1fs LRCK BCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 16. EXT Slave Mode MS0672-E-00 2007/11 - 26 - [AK4691] ■ System Reset When power-up, the AK4691 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle when the PMADC1 or PMADC2 bit is changed from “0” to “1” at PMDAC bit = “0”. The initialization cycle time is 1059/fs=22ms@fs=48kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADC1 = PMADC2 = INITDA bits = “0”. The initialization cycle time is 1059/fs=22ms@fs=48kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”. The DAC output reflects the digital input data after the initialization cycle is complete and group delay of DAC (26/fs = 0.54ms @ fs=48kHz) is passed. When INITDA bits = “1”, the DAC does not do initialization cycle. When PMADC1 or PMADC 2 bit is “1”, INITDA bit should be set to “0”. When PMDAC bit is “0”, INITDA bit should be changed. ■ Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 13). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4691 in master mode, but must be input to the AK4691 in slave mode. The SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). SDTO1’s Audio interface format is the same as SDTO2’s. Mode DIF1 bit DIF0 bit 0 1 2 3 0 0 1 1 0 1 0 1 SDTO1 (ADC1) SDTI (DAC) SDTO2 (ADC2) TDM Mode TDM Mode MSB justified LSB justified MSB justified MSB justified 2 I S compatible I2S compatible Table 13. Audio Interface Format BICK Figure 64fs ≥ 32fs ≥ 32fs ≥ 32fs Figure 17 Figure 18 Figure 19 Figure 20 (default) If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data which is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. MS0672-E-00 2007/11 - 27 - [AK4691] 64BICK LRCK 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO1(o) 15 14 13 1 0 15 14 13 1 0 15 14 R2 L2 R1 L1 16 BICK 16 BICK SDTO2(o) SDTI(i) 1 0 15 1 0 15 14 "L" Output 15 14 13 Don't Care 1 0 1 0 15 14 15 15:MSB, 0:LSB Lch Data Rch Data 16 BICK 16 BICK Note 48. When PMADC1 bit is “0”, SDTO1 is output to “0” data during the period of L1 and R1. When PMADC2 bit is “0”, SDTO2 is output to “0” data during the period of L2 and R2. Figure 17. Mode 0 Timing (TDM Mode) LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 Don't Care 15 14 13 15 14 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 18. Mode 1 Timing MS0672-E-00 2007/11 - 28 - [AK4691] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 19. Mode 2 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 20. Mode 3 Timing MS0672-E-00 2007/11 - 29 - [AK4691] ■ MIC BLOCK 1. Pre- Amp Pre-Amp includes a selector, Internal MIC or External MIC Mode can be selected by PRSL2-1 and PRSR2-1 bits. The Pre-Amp is non-inverting amplifier and internally biased to VCOM voltage with 100kΩ (typ.). The gain from Pre-Amp #1 to MIXL/R-Amp is set by PRG12-10, and the gain from Pre-Amp #2 to MIXL/R-Amp is set by PRG22-20 bits (Table 15). Lch Pre-Amp #1 Input Signal Source INTL1 pin EXTL1 pin PRSL1 bit 0 1 Rch Pre-Amp #1 Input Signal Source INTR1 pin EXTR1 pin PRSR1 bit 0 1 Lch Pre-Amp #2 Rch Pre-Amp #2 PRSR2 bit Input Signal Source Input Signal Source INTL2 pin 0 INTR2 pin EXTL2 pin 1 EXTR2 pin Table 14. Pre-Amp Input Signal Source Select PRSL2 bit 0 1 An external capacitor (C1) is needed to cancel DC gain. The cut-off frequency is determined by an external capacitor (C1) and internal feedback resistor (Rn). The internal feedback resistor (Rn) depends on Pre-Amp Gain and is typ ± 30%. PRG12 bit PRG11 bit PRG10 bit Gain Rn(typ) PRG22 bit PRG21 bit PRG20 bit FB bit = “0” FB bit = “1” 0 0 0 -4.4dB (Note 49) 0dB (Note 49) 3.5kΩ 0 0 1 +18dB +22.4dB 4.4 kΩ 1 0 0 +20dB +24.4dB 3.5kΩ 1 0 1 +24dB (default) +28.4dB 2.2kΩ 0 1 0 +28dB +32.4dB 1.4kΩ 1 0 1 1 1 0 N/A 1 1 1 Note 49. Input signal is bypassed to Pre-Amp and is inputted to MIX-Amp. The cut-off frequency is determined by input impedance (typ. 100kΩ) and external capacitors (C2, C3). Table 15. Relationship between Pre-Amp Gain and Feedback resistor (N/A: Not available) C1 + Rn C2 + INT pin EXT pin - PRSx bit To MIX-Amp + + Pre-Amp C3 To MIX-Amp (@ PRG12-10/PRG22-20 bits = “000”) Figure 21. Pre-Amp MS0672-E-00 2007/11 - 30 - [AK4691] 2. Power Supply for MIC The Power Supply for microphone device is supplied from the MPWR pin. The MPWR pin can supply the current up to 4mA. When the output current is 0mA, the output voltage is typically (MVDD – 1.1) V at MVDD=3.0V and typically (MVDD – 1.4) V at MVDD=4.5V. When the output current is 4mA, the output voltage is typically (MVDD – 1.3) V at MVDD=3.0V and typically (MVDD – 1.5) V at MVDD=4.5V. When PMMP bit is “0”, the output current is not supplied. PMMP bit 0 1 MPWR pin Pull-down to VSS1 with 5.3kΩ(typ.) Output Table 16. MIC Power (default) MIC Power ≥ 1kΩ ≥ 1kΩ ≥ 1kΩ ≥ 1kΩ MPWR pin Microphone INTL1 pin Microphone INTR1 pin Microphone INTL2 pin Microphone INTR2 pin Figure 22. MIC Block Circuit example MS0672-E-00 2007/11 - 31 - [AK4691] ■ MIC Sensitivity Compensation The AK4691 has MIC sensitivity (Interchannel gain mismatch) compensation function. The gain of each channel for compensation is set by the resister as shown in Table 17. This function is enabled when Pre-Amp gain is from +18dB to +32.4dB. It is ignored when Pre-Amp gain is 0dB or -4.4dB. Register Input pin MGL12-10 bits INTL1/EXTL1 MGR12-10 bits INTR1/EXTR1 MGL22-20 bits INTL2/EXTL2 MGR22-20 bits INTR2/EXTR2 Table 17. Relationship between register and input pin MGL12 bit MGL11 bit MGL10 bit MGR12 bit MGR11 bit MGR10 bit Gain MGL22 bit MGL21 bit MGL20 bit MGR22 bit MGR21 bit MGR20 bit 0 0 0 +2dB 0 0 1 +1dB 0 1 0 0dB (default) 0 1 1 -1dB 1 0 0 -2dB 1 0 1 1 1 0 N/A 1 1 1 Table 18. MIC Sensitivity Compensation function (N/A: Not available) ■ Analog Mixing Circuit for Recording Block typ.60kΩ /100kΩ LIN pin (RIN pin) Analog Signal 6.2kΩ typ.100kΩ AIN bit 6.2kΩ + To ADC1 MIXL-Amp (MIXR-Amp) typ. 60kΩ From Pre-Amp1 PRE bit Figure 23. Analog Mixing Circuit for Recording Block 1. LINE Input Input resistance of LIN and RIN pins are typically 100kΩ and centered around the VCOM voltage. When the input voltage exceeds +2dBV, the input signals should be attenuated down to –3.7dBV at AVDD=3.0V by external resistor divider. When AIN bit is “1”, LIN and RIN pins are selected. The MIX-Amp gain is changed by FB bit. FB bit Gain 0 -4.4dB (default) 1 0dB Table 19. MIX-Amp gain at LINE Input MS0672-E-00 2007/11 - 32 - [AK4691] 2. MIX-Amp MIX1-Amp is powered-up when PMADC1 bit = “1”. MIX-Amp mixes the MIC input and the line input. Mixing ratio is “1:0.6” at FB bit = “0” and “1.67:1” at FB bit = “1”. 3. Polarity INTL1/INTR1, INTL2/INTR2, EXTL1/EXTR1, EXTL2/EXTR2, and LIN/RIN pins output non-inverted input signals from ADC. Signal Path Polarity INTL1/INTR1 Æ ADC1 Non-inverted INTL2/INTR2 Æ ADC2 EXTL2/EXTR2 Æ ADC1 Non-inverted EXTL2/EXTR2 Æ ADC2 LIN/RIN Æ ADC1 Non-inverted Table 20. Polarity of Recording Block 4. Mono Analog Loopback Selector When Pre-Amp gain is +18dB, +20dB, +24dB or +28dB, signal from Lch Pre-Amp #1 (MICL1 bit), Rch Pre-Amp #1 (MICR1 bit), and Lch Pre-Amp #2 (MICL2 bit) can be output from the LOUT pin. This path does not pass through the block of MIC sensitivity compensation. MICL1 bit is enabled at PMMICL1 = PMLO bits = “1”. MICR1 bit is enabled at PMMICR1 = PMLO bits = “1”. MICL2 bit is enabled at PMMICL2 = PMLO bits = “1”. MICL1 bit From Lch Pre-Amp #1 MICR1 bit To LOUT From Rch Pre-Amp #1 MICL2 bit From Lch Pre-Amp #2 Figure 24. Mono Analog Loopback Selector 5. MONO Mode ADC1 and ADC2 support mono data output. The both output mode of ADC1 and ADC2 are selected by ADM1-0 bits. This conversion to mono data from stereo data is done before window noise reduction circuit (Figure 25). ADC output Lch Rch Lch Data Rch Data Lch Data Lch Data Rch Data Rch Data (L+R)/2 (L+R)/2 Table 21. ADC output data ADM1 bit ADM0 bit 0 0 1 1 0 1 0 1 (default) After setting ADM1-0 bits, ADC should be power-up by setting PMADC1 bit = “1” or PMADC2 bit = “1”. When changing ADM1-0 bits during ADC is working, the pop noise may occur. MS0672-E-00 2007/11 - 33 - [AK4691] ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@ fs = 48kHz) and scales with sampling rate (fs). ADC1 and DAC use common HPF. When ADC side is powered-up (PMADC1 bit = “1” or PMADC2 bit = “1”), the HPF of ADC1 is enabled but the HPF of DAC is disabled. When ADC side is powered-down (PMADC1 = PMADC2 bits = “0”) and DAC is powered-up (PMDAC bit = “1”), the HPF of DAC is enabled (@ HPFN bit = “0”). When the HPF of DAC is enabled, ON/OFF of the HPF can be selected by HPFN bit. When changing HPFN bit, DAC should be powered-down. When ADC side is powered-up, HPFN bit must be set to “0”. PMADC2-1 bits 01, 10 or 11 00 PMDAC bit x 0 HPFN bit 1 x 0 1 1 Table 22. HPF ON/OFF (x: Don’t care) HPF ADC OFF DAC OFF ■ Digital EQ/HPF/LPF The AK4691 has wind-noise reduction filter (FIL1), stereo separation emphasis (FIL3), gain compensation (EQ) and ALC (Automatic Level Control) in digital domain for A/D converted data (Figure 25). ADC1 and ADC2 have FIL1, FIL3, and EQ blocks independently. ALC block is common to ADC1 and ADC2. FIL1, FIL3, and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit in ADC1 operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit in ADC1 operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3A, EQA, FIL1A, GN1A, GN0A bits should be set to “0” if digital EQ/HPF/LPF in ADC1 is not used for playback path. When digital EQ/HPF/LPF blocks change from recording path to playback path, ADC1, ADC2 and DAC (PMADC1=PMADC2=PMDAC bits = “0”) should be powered-down. MS0672-E-00 2007/11 - 34 - [AK4691] PMADC2 -1 bits PMDAC bit 0 1 0 1 LOOP1-0 bits (Note 50) x x x 00 Status Digital EQ/HPF/LPF Power-down Playback path Recording path Recording path Power-down Playback Recording 01, 10 or 11 Recording & Playback Recording Monitor Playback 01, 11 Recording path 01 1 (ADC1 Æ DAC) 10 Recording & Playback Recording path 01 Recording & Playback Recording path Recording path 10 1 Recording Monitor Playback 10, 11 (ADC2 Æ DAC) Recording path Recording (ADC2) 01, 11 Recording Monitor Playback Recording path (ADC1 Æ DAC) 11 1 Recording (ADC1) 10 Recording Monitor Playback Recording path (ADC2 Æ DAC) Note 50. When LOOP1-0 bits = “10”, TDM mode (DIF1-0 bits = “00”) is not supported. Note 51. Stereo emphasis circuit in ADC1 and ADC2 is effective only at stereo operation. Table 23. Digital EQ/HPF/LPF Circuit Setting (x: Don’t care) 00 (default) When the below recording channels (PMADC2-1 bits = “01” Î PMADC2-1 bits = “10” or PMADC2-1 bits = “10” Î PMADC2-1 bits = “01”) are changed at PMDAC bit = “1, PMADC1 = PMADC2 bits = “11” should be set more than 2/fs. <Example of Sequence> a. PMADC2-1 bits = “01” (“10”) b. PMADC2-1 bits = “11” c. Delay ( ≥ 2/fs ) d. PMADC2-1 bits = “10” (“01”) MS0672-E-00 2007/11 - 35 - [AK4691] FIL3A, EQA, FIL1A, GN1A, and GN0A bits are for ADC1. FIL3B, EQB, FIL1B, GN1B, and GN0B bits are for ADC2. FIL3A(FIL3B) coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0A(GN1-0B) bits (Table 24) and EQA(EQB) coefficient set the compensation gain. FIL1A(FIL1B) and FIL3A(FIL3B) blocks become HPF when F1ASA(F1ASB) and F3ASA(F3ASB) bits are “0” and become LPF when F1ASA(F1ASB) and F3ASA(F3ASB) bits are “1”, respectively. When EQA(EQB) and FIL1A(FIL1B) bits are “0”, EQA(EQB) and FIL1A(FIL1B) blocks become “through” (0dB). When FIL3A(FIL3B) bit is “0”, FIL3A(FIL3B) block become “MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3A (FIL3B)). Wind-noise reduction FIL1A Any coefficient F1A13A-0A F1B13A-0A F1ASA Wind-noise reduction FIL1B Any coefficient F1A13B-0B F1B13B-0B F1ASB Stereo separation emphasis Gain compensation FIL3A EQA Any coefficient 0dB ∼ -10dB F3A13A-0A MUTE F3B13A-0A (set by F3ASA FIL3A coefficient) Any coefficient EQA15A-0A EQB13A-0A EQC15A-0A +12dB ∼ 0dB Stereo separation emphasis ADC1 GN1A-0A +24/+12/0dB ALC Gain compensation FIL3B EQB Any coefficient 0dB ∼ -10dB F3A13B-0B MUTE F3B13B-0B (set by F3ASB FIL3B coefficient) Gain Any coefficient EQA15B-0B EQB13B-0B EQC15B-0B +12dB ∼ 0dB Gain ADC2 GN1B-0B +24/+12/0dB Figure 25. Digital EQ/HPF/LPF GN1A bit GN0A bit Gain GN1B bit GN0B bit 0 0 0dB (default) 0 1 +12dB 1 x +24dB Table 24. Gain select of gain block (x: Don’t care) MS0672-E-00 2007/11 - 36 - [AK4691] [Filter Coefficient Setting] 1) When FIL1A(FIL1B) and FIL3A(FIL3B) are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1A(FIL1B) should be set to 0dB.) Register setting for ADC1 FIL1A: F1ASA bit = “0”, F1A[13:0]A bits =A, F1B[13:0]A bits =B FIL3A: F3ASA bit = “0”, F3A[13:0]A bits =A, F3B[13:0]A bits =B (MSB=F1A13A, F1B13A, F3A13A, F3B13A; LSB=F1A0A, F1B0A, F3A0A, F3B0A) Register setting for ADC2 FIL1B: F1ASB bit = “0”, F1A[13:0]B bits =A, F1B[13:0]B bits =B FIL3B: F3ASB bit = “0”, F3A[13:0]B bits =A, F3B[13:0]B bits =B (MSB=F1A13B, F1B13B, F3A13B, F3B13B; LSB=F1A0B, F1B0B, F3A0B, F3B0B) A = 10K/20 x 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function Amplitude 1 − z −1 H(z) = A 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 1 + B2 + 2Bcos (2πf/fs) Phase θ(f) = tan −1 (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1A(FIL1B) and FIL3A(FIL3B) are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1A (FIL1B) should be set to 0dB.) Register setting for ADC1 FIL1A: F1ASA bit = “0”, F1A[13:0]A bits =A, F1B[13:0]A bits =B FIL3A: F3ASA bit = “0”, F3A[13:0]A bits =A, F3B[13:0]A bits =B (MSB=F1A13A, F1B13A, F3A13A, F3B13A; LSB=F1A0A, F1B0A, F3A0A, F3B0A) Register setting for ADC2 FIL1B: F1ASB bit = “0”, F1A[13:0]B bits =A, F1B[13:0]B bits =B FIL3B: F3ASB bit = “0”, F3A[13:0]B bits =A, F3B[13:0]B bits =B (MSB=F1A13B, F1B13B, F3A13B, F3B13B; LSB=F1A0B, F1B0B, F3A0B, F3B0B) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) Transfer function 1 + Bz −1 1 + 1 / tan (πfc/fs) Amplitude 1 + z −1 H(z) = A B= 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0672-E-00 Phase θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2007/11 - 37 - [AK4691] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting for ADC1 EQA[15:0]A bits =A, EQB[13:0]A bits =B, EQC[15:0]A bits =C (MSB=EQA15A, EQB13A, EQC15A; LSB=EQA0A, EQB0A, EQC0A) Register setting for ADC2 EQA[15:0]B bits =A, EQB[13:0]A bits =B, EQC[15:0]B bits =C (MSB=EQA15B, EQB13B, EQC15B; LSB=EQA0B, EQB0B, EQC0B) A = 10K/20 x 1 + 1 / tan (πfc2/fs) , B= 1 + 1 / tan (πfc1/fs) A + Cz C =10K/20 x Amplitude −1 1 + Bz −1 , 1 + 1 / tan (πfc1/fs) Transfer function H(z) = 1 − 1 / tan (πfc1/fs) 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Phase 2 A + C + 2ACcos (2πf/fs) M(f) = 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1Ablock Example: HPF, fs=44.1kHz, fc=100Hz F1ASAbit = “0” F1A[13:0]A bits = 01 1111 1100 0110 F1B[13:0]A bits = 10 0000 0111 0100 2) EQA block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0]A bits = 0000 1001 0110 1110 EQB[13:0]A bits = 10 0001 0101 1001 EQC[15:0]A bits = 1111 1001 1110 1111 MS0672-E-00 2007/11 - 38 - [AK4691] ■ ALC Operation The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. The ALC block is common to ADC1 and ADC2. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC1 or ADC2 is powered-up or ADC1, ADC2, and DAC are powered-up, ALC circuit operates at recording path. PMADC2 -1 bits PMDAC bit Status ALC Power-down Power-down Playback Playback path Recording Recording path 01, 10 or 11 Recording & Playback Recording path Recording Monitor Playback 01, 11 Recording path 01 1 (ADC1 Æ DAC) 10 Recording & Playback Recording path 01 Recording & Playback Recording path Recording path 10 1 Recording Monitor Playback 10, 11 (ADC2 Æ DAC) Recording path Recording (ADC2) 01, 11 Recording Monitor Playback Recording path (ADC1 Æ DAC) 11 1 Recording (ADC1) 10 Recording Monitor Playback Recording path (ADC2 Æ DAC) Note 52. When LOOP1-0 bits = “10”, TDM mode (DIF1-0 bits = “00”) is not supported. Table 25. ALC Setting (x: Don’t care) 00 1. 0 1 0 1 LOOP1-0 bits (Note 52) x x x 00 (default) ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch in ADC1 and ADC2 exceeds the ALC limiter detection level (Table 26), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 27). The IVL and IVR are then set to the same value for both channels. When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 28). When ALC output level exceeds full-scale at LFST bit = “1”, IVL and IVR values are immediately (Period: 1/fs) changed. When ALC output level is less than full-scale, IVL and IVR values are changed at the individual zero crossing point of each channels or at the zero crossing timeout. When LFST bit = “1”, the attenuation level is fixed to 1 step regardless of the setting of LMAT1-0 bits. When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table 26) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds LMTH1-0 bits. The ALC operation corresponds to the impulse noise. When the impulse noise is input at ZELNN bit = “0”, the ALC limiter operation becomes faster than the setting of ZTM1-0 bits (fast limiter operation). The speed of fast limiter operation is set by RFST1-0 bits (Table 32). MS0672-E-00 2007/11 - 39 - [AK4691] LMTH1 bit 0 0 1 1 LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level bit 0 ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS 1 ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS 0 ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS 1 ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS Table 26. ALC Limiter Detection Level / Recovery Counter Reset Level (default) ALC Limiter ATT Step ZELMN bit LMAT1 bit LMAT0 bit 0 0 0 1 1 0 1 1 0 1 ALC Output ≥ LMTH ALC Output ≥ FS ALC Output ≥ FS + 6dB ALC Output ≥ FS + 12dB 1step (0.375dB) 2 step (0.75dB) 2 step (0.75dB) 1step (0.375dB) 1step (0.375dB) 2 step (0.75dB) 4 step (1.5dB) 2 step (0.75dB) 1step (0.375dB) 2 step (0.75dB) 4 step (1.5dB) 4 step (1.5dB) 1step (default) (0.375dB) 2 step (0.75dB) 8 step (3.0dB) 8 step (3.0dB) 1 step 1 step 1 step 1 step (0.375dB) (0.375dB) (0.375dB) (0.375dB) Table 27. ALC Limiter ATT Step (x: Don’t care) x x ZTM1 bit ZTM0 bit 0 0 1 1 0 1 0 1 Zero Crossing Timeout Period 8kHz 32kHz 48kHz 128/fs 16ms 4ms 2.7ms 256/fs 32ms 8ms 5.3ms 512/fs 64ms 16ms 10.7ms 1024/fs 128ms 32ms 21.3ms Table 28. ALC Zero Crossing Timeout Period MS0672-E-00 (default) 2007/11 - 40 - [AK4691] 2. ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits (Table 29) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 26) during the wait time, the ALC recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 30) up to the set reference level (Table 31) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 28). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation period is set by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery operation waits until WTM2-0 period and the next recovery operation is executed. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0 bits), the IVOL values are not increased. When “ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation is set by RFST1-0 bits (Table 32). WTM2 bit 0 0 0 0 1 1 1 1 WTM1 bit 0 0 1 1 0 0 1 1 WTM0 ALC Recovery Operation Waiting Period bit 8kHz 32kHz 48kHz 0 128/fs 16ms 4ms 2.7ms 1 256/fs 32ms 8ms 5.3ms 0 512/fs 64ms 16ms 10.7ms 1 1024/fs 128ms 32ms 21.3ms 0 2048/fs 256ms 64ms 42.7ms 1 4096/fs 512ms 128ms 85.3ms 0 8192/fs 1024ms 256ms 170.7ms 1 16384/fs 2048ms 512ms 341.3ms Table 29. ALC Recovery Operation Waiting Period RGAIN1 bit 0 0 1 1 RGAIN0 bit GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 30. ALC Recovery GAIN Step MS0672-E-00 (default) (default) 2007/11 - 41 - [AK4691] REF7-0 bits GAIN(dB) MIC LINE (GSEL bit = “0”) (GSEL bit = “1”) F1H +36.0 +6.0 F0H +35.625 +5.625 EFH +35.25 +5.25 : : : E2H +30.375 +0.375 E1H +30.0 0 (default) E0H +29.625 -0.375 DFH +29.25 -0.75 : : : 04H -52.875 -82.875 03H -53.25 -83.25 02H -53.625 -83.625 01H -54.0 -84.0 00H MUTE MUTE Table 31. Reference Level at ALC Recovery operation (0.375dB step) RFST1 bit RFST0 bit Limiter / Recovery Speed 0 0 4 times (default) 0 1 8 times 1 0 16 times 1 1 N/A Table 32. Fast Limiter / Recovery Speed Setting (N/A: Not Available) MS0672-E-00 2007/11 - 42 - [AK4691] 3. Example of ALC Operation Table 33 shows the examples of the ALC setting for MIC recording. Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or larger data to ZTM1-0 bits Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Gain of IVOL Limiter ATT step Recovery GAIN step ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=48kHz Operation −4.1dBFS Enable 21.3ms 001 32ms 011 21.3ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 00 00 1 1 step 1 step Enable 00 1 step 00 1 step 1 Enable Table 33. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = “0” or PMADC1=PMADC2 = PMDAC bits = “0”. • LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, GSEL, RFST1-0, LFST bits Manual Mode Example: MIC Input Recording Limiter = Zero crossing Enable Recovery Cycle = 21.3ms@48kHz Zero Crossing Timeout Period = 21.3ms@48kHz Limiter and Recovery Step = 1 Fast Limiter/Recovery Speed = 4 step Gain of IVOL = +30.0dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS LFST bit = “0” ALC bit = “1” WR (ZTM1-0, WTM2-0) (1) Addr=0AH, Data=1BH WR (ZELMN, RGAIN1-0, LMAT1-0) (2) Addr=0BH, Data=00H WR (LFST, RFST1-0, GSEL, LMTH1-0) (3) Addr=0CH, Data=01H WR (REF7-0) * The value of IVL/R should be the same or smaller than REF’s (4) Addr=0DH, Data=E1H WR (IVL/R7-0) (5) Addr=0EH & 10H, Data=E1H WR (ALC= “1”) (6) Addr=12H, Data=04H ALC Operation Note : WR : Write Figure 26. Registers set-up sequence at ALC operation MS0672-E-00 2007/11 - 43 - [AK4691] ■ FADEIN Mode In FADEIN Mode, the IVL/R values increase gradually by the step set by FDATT1-0 bits when FDIN bit changes from “0” to “1”. The FADEIN period is set by REF7-0, FDATT1-0 (Table 35) and FDTM1-0 (Table 34) bits. The FADEIN operation is executed by the zero crossing detection. The operation stops when the IVL/R values become the REF value or the limiter detection level (LMTH1-0). If the limiter operation is executed during FADAIN period, the FADEIN operation stops and the ALC operation starts. NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation. SDTO1, 2 IVL/R7-0 bits XXH 00H ALC bit FDIN bit (5) (1) (3) (2) (4) Figure 27. Example for controlling sequence in FADEIN operation (1) WR(IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”. (2) WR (ALC bit = FDIN bit = “0”): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written in “0”. (3) WR (ALC bit = FDIN bit = “1”): The FADEIN operation starts. The IVL/R is fade-in from MUTE state. (4) The FADEIN operation is repeated until the limiter detection level (LMTH1-0 bits) or the reference level (REF7-0 bits). After completing the FADEIN operation, the ALC operation starts. (5) FADEIN time is set by REF7-0, FDTM1-0, and FDATT bits e.g. REF7-0 = E1H(225 dec), FDTM1-0 = “01” (= 42.7ms @ fs = 48kHz), FDATT1-0 = 2 step (225 x FDTM1-0) / FDATT1-0 = 225 x 42.7ms /2 = 4.8s FDTM1 bit FDTM0 bit 0 0 1 1 0 1 0 1 FADEIN/OUT Period 8kHz 32kHz 1024/fs 128ms 32ms 2048/fs 256ms 64ms 2304/fs 288ms 72ms 2560/fs 320ms 80ms Table 34. FADEIN/OUT Period FDATT1 bit FDATT0 bit (default) ATT STEP 0 0 1 0 1 2 1 0 3 1 1 4 Table 35. FADEIN/OUT ATT Step Setting MS0672-E-00 48kHz 21.3ms 42.7ms 48ms 53.3ms (default) 2007/11 - 44 - [AK4691] ■ FADEOUT Mode In FADEOUT mode, the present IVL/R values decrease gradually down to the MUTE state when FDOUT bit changes from “0” to “1”. The operation is executed by the zero crossing detection. If the large signal is supplied to the ALC circuit during the FADEOUT operation, the ALC limiter operation starts. However, the total time of the FADEOUT operation is the same time, even if the limiter operation is executed. The period of FADEOUT is set by FDTM1-0 bits (Table 34), the number of step is set by FDATT1-0 bits (Table 35). When FDOUT bit changes into “0” during the FADEOUT operation, the ALC operation starts from the present IVL/R values. When FDOUT and ALC bits change into “0” at the same time, the FADEOUT operation stops and the IVL/R keeps the value at that time. NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation. SDTO1, 2 IVL/R7-0 bits XXH 00H ALC bit FDOUT bit (2) (1) (3) (4) (5) (6) (7) (8) (9) Figure 28. Example for controlling sequence in FADEOUT operation (1) WR (FDOUT bit = “1”): The FADEOUT operation starts. Then ALC bit should be always “1”. (2) FADEOUT time is set by REF7-0, FDTM1-0 and FDATT bits. e.g. REF7-0 = E1H(225 dec), FDTM1-0 = “01” (= 42.7ms @ fs = 48kHz), FDATT1-0 = 2 step (225 x FDTM1-0) / FDATT1-0 = 225 x 42.7ms / 2 = 4.8s (3) The FADEOUT operation is completed. The IVL/R values are the MUTE state. If FDOUT bit keeps “1”, the IVL/R values keep the MUTE state. (4) Analog and digital outputs are muted externally. Then the IVL/R values are MUTE state. (5) WR (IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”. (6) WR (ALC bit = FDOUT bit = “0”): Exit the ALC and FADEOUT operations (7) WR (IVL/R7-0 bits = XXH): The IVL/R value should be set to the same or smaller than REF’s. (8) WR (ALC bit = “1”, FDOUT bit = “0”): The ALC operation restarts. But the ALC bit should be written until completing zero crossing detection operation of IVL/R. (9) Release an external mute function for analog and digital outputs. MS0672-E-00 2007/11 - 45 - [AK4691] ■ Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is for the case shown below. The volume setting is common to ADC1 and ADC2 and has two tables that are LINE and MIC. 1. 2. 3. After exiting reset state, when setting up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 36). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADC1 = PMADC2 = PMDAC bits = “0”, IVOL operation starts with the written values at the end of the ADC/DAC initialization cycle after PMADC1, PMADC2, or PMDAC bit is changed to “1”. Even if the path is switched from recording to playback, the register setting of IVL/R remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB) at GSEL bit = “0”. GAIN(dB) MIC LINE (GSEL bit = “0”) (GSEL bit = “1”) F1H +36.0 +6.0 F0H +35.625 +5.625 EFH +35.25 +5.25 : : : E2H +30.375 +0.375 E1H +30.0 0 (default) E0H +29.625 -0.375 DFH +29.25 -0.75 : : : 04H -52.875 -82.875 03H -53.25 -83.25 02H -53.625 -83.625 01H -54.0 -84.0 00H MUTE MUTE Table 36. Input Digital Volume Setting IVL7-0 bits IVR7-0 bits MS0672-E-00 2007/11 - 46 - [AK4691] When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written in an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero-crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero-crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) Disable E1(+30dB) --> F1(+36dB) (1) E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 29. IVOL value during ALC operation (GSEL bit = “0”) (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. (2) Writing to IVL and IVR registers (0EH, 10H) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” with an interval more than zero crossing timeout period after ALC bit = “0”. ■ De-emphasis Filter The AK4691 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 37). DEM1 bit 0 0 1 1 DEM0 bit Mode 0 44.1kHz 1 OFF 0 48kHz 1 32kHz Table 37. De-emphasis Control MS0672-E-00 (default) 2007/11 - 47 - [AK4691] ■ Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 38). If the BST1-0 bits are set to “01” (MIN Level), use a 47μF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 30 shows the boost frequency response at –20dB signal input. Boost Filter (fs=48kHz) 20 MAX Level [dB] 15 MID 10 MIN 5 0 -5 10 100 1000 10000 Frequency [Hz] Figure 30. Bass Boost Frequency Response (fs = 48kHz) BST1 bit 0 0 1 1 BST0 bit Mode 0 OFF 1 MIN 0 MID 1 MAX Table 38. Bass Boost Control MS0672-E-00 (default) 2007/11 - 48 - [AK4691] ■ Digital Output Volume The AK4691 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is placed in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transit function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 40). When DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=22.1ms@fs=48kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 bits Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB : : 18H 0dB (default) : : FDH −114.5dB FEH −115.0dB FFH MUTE (−∞) Table 39. Digital Volume Code Table DVTM bit 0 1 Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=48kHz 1061/fs 133ms 22.1ms 256/fs 32ms 5.3ms Table 40. Transition Time Setting of Digital Output Volume MS0672-E-00 (default) 2007/11 - 49 - [AK4691] ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit is changed to “1”, the output signal is attenuated by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 31). S M U T E bit D VTM bit D VL/R 7-0 bits D VTM bit (1) (3) A ttenuation -∞ GD (2) GD A nalog O utput Figure 31. Soft Mute Function (1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0672-E-00 2007/11 - 50 - [AK4691] ■ Analog Mixing: Mono Input When the PMBP bit is set to “1”, the mono input is powered-up. When the BEEPS bit is set to “1”, the input signal from the BEEP pin is output to Speaker-Amp. When the BEEPH bit is set to “1”, the input signal from the BEEP pin is output to Headphone-Amp. When the BEEPL bit is set to “1”, the input signal from the BEEP pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of BEEP input. Table 41, Table 42 and Table 43 show the typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Ri BEEPL bit Signal LOUT/ROUT pin BEEP pin BEEPH bit HPL/HPR pin BEEPS bit SPP/SPN pin Figure 32. Block Diagram of BEEP pin LVOL2 bit LVOL1 bit LVOL0 bit BEEP Æ LOUT/ROUT 0 0 0 0dB (default) 0 0 1 +2dB 0 1 0 +5.9dB 0 1 1 +6.5dB 1 0 0 +7.1dB 1 0 1 N/A 1 1 x N/A Table 41. BEEP Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ (N/A: Not available) HPG bit BEEP Æ HPL/HPR 0 (default) −20dB 1 −16.4dB Table 42. BEEP Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ BEEP Æ SPP/SPN ALC bit = “0” ALC bit = “1” 00 +4.43dB +6.43dB (default) 01 +6.43dB +8.43dB 10 +10.65dB +12.65dB 11 +12.65dB +14.65dB Table 43. BEEP Input Æ Speaker-Amp Output Gain (typ) at Ri = 20kΩ SPKG1-0 bits MS0672-E-00 2007/11 - 51 - [AK4691] ■ Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is muted and LOUT/ROUT pins output LVCM voltage. The load impedance is 10kΩ (min.). LVOL2-0 bits set the gain of stereo line output. The Power supply voltage for LINEOUT-Amp is supplied from LVDD pin. The output level of LINEOUT is constant regardless of LVDD voltage. When the output voltage of LVDD pin is low, the distortion of LINEOUT degrades. Stereo LINEOUT has two kinds of power-save mode in order to support a common connector of LINEIN/OUT. DACL bit LVOL2-0 bits LOUT pin DAC ROUT pin Figure 33. Stereo Line Output LVOL2 bit 0 0 0 0 1 1 1 LVOL1 bit LVOL0 bit Gain AVDD voltage LINEOUT 0 0 0dB 3.0V -3.9dBV 0 1 +2dB 3.0V -1.9dBV 1 0 +5.9dB 3.0V +2dBV 1 1 +6.5dB 2.8V +2dBV 0 0 +7.1dB 2.6V +2dBV 0 1 N/A 1 x Table 44. Stereo Line Output Volume Setting (x: Don’t care, N/A: Not Available) (default) 1. LMODE bit = “1” (When Line input and Line output are not used as a common connector.) When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS4 by 100kΩ (typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS4 by 20kΩ after AC coupled as Figure 34. Rise/Fall time is 300ms (max) at C=1μF. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation. LOPS bit 0 1 PMLO bit Mode LOUT/ROUT pins 0 Power-down Pull-down to VSS4 1 Normal Operation Normal Operation 0 Power-save Fall down to VSS4 1 Power-save Rise up to LVCM Table 45. Stereo Line Output Mode Select @ LMODE bit = “1” LOUT pin ROUT pin (default) 220Ω 1μF 20kΩ Figure 34. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0672-E-00 2007/11 - 52 - [AK4691] Rising Time (Note 53) Falling Time (Note 54) typ. max typ. max. 3.6V 200ms 300ms 200ms 300ms 5.5V 220ms 400ms 260ms 440ms Note 53. Rising time of stereo line output (0.9 x LVCM) Note 54. Falling time of stereo line output (This time is until the voltage between 220Ω and 20kΩ resistors as shown in Figure 34 becomes less than 50mV.) Table 46. Rising / Falling time of stereo line output LVDD [Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)] E.g. In case of LVDD = 3.6V (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 35. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to LVCM voltage. Rise time is 200ms (max 300ms) at C=1μF. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “1”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to VSS4. Fall time is 200ms (max 300ms) at C=1μF. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0672-E-00 2007/11 - 53 - [AK4691] 2. LMODE bit = “0” (When Line input and Line output are used as a common connector.) When PMLO bit bit = “0”, the stereo line output enters power-down mode and the output becomes Hi-Z status. When the LOPS bit is “1”, stereo line output (LOUT/ROUT pins) enters power-save mode and outputs LVCM voltage via an internal resistor (typ. 200kΩ). In power-save mode, the signal path of stereo line output (DACL, BEEPL, MICL1, MICL2, and MICR1 bits) is OFF. Pop noise can be decreased by using power-save mode. When using line input, the AK4691 should be in the power-save mode. PMLO bit 0 LOPS bit Mode LOUT/ROUT pins x Power-down Hi-Z (default) 1 Power-save LVCM 1 0 Normal Operation Normal Operation Table 47. External Circuit for Stereo Line Output @ LMODE bit = “0” (x: Don’t care) typ.60kΩ /100kΩ 6.2kΩ LIN pin (RIN pin) typ.100kΩ - Connector AIN bit = “1” 6.2kΩ To ADC1 + MIX-Amp VCOM typ. 60kΩ From Pre-Amp1 PRE bit = “0” LOUT pin (ROUT pin) typ.200kΩ LVCM Power-save Mode Figure 36. Connection Example (When Line input and Line output are used as a common connector.) MS0672-E-00 2007/11 - 54 - [AK4691] ■ Headphone Output Power supply voltage for the Headphone-Amp is supplied from the LVDD pin and centered on the LVDD/2 voltage. The load resistance is 16Ω (min). HPG bit selects the output voltage (Table 48). HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Table 48. Headphone-Amp Output Voltage When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) become to “L” (VSS4). When HPMTN bit is “1”, the common voltage rises to LVDD/2. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to LVDD voltage and the capacitor at the MUTET pin. LVDD Capacitor value of MUTET pin HPMTN bit= “0” Æ “1” (Note 55) typ. max 120ms 210ms 160ms 270ms 260ms 460ms 340ms 590ms HPMTN bit = “1” Æ “0” (Note 56) typ. max. 140ms 260ms 170ms 300ms 310ms 560ms 370ms 600ms 3.6V 1μF±30% 5.5V 3.6V 2.2μF±30% 5.5V Note 55. Rising time of HP-Amp (0.8 x LVDD/2) Note 56. Time until the common voltage settles to VSS4 Table 49. Relationship between capacitor value of MUTET pin and MUTE ON/OFF time (HPG bit = “0”) When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) become to “L” (VSS4). PMHPL/R bits 0 1 HPMTN bit x Mode HPL pin HPR pin Power-down “L”(VSS4) “L”(VSS4) Fall down to 0 “L”(VSS4) “L”(VSS4) common voltage Rise up to common 1 Normal operation Normal operation voltage Table 50. Headphone-Amp Mode Setting (x: Don’t care) MS0672-E-00 (default) 2007/11 - 55 - [AK4691] PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 37. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still VSS4. (2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are VSS4. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage settles to VSS4, some POP noise occurs. When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 51 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at AVDD = LVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp)@HPG bit = “0”, 0.91 x AVDD(Vpp)@HPG bit = “1”. When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22μF±20% capacitor and 10Ω±20% resistor) because there is a possibility that Headphone-Amp oscillates. HP-AMP AK4691 R 0.22μ C Headphone 16Ω 10Ω Figure 38. External Circuit Example of Headphone HPG bit R [Ω] 6.8 0 16 0 1 100 C [μF] 100 47 100 47 220 100 22 10 fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN @fs=44.1kHz 70 28 149 78 50 19 106 47 45 17 100 43 62 25 137 69 Table 51. External Circuit Example MS0672-E-00 Output Power [mW]@0dBFS 2.7V 3.0V 3.3V 10.1 12.5 15.1 5.1 6.3 7.7 33 41 50 0.9 1.1 1.3 2007/11 - 56 - [AK4691] ■ Speaker Output When DACS bit is set to “1”, the DAC output signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits. SPKG1-0 bits 00 01 10 11 Gain ALC bit = “0” ALC bit = “1” +4.43dB +6.43dB +6.43dB +8.43dB +10.65dB +12.65dB +12.65dB +14.65dB Table 52. SPK-Amp Gain (default) SPK-Amp Output (DAC Input = 0dBFS) ALC bit = “0” ALC bit = “1” (LMTH1-0 bits = “00”;-2.5dBFS) 00 3.0Vpp 2.83Vpp 01 3.77Vpp 3.56Vpp 3.0V 10 4.0Vpp (Note 57) 4.0Vpp (Note 57) 11 4.0Vpp (Note 57) 4.0Vpp (Note 57) 3.0V 00 3.0Vpp 2.83Vpp 01 3.77Vpp 3.56Vpp 3.3V 10 4.6Vpp (Note 57) 4.6Vpp (Note 57) 11 4.6Vpp (Note 57) 4.6Vpp (Note 57) Note 57. The output level is calculated on the assumption that output signal is not clipped. In actual case, output signal may be clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital volume so that Speaker-Amp output level is 4.0Vpp (@ SVDD = 3.0V), 4.6Vpp (@ SVDD = 3.3V) or less and output signal is not clipped. Table 53. SPK-Amp Output Level AVDD SVDD SPKG1-0 bits MS0672-E-00 2007/11 - 57 - [AK4691] <ALC Operation Example of Speaker Playback> fs=48kHz Operation −2.5dBFS Enable 10.7ms Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or larger data to ZTM1-0 bits Maximum gain at recovery operation 011 21.3ms C1H +18dB Gain of IVOL 91H 0dB WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Data 00 0 10 Limiter ATT step 00 Recovery GAIN step 00 ALC enable 1 Table 54. ALC Operation Example of Speaker Playback 1 step 1 step Enable <Speaker-Amp Control Sequence> Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pin are in Hi-Z state. When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, the SPP pin is placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage. Power-save mode can reduce pop noise at power-up and power-down. PMSPK bit 0 1 SPPSN bit Mode SPP pin SPN pin x Power-down Hi-Z Hi-Z 0 Power-save Hi-Z SVDD/2 1 Normal Operation Normal Operation Normal Operation Table 55. Speaker-Amp Mode Setting (x: Don’t care) (default) PMSPK bit SPPSN bit SPP pin SPN pin Hi-Z Hi-Z Hi-Z SVDD/2 SVDD/2 Hi-Z Figure 39. Power-up/Power-down Timing for Speaker-Amp ■ MUTE Function When the MUTE pin is “H”, the output signals of LINEOUT, Headphone-Amp, and Speaker-Amp are muted, and become VCOM or LVCM voltage. LINEOUT and Speaker-Amp become Power-save mode, HP-Amp is in mute state. And switches of DACL, DACS, DACH, BEEPL, BEEPS, BEEPH, MICL1, MICR1, and MICL2 become “OFF” at the same time. MS0672-E-00 2007/11 - 58 - [AK4691] ■ Serial Control Interface (1) 3-wire Serial Control Mode (I2CN pin = “H”) (1)-1. Specific address WRITE Mode Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Writing data becomes effective between the 16th CCLK rising edge (“↑”) and CSN rising edge (“↑”) after CSN falling edge(“↓”). CSN should be set to “H” every one command. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK Clock, “H” or “L” CDTI “H” or “L” Clock, “H” or “L” C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “1” C1: R/W: A5-A0: D7-D0: “H” or “L” Chip Address; Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 40. Serial Control I/F Timing 1 MS0672-E-00 2007/11 - 59 - [AK4691] (1)-2. Continuous Data WRITE Mode In this mode, data can be written continuously and address counter is incremented automatically. Internal registers may be written by the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control data (MSB first, 8bits x N). Each bit is clocked in on the rising edge (“↑”) of CCLK. Writing data becomes effective between the 16th CCLK rising edge (“↑”) and falling edge (“↓”). When the μP continues sending CDTI and CCLK in CSN = “L”, address counter is incremented automatically, and writing data becomes effective between the 8th CCLK rising edge (“↑”) and falling edge (“↓”). For the last address (33H), writing data becomes effective between the 8th CCLK rising edge (“↑”) and CSN rising edge (“↑”). When data is written to an arbitrary address before the last address, WRITE operation can be finished by setting CSN = “H”. Note 58. When CSN is set to “H” while data is written, the data is ignored. Note 59. After data in the last address (33H) becomes effective, CSN should be set to “H”. If the uP continues sending CCLK and CDTI in CSN = “L”, data is rewritten in address 33H. CSN 0 CCLK Clock, ‘H’ or ‘L’ CDTI ‘H’ or ‘L’ 1 2 3 4 5 6 7 8 9 14 15 0 1 6 7 0 1 6 7 Clock, ‘H’ or ‘L’ C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 “1” D1 D0 D7 D6 D1 D0 D7 D6 D1 D0 ‘H’ or ‘L’ “1” Data (n) Data (n+1) Data (n+N-1) Address (n) C1: R/W: A5-A0: D7-D0: Chip Address (C1= “1”); Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 41. Control Data Timing 2 MS0672-E-00 2007/11 - 60 - [AK4691] (2) I2C-bus Control Mode (I2CN pin = “L”) The AK4691 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at the SCL and SDA pins should be connected to (TVDD2 + 0.3)V or less voltage. (2)-1. WRITE Operations Figure 42 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 48). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure 43). If the slave address matches that of the AK4691, the AK4691 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 49). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4691. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 44). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 45). The AK4691 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 48). The AK4691 can perform more than one byte write operation per sequence. After receiving the third byte the AK4691 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 50) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 42. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CAD0 R/W A2 A1 A0 D2 D1 D0 (The CAD0 should match with CAD0 pin) Figure 43. The First Byte 0 0 A5 A4 A3 Figure 44. The Second Byte D7 D6 D5 D4 D3 Figure 45. Byte Structure after the second byte MS0672-E-00 2007/11 - 61 - [AK4691] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4691. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after receiving the first data word. After receiving each data packet the internal 5-bit address counter is incremented, and the next data is automatically taken into the next address. If the address exceeds 33H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4691 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4691 contains an internal address counter. The “current address read” operation reads the data appointed by the counter. The counter is incremented by one from the address number of the last word accessed. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receiving the slave address with R/W bit “1”, the AK4691 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4691 ceases transmission. S T A R T Slave S Address SDA S T O P R/W="1" Data(n) Data(n+1) Data(n+2) MA AC SK T E R A C K MA AC SK T E R Data(n+x) MA AC SK T E R MA AC SK T E R P MN AA SC T EK R Figure 46. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4691 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4691 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) MA AC S K T E R Data(n+x) MA AC S T K E R MA AC S T K E R P MN A A S T C E K R Figure 47. RANDOM ADDRESS READ MS0672-E-00 2007/11 - 62 - [AK4691] SDA SCL S P start condition stop condition Figure 48. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 49. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 50. Bit Transfer on the I2C-Bus MS0672-E-00 2007/11 - 63 - [AK4691] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H Register Name Power Management 1 Power Management 2 Mode Control 1 Mode Control 2 Mode Control 3 Pre-Amp Gain Select Signal Select 1 Signal Select 2 HP/SPK Gain Select Mode Control 4 Timer Select ALC Mode Control 1 ALC Mode Control 2 ALC Mode Control 3 Lch Input Volume Control Lch Digital Volume Control Rch Input Volume Control Rch Digital Volume Control ALC Mode Control 4 Mode Control 5 Mode Control 6 Mode Control 7 Digital Filter Select 1 FIL3A Co-efficient 0 FIL3A Co-efficient 1 FIL3A Co-efficient 2 FIL3A Co-efficient 3 EQA Co-efficient 0 EQA Co-efficient 1 EQA Co-efficient 2 EQA Co-efficient 3 EQA Co-efficient 4 EQA Co-efficient 5 FIL1A Co-efficient 0 FIL1A Co-efficient 1 FIL1A Co-efficient 2 FIL1A Co-efficient 3 Digital Filter Select 2 FIL3B Co-efficient 0 FIL3B Co-efficient 1 FIL3B Co-efficient 2 FIL3B Co-efficient 3 EQB Co-efficient 0 EQB Co-efficient 1 EQB Co-efficient 2 EQB Co-efficient 3 EQB Co-efficient 4 EQB Co-efficient 5 FIL1B Co-efficient 0 FIL1B Co-efficient 1 FIL1B Co-efficient 2 FIL1B Co-efficient 3 D7 PMMP 0 0 PLL3 ADM1 0 0 SPPSN 0 LVOL2 FDTM1 0 0 REF7 D6 D5 D4 D3 D2 D1 PMMICR2 PMMICL2 PMMICR1 PMMICL1 PMADC2 PMADC1 HPMTN 0 PLL2 ADM0 0 FB BEEPS 0 LVOL1 FDTM0 ZELMN 0 REF6 PMHPR BCKO PLL1 0 PRG22 AIN DACS MICL2 LVOL0 0 FDATT1 LFST REF5 PMHPL M/S PLL0 INITDA PRG21 PRE BEEPL MICR1 LOPS ZTM1 FDATT0 RFST1 REF4 PMSPK PS1 FS3 LMODE PRG20 PRSR2 DACL MICL1 0 ZTM0 RGAIN1 RFST0 REF3 PMLO PS0 FS2 HPFN PRG12 PRSL2 HPM HPG 0 WTM2 RGAIN0 GSEL REF2 PMDAC MCKO FS1 DIF1 PRG11 PRSR1 BEEPH SPKG1 DVOLC WTM1 LMAT1 LMTH1 REF1 D0 PMVCM PMBP PMPLL FS0 DIF0 PRG10 PRSL1 DACH SPKG0 IVOLC WTM0 LMAT0 LMTH0 REF0 IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 DVL7 IVR7 DVR7 0 LOOP1 0 0 GN1A F3A7A F3ASA F3B7A 0 EQA7A EQA15A EQB7A 0 EQC7A EQC15A F1A7A F1ASA F1B7A 0 GN1B F3A7B F3ASB F3B7B 0 EQA7B EQA15B EQB7B 0 EQC7B EQC15B F1A7B F1ASB F1B7B 0 DVL6 IVR6 DVR6 0 LOOP0 0 0 GN0A F3A6A 0 F3B6A 0 EQA6A EQA14A EQB6A 0 EQC6A EQC14A F1A6A 0 F1B6A 0 GN0B F3A6B 0 F3B6B 0 EQA6B EQA14B EQB6B 0 EQC6B EQC14B F1A6B 0 F1B6B 0 DVL5 IVR5 DVR5 0 SMUTE MGR12 MGR22 0 F3A5A F3A13A F3B5A F3B13A EQA5A EQA13A EQB5A EQB13A EQC5A EQC13A F1A5A F1A13A F1B5A F1B13A 0 F3A5B F3A13B F3B5B F3B13B EQA5B EQA13B EQB5B EQB13B EQC5B EQC13B F1A5B F1A13B F1B5B F1B13B DVL4 IVR4 DVR4 0 DVTM MGR11 MGR21 FIL1A F3A4A F3A12A F3B4A F3B12A EQA4A EQA12A EQB4A EQB12A EQC4A EQC12A F1A4A F1A12A F1B4A F1B12A FIL1B F3A4B F3A12B F3B4B F3B12B EQA4B EQA12B EQB4B EQB12B EQC4B EQC12B F1A4B F1A12B F1B4B F1B12B DVL3 IVR3 DVR3 0 BST1 MGR10 MGR20 EQA F3A3A F3A11A F3B3A F3B11A EQA3A EQA11A EQB3A EQB11A EQC3A EQC11A F1A3A F1A11A F1B3A F1B11A EQB F3A3B F3A11B F3B3B F3B11B EQA3B EQA11B EQB3B EQB11B EQC3B EQC11B F1A3B F1A11B F1B3B F1B11B DVL2 IVR2 DVR2 ALC BST0 MGL12 MGL22 FIL3A F3A2A F3A10A F3B2A F3B10A EQA2A EQA10A EQB2A EQB10A EQC2A EQC10A F1A2A F1A10A F1B2A F1B10A FIL3B F3A2B F3A10B F3B2B F3B10B EQA2B EQA10B EQB2B EQB10B EQC2B EQC10B F1A2B F1A10B F1B2B F1B10B DVL1 IVR1 DVR1 FDOUT DEM1 MGL11 MGL21 0 F3A1A F3A9A F3B1A F3B9A EQA1A EQA9A EQB1A EQB9A EQC1A EQC9A F1A1A F1A9A F1B1A F1B9A 0 F3A1B F3A9B F3B1B F3B9B EQA1B EQA9B EQB1B EQB9B EQC1B EQC9B F1A1B F1A9B F1B1B F1B9B DVL0 IVR0 DVR0 FDIN DEM0 MGL10 MGL20 0 F3A0A F3A8A F3B0A F3B8A EQA0A EQA8A EQB0A EQB8A EQC0A EQC8A F1A0A F1A8A F1B0A F1B8A 0 F3A0B F3A8B F3B0B F3B8B EQA0B EQA8B EQB0B EQB8B EQC0B EQC8B F1A0B F1A8B F1B0B F1B8B Note 60. PDN pin = “L” resets the registers to their default values. Note 61. Write “0” data to the bits named “0”. MS0672-E-00 2007/11 - 64 - [AK4691] ■ Register Definitions Addr 00H Register Name Power Management 1 R/W Default D7 PMMP R/W 0 D6 D5 D4 D3 D2 D1 PMMICR2 PMMICL2 PMMICR1 PMMICL1 PMADC2 PMADC1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D0 PMVCM R/W 0 PMVCM: VCOM and LVCM Power Management 0: Power-down (default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H and 01H, PMPLL and MCKO bits are “0”. PMADC1: ADC1 Power Management 0: Power-down (default) 1: Power-up PMADC2: ADC2 Power Management 0: Power-down (default) 1: Power-up When the PMADC1 or PMADC2 bit is changed from “0” to “1”, the initialization cycle (1059/fs=22.1ms @48kHz) starts. After initializing, digital data of the ADC is output. PMMICL1: Lch Pre-Amp #1 Power Management 0: Power-down (default) 1: Power-up PMMICR1: Rch Pre-Amp #1 Power Management 0: Power-down (default) 1: Power-up PMMICL2: Lch Pre-Amp #2 Power Management 0: Power-down (default) 1: Power-up PMMICR2: Rch Pre-Amp #2 Power Management 0: Power-down (default) 1: Power-up PMMP: MPWR pin Power Management 0: Power-down. Pull-down to VSS1 with 5.3kΩ (typ.) (default) 1: Power-up MS0672-E-00 2007/11 - 65 - [AK4691] Addr 01H Register Name Power Management 2 R/W Default D7 0 RD 0 D6 HPMTN R/W 0 D5 PMHPR R/W 0 D4 PMHPL R/W 0 D3 PMSPK R/W 0 D2 PMLO R/W 0 D1 PMDAC R/W 0 D0 PMBP R/W 0 PMBP: BEEP Input Power Management 0: Power-down (default) 1: Power-up Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL, BEEPH, BEEPS, MICL1, MICR1, or MICL2 bit is used to control each path when BEEP input is used. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Lineout Power Management 0: Power-down (default) 1: Power-up PMSPK: Speaker-Amp Power Management 0: Power-down (default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (default) 1: Power-up PMHPR: Headphone-Amp Rch Power Management 0: Power-down (default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (default) 1: Normal operation Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H and 01H addresses, PMPLL bit and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0672-E-00 2007/11 - 66 - [AK4691] Addr 02H Register Name Mode Control 1 R/W Default D7 0 RD 0 D6 0 RD 0 D5 BCKO R/W 0 D4 M/S R/W 0 D3 PS1 R/W 0 D2 PS0 R/W 0 D1 MCKO R/W 0 D0 PMPLL R/W 0 D3 FS3 R/W 0 D2 FS2 R/W 0 D1 FS1 R/W 0 D0 FS0 R/W 0 D1 DIF1 R/W 1 D0 DIF0 R/W 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (default) 1: Enable: Output frequency is selected by PS1-0 bits. PS1-0: MCKO Output Frequency Select (Table 9) Default: “00” (256fs) M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode BCKO: BICK Output Frequency Select at Master Mode (Table 10) Default: “0” (32fs) Addr 03H Register Name Mode Control 2 R/W Default D7 PLL3 R/W 0 D6 PLL2 R/W 0 D5 PLL1 R/W 0 D4 PLL0 R/W 0 FS3-0: Sampling Frequency Select (Table 5, Table 6.) and MCKI Frequency Select (Table 11) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. PLL3-0: PLL Reference Clock Select (Table 4) Default: “0000”(LRCK pin) Addr 04H Register Name Mode Control 3 R/W Default D7 ADM1 R/W 0 D6 ADM0 R/W 0 D5 0 RD 0 D4 INITDA R/W 0 D3 LMODE R/W 0 D2 HPFN R/W 0 DIF1-0: Audio Interface Format (Table 13) Default: “10” (Left justified) HPFN: HPF Control on DAC 0: Enable (default) 1: Disable LMODE: Select power-save mode of stereo line output (Table 45, Table 47) INITDA: DAC Initialization Cycle Enable 0: Enable (Initialization Cycle= 1059/fs) (default) 1: Disable ADM1-0: ADC Mono Mode (Table 21) Default: “00” (Stereo Output) MS0672-E-00 2007/11 - 67 - [AK4691] Addr 05H Register Name Pre-Amp Gain Select R/W Default D7 0 RD 0 D6 0 RD 0 D5 PRG22 R/W 0 D4 PRG21 R/W 1 D3 PRG20 R/W 1 D2 PRG12 R/W 0 D1 PRG11 R/W 1 D0 PRG10 R/W 1 D5 AIN R/W 0 D4 PRE R/W 1 D3 PRSR2 R/W 0 D2 PRSL2 R/W 0 D1 PRSR1 R/W 0 D0 PRSL1 R/W 0 PRG12-10: Pre-Amp #1 Gain Setting (Table 15) Default: “011” (+24dB) PRG22-20: Pre-Amp #2 Gain Setting (Table 15) Default: “011” (+24dB) Addr 06H Register Name Signal Select 1 R/W Default D7 0 RD 0 D6 FB R/W 0 PRSL1: Select input signal of Lch Pre-Amp #1 0: INTL1 pin (default) 1: EXTL1 pin PRSR1: Select input signal of Rch Pre-Amp #1 0: INTR1 pin (default) 1: EXTR1 pin PRSL2: Select input signal of Lch Pre-Amp #2 0: INTL2 pin (default) 1: EXTL2 pin PRSR2: Select input signal of Rch Pre-Amp #2 0: INTR2 pin (default) 1: EXTR2 pin PRE: Enable input signal from Pre-Amp 1 to ADC1 0: OFF 1: ON (default) AIN: Enable input signal from LIN/RIN pin to ADC1 0: OFF (default) 1: ON FB: Select MIX-Amp feedback resistor 0: 60kΩ (typ) (default) 1: 100kΩ (typ) MS0672-E-00 2007/11 - 68 - [AK4691] Addr 07H Register Name Signal Select 2 R/W Default D7 SPPSN R/W 0 D6 BEEPS R/W 0 D5 DACS R/W 0 D4 BEEPL R/W 0 D3 DACL R/W 0 D2 HPM R/W 0 D1 BEEPH R/W 0 D0 DACH R/W 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (default) 1: ON BEEPH: Switch Control from the BEEP pin to Headphone-Amp 0: OFF (default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (default) 1: Mono When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-Amp. Both PMHPL and PMHPR bits should be “1” when HPM bit is “1”. DACL: Switch Control from DAC to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, DACL bit is enabled. BEEPL: Switch Control from the BEEP pin to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, BEEPL bit is enabled. DACS: Switch Control from DAC to Speaker-Amp 0: OFF (default) 1: ON When DACS bit is “1”, DAC output signal is input to Speaker-Amp. BEEPS: Switch Control from BEEP pin to Speaker-Amp 0: OFF (default) 1: ON When BEEPS bit is “1”, mono signal is input to Speaker-Amp. SPPSN: Speaker-Amp Power-Save Mode 0: Power-Save Mode (default) 1: Normal Operation When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, the SPP pin changes to Hi-Z and the SPN pin outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “H”, Speaker-Amp is in power-down mode since PMSPK bit is “0”. MS0672-E-00 2007/11 - 69 - [AK4691] Addr 08H Register Name HP/SPK Gain R/W Default D7 0 RD 0 D6 0 RD 0 D5 MICL2 R/W 0 D4 MICR1 R/W 0 D3 MICL1 R/W 0 D2 HPG R/W 0 D1 SPKG1 R/W 0 D0 SPKG0 R/W 0 D4 LOPS R/W 0 D3 0 RD 0 D2 0 RD 0 D1 DVOLC R/W 1 D0 IVOLC R/W 1 SPKG1-0: Speaker-Amp Output Gain Select (Table 52) HPG: Headphone-Amp Gain Select (Table 48) 0: 0dB (default) 1: +3.6dB MICL1: Select path from Lch Pre-Amp #1 to LOUT pin. 0: OFF (default) 1: ON When PMMICL1 = PMLO bits = “1”, MICL1 bit is enabled. MICR1: Select path from Rch Pre-Amp #1 to LOUT pin 0: OFF (default) 1: ON When PMMICR1 = PMLO bits = “1”, MICR1 bit is enabled. MICL2: Select path from Lch Pre-Amp #2 to LOUT pin 0: OFF (default) 1: ON When PMMICL2 = PMLO bits = “1”, MICL2 bit is enabled. Addr 09H Register Name Mode Control 4 R/W Default D7 LVOL2 R/W 0 D6 LVOL1 R/W 0 D5 LVOL0 R/W 0 IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (default) 1: Power-Save Mode LVOL2-0: Stereo Line Output Gain Select (Table 44) Default: “000” (0dB) MS0672-E-00 2007/11 - 70 - [AK4691] Addr 0AH Register Name Timer Select R/W Default D7 FDTM1 R/W 0 D6 FDTM0 R/W 1 D5 0 RD 0 D4 ZTM1 R/W 0 D3 ZTM0 R/W 0 D2 WTM2 R/W 1 D1 WTM1 R/W 0 D0 WTM0 R/W 0 D0 LMAT0 R/W 0 D0 LMTH0 R/W 0 WTM2-0: ALC Recovery Waiting Period (Table 29) Default: “100” (2048/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 28.) Default: “00” (128/fs) FDTM1-0: FADEIN/OUT Cycle Setting (Table 34) Default: “01” (2048/fs) Addr 0BH Register Name ALC Mode Control 1 R/W Default D7 0 RD 0 D6 ZELMN R/W 0 D5 D4 D3 D2 FDATT1 FDATT0 RGAIN1 RGAIN0 R/W 0 R/W 0 R/W 0 R/W 0 D1 LMAT1 R/W 0 D3 RFST0 R/W 0 D2 GSEL R/W 0 D1 LMTH1 R/W 0 LMAT1-0: ALC Limiter ATT Step (Table 27) Default: “00” RGAIN1-0: ALC Recovery GAIN Step (Table 30) Default: “00” FDATT1-0: FADEIN/OUT ATT Step Setting (Table 35) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable Addr 0CH Register Name ALC Mode Control 2 R/W Default D7 0 RD 0 D6 0 RD 0 D5 LFST R/W 0 D4 RFST1 R/W 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 26) Default: “00” GSEL: Select IVOL Gain 0: MIC (default) 1: LINE RFST1-0: ALC First limiter/recovery Speed (Table 32) Default: “00” (4 times) LFST: Setting of Limiter operation when input signal exceeds full-scale level 0: IVL/R values are changed at zero-crossing detection or zero-crossing timeout. (default) 1: IVL/R values are immediately (period: 1/fs) attenuated by 1step when ALC output signal exceeds full-scale level. MS0672-E-00 2007/11 - 71 - [AK4691] Addr 0DH Register Name ALC Mode Control 3 R/W Default D7 REF7 R/W 1 D6 REF6 R/W 1 D5 REF5 R/W 1 D4 REF4 R/W 0 D3 REF3 R/W 0 D2 REF2 R/W 0 D1 REF1 R/W 0 D0 REF0 R/W 1 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 31) Default: “E1H” (+30.0dB) Addr 0EH 10H Register Name Lch Input Volume Control Rch Input Volume Control R/W Default D7 IVL7 IVR7 R/W 1 D6 IVL6 IVR6 R/W 1 D5 IVL5 IVR5 R/W 1 D4 IVL4 IVR4 R/W 0 D3 IVL3 IVR3 R/W 0 D2 IVL2 IVR2 R/W 0 D1 IVL1 IVR1 R/W 0 D0 IVL0 IVR0 R/W 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 36) Default: “E1H” (+30.0dB) Addr 0FH 11H Register Name Lch Digital Volume Control Rch Digital Volume Control R/W Default D7 DVL7 DVR7 R/W 0 D6 DVL6 DVR6 R/W 0 D5 DVL5 DVR5 R/W 0 D4 DVL4 DVR4 R/W 1 D3 DVL3 DVR3 R/W 1 D2 DVL2 DVR2 R/W 0 D1 DVL1 DVR1 R/W 0 D0 DVL0 DVR0 R/W 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 ALC R/W 0 D1 FDOUT R/W 0 D0 FDIN R/W 0 DVL7-0, DVR7-0: Output Digital Volume (Table 39) Default: “18H” (0dB) Addr 12H Register Name ALC Mode Control 4 R/W Default D7 0 RD 0 D6 0 RD 0 ALC: ALC Enable 0: ALC Disable (default) 1: ALC Enable FDOUT: FADEOUT Enable 0: Disable (default) 1: Enable FDIN: FADEIN Enable 0: Disable (default) 1: Enable MS0672-E-00 2007/11 - 72 - [AK4691] Addr 13H Register Name Mode Control 5 R/W Default D7 LOOP1 R/W 0 D6 LOOP0 R/W 0 D5 SMUTE R/W 0 D4 DVTM R/W 0 D3 BST1 R/W 0 D2 BST0 R/W 0 D1 DEM1 R/W 0 D0 DEM0 R/W 1 DEM1-0: De-emphasis Frequency Select (Table 37) Default: “01” (OFF) BST1-0: Bass Boost Function Select (Table 38) Default: “00” (OFF) DVTM: Digital Volume Transition Time Setting (Table 40) 0: 1061/fs (default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted LOOP1-0: Digital Internal Loopback (Table 23, Table 25) 00: SDTI → DAC (default) 01: SDTO1 → DAC 10: SDTO2 → DAC 11: SDTO1 → DAC When LOOP1-0 bits = “10” (SDTO2 Æ DAC), TDM mode (DIF1-0 bits = “00”) is not supported. Addr 14H 15H Register Name Mode Control 6 Mode Control 6 R/W Default D7 0 0 RD 0 D6 0 0 RD 0 D5 MGR12 MGR22 R/W 0 D4 MGR11 MGR21 R/W 1 D3 MGR10 MGR20 R/W 0 D2 MGL12 MGL22 R/W 0 D1 MGL11 MGL21 R/W 1 D0 MGL10 MGL20 R/W 0 MGL12-10: MIC sensitivity compensation for INTL1/EXTL1 input MGR12-10: MIC sensitivity compensation for INTR1/EXTR1 input MGL22-20: MIC sensitivity compensation for INTL2/EXTL2 input MGR22-20: MIC sensitivity compensation for INTR2/EXTR2 input Default: “010” (0dB) (Table 17, Table 18) MS0672-E-00 2007/11 - 73 - [AK4691] Addr 16H Register Name Digital Filter Select 1 R/W Default D7 GN1A R/W 0 D6 GN0A R/W 0 D5 0 RD 0 D4 FIL1A R/W 0 D3 EQA R/W 0 D2 FIL3A R/W 0 D1 0 RD 0 D0 0 RD 0 FIL3A: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3A bit is “1”, the settings of F3A13A-0A and F3B13A-0A bits are enabled. When FIL3A bit is “0”, FIL3A block is OFF (MUTE). EQA: EQA (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQA bit is “1”, the settings of EQA15A-0A, EQB13A-0A and EQC15A-0A bits are enabled. When EQA bit is “0”, EQA block is through (0dB). FIL1A: FIL1A (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1A bit is “1”, the settings of F1A13A-0A and F1B13A-0A bits are enabled. When FIL1A bit is “0”, FIL1A block is through (0dB). GN1A-0A: Gain Select at GAIN block in ADC1 (Table 24) Default: “00” (0dB) MS0672-E-00 2007/11 - 74 - [AK4691] Addr 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name FIL3A Co-efficient 0 FIL3A Co-efficient 1 FIL3A Co-efficient 2 FIL3A Co-efficient 3 EQA Co-efficient 0 EQA Co-efficient 1 EQA Co-efficient 2 EQA Co-efficient 3 EQA Co-efficient 4 EQA Co-efficient 5 FIL1A Co-efficient 0 FIL1A Co-efficient 1 FIL1A Co-efficient 2 FIL1A Co-efficient 3 R/W Default D7 D6 D5 F3A7A F3A6A F3A5A F3ASA 0 F3A13A F3B7A F3B6A F3B5A 0 0 F3B13A EQA7A EQA6A EQA5A EQA15A EQA14A EQA13A EQB7A EQB6A EQB5A 0 0 EQB13A EQC7A EQC6A EQC5A EQC15A EQC14A EQC13A F1A7A F1A6A F1A5A F1ASA 0 F1A13A F1B7A F1B6A F1B5A 0 0 F1B13A R/W R/W R/W 0 0 0 D4 F3A4A F3A12A F3B4A F3B12A EQA4A EQA12A EQB4A EQB12A EQC4A EQC12A F1A4A F1A12A F1B4A F1B12A R/W 0 D3 D2 F3A3A F3A2A F3A11A F3A10A F3B3A F3B2A F3B11A F3B10A EQA3A EQA2A EQA11A EQA10A EQB3A EQB2A EQB11A EQB10A EQC3A EQC2A EQC11A EQC10A F1A3A F1A2A F1A11A F1A10A F1B3A F1B2A F1B11A F1B10A R/W R/W 0 0 D1 F3A1A F3A9A F3B1A F3B9A EQA1A EQA9A EQB1A EQB9A EQC1A EQC9A F1A1A F1A9A F1B1A F1B9A R/W 0 D0 F3A0A F3A8A F3B0A F3B8A EQA0A EQA8A EQB0A EQB8A EQC0A EQC8A F1A0A F1A8A F1B0A F1B8A R/W 0 F3A13A-0A, F3B13A-0A: FIL3A (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3ASA: FIL3A (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15A-0A, EQB13A-0A, EQC15A-C0A: EQA (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13A-0A, F1B13A-B0A: FIL1A (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1ASA: FIL1A (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF MS0672-E-00 2007/11 - 75 - [AK4691] Addr 25H Register Name Digital Filter Select 2 R/W Default D7 GN1B R/W 0 D6 GN0B R/W 0 D5 0 RD 0 D4 FIL1B R/W 0 D3 EQB R/W 0 D2 FIL3B R/W 0 D1 0 RD 0 D0 0 RD 0 FIL3B: FIL3B (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3B bit is “1”, the settings of F3A13B-0B and F3B13B-0B bits are enabled. When FIL3B bit is “0”, FIL3B block is OFF (MUTE). EQB: EQB (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQB bit is “1”, the settings of EQA15B-0B, EQB13B-0B and EQC15B-0B bits are enabled. When EQB bit is “0”, EQB block is through (0dB). FIL1B: FIL1B (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1B bit is “1”, the settings of F1A13B-0B and F1B13B-0B bits are enabled. When FIL1B bit is “0”, FIL1B block is through (0dB). GN1B-0B: Gain Select at GAIN block in ADC2 (Table 24) Default: “00” (0dB) MS0672-E-00 2007/11 - 76 - [AK4691] Addr 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H Register Name FIL3B Co-efficient 0 FIL3B Co-efficient 1 FIL3B Co-efficient 2 FIL3B Co-efficient 3 EQB Co-efficient 0 EQB Co-efficient 1 EQB Co-efficient 2 EQB Co-efficient 3 EQB Co-efficient 4 EQB Co-efficient 5 FIL1B Co-efficient 0 FIL1B Co-efficient 1 FIL1B Co-efficient 2 FIL1B Co-efficient 3 R/W Default D7 D6 D5 F3A7B F3A6B F3A5B F3ASB 0 F3A13B F3B7B F3B6B F3B5B 0 0 F3B13B EQA7B EQA6B EQA5B EQA15B EQA14B EQA13B EQB7B EQB6B EQB5B 0 0 EQB13B EQC7B EQC6B EQC5B EQC15B EQC14B EQC13B F1A7B F1A6B F1A5B F1ASB 0 F1A13B F1B7B F1B6B F1B5B 0 0 F1B13B R/W R/W R/W 0 0 0 D4 F3A4B F3A12B F3B4B F3B12B EQA4B EQA12B EQB4B EQB12B EQC4B EQC12B F1A4B F1A12B F1B4B F1B12B R/W 0 D3 D2 F3A3B F3A2B F3A11B F3A10B F3B3B F3B2B F3B11B F3B10B EQA3B EQA2B EQA11B EQA10B EQB3B EQB2B EQB11B EQB10B EQC3B EQC2B EQC11B EQC10B F1A3B F1A2B F1A11B F1A10B F1B3B F1B2B F1B11B F1B10B R/W R/W 0 0 D1 F3A1B F3A9B F3B1B F3B9B EQA1B EQA9B EQB1B EQB9B EQC1B EQC9B F1A1B F1A9B F1B1B F1B9B R/W 0 D0 F3A0B F3A8B F3B0B F3B8B EQA0B EQA8B EQB0B EQB8B EQC0B EQC8B F1A0B F1A8B F1B0B F1B8B R/W 0 F3A13B-0B, F3B13B-0B: FIL3B (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3ASB: FIL3B (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15B-0B, EQB13B-0B, EQC15B-C0B: EQB (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13B-0B, F1B13B-B0B: FIL1B (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1ASB: FIL1B (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF MS0672-E-00 2007/11 - 77 - [AK4691] SYSTEM DESIGN Figure 51 shows the system connection diagram for the AK4691. The evaluation board [AKD4691] demonstrates the optimum layout, power supply arrangements and measurement results. LINEIN LNEOUT (see Figure 23) (see Figure 34, Figgure 36) Analog Supply 2.6 ~ 5.5V Analog Supply 2.6 ~ 3.6V 10μ 0.1μ 2.2μ Rp 2.2μ 0.1μ 10μ 0.1μ Analog Supply 2.6 ~ 5.5V R NC VCOC VCOM MRF PRELN1 VSS1 1μ 0.1μ Cp AVDD RIN LOUT LVCM MUTET LIN BEEP ROUT LVDD HPL VSS4 VSS3 HPR NC 1μ Headphone 10μ 0.1μ (see Figure 38) PRERN2 PRELN2 10μ 0.1μ 1.8k 1.8k 1.8k 1.8k PRERN1 MVDD SVDD SPP PDN SPN Speaker Top View Internal MIC MPWR INTL1 INTL2 EXTL1 INTR1 EXTL2 CDTI/SDA NC uP MUTE CSN/CAD0 CCLK/SCL 0.1μ External MIC Analog Supply 2.6 ~ 3.6V INTR2 EXTR1 NC EXTR2 TVDD1 MCKI SDTO2 LRCK MCKO TVDD2 NC SDTI SDTO1 BICK DVDD VSS2 NC I2CN Digital Supply 1.6 ~ 3.6V 0.1μ 0.1μ 10 Analog Ground Digital Ground DSP Digital Supply 1.6 ~ 3.6V Notes: - VSS1, VSS2, VSS3 and VSS4 of the AK4691 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4691 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed. - When the AK4691 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table 4. - When the AK4691 is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4691. Figure 51. Typical Connection Diagram (I2CN pin = “H”, 3-wire Mode) MS0672-E-00 2007/11 - 78 - [AK4691] PACKAGE 57pin BGA (Unit: mm) 5.0 ± 0.1 φ 0.05 A 57 - φ 0.3 ± 0.05 M S AB 9 8 7 65 4 3 2 1 4.0 5.0 ± 0.1 A B C D E B F G H J 0.5 0.5 1.0MAX 0.25 ± 0.05 S 0.08 S ■ Material & Lead finish Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu MS0672-E-00 2007/11 - 79 - [AK4691] MARKING 4691 XXXX XXXX: Date code (4 digits) Pin #1 indication REVISION HISTORY Date (YY/MM/DD) 07/11/02 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0672-E-00 2007/11 - 80 -