ASAHI KASEI [AK4645] AK4645 Stereo CODEC with MIC/HP-AMP AK4645 CODEC PLL 1. 2. ) 32pin QFN •4 • ( or ) • • (+32dB/+26dB/+20dB or 0dB) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • ADC : S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) • • • Programmable EQ • (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz) • • • (+12dB ∼ −115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • • Programmable EQ • : S/(N+D): 88dB, S/N: 92dB • - HP-AMP : S/(N+D): [email protected], S/N: 90dB : 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V) ON/OFF • :4 3. 4. : (1) PLL • (2) 5. 6. PMP( AK4645 : 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) • : 256fs, 512fs or 1024fs (MCKI pin) : 32fs/64fs/128fs/256fs : • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz MS0543-J-00 2006/09 -1- ASAHI KASEI 7. 8. 9. 10. 11. 12. 13. [AK4645] • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) µP :3 , I2C (Ver 1.0, 400kHz ) : MSB First, 2’s complement • ADC : 16bit , I2S, DSP Mode • DAC : 16bit , 16bit , 16-24bit I2S, DSP Mode Ta = −30 ∼ 85°C : • AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V) • HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V) • TVDD (Digital I/O): 1.6 ∼ 3.6V (typ. 3.3V) : 32pin QFN (5mm x 5mm, 0.5mm pitch) AK4644 AVSS AVDD VCOM TVDD DVDD PMMP MPWR MIC Power Supply I2C Control Register PMADL or PMMICL LIN1 CSN CCLK CDTI Internal MIC A/D MIC-Amp LIN2 External MIC PDN PMADL or PMADR RIN1 HPF Wind-Noise Stereo ALC Reduction Separation PMADR or PMMICR BICK RIN2 LRCK SDTO PMAINR2 LIN3/MIN Line In RIN3/VCOC Line In RIN4 Audio I/F PMAINL2 SDTI LIN4 PMAINR3 PMAINR4 PMAINL3 PMAINL4 PMMIN PMLO PMDAC LOUT Stereo Line Out D/A Stereo DATT Bass ALC Separation SMUTE Boost HPF ROUT MCKO PMPLL PMHPL PLL VCOC HPL Headphone MCKI PMHPR HPR MUTET HVDD HVSS Figure 1. MS0543-J-00 2006/09 -2- ASAHI KASEI [AK4645] −30 ∼ +85°C AK4645 AK4645EN AKD4645 32pin QFN (0.5mm pitch) RIN4 / IN4− MUTET HPL HPR HVDD HVSS MCKO MCKI 24 23 22 21 20 19 18 17 LRCK RIN2 / IN2− 29 Top View 12 SDTO LIN2 / IN2+ 30 11 SDTI LIN1 / IN1− 31 10 CDTI / SDA RIN1 / IN1+ 32 9 CCLK / SCL 8 13 CSN / CAD0 AK4645EN 7 28 PDN MIN / LIN3 6 BICK I2C 14 5 27 VCOC / RIN3 LOUT / LOP 4 DVDD AVDD 15 3 26 AVSS ROUT / LON 2 TVDD VCOM 16 1 25 MPWR LIN4 / IN4+ AK4643/44 1. Function Function Digital I/O of µP I/F Analog Mixing for Playback Input Selector for Recording HP-Amp Hi-Z Setting for wired OR PLL Speaker-Amp Receiver-Amp AK4643 2.6 to 3.6V 3 Stereo 3 Stereo No 11.2896/12/12.288/ 13.5/24/27MHz Yes Yes MS0543-J-00 AK4644 Å Å Å Å Å No Å AK4645 1.6 to 3.6V 4 Stereo 4 Stereo Yes 11.2896/12/12.288/13/ 13.5/19.2/24/26/27MHz Å No 2006/09 -3- ASAHI KASEI [AK4645] 2. Pin Pin# 16 19 20 21 22 23 24 25 26 27 3. Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H (AK4644 Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved AK4643 DVSS SPN SPP HVDD HVSS HPR HPL MUTET ROUT/RCN LOUT/RCP AK4644 Å TEST1 TEST2 Å Å Å Å Å Å Å AK4645 TVDD HVSS HVDD HPR HPL MUTET RIN4 / IN4− LIN4 / IN4+ ROUT/LON LOUT/LOP ) D7 0 HPZ 0 LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 D6 PLL1 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR4 0 LOM 0 0 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 LOM3 HPM3 0 AK4645 MICR3 RINR4 RINH4 0 MICL3 LINL4 LINH4 0 L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF PMVCM D5 PMMIN PMHPL 0 MGAIN1 MS0543-J-00 D0 PMADL PMPLL MGAIN0 LINL2 LINH2 0 2006/09 -4- ASAHI KASEI No. 1 [AK4645] Pin Name MPWR I/O O Function , 0.45 x AVDD 2 VCOM O 3 4 AVSS AVDD - VCOC O RIN3 I 6 I2C I “H”: I2C 7 PDN I “H”: “L”: 5 11 12 13 14 15 16 17 18 19 20 21 22 CSN CAD0 CCLK SCL CDTI SDA SDTI SDTO LRCK BICK DVDD TVDD MCKI MCKO HVSS HVDD HPR HPL I I I I I I/O I O I/O I/O I O O O 23 MUTET O 8 9 10 24 25 26 27 28 29 30 31 32 DAC PLL AVSS Rch (AIN3 bit = “0”: PLL 3 (AIN3 bit = “1”: PLL Note 1. AVDD ) ) , “L”: 3 0 (I2C pin = “L”: 3 ) (I2C pin = “H” : I2C ) (I2C pin = “L”: 3 (I2C pin = “H”: I2C (I2C pin = “L”: 3 (I2C pin = “H”: I2C ) ) ) ) I/O Rch Lch HVSS pin I Rch 4 (L4DIF bit = “0”: I 4 (L4DIF bit = “1”: ) I Lch 2 (L4DIF bit = “0”: I 4 (L4DIF bit = “1”: ) O Rch (LODIF bit = “0”: O (LODIF bit = “1”: O Lch (LODIF bit = “0”: O (LODIF bit = “1”: I (AIN3 bit = “0”: PLL I Lch 3 (AIN3 bit = “1”: PLL ) I Rch 2 (MDIF2 bit = “0”: I 2 (MDIF2 bit = “1”: ) I Lch 2 (MDIF2 bit = “0”: I 2 (MDIF2 bit = “1”: ) I Lch 1 (MDIF1 bit = “0”: I 1 (MDIF1 bit = “1”: ) I Rch 1 (MDIF1 bit = “0”: I 1 (MDIF1 bit = “1”: ) (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, RIN4) RIN4 IN4− LIN4 IN4+ ROUT LON LOUT LOP MIN LIN3 RIN2 IN2− LIN2 IN2+ LIN1 IN1− RIN1 IN1+ Note 2. I2C pin ADC ) ) ) ) ) ) ) ) ) ) ) AVSS MS0543-J-00 2006/09 -5- ASAHI KASEI [AK4645] Analog Digital MPWR, VCOC/RIN3, HPR, HPL, MUTET, RIN4/IN4−, LIN4/IN4+, ROUT/LON, LOUT/LOP, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ MCKO MCKI (AVSS, HVSS=0V; Note 3) Parameter Power Supplies: Analog Digital Digital I/O Headphone-Amp |AVSS – HVSS| (Note 4) Input Current, Any Pin Except Supplies Analog Input Voltage (Note 5) Digital Input Voltage (Note 6) Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD TVDD HVDD ∆GND2 IIN VINA VIND Ta Tstg HVSS Min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −30 −65 max 6.0 6.0 6.0 6.0 0.3 ±10 AVDD+0.3 TVDD+0.3 85 150 Units V V V V V mA V V °C °C Note 3. Note 4. AVSS HVSS Note 5. I2C, RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins SDA, SCL pins (TVDD+0.3)V : (AVSS, HVSS=0V; Note 3) Parameter Power Supplies Analog (Note 7) Digital Digital I/O HP-Amp Difference Symbol AVDD DVDD TVDD HVDD AVDD−DVDD Note 3. Note 7. AVDD, DVDD, TVDD, HVDD TVDD OFF DVDD OFF TVDD AVDD, HVDD OFF min 2.6 2.6 1.6 2.6 −0.3 typ 3.3 3.3 3.3 3.3 / 5.0 0 DVDD max 3.6 3.6 DVDD 5.25 +0.3 Units V V V V V AVDD, HVDD, AVDD, HVDD, DVDD TVDD OFF : MS0543-J-00 2006/09 -6- ASAHI KASEI [AK4645] (Ta=25°C; AVDD, DVDD, TVDD, HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) min typ max Units Parameter MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”); MDIF1=MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” 40 60 80 kΩ Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 kΩ MGAIN1-0 bits = “00” 0 dB MGAIN1-0 bits = “01” +20 dB Gain MGAIN1-0 bits = “10” +26 dB MGAIN1-0 bits = “11” +32 dB MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Input Voltage (Note 8) MGAIN1-0 bits = “01” 0.228 Vpp MGAIN1-0 bits = “10” 0.114 Vpp MGAIN1-0 bits = “11” 0.057 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 0.5 kΩ Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”) → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution 16 Bits (Note 11) 0.168 0.198 0.228 Vpp Input Voltage (Note 10) (Note 12) 1.68 1.98 2.28 Vpp (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 dBFS S/(N+D) (Note 11, LIN3/RIN3/LIN4/RIN4) 83 dBFS (−1dBFS) (Note 12, except for LIN3/RIN3) 88 dBFS (Note 12, LIN3/RIN3) 72 dBFS (Note 11) 76 86 dB D-Range (−60dBFS, A-weighted) (Note 12) 95 dB (Note 11) 76 86 dB S/N (A-weighted) (Note 12) 95 dB (Note 11) 75 90 dB Interchannel Isolation (Note 12) 100 dB (Note 11) 0.1 0.8 dB Interchannel Gain Mismatch (Note 12) 0.1 0.8 dB Note 8. AC MGAIN1-0 bits = “00” IN1+, IN1−, IN2+, IN2− pin AVDD Vin = |(IN+) − (IN−)| = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. ADC Note 9. AVDD Vout = 0.75 x AVDD (typ) Note 10. AVDD Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 11. MGAIN1-0 bits = “01” (+20dB) Note 12. MGAIN1-0 bits = “00” (0dB) MS0543-J-00 2006/09 -7- ASAHI KASEI [AK4645] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “0”, RL=10kΩ; unless otherwise specified. Output Voltage (Note 13) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 kΩ Load Capacitance 30 pF Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential) Output Voltage (Note 14) LOVL bit = “0” 3.52 3.96 4.36 Vpp LOVL bit = “1” 5.00 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 85 95 dB Load Resistance (LOP/LON pins, respectively) 10 kΩ Load Capacitance (LOP/LON pins, respectively) 30 pF Note 13. Note 14. AVDD AVDD Vout = 0.6 x AVDD (typ)@LOVL bit = “0”. Vout = (LOP) − (LON) = 1.2 x AVDD (typ)@LOVL bit = “0”. MS0543-J-00 2006/09 -8- ASAHI KASEI [AK4645] min typ max Units Parameter Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = “0”; unless otherwise specified. Output Voltage (Note 15) 1.58 1.98 2.38 Vpp HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω 2.40 3.00 3.60 Vpp HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 1.0 Vrms HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 1.06 Vrms S/(N+D) 60 70 dBFS HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω 80 dBFS HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 20 dBFS HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 70 dBFS (Note 16) 80 90 dB S/N (A-weighted) (Note 17) 90 dB (Note 16) 65 75 dB Interchannel Isolation (Note 17) 80 dB (Note 16) 0.1 0.8 dB Interchannel Gain Mismatch (Note 17) 0.1 0.8 dB Load Resistance 16 Ω 30 pF Figure 2 C1 Load Capacitance 300 pF Figure 2 C2 Note 15. AVDD Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”. Note 16. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω. Note 17. HPG bit = “1”, HVDD=5V, RL=100Ω. HP-Amp HPL/HPR pin Measurement Point 47µF 6.8Ω C1 0.22µF C2 16Ω 10Ω Figure 2. MS0543-J-00 2006/09 -9- ASAHI KASEI [AK4645] min typ Parameter Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ) Maximum Input Voltage (Note 18) 1.98 Gain (Note 19) MIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 HPG bit = “1” −16.4 Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”) Maximum Input Voltage (Note 20) 1.98 Gain LIN/RIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 LIN/RIN Æ HPL/HPR HPG bit = “0” 0 −4.5 HPG bit = “1” +3.6 Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”) Maximum Input Voltage (Note 21) 3.96 Gain LOVL bit = “0” IN4+/− Æ LOUT/ROUT −10.5 −6 (LODIF bit = “0”) LOVL bit = “1” −4 LOVL bit = “0” 0 IN4+/− Æ LOP/LON −4.5 (LODIF bit = “1”, Note 22) LOVL bit = “1” +2 HPG bit = “0” IN4+/− Æ HPL/HPR −10.5 −6 HPG bit = “1” −2.4 Power Supplies: Power Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD+TVDD (Note 23) 16 HVDD: HP-Amp Normal Operation 5 No Output (Note 24) Power Down (PDN pin = “L”) (Note 25) AVDD+DVDD+TVDD+HVDD 1 Note 18. Note 19. Note 20. Note 21. AVDD (Rin) max Units - Vpp +4.5 −15.5 - dB dB dB dB - Vpp +4.5 +4.5 - dB dB dB dB - Vpp −1.5 +4.5 −1.5 - dB dB dB dB dB dB 24 mA 8 mA 100 µA Vin = 0.6 x AVDD x Rin / 20kΩ (typ). AVDD Vin = 0.6 x AVDD (typ). AVDD Vin = (IN4+) − (IN4−) = 1.2 x AVDD (typ). IN4+, IN4− pins Note 22. Vout = (LOP) − (LON) at LODIF bit = “1”. Note 23. PLL Master Mode (MCKI=12.288MHz) PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1” MPWR pin 0mA AVDD=11mA(typ), DVDD=3mA(typ), TVDD=2mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”) : AVDD=10mA(typ), DVDD=3mA(typ), TVDD=0.03mA(typ). Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1” Note 25. TVDD HVSS MS0543-J-00 2006/09 - 10 - ASAHI KASEI [AK4645] : Ta=25°C; AVDD=DVDD=TVDD=HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone = No output. PMDAC PMADL PMHPR PMADR PMMICL PMMICR PMAINL2 PMAINR2 PMAINL3 PMAINR3 PMAINL4 PMAINR4 AVDD [mA] DVDD [mA] TVDD [mA] PMHPL HVDD [mA] Total Power [mW] 20H PMLO 10H PMMIN 01H PMVCM 00H Power Management Bit 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.4 3.8 1.9 5.5 3.5 0 1.8 1.8 0 1.6 1.5 0 0.03 0.03 0 0.03 0.03 0 0.2 5 5 0.2 0.2 0 21.2 35.1 22.8 24.2 17.3 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 8.3 2.7 0.03 5 52.9 Mode All Power-down DAC Æ Lineout DAC Æ HP LIN2/RIN2 Æ HP LIN2/RIN2 Æ ADC LIN1 (Mono) Æ ADC LIN2/RIN2 Æ ADC & DAC Æ HP Table 1. Power Consumption for each operation mode (typ) MS0543-J-00 2006/09 - 11 - ASAHI KASEI [AK4645] (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 26) PB 0 17.3 kHz ±0.16dB 19.4 kHz −0.66dB 19.9 kHz −1.1dB 22.1 kHz −6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 27) GD 19 1/fs Group Delay Distortion 0 ∆GD µs ADC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 26) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 27) GD 25 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB BOOST Filter: (Note 29) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 26. Note 27. fs ( PB=20.0kHz(@−0.7dB) ) 0.454 x fs (DAC) ADC 1kHz 16 PMADL=PMADR bits = “0” DAC Group Delay 25/fs(typ) Note 28. PMADL bit = “1” or PMADR bit = “1” ADC HPF ON DAC HPF OFF PMADL=PMADR bits = “0”, PMDAC bit = “1” DAC HPF ON ADC HPF Note 29. 16 DAC MS0543-J-00 OFF 2006/09 - 12 - ASAHI KASEI [AK4645] DC (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage 2.2V≤TVDD≤3.6V VIH 70%TVDD 1.6V≤TVDD<2.2V VIH 75%TVDD Low-Level Input Voltage 2.2V≤TVDD≤3.6V VIL 1.6V≤TVDD<2.2V VIL High-Level Output Voltage VOH (Iout=−200µA) TVDD−0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200µA) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin - typ - max 30%TVDD 25%TVDD - Units V V V V V - 0.2 0.4 ±10 V V µA (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns MCKO Output Timing Frequency fMCK 0.2352 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK 33 % LRCK Output Timing Frequency fs 7.35 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK ns Except DSP Mode: Duty Cycle Duty 50 % BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) ns BCKO bit = “1” tBCK 1/(64fs) ns Duty Cycle dBCK 50 % PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns MCKO Output Timing Frequency fMCK 0.2352 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK 33 % LRCK Input Timing Frequency fs 7.35 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK−60 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 55 % BICK Input Timing Period tBCK 1/(64fs) 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK ns Pulse Width High tBCKH 0.4 x tBCK ns MS0543-J-00 2006/09 - 13 - ASAHI KASEI [AK4645] Parameter Symbol PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period PLL3-0 bits = “0010” tBCK PLL3-0 bits = “0011” tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Output Timing Period BCKO bit = “0” tBCK BCKO bit = “1” tBCK Duty Cycle dBCK MS0543-J-00 min typ max Units 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 1/(64fs) 130 130 - 1/(32fs) - ns ns ns 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 0.4 x tBCK 0.4 x tBCK 1/(32fs) 1/(64fs) - - ns ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 7.35 7.35 tBCK−60 45 - 48 26 13 1/fs − tBCK 55 kHz kHz kHz ns % 312.5 130 130 - - ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 - tBCK 50 48 - kHz ns % - 1/(32fs) 1/(64fs) 50 - ns ns % 2006/09 - 14 - ASAHI KASEI [AK4645] Parameter Symbol Audio Interface Timing (DSP Mode) Master Mode tDBF LRCK “↑” to BICK “↑” (Note 30) tDBF LRCK “↑” to BICK “↓” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK “↑” to BICK “↑” (Note 30) tLRB LRCK “↑” to BICK “↓” (Note 31) tBLR BICK “↑” to LRCK “↑” (Note 30) tBLR BICK “↓” to LRCK “↑” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS Audio Interface Timing (Right/Left justified & I2S) Master Mode tMBLR BICK “↓” to LRCK Edge (Note 32) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK Edge to BICK “↑” (Note 32) tBLR BICK “↑” to LRCK Edge (Note 32) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS Note 30. MSBS, BCKP bits = “00” or “11”. Note 31. MSBS, BCKP bits = “01” or “10”. Note 32. LRCK BICK min typ max Units 0.5 x tBCK − 40 0.5 x tBCK − 40 −70 −70 50 50 0.5 x tBCK 0.5 x tBCK - 0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 - ns ns ns ns ns ns 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 50 50 - 80 80 - ns ns ns ns ns ns ns ns −40 −70 - 40 70 ns ns −70 50 50 - 70 - ns ns ns 50 50 - - 80 ns ns ns 50 50 - 80 - ns ns ns “↑” MS0543-J-00 2006/09 - 15 - ASAHI KASEI Parameter Control Interface Timing (3-wire Serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 34) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive Load on Bus Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 35) PMADL or PMADR “↑” to SDTO valid (Note 36) Note 33. I2C Philips Semiconductors Note 34. 300ns (SCL ) Note 35. AK4645 PDN pin = “L” Note 36. PMADL bit PMADR bit [AK4645] Symbol min typ max Units tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 - - ns ns ns ns ns ns ns ns fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 - 400 0.3 0.3 400 50 kHz µs µs µs µs µs µs µs µs µs µs pF ns tPD tPDV 150 - 1059 - ns 1/fs LRCK MS0543-J-00 “↑” 2006/09 - 16 - ASAHI KASEI [AK4645] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%TVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 1/fMCK 50%TVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL/EXT Master mode) Note 37. MCKO is not available at EXT Master mode. tLRCKH LRCK 50%TVDD tBCK tDBF dBCK BICK (BCKP = "0") 50%TVDD BICK (BCKP = "1") 50%TVDD tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”) MS0543-J-00 2006/09 - 17 - ASAHI KASEI [AK4645] tLRCKH LRCK 50%TVDD tBCK tDBF dBCK BICK (BCKP = "1") 50%TVDD BICK (BCKP = "0") 50%TVDD tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) 50%TVDD LRCK tBLR tBCKL BICK 50%TVDD tLRD tBSD SDTO 50%TVDD tSDH tSDS VIH SDTI VIL Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0543-J-00 2006/09 - 18 - ASAHI KASEI [AK4645] 1/fs VIH LRCK VIL tLRCKH tBLR tBCK VIH BICK (BCKP = "0") VIL tBCKH tBCKL VIH BICK (BCKP = "1") VIL Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”) 1/fs VIH LRCK VIL tLRCKH tBLR tBCK VIH BICK (BCKP = "1") VIL tBCKH tBCKL VIH BICK (BCKP = "0") VIL Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0543-J-00 2006/09 - 19 - ASAHI KASEI [AK4645] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH BICK VIL tBCKH tBCKL fMCK 50%TVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode) tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "0") VIH BICK (BCKP = "1") VIL tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI MSB VIL Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”) MS0543-J-00 2006/09 - 20 - ASAHI KASEI [AK4645] tLRCKH VIH LRCK VIL tLRB VIH BICK VIL (BCKP = "1") VIH BICK (BCKP = "0") VIL tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI MSB VIL Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 12. Clock Timing (EXT Slave mode) MS0543-J-00 2006/09 - 21 - ASAHI KASEI [AK4645] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRD tBSD SDTO 50%TVDD MSB tSDH tSDS VIH SDTI VIL Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode) VIH CSN VIL tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 14. WRITE Command Input Timing MS0543-J-00 2006/09 - 22 - ASAHI KASEI [AK4645] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 15. WRITE Data Input Timing VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 16. I2C PMADL bit or PMADR bit tPDV SDTO 50%TVDD Figure 17. Power Down & Reset Timing 1 tPD PDN VIL Figure 18. Power Down & Reset Timing 2 MS0543-J-00 2006/09 - 23 - ASAHI KASEI [AK4645] I/F 4 (See Table 2 and Table 3.) Mode PLL Master Mode (Note 38) PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode EXT Master Mode Note 38. PLL Master Mode PMPLL bit 1 M/S bit 1 PLL3-0 bits See Table 5 Figure Figure 19 1 0 See Table 5 Figure 20 1 0 See Table 5 0 0 x 0 1 x M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1” Figure 21 Figure 22 Figure 23 Figure 24 MCKO pin Table 2. Clock Mode Setting (x: Don’t care) Mode MCKO bit 0 PLL Master Mode 1 0 PLL Slave Mode (PLL Reference Clock: MCKI pin) MCKO pin “L” PS1-0 bits “L” PS1-0 bits 1 PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) 0 “L” EXT Slave Mode 0 “L” EXT Master Mode 0 “L” MCKI pin PLL3-0 bits PLL3-0 bits GND FS1-0 bits FS1-0 bits BICK pin Output (BCKO bit ) LRCK pin Input (≥ 32fs) Input (1fs) Input (PLL3-0 bits ) Input (≥ 32fs) Output (BCKO bit ) Output (1fs) Input (1fs) Input (1fs) Output (1fs) Table 3. Clock pins state in Clock Mode M/S bit (PDN pin = “L”) AK4645 M/S bit “1” “0” “1” M/S bit “1” AK4645 LRCK, BICK pin AK4645 LRCK, BICK pin 100kΩ M/S bit Mode 0 Slave Mode 1 Master Mode Table 4. Select Master/Slave Mode MS0543-J-00 Default 2006/09 - 24 - ASAHI KASEI PLL [AK4645] (AIN3 bit = “0”, PMPLL bit = “1”) PMPLL bit = “1” PLL PLL FS3-0 bits, PLL3-0 bits PMPLL bit “0” Æ “1” Table 5 AIN3 bit = “1” PLL 1) PLL Mode PLL PLL3 bit PLL2 bit PLL1 bit PLL0 bit 0 1 2 0 0 0 0 0 0 0 0 1 0 1 0 LRCK pin N/A BICK pin 1fs 32fs 3 0 0 1 1 BICK pin 64fs 4 5 6 7 8 12 13 14 15 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 Mode Others Others VCOC pin R,C R[Ω] C[F] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n 10k 220n 10k 220n MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 19.2MHz MCKI pin 13.5MHz MCKI pin 27MHz MCKI pin 13MHz MCKI pin 26MHz N/A Table 5. Setting of PLL Mode (*fs: Sampling Frequency) PLL (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 60ms 60ms Default 2) PLL Mode MCKI Table 6 Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin) MS0543-J-00 2006/09 - 25 - ASAHI KASEI [AK4645] LRCK or BICK FS3, FS1-0 bits (Table 7) Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don’t care 0 0 0 Default 7.35kHz ≤ fs ≤ 8kHz 0 Don’t care 1 1 0 8kHz < fs ≤ 12kHz 0 Don’t care 0 2 1 12kHz < fs ≤ 16kHz 0 Don’t care 1 3 1 16kHz < fs ≤ 24kHz 1 Don’t care 0 6 1 24kHz < fs ≤ 32kHz 1 Don’t care 1 7 1 32kHz < fs ≤ 48kHz Others Others N/A Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin) PLL 1) PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”) bit = “1” MCKO pin PLL PMPLL bit = “0” Æ “1” PLL MCKO pin “L” (See Table 8) BICK LRCK BICK “L” LRCK “L” MCKO bit = “0” 1 MCKO LRCK, BICK 1fs PMPLL bit = “0” LRCK BICK, “L” MCKO pin BICK pin LRCK pin MCKO bit = “0” MCKO bit = “1” “L” Output “L” Output “L” Output PMPLL bit “0” Æ “1” “L” Output PLL Unlock ( ) “L” Output 1fs Output See Table 10 See Table 11 PLL Lock Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State 2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) DAC PMPLL bit = “0” Æ “1” PLL PLL DACL, DACH bits “0” PLL MCKO pin ADC DAC MCKO Table 10 MCKO pin MCKO bit = “0” MCKO bit = “1” “L” Output PMPLL bit “0” Æ “1” “L” Output PLL Unlock ( ) “L” Output Output PLL Lock Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PLL State MS0543-J-00 2006/09 - 26 - ASAHI KASEI [AK4645] PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”) 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz PLL MCKO, BICK, LRCK PS1-0 bits (Table 10) MCKO bit ON/OFF BICK 32fs or 64fs (See Table 11) (MCKO) BCKO bit 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz DSP or µP AK4645 MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 19. PLL Master Mode Mode PS1 bit 0 0 1 0 2 1 3 1 Table 10. MCKO PS0 bit 0 1 0 1 (PLL MCKO pin 256fs Default 128fs 64fs 32fs , MCKO bit = “1”) BCKO bit BICK 0 32fs Default 1 64fs Table 11. BICK Output Frequency at Master Mode MS0543-J-00 2006/09 - 27 - ASAHI KASEI [AK4645] PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) MCKI, BICK or LRCK pin PLL PLL a) PLL : MCKI pin MCKO BICK, LRCK bit AK4645 (Table 5) PLL3-0 bits MCKO LRCK (MCKO pin) PS1-0 bits (Table 10) FS3-0 bits ON/OFF MCKO (See Table 6) 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz AK4645 DSP or µP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs ≥ 32fs 1fs MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) MS0543-J-00 2006/09 - 28 - ASAHI KASEI b) PLL FS3-0 bits [AK4645] : BICK or LRCK pin 7.35kHz ∼ 48kHz (See Table 7.) AK4645 DSP or µP MCKO MCKI BICK LRCK 32fs or 64fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 21. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4645 DSP or µP MCKO MCKI BICK LRCK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 22. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin) ADC or DAC LRCK) (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”) (MCKI, BICK, (PMADL=PMADR=PMDAC bits = “0”) MS0543-J-00 2006/09 - 29 - ASAHI KASEI [AK4645] EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PMPLL bit “0” ADC, DAC Mode 0 1 2 3 (EXT Mode) MCKI pin PLL CODEC I/F MCKI (256fs, 512fs or 1024fs), BICK (≥32fs), LRCK(fs) MCKI MCKI FS1-0 bit (See Table 12) MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 256fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Table 12. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) MCKI FS3-2 bits FS1 bit LRCK FS0 bit DAC S/N S/N Table 13 DAC Default MCKI LOUT/ROUT pins S/N S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI ADC or DAC LRCK) (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”) (MCKI, BICK, (PMADL=PMADR=PMDAC bits = “0”) AK4645 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK MCLK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 23. EXT Slave Mode MS0543-J-00 2006/09 - 30 - ASAHI KASEI [AK4645] EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) PMPLL bit = “0” M/S bit = “1” MCKI pin PLL (256fs, 512fs or 1024fs) MCKI Mode 0 1 2 3 (EXT Master Mode) ADC,DAC MCKI (See Table 14) FS1-0 bits MCKI Input Frequency Don’t care 0 0 256fs Don’t care 0 1 1024fs Don’t care 1 0 256fs Don’t care 1 1 512fs Table 14. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) FS3-2 bits FS1 bit FS0 bit DAC S/N S/N Table 15 DAC Sampling Frequency Range 7.35kHz ∼ 48kHz 7.35kHz ∼ 13kHz 7.35kHz ∼ 48kHz 7.35kHz ∼ 26kHz MCKI Default MCKI LOUT/ROUT pins S/N S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI ADC DAC MCKI (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”) MCKI MCKI (PMADL=PMADR=PMDAC bits = “0”) AK4645 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK MCLK 32fs or 64fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 24. EXT Master Mode BCKO bit BICK 0 32fs Default 1 64fs Table 16. BICK Output Frequency at Master Mode MS0543-J-00 2006/09 - 31 - ASAHI KASEI [AK4645] PDN pin “L” AK4645 PMADR bit “0” → “1” 1059/fs=24ms@fs=44.1kHz “0” ADC PMDAC bit = “1” ADC PMDAC bit = “0” PMADL bit 2’s PMADL=PMADR bits = “0” PMDAC bit = “0” Æ “1” 1059/fs=24ms@fs=44.1kHz “0” DAC DAC ADC ADC DAC DAC 2’s DAC (25/fs=0.6ms@fs=44.1kHz) PMADL bit PMADR bit “1” 4 (Table 17) LRCK Mode 0 1 2 3 DIF1 bit 0 0 1 1 Mode 1, 2, 3 SDTO Mode 0 (DSP (Table 18) ) DIF1 0 DIF0 “−1” SDTO (ADC) DSP Mode SDTI (DAC) DSP Mode 2 2 IS IS Table 17. Audio Interface Format “↓” SDTI BICK BCKP, MSBS bits MSBS BCKP 0 0 0 1 1 0 1 1 0 ADC MSB 16bit 8bit “–256” BICK ≥ 32fs ≥ 32fs ≥ 32fs ≥ 32fs Figure Table 18 Figure 29 Figure 30 Figure 31 Default “↑” I/F Audio Interface Format MSB LRCK “↑” 1 BICK “↓” Figure SDTO BICK “↑” SDTI MSB SDTO MSB LRCK “↑” 1 BICK “↓” BICK “↑” SDTI MSB SDTO MSB LRCK “↑” 1 BICK “↓” BICK “↑” BICK “↓” SDTI MSB SDTO MSB LRCK “↑” 1 BICK “↑” BICK “↓” BICK “↑” SDTI MSB Table 18. Audio Interface Format in Mode 0 8bit “−1” 2’s BICK DIF0 bit 0 1 0 1 BICK DIF1-0 bits 8bit 8bit 16bit “−1” Figure 25 Default Figure 26 Figure 27 Figure 28 16bit 16bit DAC 16bit (128) MS0543-J-00 2006/09 - 32 - ASAHI KASEI [AK4645] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 2 1 0 15 14 1 0 2 1 0 Rch Lch SDTI(i) 2 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 25. Mode 0 Timing (BCKP = “0”, MSBS = “0”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 18 24 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 2 1 0 15 14 2 1 0 2 1 0 Rch Lch SDTI(i) 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0543-J-00 2006/09 - 33 - ASAHI KASEI [AK4645] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 15 14 Lch SDTI(i) 2 1 0 2 1 0 Rch 15 14 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 27. Mode 0 Timing (BCKP = “0”, MSBS = “1”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 Lch SDTI(i) 15 14 15 14 2 1 0 2 1 0 Rch 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 28. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0543-J-00 2006/09 - 34 - ASAHI KASEI [AK4645] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 15 14 13 15 14 Don't Care 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 29. Mode 1 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 30. Mode 2 Timing MS0543-J-00 2006/09 - 35 - ASAHI KASEI [AK4645] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 31. Mode 3 Timing PMADL, PMADR, MIX bits ADC bit = “1” EQ=FIL3 bits = “0” (ALC bit = “0”) PMADL bit 0 0 1 PMADR bit 0 1 0 1 1 Table 19. MIX bit x x x 0 1 MIX ALC (ALC bit = “1”) ADC Lch data ADC Rch data All “0” All “0” Rch Input Signal Rch Input Signal Lch Input Signal Lch Input Signal Lch Input Signal Rch Input Signal (L+R)/2 (L+R)/2 (x: Don’t care) Default HPF AK4645 DC 44.1kHz) ADC HPF ON DAC HPF ON ADC HPF OFF OFF HPF HPF 0.9Hz (@fs= (fs) PMADL bit = “1” or PMADR bit = “1” PMADL=PMADR bits = “0”, PMDAC bit = “1” DAC HPF MS0543-J-00 2006/09 - 36 - ASAHI KASEI [AK4645] AK4645 bits LIN1/LIN2/LIN3/LIN4, RIN1/RIN2/RIN3/RIN4 MDIF2 bits = “1” LIN1, RIN1, LIN2, RIN2 pins (Figure 33) Table 21 MDIF1 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Others MDIF2 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 INL1 bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 INL0 bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 INR1 bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 MDIF1, MDIF2 bits = “0” INL1-0, INR1-0 MDIF1, IN1−, IN1+, IN2+, IN2− pins “X” INR0 bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 Lch LIN1 LIN1 LIN1 LIN1 LIN2 LIN2 LIN2 LIN2 LIN3 LIN3 LIN3 LIN3 LIN4 LIN4 LIN4 LIN4 LIN1 LIN3 LIN4 IN1+/− IN1+/− IN1+/− IN1+/− N/A Rch RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 IN2+/− IN2+/− IN2+/− RIN2 RIN3 RIN4 IN2+/− N/A Default Table 20. MIC/Line In Path Select Register AIN3 bit 0 0 0 0 1 1 1 1 Pin LIN1 RIN2 RIN1 LIN2 MIN VCOC LIN4 MDIF1 bit MDIF2 bit IN1+ IN2+ LIN3 RIN3 IN4+ IN1− IN2− 0 0 O O O O O O 0 1 O X O O O O 1 0 O O X O O X 1 1 O O O O O X 0 0 O O O O O O O 0 1 O X O O O X O 1 0 O O X O X O X 1 1 O O O O X X X Table 21. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.) MS0543-J-00 RIN4 IN4− O X O X O X O X 2006/09 - 37 - ASAHI KASEI [AK4645] AK4645 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp These blocks are not available at PLL mode. MIN/LIN3 pin PMAINL3 bit PMAINR2 bit PMAINL2 bit PMAINR4 bit PMAINL4 bit RIN4/IN4− pin MICR3 bit LIN4/IN4+ pin PMAINR3 bit MICL3 bit VCOC/RIN3 pin Lineout, HP-Amp Figure 32. AK4645 MPWR pin 1k IN1− pin MIC-Amp IN1+ pin A/D SDTO pin 1k Figure 33. IN1+/− pins MDIF1 bit 1 0 (MDIF1/2 bits = “1”) LIN2/RIN2 pins MDIF2 bit 0 0 2 INL1 bit INL0 bit INR1 bit INR0 bit 0 0 0 1 0 1 0 1 Table 22. MIC/Line In Path Select Example MS0543-J-00 Lch IN1+/− LIN2 Rch RIN2 RIN2 2006/09 - 38 - ASAHI KASEI [AK4645] AK4645 (Table 23) typ. 30kΩ MGAIN1-0 bit MGAIN1-0 bits = “00” typ. 60kΩ MGAIN1 bit 0 0 1 1 MGAIN0 bit 0 1 0 1 Table 23. Input Gain 0dB +20dB +26dB +32dB MGAIN1-0 bits = “01”, “10”, “11” Default PMMP bit = “1” AVDD)V (typ) MPWR pin MPWR pin min. 0.5kΩ (0.75 x min. 2kΩ 2 (Figure 34 ) PMMP bit MPWR pin 0 Hi-Z 1 Output Table 24. Default MIC Power ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 34. MIC Block Circuit MS0543-J-00 2006/09 - 39 - ASAHI KASEI [AK4645] Digital EQ/HPF/LPF AK4645 A/D ALC (Figure 35 ) FIL1, FIL3, EQ “ALC ” ALC DAC 1 IIR Digital EQ/HPF/LPF ADC ADC DAC Digital EQ/HPF/LPF FIL3, EQ, FIL1, GN1-0 bits “0” PMADL bit, PMADR bit “00” PMDAC bit 0 1 0 “01”, “10” or “11” LOOP bit x x x 0 1 1 Digital EQ/HPF/LPF Default , Note 39. Table 25. Digital EQ/HPF/LPF ATT FIL3 GN1-0 bits (Table 26 FIL1, FIL3 FIL3 F1AS, F3AS bits OFF(MUTE) (x: Don’t care) EQ, FIL1 “0” ) EQ HPF F1AS, F3AS bits 0dB (FIL3 MIX bit = “1” FIL1 FIL3, EQ, FIL1 bits MUTE) LPF “0” EQ=FIL3 bits = “0” FIL1 F1A13-0 F1B13-0 F1AS “1” FIL3 F3A13-0 F3B13-0 F3AS 0dB ∼ -10dB MUTE (FIL3 EQ ) EQA15-0 EQB13-0 EQC15-0 +12dB ∼ 0dB Gain ALC GN1-0 +24/+12/0dB Figure 35. Digital EQ/HPF/LPF GN1 GN0 0 0 0 1 1 x Table 26. Gain Gain 0dB Default +12dB +24dB (x: Don’t care) MS0543-J-00 2006/09 - 40 - ASAHI KASEI [AK4645] [ ] 1) FIL1, FIL3 fs: fc: f: K: HPF [dB] (FIL1 0dB ) FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) A = 10K/20 x , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) 1 − z −1 H(z) = A 2) FIL1, FIL3 fs: fc: f: K: 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 θ(f) = tan −1 1 + B2 + 2Bcos (2πf/fs) (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) LPF [dB] (FIL1 0dB ) FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) 1 + z −1 H(z) = A 1 + Bz −1 B= 1 + 1 / tan (πfc/fs) 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0543-J-00 θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2006/09 - 41 - ASAHI KASEI [AK4645] 3) EQ fs: fc1: fc2: f: K: [dB] ( +12dB ) EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc2/fs) , B= , 1 + 1 / tan (πfc1/fs) A + Cz −1 H(z) = 1 + 1 / tan (πfc1/fs) A2 + C2 + 2ACcos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) [ 2 (2 ) x 213 X=( X 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) (AB−C)sin (2πf/fs) θ(f) = tan −1 M(f) = 1 + Bz −1 C =10K/20 x A + BC + (AB+C)cos (2πf/fs) ) (2 ] ) MSB [ ] 1) FIL1 : fs=44.1kHz, fc=100Hz HPF F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ : fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0543-J-00 2006/09 - 42 - ASAHI KASEI [AK4645] ALC ALC bit = “1” ALC ALC PMADL bit, PMADR bit “00” ALC PMDAC bit 0 1 0 “01”, “10” or “11” 1. DAC ALC 1 LOOP bit x x x 0 1 Table 27. ALC ALC Default , (x: Don’t care) ALC ALC Lch, Rch LMAT1-0 bits ZELMN bit = “0”( (Table 29) ) ZTM1-0 bits ALC IVL, IVR (L/R (Table 28) ) ALC IVL, IVR ) ALC LMAT1-0 bits IVL, IVR 1 step L/R (Table 30) ZELMN bit = “1”( ALC bit LMTH1 0 0 1 1 “0” LMAT1 0 0 0 1 1 1 x Table 29. ALC ZTM1 ZTM0 0 0 1 1 0 1 0 1 128/fs 256/fs 512/fs 1024/fs Table 30. ALC : 1/fs) ALC LMTH0 ALC 0 ALC Output ≥ −2.5dBFS 1 ALC Output ≥ −4.1dBFS 0 ALC Output ≥ −6.0dBFS 1 ALC Output ≥ −8.5dBFS Table 28. ALC ZELMN ( ALC −2.5dBFS > ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS LMAT0 ALC 0 1 step 1 2 step 0 4 step 1 8 step x 1step ATT 8kHz 16ms 32ms 64ms 128ms MS0543-J-00 Default ATT 0.375dB Default 0.750dB 1.500dB 3.000dB 0.375dB (x: Don’t care) 16kHz 8ms 16ms 32ms 64ms 44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms Default 2006/09 - 43 - ASAHI KASEI 2. [AK4645] ALC ALC WTM2-0 (Table 31) (Table 28) ALC (Table 33) ZTM1-0 bits (Table 30) RGAIN1-0 bits (Table 32) IVL, IVR (L/R ) WTM2-0 bits WTM2-0 bits ZTM1-0 bits IVL, IVR 30H IVL, IVR 32H IVL, IVR bits) RGAIN1-0 bits = “01”(2 steps) 0.75dB(0.375dB x 2) ALC ALC ALC ZTM1-0 bits ALC ALC IVL, IVR (REF7-0 ALC ( ) ≤ Output Signal < ( ( ) > Output Signal ALC ) ALC ( ) RFST1-0 bits WTM2 WTM1 WTM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 RGAIN1 0 0 1 1 128/fs 256/fs 512/fs 1024/fs 2048/fs 4096/fs 8192/fs 16384/fs Table 31. ALC RGAIN0 0 1 0 1 Table 32. ALC (Table 34) ALC 8kHz 16ms 32ms 64ms 128ms 256ms 512ms 1024ms 2048ms 16kHz 8ms 16ms 32ms 64ms 128ms 256ms 512ms 1024ms GAIN STEP 1 step 0.375dB 2 step 0.750dB 3 step 1.125dB 4 step 1.500dB MS0543-J-00 44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms 46.4ms 92.9ms 185.8ms 371.5ms Default Default 2006/09 - 44 - ASAHI KASEI [AK4645] REF7-0 GAIN(dB) F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 E1H +30.0 E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 33. ALC RFST1 bit 0 0 1 1 RFST0 bit 0 1 0 1 Step 0.375dB 4 8 16 N/A Default Default Table 34. MS0543-J-00 2006/09 - 45 - ASAHI KASEI 3. [AK4645] ALC Table 35 ALC Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 RFST1-0 ALC ALC bit = “0” Gain of IVOL Limiter ATT step Recovery GAIN step Fast Recovery Speed ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation −4.1dBFS Enable 23.2ms 001 32ms 011 23.2ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 1 step 1 step 4 times Enable 00 00 00 1 1 step 1 step 4 times Enable 00 00 00 1 Table 35. ALC ALC (ALC PMADL = PMADR bits = “0”) LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0 Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” Manual Mode WR (ZTM1-0, WTM2-0, RFST1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’s WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”) (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 36. ALC MS0543-J-00 2006/09 - 46 - ASAHI KASEI [AK4645] ( ) ALC bit = “0” 1. 2. ALC (ZTM1-0, LMTH1-0 bits ALC ) 3. IVL7-0, IVR7-0 bits PMADL = PMADR bits = “0” = “1” ADC (Table 36) ZTM1-0 bits IVL7-0, IVR7-0 bits L/R PMADL bit = “1” or PMADR bit IVOL IVL7-0 = IVR7-0 bits = “91H” (0dB) IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H Table 36. GAIN (dB) +36.0 +35.625 +35.25 : +30.375 +30.0 +29.625 : −53.25 −53.625 −54 MUTE MS0543-J-00 Step 0.375dB Default 2006/09 - 47 - ASAHI KASEI [AK4645] IVL7-0, IVR7-0 bits ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) (1) E1(+30dB) (2) E1(+30dB) --> F1(+36dB) Figure 37. ALC IVL IVR IVL7-0 bits (WTM2-0 bits) + (2) ALC IVL, IVR Disable C6H(+20dB) IVOL (1) ALC IVL ALC bit = “1” ALC (ZTM1-0 bits) (09H, 0CH) ALC bit = “0” MS0543-J-00 ALC Disable ALC Enable ALC bit = “1” 2006/09 - 48 - ASAHI KASEI [AK4645] IIR 3 (32kHz, 44.1kHz, 48kHz) DEM1-0 bits (tc=50/15µs ) (Table 37) DEM1 DEM0 0 0 0 1 1 0 1 1 Table 37. Mode 44.1kHz OFF 48kHz 32kHz Default BST1-0 bits 38) BST1-0 bits = “01”(MIN) DAC (Table 47µF DC DAC Figure 38 −20dB Boost Filter (fs=44.1kHz) 0 MAX Level [dB] -5 MID -10 MIN -15 -20 -25 10 100 1000 10000 Frequency [Hz] Figure 38. (fs=44.1kHz) BST1 BST0 0 0 0 1 1 0 1 1 Table 38. Mode OFF MIN MID MAX MS0543-J-00 Default 2006/09 - 49 - ASAHI KASEI [AK4645] AK4645 MUTE 0.5dB DAC DVOLC bit “1” bit “0” Lch, Rch 256/fs 00H(+12dB) FFH(MUTE) 256 +12dB DVL7-0 bits 0 1 −115dB Lch, Rch DVOLC ATT 1061 DVTM bit = “0” DVTM bit 1061/fs(24ms@fs=44.1kHz) DVL/R7-0 00H 01H 02H : 18H : FDH FEH FFH DVTM bit (DATT) Gain Step +12.0dB +11.5dB +11.0dB : 0.5dB 0dB : −114.5dB −115.0dB MUTE (−∞) Table 39. Digital Volume Code Table DVL/R7-0 bits = 00H FFH fs=8kHz 1061/fs 133ms 256/fs 32ms Table 40. MS0543-J-00 Default fs=44.1kHz 24ms 6ms Default 2006/09 - 50 - ASAHI KASEI [AK4645] DAC SMUTE bit “1” SMUTE bit “0” SMUTE bit −∞(“0”) DVTM bit −∞ −∞ bits DVTM bit DVTM bit DVL/R7-0 bits DVL/R7-0 (Figure 39) S M U T E bit D VTM bit D VL/R 7-0 bits D VTM bit (1) (3) A ttenuation -∞ GD (2) GD A nalog O utput Figure 39. (1) DVTM bit (2) (3) −∞(“0”) (GD) DVTM bit DVL/R7-0 bits MS0543-J-00 2006/09 - 51 - ASAHI KASEI [AK4645] : (LIN2/RIN2/LIN4/RIN4 pins, AIN3 bit = “1”: LIN3/RIN3 pins) PMAINL2=PMAINR2 bits = “1” LINH2 bit RINH2 bit “1” LIN2/RIN2 pins “1” LINL2 bit RINR2 bit PMAINL4=PMAINR4 bits = “1” LINH4 bit RINH4 bit “1” LIN4/RIN4 pins “1” LINL4 bit RINR4 bit PMADL bit PMADR bit “1” MGAIN1-0 bits = “00” LIN2/RIN2/LIN4/RIN4 pins bits = “01”, “10”, “11” typ. 20kΩ AIN3 bit = “1” MIN/VCOC pins LIN3/RIN3 pins PMAINL3=PMAINR3 bits = “1” LIN3/RIN3 pins PMMICL=PMMICR=MICL3=MICR3 bits = “1” MIC-Amp LINH3 bit RINH3 bit LINL3 bit RINR3 bit “1” A/D typ. 30kΩ MGAIN1-0 PLL LIN3/RIN3 pins “1” PMADL bit PMADR bit “1” A/D LIN3/RIN3 pins MICL3=MICR3 bits = “0” MGAIN1-0 bits = “00” typ. 30kΩ MGAIN1-0 bits = “01”, “10”, “11” typ. 20kΩ MICL3=MICR3 bits = “1” MGAIN1-0 bits = “00” typ. 60kΩ MGAIN1-0 bits = “01”, “10”, “11” typ. 30kΩ (typ) Table 41, Table 42, Table 43 AK4645 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp These blocks are not available at PLL mode. MIN/LIN3 pin MICR3 bit PMAINR3 bit PMAINR2 bit PMAINL2 bit PMAINR4 bit PMAINL4 bit RIN4/IN4− pin MICL3 bit LIN4/IN4+ pin PMAINL3 bit VCOC/RIN3 pin Lineout, HP-Amp Figure 40. ( MS0543-J-00 ) 2006/09 - 52 - ASAHI KASEI [AK4645] PMAINL2 bit PMAINR2 bit LINL2/RINR2 LOUT/LOP pin, ROUT/LON pin LIN2/RIN2 LINH2/RINH2 HPL, HPR pins Figure 41. (LIN2/RIN2) PMAINL4 bit PMAINR4 bit LINL4/RINR4 LOUT/LOP pin, ROUT/LON pin LIN4/RIN4 LINH4/RINH4 HPL, HPR pins Figure 42. (LIN4/RIN4) PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/LOP pin, ROUT/LON pin LIN3/RIN3 LINH3/RINH3 HPL, HPR pins Figure 43. (LIN3/RIN3: PLL ) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOUT/ROUT 0 0dB Default 1 +2dB Table 41. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOUT/ROUT Output Gain (typ) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOP/LON 0 0dB Default 1 +2dB Table 42. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOP/LON Output Gain (typ) HPG bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ HPL/HPR 0 0dB Default 1 +3.6dB Table 43. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Headphone-Amp Output Gain (typ) MS0543-J-00 2006/09 - 53 - ASAHI KASEI [AK4645] : L4DIF bit = “1” LIN4, RIN4 pins (L4DIF bit = “1”: IN4+/IN4− pins) IN4+, IN4− pins PMAINL4 bit = “1” IN4+, IN4− pins LINH4 bit RINH4 bit “1” (typ) LINL4 bit RINR4 bit “1” (IN4+) − (IN4−) Table 44, Table 45, Table 46 AK4645 MIC-Amp Lch LIN4/IN4+ pin L4DIF bit PMAINL4 bit MIC-Amp Rch RIN4/IN4− pin PMAINR4 bit Lineout, HP-Amp Figure 44. Full-differential Mono Analog Mixing Circuit LOVL bit IN4+/IN4− Æ LOUT/ROUT 0 Default −6dB 1 −4dB Table 44. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ) LOVL bit IN4+/IN4− Æ LOP/LON 0 0dB Default 1 +2dB Table 45. IN4+/IN4− Input Æ LOP/LON Output Gain (typ) HPG bit IN4+/IN4− Æ HPL/HPR 0 Default −6dB 1 −2.4dB Table 46. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ) MS0543-J-00 2006/09 - 54 - ASAHI KASEI [AK4645] AIN3 bit = “0” MINH bit : (AIN3 bit = “0”: MIN pin) MIN pin PMMIN bit = “1” “1” MINL bit Ri Ri 47, Table 48, Table 49 Ri “1” Ri = 20kΩ (typ) Table MINL MIN LOUT/LOP pin, ROUT/LON pin MINH HPL, HPR pin Figure 7. Block Diagram of MIN pin LOVL bit 0 1 Table 47. Ri = 20kΩ LOVL bit 0 1 Table 48. Ri = 20kΩ HPG bit 0 1 Table 49. Ri = 20kΩ MIN Æ LOUT/ROUT 0dB +2dB MIN Æ LOUT/ROUT MIN Æ LOP/LON +6dB +8dB MIN Æ LOP/LON MIN Æ HPL/HPR −20dB −16.4dB MIN Æ MS0543-J-00 Default (typ) Default (typ) Default (typ) 2006/09 - 55 - ASAHI KASEI [AK4645] (LOUT/ROUT pins) DACL bit “1” DACL bit “0” AVSS 100kΩ(typ) LOPS bit = “1” 20kΩ 300ms DAC Lch, Rch OFF min. 10kΩ LOUT, ROUT pins LOUT, ROUT pins VCOM PMLO=LOPS bits = “0” LOPS bit = “1” PMLO bit ON/OFF ON/OFF Figure 46 C C=1µF, AVDD=3.3V PMLO bit = “1” LOPS bit = “0” LOVL bit LOM bit = “1” LOM3 bit = “1” DAC [(L+R)/2] MICL3, MICR3 bits LOUT, ROUT pins (LIN3/RIN3 “DACL” LOUT, ROUT pins MIC-Amp ) [(L+R)/2] “LOVL” LOUT pin DAC ROUT pin Figure 45. LOPS 0 1 PMLO 0 1 0 1 Table 50. Mode LOUT/ROUT pin Pull-down to AVSS Default Fall down to AVSS Rise up to VCOM (x: Don’t care) LOVL Gain 0 0dB 1 +2dB Table 51. (typ) 0.6 x AVDD 0.757 x AVDD LOUT ROUT 1µF Default 220Ω 20kΩ Figure 46. ( MS0543-J-00 ) 2006/09 - 56 - ASAHI KASEI [AK4645] ( ) (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 47. (1) (2) ON ) C=1µF, AVDD=3.3V 200ms (max LOPS bit = “1” PMLO bit = “1” LOUT, ROUT pins 300ms) (3) LOUT, ROUT pins (4) (5) ( LOPS bit = “0” ON LOPS bit = “1” PMLO bit = “0” LOUT, ROUT pins 300ms) (6) LOUT, ROUT pins C=1µF, AVDD=3.3V 200ms (max LOPS bit = “0” MS0543-J-00 2006/09 - 57 - ASAHI KASEI [AK4645] AIN3 bit = “0” MIN LIN2/RIN2/LIN4/RIN4/DAC ON/OFF DACL, MINL, LINL2, RINR2, LINL4, RINR4 bits 20kΩ 0dB(typ)@LOVL bit = “0” 0dB(typ)@LOVL bit = “0” LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin M 0dB MINL bit MIN pin 0dB I LOUT pin X DACL bit DAC Lch 0dB Figure 48. LOUT (AIN3 bit = “0”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin M 0dB MINL bit MIN pin 0dB I ROUT pin X DACL bit DAC Rch Figure 49. ROUT 0dB (AIN3 bit = “0”, LOVL bit = “0”) MS0543-J-00 2006/09 - 58 - ASAHI KASEI AIN3 bit = “1” MICL3, MICR3 bits [AK4645] ON/OFF DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, 0dB(typ) LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. LOUT pin X DACL bit DAC Lch Figure 50. LOUT 0dB (AIN3 bit = “1”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINR3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. ROUT pin X DACL bit DAC Rch Figure 51. ROUT 0dB (AIN3 bit = “1”, LOVL bit = “0”) MS0543-J-00 2006/09 - 59 - ASAHI KASEI [AK4645] (LOP/LON pins) LODIF bit = “1” LOUT/ROUT pins LOP/LON pins LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 [(L+R)/2] min. 10kΩ PMLO bit = “0” LOP/LON pins Hi-Z PMLO bit = “1”, LOPS bit = “1” PMLO bit = “1”, LOPS bit = “0” DAC LOP/LON pins LOVL bit (LOP) − (LON) = (IN4+) − (IN4−) L4DIF=LODIF bits = “1” “DACL” “LOVL” LOP pin DAC LON pin Figure 52. Mono Line Output PMLO 0 1 LOPS Mode LOP LON x Power-down Hi-Z Hi-Z 1 Power-save Hi-Z VCOM 0 Normal Operation Normal Operation Normal Operation Table 52. Mono Line Output Mode Setting (x: Don’t care) LOVL 0 1 Default Gain Output Voltage (typ) +6dB 1.2 x AVDD Default +8dB 1.5 x AVDD Table 53. Mono Line Output Volume Setting PMLO bit LOPS bit LOP pin LON pin Hi-Z Hi-Z Hi-Z VCOM VCOM Hi-Z Figure 53. Power-up/Power-down Timing for Mono Line Output MS0543-J-00 2006/09 - 60 - ASAHI KASEI [AK4645] AIN3 bit = “0” MIN LIN2/RIN2/LIN4/RIN4/DAC ON/OFF DACL, MINL, LINL2, RINR2, LINL4, RINR4 bits 20kΩ +6dB(typ)@LOVL bit = “0” 0dB(typ)@LOVL bit = “0” LINL2 bit LIN2 pin 0dB RINR2 bit RIN2 pin 0dB LINL4 bit LIN4 pin 0dB M RINR4 bit RIN4 pin LOP/N pin I 0dB X MINL bit MIN pin +6dB DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB Figure 54. AIN3 bit = “1” MICL3, MICR3 bits (AIN3 bit = “0”, LOVL bit = “0”) ON/OFF DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, 0dB(typ)@LOVL bit = “0” LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit 0dB MIC-Amp Lch *These blocks are not available at PLL mode. RINR2 bit RIN2 pin M 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin I LOP/N pin X RINR3 bit 0dB MIC-Amp Rch *These blocks are not available at PLL mode. DACL bit DAC Lch 0dB DAC Rch 0dB DACL bit Figure 55. (AIN3 bit = “1”, LOVL bit = “0”) MS0543-J-00 2006/09 - 61 - ASAHI KASEI [AK4645] (HPL/HPR pins) HVDD HPG bit 16Ω (min) HPM bit = “1” HPM3 bit = “1” HVDD/2@VBAT bit = “0” (Table 54) HPL, HPR pins (LIN3/RIN3 MIC-Amp ) DAC [(L+R)/2] MICL3, MICR3 bits HPL, HPR pins HPG bit Output Voltage [Vpp] 0 0.6 x AVDD [(L+R)/2] 1 0.91 x AVDD Table 54. HPMTN bit “0” HVSS HPMTN bit “1” MUTET pin MUTET pin HVDD/2@VBAT bit = “0” HVDD : MUTET pin C=1µF, HVDD=3.3V : 100ms(typ), 250ms(max) : 500ms(max) PMHPL, PMHPR bits “0” HPL, HPR pins “L” (HVSS) PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 56. (1) (2) (3) (4) (PMHPL, PMHPR bits = “1”) (HPMTN bit = “1”) (HPMTN bit = “0”) (PMHPL, PMHPR bits = “0”) BOOST=OFF HVSS (fc) Table 55 (fc) HVDD=3.0, 3.3, 5V bit = “0”, 0.91 x AVDD (Vpp)@HPG bit = “1” R 12Ω (0.22µF±20% HVSS 10Ω±20% RL 16Ω 0.6 x AVDD (Vpp)@HPG ) MS0543-J-00 2006/09 - 62 - ASAHI KASEI [AK4645] HP-AMP C AK4645 0.22µ R Headphone 16Ω 10Ω Figure 57. HPG bit R [Ω] 0 0 6.8 16 0 1 100 fc [Hz] BOOST =OFF fc [Hz] BOOST C [µF] =MIN fs=44.1kHz 220 45 17 100 100 43 100 70 28 47 149 78 100 50 19 47 106 47 220 45 17 100 100 43 22 62 25 10 137 69 Table 55. Note 40. 16Ω Note 41. Output Power [mW]@0dBFS HVDD=3.0V HVDD=3.3V AVDD=3.0V AVDD=3.3V HVDD=5V AVDD=3.3V 25.3 30.6 30.6 12.5 15.1 15.1 6.3 7.7 7.7 51 (Note 41) 62 (Note 41) 70 1.1 1.3 1.3 PSRR HVDD RF HVDD VBAT bit = “1” AVDD(typ) PSRR AVDD=3.3V 0.64 x 2.1V VBAT bit Common Voltage [V] Table 56. HVDD 0 0.5 x HVDD 4.2V 1 0.64 x AVDD Wired OR PMVCM=PMHPL=PMHPR bits = “0”, HPZ bit = “1” 200kΩ(typ) HVSS OR PMVCM x 0 1 1 PMHPL/R 0 0 1 1 HP-Amp AK4645 HP-Amp 20µA(typ) HPMTN HPZ Mode x 0 Power-down & Mute x 1 Power-down 0 x Mute 1 x Normal Operation Table 57. HP-Amp Mode Setting (x: Don’t care) MS0543-J-00 HPL, HPR pins HP-Amp Wired HPL/R pins HVSS Pull-down by 200kΩ HVSS Normal Operation Default 2006/09 - 63 - ASAHI KASEI [AK4645] HPL pin AK4645 Headphone HPR pin Another HP-Amp Figure 58. AIN3 bit = “0” MIN LIN2/RIN2/LIN4/RIN4/DAC ON/OFF Wired OR DACH, MINH, LINH2, RINH2, LINH4, RINH4 bits 20kΩ −20dB(typ)@HPG bit = “0” 0dB(typ)@HPG bit = “0” LINH2 bit LIN2 pin 0dB LIN4 pin 0dB LINH4 bit M MINH bit −20dB MIN pin I HPL pin X DACH bit DAC Lch 0dB Figure 59. HPL (AIN3 bit = “0”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RIN4 pin 0dB RINH4 bit M MINH bit −20dB MIN pin I HPR pin X DACH bit DAC Rch Figure 60. HPR 0dB (AIN3 bit = “0”, HPG bit = “0”) MS0543-J-00 2006/09 - 64 - ASAHI KASEI AIN3 bit = “1” MICL3, MICR3 bits [AK4645] ON/OFF DACH, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, 0dB(typ) LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINH3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. HPL pin X DACH bit DAC Lch Figure 61. HPL 0dB (AIN3 bit = “1”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINH3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. HPR pin X DACH bit DAC Rch Figure 62. HPR 0dB (AIN3 bit = “1”, HPG bit = “0”) MS0543-J-00 2006/09 - 65 - ASAHI KASEI [AK4645] (1) 3 (I2C pin = “L”) 3 I/F (CSN, CCLK, CDTI) address (1bit, “1” ), Read/Write (1bit, “1” ), Register address (MSB first, 6bits) 8bits) CCLK “↓” CSN “↓” 16 CCLK “↑” CCLK (max) PDN pin = “L” I/F Chip Control Data (MSB first, “↑” 5MHz CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “1” C1: R/W: A5-A0: D7-D0: Chip Address; Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 63. MS0543-J-00 2006/09 - 66 - ASAHI KASEI (2) I2C AK4645 [AK4645] (I2C pin = “H”) I 2C (max:400kHz) SDA, SCL pins (TVDD+0.3)V (2)-1. WRITE I2C (Start Condition) (Figure 70) 8 IC AK4645 SDA R/W bit “1” 2 MSB first “L” IC “H” SDA “L” 7 (R/W) 6 “001001” (Figure 65) CAD0 pin 1 (Acknowledge) (Figure 71) ( ) (Figure 66) 3 (Figure 67) AK4645 “0” SDA Figure 64 “H” SCL 8 “0” MSB first 2 8 (Stop Condition) (Figure 70) “H” R/W bit AK4645 SCL “H” 1 “24H” “00H” “H” SDA SCL “L” (Figure 72) “H” SCL “L” “H” SDA S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K P A C K A C K Figure 64. I2C 0 0 1 0 0 (CAD0 Figure 65. 0 0 A5 D6 D5 Figure 67. CAD0 R/W A3 A2 A1 A0 D3 D2 D1 D0 ) 1 A4 Figure 66. D7 1 2 D4 3 MS0543-J-00 2006/09 - 67 - ASAHI KASEI [AK4645] (2)-2. READ R/W bit “1” AK4645 READ “24H” “00H” AK4645 2 READ (2)-2-1. AK4645 AK4645 (READ WRITE “n+1” (R/W bit = “1”) READ ) “n” 1 READ S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) Data(n+2) A C K A C K Data(n+x) A C K P A C K A C K Figure 68. (2)-2-2. READ (R/W bit = “1”) WRITE WRITE = “0”) AK4645 (R/W bit= “1”) READ (R/W bit AK4645 1 READ S T A R T SDA S T A R T R/W="0" Sub Address(n) Slave S Address A C K Slave S Address A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 69. MS0543-J-00 2006/09 - 68 - ASAHI KASEI [AK4645] SDA SCL S P start condition stop condition Figure 70. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 71. I2C SDA SCL data line stable; data valid change of data allowed Figure 72. I2C MS0543-J-00 2006/09 - 69 - ASAHI KASEI [AK4645] Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved Note 42. PDN pin Note 43. “0” D7 0 HPZ 0 LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 D6 PLL1 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR4 0 LOM 0 0 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 LOM3 HPM3 0 MICR3 RINR4 RINH4 0 MICL3 LINL4 LINH4 0 L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF PMVCM D5 PMMIN PMHPL 0 MGAIN1 D0 PMADL PMPLL MGAIN0 LINL2 LINH2 0 “L” “1” MS0543-J-00 2006/09 - 70 - ASAHI KASEI [AK4645] Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 PMADL: MIC-Amp Lch, ADC Lch 0: Power down (Default) 1: Power up PMADL PMADR bit “0” D5 PMMIN 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 “1” D1 0 0 D0 PMADL 0 (1059/[email protected]) ADC PMDAC: DAC 0: Power down (Default) 1: Power up PMLO: 0: Power down (Default) 1: Power up PMMIN: 0: Power down (Default) 1: Power up PMMIN or PMAINL3 bit = “1” PMVCM: VCOM 0: Power down (Default) 1: Power up PMVCM bit “1” 00H, 01H, 02H, 10H, 20H “0” MCKO bit PMVCM bit “0” ON/OFF (“1”/“0”) PDN pin “L” 00H, 01H, 02H, 10H, 20H 20µA(typ) ADC MCKO bit (typ. 1µA) DAC PDN pin = “L” ADC MS0543-J-00 “0” DAC 2006/09 - 71 - ASAHI KASEI Addr 01H [AK4645] Register Name Power Management 2 Default D7 HPZ 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 PMPLL 0 PMPLL: PLL 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up MCKO: MCKO 0: Disable: MCKO pin = “L” (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PMHPR: Rch 0: Power down (Default) 1: Power up PMHPL: Lch 0: Power down (Default) 1: Power up HPMTN: 0: Mute (Default) 1: Normal operation HPZ: HP-Amp 0: 1: 200kΩ(typ) Addr 02H (Default) Register Name Signal Select 1 Default MGAIN1-0: MGAIN1 bit D7 0 0 D6 0 0 D5 0 0 D0 MGAIN0 1 (See Table 23) 03H D5 bit PMMP: MPWR pin 0: Power down: Hi-Z (Default) 1: Power up DACL: DAC 0: OFF (Default) 1: ON PMLO bit = “1” PMLO bit = “0” MS0543-J-00 LOUT, ROUT pins AVSS 2006/09 - 72 - ASAHI KASEI Addr 03H [AK4645] Register Name Signal Select 2 Default D7 LOVL 0 MINL: 0: OFF (Default) 1: ON PMLO bit = “1” D6 LOPS 0 D5 D4 0 0 MGAIN1 0 D3 0 0 D2 MINL 0 D1 0 0 D0 0 0 MIN PMLO bit = “0” MGAIN1: LOUT, ROUT pins AVSS (See Table 23) LOPS: 0: Normal Operation (Default) 1: Power Save Mode LOVL: 0: 0dB/+6dB (Default) 1: +2dB/+8dB Addr 04H / Register Name Mode Control 1 Default DIF1-0: Default: “10” ( BCKO: D7 PLL3 0 D6 PLL2 0 Register Name Mode Control 2 Default D2 0 0 D1 DIF1 1 D0 DIF0 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 (See Table 5) D7 PS1 0 D6 PS0 0 D5 FS3 0 PLL BICK , “↓” , “↑” MSBS: DSP Mode LRCK “0”: LRCK “↑” “1”: LRCK “↑” PS1-0: MCKO Default: “00”(256fs) D3 BCKO 0 (See Table 11) (See Table 6 and Table 7) BCKP: DSP Mode “0”: “↑” SDTO “1”: “↓” SDTO D4 PLL0 0 ) BICK FS3-0: D5 PLL1 0 (See Table 17) PLL3-0: PLL Default: “0000”(LRCK pin) Addr 05H (See Table 51, Table 53) SDTI SDTI D4 MSBS 0 MCKI EXT (See Table 12) MCKI (See Table 18) (Default) (See Table 18) BICK (Default) BICK 1 (See Table 10) MS0543-J-00 2006/09 - 73 - ASAHI KASEI Addr 06H [AK4645] Register Name Timer Select Default D7 DVTM 0 RFST1-0: ALC Default: “00”(4 D6 WTM2 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 RFST1 0 D0 RFST0 0 D3 LMAT1 0 D2 LMAT0 0 D1 RGAIN0 D0 LMTH0 0 (See Table 34) ) WTM2-0: ALC ALC “000” (128/fs) (See Table 31) ZTM1-0: ALC (See Table 30) ALC “00” (128/fs) DVTM: Digital Volume 0: 1061/fs (Default) 1: 256/fs DVL7-0, DVR7-0 bits Addr 07H Register Name ALC Mode Control 1 Default LMTH1-0: ALC Default: “00” LMTH1 bit RGAIN1-0: ALC Default: “00” RGAIN1 bit D7 0 0 D6 0 0 00H D5 ALC 0 FFH D4 ZELMN 0 / 0BH 0 (See Table 28) D6 bit (See Table 32) 0BH LMAT1-0: ALC Default: “00” D7 bit ATT (See Table 29) ZELMN: ALC 0: Enable (Default) 1: Disable ALC: ALC 0: ALC Disable (Default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default REF7-0: ALC Default: “E1H” (+30.0dB) D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 0.375dB step, 242 Level (See Table 33) MS0543-J-00 2006/09 - 74 - ASAHI KASEI Addr 09H 0CH [AK4645] Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 IVL7-0, IVR7-0: Default: “E1H” (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default Register Name ALC Mode Control 3 Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D4 0 0 D3 0 0 D2 0 0 D1 VBAT 0 D0 0 0 (See Table 39) D7 RGAIN1 0 D6 LMTH1 0 VBAT: 0: 0.5 x HVDD (Default) 1: 0.64 x AVDD / RGAIN1: ALC Register Name Mode Control 3 Default DEM1-0: Default: “01” (OFF) BST1-0: Default: “00” (OFF) DVOLC: 0: Independent 1: Dependent (Default) DVOLC bit = “1” DVR7-0 bit DVL7-0 bit D5 0 0 (See Table 56) LMTH1: ALC Addr 0EH D4 IVL4 IVR4 0 ; 0.375dB step, 242 Level (See Table 36) DVL7-0, DVR7-0: Default: “18H” (0dB) Addr 0BH D5 IVL5 IVR5 1 (See Table 28) (See Table 32) D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 (See Table 37) (See Table 38) DVL7-0 bit SMUTE: 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: 0: SDTI → DAC (Default) 1: SDTO → DAC MS0543-J-00 2006/09 - 75 - ASAHI KASEI Addr 0FH [AK4645] Register Name Mode Control 4 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 MINH 0 D0 DACH 0 DACH: DAC 0: OFF (Default) 1: ON MINH: MIN pin 0: OFF (Default) 1: ON HPM: 0: 1: (Default) HPM bit = “1” DAC IVOLC: IVOL 0: Independent 1: Dependent (Default) IVOLC bit = “1” Addr 10H (L+R)/2 IVL7-0 bit Register Name Power Management 3 Default D7 INR1 0 IVOL D6 INL1 0 D5 HPG 0 D4 MDIF2 0 IVR7-0 bit D3 MDIF1 0 D2 INR0 0 D1 INL0 0 IVL7-0 bit D0 PMADR 0 PMADR: MIC-Amp Rch, ADC Rch 0: Power down (Default) 1: Power up INL1-0: ADC Lch Default: 00 (LIN1 pin) (See Table 20) INR1-0: ADC Rch Default: 00 (RIN1 pin) (See Table 20) MDIF1: 0: 1: MDIF2: 0: 1: / 1 (LIN1/RIN1 pin: Default) (IN1+/IN1− pin) Pin#32 #31 2 (LIN2/RIN2 pin: Default) (IN2+/IN2− pin) Pin#30 #29 HPG: 0: 0dB (Default) 1: +3.6dB / (See Table 54) MS0543-J-00 2006/09 - 76 - ASAHI KASEI Addr 11H Register Name Digital Filter Select Default GN1-0: Gain Default: “00” (0dB) FIL3: 0: 1: [AK4645] D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D0 0 0 FIL3 (Default) FIL3 bit = “0” FIL3 (Default) EQ bit = “1” EQ FIL1: 0: 1: D1 0 0 (See Table 26) FIL3 bit = “1” F3A13-0, F3B13-0 bit OFF(MUTE) EQ: 0: 1: D2 FIL3 0 EQA15-0, EQB13-0, EQC15-0 bit (0dB) EQ bit = “0” FIL1 (Default) FIL1 bit = “1” F1A13-0, F1B13-0 bit FIL1 bit = “0” FIL1 (0dB) Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 F3A13-0, F3B13-0: Default: “0000H” F3AS: 0: HPF (Default) 1: LPF D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 FIL3 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 (14bit x 2) FIL3 EQA15-0, EQB13-0, EQC15-C0: Default: “0000H” F1A13-0, F1B13-B0: Default: “0000H” F1AS: 0: HPF (Default) 1: LPF D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 (14bit x 2 + 16bit x 1) FIL1 (14bit x 2) FIL1 MS0543-J-00 2006/09 - 77 - ASAHI KASEI Addr 20H Register Name Power Management 4 Default [AK4645] D7 D6 D5 D4 D3 D2 D1 D0 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 0 0 0 0 0 0 0 PMMICL: MIC-Amp Lch 0: Power down (Default) 1: Power up PMMICR: MIC-Amp Rch 0: Power down (Default) 1: Power up PMAINL2: LIN2 0: Power down (Default) 1: Power up PMAINR2: RIN2 0: Power down (Default) 1: Power up PMAINL3: LIN3 0: Power down (Default) 1: Power up PMMIN or PMAINL3 bit = “1” PMAINR3: RIN3 0: Power down (Default) 1: Power up PMAINL4: LIN4 0: Power down (Default) 1: Power up PMAINR4: RIN4 0: Power down (Default) 1: Power up MS0543-J-00 2006/09 - 78 - ASAHI KASEI Addr 21H [AK4645] Register Name Mode Control 5 Default D7 0 0 LODIF: 0: 1: AIN3: 0: 1: MIX: 0: 1: L4DIF: 0: 1: D6 0 0 D5 MICR3 0 D4 MICL3 0 D3 L4DIF 0 D2 MIX 0 D1 AIN3 0 D0 LODIF 0 (LOUT/ROUT pins) (Default) (LOP/LON pins) (MIN pin) (Default) (LIN3/RIN3 pins): PLL (Default) : (L+R)/2 : LIN4/RIN4 pins (Default) : IN4+/− pins MICL3: 0: LIN3 pin (Default) 1: MIC-Amp Lch MICR3: 0: RIN3 pin (Default) 1: MIC-Amp Rch MS0543-J-00 2006/09 - 79 - ASAHI KASEI Addr 22H Register Name Lineout Mixing Select Default [AK4645] D7 LOM 0 D6 LOM3 0 D5 RINR4 0 D4 LINL4 0 D3 RINR3 0 D2 LINL3 0 D1 RINR2 0 LINL2: LIN2 0: OFF (Default) 1: ON (MIC-Amp ) RINR2: RIN2 0: OFF (Default) 1: ON (MIC-Amp ) LINL4: LIN4 0: OFF (Default) 1: ON (MIC-Amp ) RINR4: RIN4 0: OFF (Default) 1: ON (MIC-Amp ) D0 LINL2 0 LINL3: LIN3 (or MIC-Amp Lch) 0: OFF (Default) 1: ON RINR3: RIN3 (or MIC-Amp Rch) 0: OFF (Default) 1: ON LOM3: MIC-Amp (or LIN3/RIN3) 0: Stereo Mixing (Default) 1: Mono Mixing LOM: DAC 0: Stereo Mixing (Default) 1: Mono Mixing MS0543-J-00 2006/09 - 80 - ASAHI KASEI Addr 23H Register Name HP Mixing Select Default [AK4645] D7 0 0 D6 HPM3 0 D5 RINH4 0 D4 LINH4 0 D3 RINH3 0 D2 LINH3 0 D1 RINH2 0 LINH2: LIN2 0: OFF (Default) 1: ON (MIC-Amp ) RINH2: RIN2 0: OFF (Default) 1: ON (MIC-Amp ) LINH4: LIN4 0: OFF (Default) 1: ON (MIC-Amp ) RINH4: RIN4 0: OFF (Default) 1: ON (MIC-Amp ) D0 LINH2 0 LINH3: LIN3 (or MIC-Amp Lch) 0: OFF (Default) 1: ON RINH3: RIN3 (or MIC-Amp Rch) 0: OFF (Default) 1: ON HPM3: MIC-Amp (or LIN3/RIN3) 0: Stereo Mixing (Default) 1: Mono Mixing MS0543-J-00 2006/09 - 81 - ASAHI KASEI Figure 73 [AK4645] Figure 74 (AKD4645) Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V Power Supply 1.6 ∼ 3.6V 10 0.22u 17 18 MCKO 0.1u MCKI 19 HVSS 20 HVDD 0.1u 21 22 HPR Line In MUTET 23 RIN4 External SPK-Amp HPL 24 1u 25 LIN4 TVDD 16 26 ROUT DVDD 15 27 LOUT BICK 14 Speaker 0.1u Mono In External MIC DSP 28 MIN AK4645EN LRCK 13 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 I2C PDN CSN 6 7 8 VCOC 5 4 µP Rp AVDD 3 2.2u 0.1u VCOM AVSS 2 MPWR 1 0.1u 2.2k 2.2k 2.2k 2.2k Internal MIC Cp Analog Ground : - AK4645 - EXT - PLL - Digital Ground AVSS, HVSS (PMPLL bit = “0”) (PMPLL bit = “1”) Figure 73. VCOC pin Cp Rp Table 5 M/S bit “1” AK4645 AK4645 LRCK, BICK pin 100kΩ (AIN3 bit = “0”, MS0543-J-00 LRCK, BICK pin ) 2006/09 - 82 - ASAHI KASEI [AK4645] Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 ∼ 3.6V Power Supply 1.6 ∼ 3.6V 10 0.22u 17 18 MCKO MCKI 19 20 HVDD HVSS 21 HPR 22 26 ROUT DVDD 15 27 LOUT BICK 14 0.1u DSP 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 µP 2.2u 0.1u 1 0.1u 8 SDTI CSN 30 LIN2 PDN 12 7 SDTO I2C Top View 6 29 RIN2 RIN3 13 5 LRCK AVDD AK4645EN 4 28 LIN3 MPWR Line In 16 VCOM 1u TVDD AVSS 200 0.1u 25 LIN4 3 1u 2 Line Out 200 MUTET 23 Line In HPL RIN4 24 20k 20k 0.1u 1u Analog Ground : - AK4645 - Digital Ground AVSS, HVSS Figure 74. M/S bit “1” AK4645 LRCK, BICK pin (AIN3 bit = “1”: PLL MS0543-J-00 , AK4645 100kΩ LRCK, BICK pin ) 2006/09 - 83 - ASAHI KASEI [AK4645] 1. AVDD, DVDD, TVDD, HVDD AVDD, DVDD, TVDD, HVDD AVSS, HVSS PC 2. VCOM 2.2µF 0.1µF AVSS VCOM pin VCOM pin 3. MIN (0.45 x AVDD) 0.06 x AVDD Vpp(typ)@MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ)@MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ)@MGAIN1-0 bits = “11” 0.6 x AVDD Vpp(typ)@MGAIN1-0 bits = “00” MIN (0.45 x AVDD) 0.6 x AVDD Vpp(typ) DC fc=1/(2πRC) AK4645 AVSS AVDD 4. DAC 8000H(@16bit) 2’s 0000H(@16bit) 0.45 x AVDD (typ) MS0543-J-00 7FFFH(@16bit) VCOM VCOM HVDD/2 2006/09 - 84 - ASAHI KASEI [AK4645] ADC DAC Power-up 1. PLL Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = “L” Æ “H” MCKO bit (Addr:01H, D1) PMPLL bit (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:27H (Addr:01H, D0) (5) MCKI pin Input M/S bit (3)Addr:00H, Data:40H (Addr:01H, D3) 40msec(max) (6) BICK pin LRCK pin Output (4)Addr:01H, Data:0BH Output MCKO, BICK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 75. Clock Set Up Sequence (1) < > PDN pin “L” Æ “H” AK4645 150ns “L” (2) DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits (3) VCOM : PMVCM bit = “0” Æ “1” VCOM (4) MCKO : MCKO bit = “1” MCKO : MCKO bit = “0” (5) PMPLL bit “0” Æ “1” MCKI pin PLL 40ms(max) (6) PLL BICK, LRCK (7) MCKO bit = “1” MCKO pin (8) MCKO bit = “1” PLL MCKO pin (1) MS0543-J-00 PLL 2006/09 - 85 - ASAHI KASEI [AK4645] 2. PLL (LRCK or BICK pin) Example: Power Supply Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 44.1kHz (1) PDN pin (2) 4fs (1)ofPower Supply & PDN pin = “L” Æ “H” (3) PMVCM bit (Addr:00H, D6) PMPLL bit (2) Addr:04H, Data:32H Addr:05H, Data:27H (Addr:01H, D0) LRCK pin BICK pin Input (3) Addr:00H, Data:40H (4) Internal Clock (5) (4) Addr:01H, Data:01H Figure 76. Clock Set Up Sequence (2) < > PDN pin “L” Æ “H” AK4645 150ns “L” (2) DIF1-0, FS3-0, PLL3-0 bits (3) VCOM : PMVCM bit = “0” Æ “1” VCOM (4) PMPLL bit “0” Æ “1” PLL (LRCK or BICK pin) PLL LRCK PLL 2ms(max) (5) PLL (1) MS0543-J-00 PLL 160ms(max), BICK PLL 2006/09 - 86 - ASAHI KASEI [AK4645] 3. PLL (MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (3) (2)Addr:04H, Data:4AH Addr:05H, Data:27H PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin (4)Addr:01H, Data:03H Input 40msec(max) (6) MCKO pin MCKO output start Output (7) (8) BICK pin LRCK pin BICK and LRCK input start Input Figure 77. Clock Set Up Sequence (3) < > PDN pin “L” Æ “H” AK4645 150ns (2) DIF1-0, PLL3-0, FS3-0 bits (3) VCOM PMVCM bit = “0” Æ “1” VCOM (4) MCKO : MCKO bit = “1” (5) PMPLL bit “0” Æ “1” MCKI pin PLL 40ms(max) (6) PLL MCKO pin (7) MCKO pin (8) MCKO BICK, LRCK (1) MS0543-J-00 “L” PLL 2006/09 - 87 - ASAHI KASEI [AK4645] 4. ( ) Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:00H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 78. Clock Set Up Sequence (4) < > PDN pin “L” Æ “H” AK4645 150ns (2) DIF1-0, FS1-0 bits (3) VCOM PMVCM bit = “0” Æ “1” VCOM (4) MCKI, LRCK, BICK (1) MS0543-J-00 “L” 2006/09 - 88 - ASAHI KASEI [AK4645] 5. ( ) Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable (1) Power Supply & PDN pin = “L” Æ “H” Power Supply (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3) Addr:04H, Data:02H Addr:05H, Data:00H Addr:01H, Data:08H (2) MCKI pin Input (3) M/S bit BICK and LRCK output (Addr:01H, D3) LRCK pin BICK pin Output (4) Addr:00H, Data:40H Figure 79. Clock Set Up Sequence (5) < > (1) PDN pin “L” Æ “H” AK4645 150ns (2) MCKI (3) DIF1-0, FS1-0 bits (4) VCOM M/S bit “1” PMVCM bit = “0” Æ “1” VCOM MS0543-J-00 “L” LRCK BICK 2006/09 - 89 - ASAHI KASEI [AK4645] Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Table 34 ALC bit=“1” 1,111 (1) MIC Control (1) Addr:05H, Data:27H 001 (Addr:02H, D2-0) 101 (2) Addr:02H, Data:05H (2) ALC Control 1 00H (Addr:06H) 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) ALC Control 2 E1H (Addr:08H) (4) (5) Addr:0BH, Data:00H ALC Control 3 00H (Addr:0BH) 00H (6) Addr:07H, Data:21H (5) ALC Control 4 07H (Addr:07H) 21H 01H (9) (6) ALC State ALC Disable ALC Enable (7) Addr:00H, Data:41H Addr:10H, Data:01H ALC Disable Recording PMADL/R bits (Addr:00H&10H, D0) ADC Internal State (8) Addr:00H, Data:40H Addr:10H, Data:00H 1059 / fs (8) (7) Power Down Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 80. MIC Input Recording Sequence < > fs=44.1kHz ALC ALC “Figure 36. ” (1) (FS3-0 bits) PLL PLL (7) ADC (2) ( 02H) (3) ALC Timer ( 06H) (4) ALC REF ( 08H) (5) LMTH1, RGAIN1 bits ( 0BH) (6) LMTH0, RGAIN0, LMAT1-0, ALC bits ( 07H) (7) ADC : PMADL = PMADR bits = “0” → “1” ADC 1059/fs=24ms@fs=44.1kHz ALC (IVL/R7-0 bits) (+30dB) HPF “1” (8) PMMP bit = “1” 4 ADC ADC ADC AC PMVCM bit = 60k(typ) Power-up : PMADL = PMADR bits = “1” → “0” ALC Disable ALC (ALC bit = “0”) ADC (PMADL = PMADR bits = “0”) PMADL = PMADR bits = “0” (IVL/R7-0 bits) (9) ALC Disable: ALC bit = “1” → “0” MS0543-J-00 2006/09 - 90 - ASAHI KASEI [AK4645] E x a m p le : FS3-0 bits (Addr:05H, D5&D2-0) 0,000 P L L M a s te r M o d e S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D V O L C b it = “ 1 ” ( d e fa u lt ) D ig it a l V o lu m e L e v e l: − 8 d B B a s s B o o s t L e v e l: M id d le D e -e m p h a s e s re s p o n s e : O F F S o f t M u t e T im e : 2 5 6 /f s 1,111 (1) ( 1 ) A d d r : 0 5 H , D a ta : 2 7 H DACH bit (2) (Addr:0FH, D0) (13) ( 2 ) A d d r : 0 F H , D a ta 0 9 H BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 00 10 00 (3) E1H (4 ) A d d r:0 9 H & 0 C H , D a ta 9 1 H 91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (3 ) A d d r:0 E H , D a ta 1 9 H (12) ( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H 18H 28H ( 6 ) A d d r : 0 0 H , D a ta 6 4 H (5) PMDAC bit ( 7 ) A d d r : 0 1 H , D a ta 3 9 H (Addr:00H, D2) (6) (11) ( 8 ) A d d r : 0 1 H , D a ta 7 9 H PMMIN bit P la y b a c k (Addr:00H, D5) ( 9 ) A d d r : 0 1 H , D a ta 3 9 H PMHPL/R bits (7) (10) (Addr:01H, D5-4) HPMTN bit ( 1 0 ) A d d r :0 1 H , D a t a 0 9 H (8) (9) (Addr:01H, D6) ( 1 1 ) A d d r :0 0 H , D a t a 4 0 H ( 1 2 ) A d d r :0 E H , D a t a 1 1 H HPL/R pins Normal Output ( 1 3 ) A d d r :0 F H , D a t a 0 8 H Figure 81. Headphone-Amp Output Sequence < > (1) (FS3-0 bits) PLL PLL (5) DAC (2) DAC Æ HP-Amp : DACH bit = “0” → “1” (3) (BST1-0 bits) (4) ( 09H&0CH) PMADL = PMADR bits = “0” IVL7-0 = IVR7-0 bits = “91H”(0dB) (5) ( 0AH&0DH) DVOLC bit = “1”(default) DVL7-0bits(0AH) Lch Rch DAC Default (0dB) (6) DAC MIN-Amp : PMDAC = PMMIN bits = “0” → “1” (1059/fs=24ms@fs=44.1kHz) DAC 2’s “0” DAC (25/fs =0.5ms@fs=44.1kHz) DAC PMADL bit PMADR bit “1” DAC ALC bit = “1” (1059/fs = 24ms @fs=44.1kHz) ALC (ALC IVL/R7-0 bits ) ALC IVL/R7-0 bits (7) : PMHPL = PMHPR bits = “0” → “1” HVSS (8) : HPMTN bit = “0” → “1” MUTET pin HVDD MUTET pin C = 1µF, HVDD=3.3V τr =100ms(typ), 250ms(max) (9) : HPMTN bit = “1” → “0” MUTET pin HVDD MUTET pin C = 1µF, HVDD=3.3V τf =100ms(typ), 250ms(max) HVSS HVSS 2 (10) : PMHPL = PMHPR bits = “1” → “0” (11) DAC MIN-Amp : PMDAC = PMMIN bits = “1” → “0” (12) OFF: BST1-0 bits = “00” (13) DAC Æ HP-Amp Disable: DACH bit = “1” → “0” MS0543-J-00 2006/09 - 91 - ASAHI KASEI [AK4645] Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB LOVL=MINL bits = “0” 1,111 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H 28H (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (5) (7) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMMIN bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H LOUT pin ROUT pin >300 ms Normal Output (11) Addr:03H, Data:00H Figure 82. Stereo Lineout Sequence < > (1) (FS3-0 bits) PLL PLL (5) DAC (2) DAC Æ : DACL bit = “0” Æ “1” (3) ( 09H&0CH) PMADL = PMADR bits = “0” IVL7-0 = IVR7-0 bits = “91H”(0dB) (4) ( 0AH&0DH) DVOLC bit = “1”(default) DVL7-0bits(0AH) Lch Rch DAC Default (0dB) (5) : LOPS bit = “0” Æ “1” (6) DAC, MIN-Amp : PMDAC = PMMIN = PMLO bits = “0” → “1” (1059/fs=24ms@fs=44.1kHz) DAC 2’s “0” DAC (25/fs=0.5ms@fs=44.1kHz) DAC PMADL bit PMADR bit “1” DAC ALC bit = “1” (1059/fs = 24ms @fs=44.1kHz) ALC (ALC IVL/R7-0 bits ) ALC IVL/R7-0 bits PMLO bit = “1” LOUT, ROUT pins C = 1µF, AVDD=3.3V max. 300ms (7) : LOPS bit = “1” Æ “0” LOUT, ROUT pins LOUT, ROUT pins : LOPS bit: “0” Æ “1” : PMDAC = PMMIN = PMLO bits = “1” → “0” C = 1µF, AVDD=3.3V max. 300ms (8) (9) DAC, MIN-Amp LOUT, ROUT pins (10) DAC Æ (11) LOUT, ROUT pins Disable: DACL bit = “1” Æ “0” : LOPS bit = “1” Æ “0” MS0543-J-00 2006/09 - 92 - ASAHI KASEI [AK4645] ADC DAC 1. PLL Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit "1" or "0" (1) (2) Addr:01H, Data:08H (Addr:01H, D1) (3) External MCKI Input (3) Stop an external MCKI Figure 83. Clock Stopping Sequence (1) < > (1) PLL (2) MCKO (3) : PMPLL bit = “1” → “0” : MCKO bit = “1” → “0” 2. PLL PLL (LRCK, BICK pin) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) External BICK Input (1) Addr:01H, Data:00H (2) External LRCK Input (2) Stop the external clocks Figure 84. Clock Stopping Sequence (2) < > (1) PLL (2) 3. PLL : PMPLL bit = “1” → “0” (MCKI pin) Example (1) Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz PMPLL bit (Addr:01H, D0) (1) MCKO bit (1) Addr:01H, Data:00H (Addr:01H, D1) (2) External MCKI Input (2) Stop the external clocks Figure 85. Clock Stopping Sequence (3) < > (1) PLL MCKO (2) : PMPLL bit = “1” → “0” : MCKO bit = “1” → “0” MS0543-J-00 2006/09 - 93 - ASAHI KASEI [AK4645] 4. (1) External MCKI Input Example (1) External BICK Input External LRCK Input Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) (1) Stop the external clocks Figure 86. Clock Stopping Sequence (4) < > (1) 5. (1) External MCKI Input Example BICK Output "H" or "L" LRCK Output "H" or "L" Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) Stop the external MCKI Figure 87. Clock Stopping Sequence (5) < > (1) MCKI BICK LRCK “H” “L” 20µA) PMVCM bit = “0” PDN pin = “L” MS0543-J-00 (typ. (typ. 1µA) 2006/09 - 94 - ASAHI KASEI [AK4645] 32pin QFN (Unit: mm) 5.00 ± 0.10 0.40 ± 0.10 4.75 ± 0.10 24 17 16 4.75 ± 0.10 B 3.5 5.00 ± 0.10 25 9 32 1 1 3.5 0.50 +0.07 -0.05 32 C0.42 8 A 0.23 Exposed Pad 0.85 ± 0.05 0.10 M AB 0.08 C : 0.04 0.01+- 0.01 0.20 C (Exposed Pad) : : : MS0543-J-00 2006/09 - 95 - ASAHI KASEI [AK4645] AKM AK4645 XXXXX 1 XXXXX : Date code identifier (5 Date (YY/MM/DD) 06/09/14 Revision 00 Reason Page ) Contents • • • • • • MS0543-J-00 2006/09 - 96 -