データシート

[AK4646]
AK4646
Stereo CODEC with MIC/SPK-AMP
AK4646
Level Control)
16bit
CODEC
ALC(Auto
32pin QFN(5mm x5mm:AK4646EN, 4mm x 4mm:AK4646EZ)
2∼3
1.
2.
•
(
or
)
•
•
(+32dB/+29dB/+26dB/+23dB/+20dB/+17dB/+10dB/0dB)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• ADC
: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB)
S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)
•
•5
•
•
(tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
•
(0dB ∼ −18dB, 6dB Step)
•
•
: S/(N+D): 88dB, S/N: 92dB
•
- SPK-AMP
: S/(N+D): 60dB@150mW, S/N: 90dB
- BTL
: 400mW@8Ω (SVDD=3.3V)
•
:
3.
4.
:
(1) PLL
•
(2)
5.
•
: 12MHz, 13.5MHz,24MHz,27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
: 256fs, 512fs or 1024fs (MCKI pin)
: 32fs/64fs/128fs/256fs
MS0557-J-06
2011/06
-1-
[AK4646]
6.
7.
8.
9.
10.
11.
12.
13.
14.
:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
μP
:3
: MSB First, 2’s compliment
• ADC : 16bit
, I2S
• DAC : 16bit
, 16bit
, 16-24bit I2S
Ta = −30 ∼ 85°C
:
• AVDD : 2.2 ∼ 3.6V (typ. 3.3V)
• DVDD : 1.6 ∼ 3.6V (typ. 3.3V)
• SVDD : 2.2 ∼ 4.0 V (typ. 3.3V)
: 19 mA
: 32pin QFN, 5mm x 5mm, 0.5mm pitch(AK4646EN)
32pin QFN, 4mm x 4mm, 0.4mm pitch(AK4646EZ)
AK4642EN/AK4643EN
/
(AK4646EN)
■
AVDD
AVSS
VCOM
DVDD
DVSS
PMMP
MPWR
CCLK
CDTIO
PMADL or PMADR
RIN1
PDN
MIC-Amp
LIN2
External
MIC
Control
Register
PMADL
LIN1
Internal
MIC
CSN
MIC Power
Supply
A/D
HPF
PMADR
PMADCL
or
PMADCR
or
PMDAC
RIN2
BICK
HPF
LRCK
LPF
SDTO
Stereo
Separation
Audio
I/F
SDTI
5 Band
EQ
PMLO
LOUT
ALC
Line Out
ROUT
PMDAC
D/A
PMSPK
DATT DEM
SMUTE
MCKO
PMPLL
SPP
Speaker
SPN
PLL
MCKI
VCOC
PMBP
SVDD
SVSS
MIN
Figure 1.
MS0557-J-06
2011/06
-2-
[AK4646]
■
−30 ∼ +85°C
−30 ∼ +85°C
AK4646
AK4646EN
AK4646EZ
AKD4646
32pin QFN (0.5mm pitch)
32pin QFN (0.4mm pitch)
■
NC
NC
SVSS
SVDD
SPP
SPN
MCKO
MCKI
24
23
22
21
20
19
18
17
AK4646EN/EZ
LRCK
RIN2 / IN2−
29
Top View
12
SDTO
LIN2 / IN2+
30
11
SDTI
LIN1 / IN1−
31
10
CDTIO
RIN1 / IN1+
32
9
CCLK
8
13
CSN
AK4646
7
28
PDN
MIN
6
BICK
NC
14
5
27
VCOC
LOUT
4
DVDD
AVDD
15
3
26
AVSS
ROUT
2
DVSS
VCOM
16
1
25
MPWR
NC
MS0557-J-06
2011/06
-3-
[AK4646]
■ AK4642/AK4643
1.
AK4642
AK4643
MIC-Amp
2.6V ∼ 3.6V
2.6V ∼ 3.6V
2.6V ∼ 5.25V (HVDD)
0.75 x AVDD
0dB/+20dB/+26dB/+32dB
HPF / LPF
1
ALC
128/fs ~ 1024/fs
AVDD
DVDD
Power Supply for SPK-Amp
AK4646
2.2V ∼ 3.6V
1.6V ∼ 3.6V
2.2V ∼ 4.0V (SVDD)
0.8 x AVDD
0dB/+10dB/+17dB/+20dB/
+23dB/+26dB/+29dB/
+32dB
HPF : 2 , LPF : 1
5
128/fs ~ 16384/fs
128/fs ~ 16384/fs
ALC
+12dB ∼ -115dB, 0.5dB Step
+36dB ∼ -54dB, 0.375dB Step
(Note 1)
0dB ∼ -18dB, 6dB Step
[email protected]
1 Mono
2 Stereo
8.5Vpp@SVDD=5V
[email protected]
1 Mono
2 Stereo
6.33Vpp@SVDD=3.8V
Headphone-Amp
Receiver-Amp
SPK-Amp
ADC
1.2W@5V
2 Stereo
3 Stereo
SPK-Amp
I/F
I/F
DSP Mode
EXT Master Mode
Master Clock
PLL Mode
Note 1. ALC
3
(Read
)
I2C
3
11.2896MHz, 12MHz, 12.288MHz, 13.5MHz
24MHz, 27MHz
(Read
)
12MHz, 13.5MHz, 24MHz,
27MHz
ALC
MS0557-J-06
2011/06
-4-
[AK4646]
No.
1
Pin Name
MPWR
I/O
O
2
VCOM
O
3
4
AVSS
AVDD
-
5
VCOC
O
6
NC
-
7
PDN
I
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CSN
CCLK
CDTIO
SDTI
SDTO
LRCK
BICK
DVDD
DVSS
MCKI
MCKO
SPN
SPP
SVDD
SVSS
29
30
31
32
NC
ROUT
LOUT
MIN
RIN2
IN2−
LIN2
IN2+
LIN1
IN1−
RIN1
IN1+
Note 2.
Function
, 0.5 x AVDD
ADC
DAC
PLL
AVSS
No Connect
“H”:
“L”:
I
I
I/O
I
O
I/O
I/O
I
O
O
O
-
No Connect
O
Rch
O
Lch
I
I
Rch
2
I
2
I
Lch
2
I
2
I
Lch
1
I
1
I
Rch
1
I
1
(MIN, LIN1, RIN1, LIN2, RIN2)
MS0557-J-06
(MDIF2 bit = “0”,
(MDIF2 bit = “1”,
(MDIF2 bit = “0”,
(MDIF2 bit = “1”,
(MDIF1 bit = “0”,
(MDIF1 bit = “1”,
(MDIF1 bit = “0”,
(MDIF1 bit = “1”,
)
)
)
)
)
)
)
)
2011/06
-5-
[AK4646]
■
Analog
Digital
MPWR, VCOC, SPN, SPP, ROUT, LOUT, MIN,
RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+
MCKO
MCKI
MS0557-J-06
DVSS
2011/06
-6-
[AK4646]
(AVSS=DVSS=SVSS=0V; Note 3)
Parameter
Symbol
Power Supplies: Analog
AVDD
Digital
DVDD
Speaker-Amp
SVDD
|AVSS – DVSS|
(Note 4)
ΔGND1
|AVSS – SVSS|
(Note 4)
ΔGND2
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 5)
VINA
Digital Input Voltage (Note 6)
VIND
AK4646EN
Ta
Ambient Temperature
(Note 7)
Ta
(powered applied)
AK4646EZ
Ta
(Note 8)
Storage Temperature
Tstg
Maximum Power Dissipation (Note 9)
Pd1
Note 3.
Note 4. AVSS DVSS, SVSS
Note 5. MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins
Note 6. PDN, CSN, CCLK, CDTIO, SDTI, LRCK, BICK, MCKI pins
Note 7.
(Exposed Pad)
Note 8.
(Exposed Pad)
Note 9.
100%
min
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−30
−30
−65
-
max
4.6
4.6
4.6
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
85
85
70
150
450
Units
V
V
V
V
V
mA
V
V
°C
°C
°C
°C
mW
AK4646
:
(AVSS=DVSS=SVSS=0V; Note 3)
Parameter
Power
Analog
Supplies
(Note 10) Digital
SPK-Amp (Note 11)
Difference
Symbol
min
typ
Max
Units
AVDD
2.2
3.3
3.6
V
DVDD
SVDD
DVDD−AVDD
DVDD−SVDD
AVDD−SVDD
1.6
2.2
-
3.3
3.3
-
3.6
4.0
+0.3
+0.3
+0.8
V
V
V
V
V
Note 3.
Note 10. AVDD, DVDD, SVDD
AVDD,
SVDD ON
DVDD OFF
DVDD
DVDD
ON
PDN pin = “L”
Note 11. 8Ω
SVDD = 2.2 ∼ 3.6V
AVDD, SVDD
OFF
OFF
:
MS0557-J-06
2011/06
-7-
[AK4646]
(Ta=25°C; AVDD=DVDD=SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs)
Input Resistance
20
30
40
kΩ
MGAIN2-0 bits = “000”
0
dB
MGAIN2-0 bits = “001”
+20
dB
Gain
MGAIN2-0 bits = “010”
+26
dB
MGAIN2-0 bits = “011”
+32
dB
MGAIN2-0 bits = “100”
+10
dB
MGAIN2-0 bits = “101”
+17
dB
MGAIN2-0 bits = “110”
+23
dB
MGAIN2-0 bits = “111”
+29
dB
MIC Amplifier: IN1+, IN1−, IN2+, IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 12)
MGAIN2-0 bits = “001”
0.242
Vpp
MGAIN2-0 bits = “010”
0.121
Vpp
MGAIN2-0 bits = “011”
0.061
Vpp
MGAIN2-0 bits = “100”
0.765
Vpp
MGAIN2-0 bits = “101”
0.342
Vpp
MGAIN2-0 bits = “110”
0.171
Vpp
MGAIN2-0 bits = “111”
0.086
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 13)
2.38
2.64
2.90
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 15)
0.178
0.210
0.242
Vpp
Input Voltage (Note 14)
1.78
2.10
2.42
Vpp
(Note 16)
(Note 15)
73
83
dBFS
S/(N+D) (−1dBFS)
88
dBFS
(Note 16)
(Note 15)
76
86
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 16)
(Note 15)
76
86
dB
S/N
(A-weighted)
95
dB
(Note 16)
(Note 15)
75
90
dB
Interchannel Isolation
100
dB
(Note 16)
(Note 15)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 16)
Note 12.
AC
MGAIN2-0 bits = “000”
IN1+, IN1−, IN2+, IN2− pin
AVDD
Vin = |(IN1/2+) − (IN1/2−)| = 0.073 x AVDD
(max)@MGAIN2-0 bits = “001”, 0.037 x AVDD (max) @MGAIN2-0 bits = “010”, 0.018 x AVDD
(max)@MGAIN2-0 bits = “011”, 0.232 x AVDD (max) @MGAIN2-0 bits = “100”, 0.104 x AVDD
(max)@MGAIN2-0 bits = “101”, 0.052 x AVDD (max )@MGAIN2-0 bits = “110”, 0.026 x AVDD
(max)@MGAIN2-0 bits = “111”.
Note 13.
AVDD
Vout = 0.8 x AVDD (typ)
Note 14.
AVDD
Vin = 0.0636 x AVDD (typ) @MGAIN2-0 bits = “001” (+20dB), Vin =
0.636 x AVDD (typ) @MGAIN2-0 bits = “000” (0dB)
Note 15. MGAIN2-0 bits = “001” (+20dB)
Note 16. MGAIN2-0 bits = “000” (0dB)
MS0557-J-06
2011/06
-8-
[AK4646]
min
typ
max
Units
Parameter
DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, OVOL=0dB, DVOL=0dB,
LOVL1-0 bit = “00”, RL=10kΩ
Output Voltage (Note 17)
LOVL1-0 bit = “00”
1.78
1.98
2.18
Vpp
LOVL1-0 bit = “01”
2.25
2.50
2.75
Vpp
S/(N+D) (−3dBFS)
78
88
dBFS
S/N
(A-weighted)
82
92
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.1
0.8
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, OVOL=0dB, RL=8Ω, BTL, SVDD=3.3V
Output Voltage (Note 18)
3.18
Vpp
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
3.20
4.00
4.80
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
1.79
Vrms
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/(N+D)
60
dB
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
20
50
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
20
dB
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/N (A-weighted)
80
90
dB
Load Resistance
8
Ω
Load Capacitance
30
pF
Note 17.
AVDD
Vout = 0.6 x AVDD (typ) @LOVL bit = “0”.
Note 18.
AVDD
DAC -0.5dBFS
Full-differential
Vout = 0.96 x AVDD (typ) @SPKG1-0 bits = “00”,
1.21 x AVDD (typ) @SPKG1-0 bits = “01”, 1.52 x AVDD (typ )@SPKG1-0 bits = “10”, 1.92 x AVDD (typ)
@SPKG1-0 bits = “11”
MS0557-J-06
2011/06
-9-
[AK4646]
min
typ
max
Units
Parameter
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, CL=3μF, Rserial=10Ω
x 2, BTL, SVDD=3.8V
Output Voltage
SPKG1-0 bits = “11”, -0.5dBFS
6.33
Vpp
(Note 18)
S/(N+D)
SPKG1-0 bits = “11”, -0.5dBFS
60
dB
(Note 19)
S/N
(A-weighted)
90
dB
Load Impedance (Note 20)
50
Ω
Load Capacitance (Note 20)
3
μF
Mono Input: MIN pin (External Input Resistance=20kΩ)
Maximum Input Voltage (Note 21)
1.98
Vpp
Gain (Note 22)
MIN Æ LOUT/ROUT LOVL1-0 bit = “00”
-4.5
0
+4.5
dB
LOVL1-0 bit = “01”
+2
dB
LOVL1-0 bit = “10”
+4
dB
LOVL1-0 bit = “11”
+6
dB
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
+0.1
+4.6
+9.1
dB
ALC bit = “0”, SPKG1-0 bits = “01”
+6.6
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+8.6
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+10.6
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+6.6
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+8.6
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+10.6
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+12.6
dB
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up (Note 23)
AVDD+DVDD
15
23
mA
SVDD (No Output)
4
12
mA
Power Down (PDN pin = “L”) (Note 24)
AVDD+DVDD+SVDD
1
100
μA
Note 19.
SPP/SPN pins
Note 20. Figure 34
Load Impedance
1kHz
Load Capacitance
SPP, SPN pin
10Ω
Note 21.
AVDD
(Rin)
Vin = 0.636 x AVDD x Rin / 20kΩ (typ).
Note 22.
Note 23. PLL Master Mode (MCKI=12MHz)
PMADL = PMADR = PMDAC = PMLO = PMSPK = PMVCM =
PMPLL = MCKO = PMBP = PMMP = M/S bits = “1”
MPWR pin
0mA
AVDD= 10mA (typ), DVDD=5mA (typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)
Note 24.
DVDD
DVSS
MS0557-J-06
: AVDD=10mA (typ), DVDD=4mA (typ).
2011/06
- 10 -
[AK4646]
(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
Passband (Note 25)
PB
0
17.3
±0.16dB
19.4
−0.66dB
19.9
−1.1dB
22.1
−6.9dB
Stopband
SB
26.1
Passband Ripple
PR
±0.1
Stopband Attenuation
SA
73
Group Delay (Note 26)
GD
19
Group Delay Distortion
0
ΔGD
DAC Digital Filter (LPF):
Passband (Note 25)
PB
0
20.0
±0.05dB
22.05
−6.0dB
Stopband
SB
24.1
Passband Ripple
PR
±0.02
Stopband Attenuation
SA
54
Group Delay (Note 26)
GD
20
DAC Digital Filter (LPF) + SCF:
FR
Frequency Response: 0 ∼ 20.0kHz
±1.0
Note 25.
fs (
)
PB=20.0kHz (@−1.0dB) 0.454 x fs
(ADC)
1kHz
Note 26.
ADC
DAC
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
kHz
kHz
kHz
dB
dB
1/fs
dB
16
16
DC
(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V)
Parameter
Symbol
min
70%DVDD
VIH
High-Level Input Voltage
(DVDD ≥ 2.2V)
80%DVDD
(DVDD < 2.2V)
VIL
Low-Level Input Voltage
(DVDD ≥ 2.2V)
(DVDD < 2.2V)
High-Level Output Voltage
(Iout=−80μA)
VOH
DVDD−0.4
Low-Level Output Voltage
(Iout= 80μA)
VOL
Input Leakage Current
Iin
-
MS0557-J-06
typ
-
max
30%DVDD
20%DVDD
0.4
±10
Units
V
V
V
V
V
V
μA
2011/06
- 11 -
[AK4646]
(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; CL=20pF)
Parameter
Symbol
min
typ
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
12
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
Duty Cycle
Duty
50
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
BCKO bit = “1”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
12
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Input Timing
Frequency
fs
7.35
Duty
Duty
45
BICK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS0557-J-06
max
Units
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
-
kHz
%
-
ns
ns
%
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
55
kHz
%
1/(32fs)
-
ns
ns
ns
2011/06
- 12 -
[AK4646]
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
Duty Cycle
Duty
BICK Input Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0557-J-06
min
typ
max
Units
7.35
45
-
48
55
kHz
%
1/(64fs)
240
240
-
1/(32fs)
-
ns
ns
ns
7.35
45
-
48
55
kHz
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
45
-
48
26
13
55
kHz
kHz
kHz
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
50
48
-
kHz
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2011/06
- 13 -
[AK4646]
Parameter
Symbol
Audio Interface Timing
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 27)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 27)
tBLR
BICK “↑” to LRCK Edge (Note 27)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Control Interface Timing
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDTIO Setup Time
tCDS
CDTIO Hold Time
tCDH
CSN “H” Time
tCSW
tCSS
CSN Edge to CCLK “↑” (Note 28)
tCSH
CCLK “↑” to CSN Edge (Note 28)
tDCD
CCLK “↓” to CDTIO (at Read Command)
tCCZ
CSN “↑” to CDTIO (Hi-Z) (at Read Command)
Power-down & Reset Timing
PDN Pulse Width
(Note 29)
tPD
tPDV
PMADL or PMADR “↑” to SDTO valid (Note 30)
Note 27.
LRCK
BICK “↑”
Note 28.
CSN
CCLK CCLK “↑”
Note 29. AK4646 PDN pin = “L”
Note 30. PMADL bit
PMADR bit
LRCK
MS0557-J-06
min
typ
max
Units
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
200
80
80
40
40
150
50
50
-
-
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
-
1059
-
ns
1/fs
“↑”
2011/06
- 14 -
[AK4646]
■
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
1/fMCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Note 31. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL/EXT Master mode)
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tDLR
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode)
MS0557-J-06
2011/06
- 15 -
[AK4646]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 5. Clock Timing (EXT Slave mode)
MS0557-J-06
2011/06
- 16 -
[AK4646]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tBSD
tLRD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Slave mode)
VIH
CSN
VIL
tCSH
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTIO
C1
C0
R/W
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTIO
D2
D1
D0
VIL
Figure 8. WRITE Data Input Timing
MS0557-J-06
2011/06
- 17 -
[AK4646]
VIH
CSN
VIL
VIH
CCLK
Clock, H or L
tCCZ
tDCD
CDTIO
D3
VIL
D2
D1
D0
Hi-Z
50%
DVDD
Figure 9. Read Data Output Timing
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 10. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 11. Power Down & Reset Timing 2
MS0557-J-06
2011/06
- 18 -
[AK4646]
■
I/F
5
(Table 1, Table 2)
Mode
PLL Master Mode (Note 32)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK
pin)
EXT Slave Mode
EXT Master Mode
Note 32. PLL Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
Table 4
Figure
Figure 12
1
0
Table 4
Figure 13
1
0
Table 4
Figure 14
Figure 15
0
0
x
0
1
x
M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”
Figure 16
Figure 17
MCKO pin
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
PS1-0 bits
MCKI pin
PLL3-0 bits
“L”
PS1-0 bits
PLL3-0 bits
GND
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK
pin)
0
“L”
EXT Slave Mode
0
“L”
EXT Master Mode
0
“L”
FS3-0 bits
FS1-0 bits
BICK pin
Output
(BCKO bit
)
Input
(BCKO bit
)
Input
(BCKO bit
)
Input
(≥ 32fs)
Output
(BCKO bit
)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Note 33. PMVCM bit = M/S bit = “1”
MCKI
PMDAC bit = PMADL bit = PMADR bit = “0”
LRCK
BICK
Table 2. Clock pins state in Clock Mode
■
M/S bit
(PDN pin = “L”)
AK4646
M/S bit
“1”
“0”
“1”
M/S bit “1”
AK4646 LRCK, BICK pin
AK4646
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS0557-J-06
(default)
2011/06
- 19 -
[AK4646]
■ PLL
PMPLL bit = “1”
PLL
PLL FS3-0 bit, PLL3-0 bit
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
PLL
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
1
2
0
0
0
0
0
0
0
0
1
0
1
0
LRCK pin
N/A
BICK pin
1fs
32fs
3
0
0
1
1
BICK pin
64fs
6
7
12
13
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
Others
Others
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
10n
10k
10n
10k
10n
10k
10n
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
PLL
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
(default)
2) PLL Mode
PLL2 bit = “1” (MCKI
)
Table 5
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
PLL2 bit = “0”
(Table 6)
(LRCK or BICK
FS2 bit
FS3, FS2 bit
Sampling Frequency
Range
0
0
0
Don’t care Don’t care
(default)
7.35kHz ≤ fs ≤ 12kHz
0
1
1
Don’t care Don’t care
12kHz < fs ≤ 24kHz
1
0
2
Don’t care Don’t care
24kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
Mode
FS3 bit
)
FS1 bit
FS0 bit
MS0557-J-06
2011/06
- 20 -
[AK4646]
■ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
bit = “1”
MCKO pin
PLL
PMPLL bit = “0” Æ “1”
MCKO pin
“L”
(Table 7)
BICK
LRCK
PLL
BICK
“L”
1fs
LRCK “L”
MCKO bit = “0”
1
PMPLL bit = “0”
LRCK
MCKO
LRCK, BICK
BICK,
“L”
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L”
Output
PLL Unlock (
)
“L” Output
1fs Output
Table 9
Table 10
PLL Lock
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PMPLL bit = “0” Æ “1”
PLL
PLL
DACL, DACS bits “0”
PLL
ADC
MCKO pin
DAC
MCKO
Table 9
DAC
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
Output
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0557-J-06
2011/06
- 21 -
[AK4646]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
12MHz ,13.5MHz, 24MHz or 27MHz
MCKO bit
ON/OFF
BICK
(MCKO)
BCKO bit
PLL
PS1-0 bit (Table 9)
32fs or 64fs
MCKO, BICK, LRCK
(Table 10)
12MHz, 13.5MHz, 24MHz, 27MHz
DSP or μP
AK4646
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 12. PLL Master Mode
Mode
0
1
2
3
PS1 bit
0
0
1
1
Table 9. MCKO
PS0 bit
0
1
0
1
(PLL
MCKO pin
256fs
(default)
128fs
64fs
32fs
, MCKO bit = “1”)
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0557-J-06
2011/06
- 22 -
[AK4646]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
PLL
a) PLL
: MCKI pin
MCKO
BICK, LRCK
bit
AK4646
(Table 4)
PLL3-0 bit
MCKO LRCK
(MCKO pin) PS1-0 bit (Table 9)
FS3-0 bit
ON/OFF
MCKO
(Table 5)
12MHz, 13.5MHz, 24MHz, 27MHz
AK4646
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 13. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0557-J-06
2011/06
- 23 -
[AK4646]
b) PLL
FS3-0 bit
: BICK or LRCK pin
7.35kHz ∼ 48kHz
(Table 6)
AK4646
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4646
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15 PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”)
MS0557-J-06
2011/06
- 24 -
[AK4646]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit “0”
ADC, DAC
(EXT Mode)
MCKI pin
PLL
CODEC
I/F
MCKI (256fs, 512fs or 1024fs), BICK (≥32fs), LRCK (fs)
MCKI
MCKI
FS1-0 bit
LRCK
(Table 11)
Mode
0
1
2
3
Others
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
512fs
7.35kHz ∼ 26kHz
Don’t care
1
1
256fs
7.35kHz ∼ 48kHz
Others
N/A
N/A
Table 11. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 12 DAC
(default)
MCKI
LOUT/ROUT pin
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”
AK4646
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16. EXT Slave Mode
MS0557-J-06
2011/06
- 25 -
[AK4646]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
PMPLL bit = “0”
M/S bit = “1”
MCKI pin
PLL
(256fs, 512fs or 1024fs)
MCKI
Mode
0
1
2
3
(EXT Master Mode)
ADC, DAC
MCKI
FS1-0 bit
(Table 13)
MCKI Input
Frequency
Don’t care
0
0
256fs
Don’t care
0
1
1024fs
Don’t care
1
0
512fs
Don’t care
1
1
256fs
Table 13. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
FS3-2 bits
FS1 bit
FS0 bit
DAC
S/N
S/N
Table 14 DAC
Sampling Frequency
Range
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 48kHz
7.35kHz ∼ 26kHz
MCKI
(default)
MCKI
LOUT/ROUT pin
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 14. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
ADC
DAC
MCKI
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
MCKI
MCKI
(PMADL=PMADR=PMDAC bits =
“0”)
AK4646
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 17. EXT Master Mode
BCKO bit
BICK
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
MS0557-J-06
2011/06
- 26 -
[AK4646]
■
PDN pin = “L”
PMADL = PMADR = “0”
PDN pin = “L”
AK4646
PMADL bit
2’s
“0”
DAC
(PMDAC bit = “0” → “1”)
67/fs = 1.52ms@fs=44.1kHz
(Note)
150ns
PMADR bit “0” → “1”
1059/fs=24ms@fs=44.1kHz
ADC
ADC
ADC
67/fs = 1.52ms@fs=44.1kHz
HPF
ADC
ADC
■
3
(Table 16)
“↓“
SDTI
Mode
0
1
2
3
ADC
“−1”
DIF1-0 bit
MSB
2’s
LRCK BICK
BICK “↑”
DIF1 bit
0
0
1
1
16bit
8bit
“–256”
DIF0 bit
0
1
0
1
SDTO
SDTO (ADC)
N/A
SDTI (DAC)
N/A
I2S
I2S
Table 16. Audio Interface Format
8bit
“−1”
8bit
8bit
BICK
N/A
≥ 32fs
≥ 32fs
≥ 32fs
16bit
“−1”
Figure
Figure 18
Figure 19
Figure 20
BICK
(default)
16bit
16bit
DAC
16bit
(128)
MS0557-J-06
2011/06
- 27 -
[AK4646]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 1
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 19. Mode 2
MS0557-J-06
2011/06
- 28 -
[AK4646]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 20. Mode 3
■
PMADL, PMADR bits
ADC
PMADL bit
0
0
1
1
ADC
PMADL bit = PMADR bit = “0”
PMADR bit
0
1
0
1
Table 17.
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
MS0557-J-06
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
(default)
2011/06
- 29 -
[AK4646]
■
AK4646
RIN1/RIN2
MDIF1, MDIF2 bit = “0”
INL, INR bit
LIN1/LIN2,
MDIF1, MDIF2 bit = “1”
LIN1, RIN1, LIN2, RIN2 pin
(Figure 22)
IN1−, IN1+, IN2+, IN2− pin
MDIF1 bit
MDIF2 bit
INL bit
INR bit
Lch
0
LIN1
0
1
LIN1
0
0
LIN2
0
1
1
LIN2
0
x
LIN1(Note 34)
1
1
x
N/A
0
N/A
0
x
1
1
IN1+/−
1
x
x
IN1+/−
Note 34. MDIF1 bit = “0”, MDIF2 bit = “1”, INL bit = “0”
RIN1 pin
Note 35. MDIF1 bit = “1”, MDIF2 bit = “0”, INR bit = “1”
LIN2 pin
Table 18. MIC/Line In Path Select
Rch
RIN1
RIN2
RIN1
RIN2
IN2+/−
N/A
N/A
RIN2(Note 35)
IN2+/−
(default)
AK4646
INL bit
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
INR bit
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
Figure 21.
AK4646
MPWR pin
R1
1k
MIC-Amp
INx− pin
INx+ pin
R2
1k
Figure 22.
(MDIF1/2 bits = “1”)
MS0557-J-06
2011/06
- 30 -
[AK4646]
■
MGAIN2-0 bit
AK4646
(Table 19)
typ. 30kΩ
MGAIN2 bit
0
0
0
0
1
1
1
1
MGAIN1 bit MGAIN0 bit
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table 19.
Input Gain
0dB
+20dB
+26dB
+32dB
+10dB
+17dB
+23dB
+29dB
(default)
■
PMMP bit = “1”
(typ)
pin
MPWR pin
min. 0.5kΩ
(0.8 x AVDD)V
min. 2kΩ
MPWR
2
(Figure 23)
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 20.
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 23. MIC Block Circuit
MS0557-J-06
2011/06
- 31 -
[AK4646]
■
Figure 24
Lch
DAFIL bit = “0”
HPF ~ ALC
ADC
DAFIL bit = “1”
HPF ~ ALC
(Figure 24 ~ Figure 27 ,Table 21) DAFIL bit = “1”
ADC
SDTO pin
“L”
Rch
ADC
Lch
Rch
PMADCL/R bit
SDTI
ADC
HPFAD bit
1st Order
HPF
PMADL bit
PMADR bit
PMDAC bit
DAFIL bit
HPF bit
LPF bit
1st Order
HPF
1st Order
LPF
FIL3 bit
Stereo
Separation
EQ0 bit
GN1-0 bits
Gain
Compensation
EQ5-1 bit
Digital
Programmable
Filter Block
SW1
“1”
“0”
ALC1/2 bits
5 Band
EQ
ALC
(Volume)
“1”
“0”
SW2
PMDAC bit
DATT
SDTO
SMUTE
DAC
SW1, SW2: Table 21
ADC: “
”
ADC
Digital Filter (LPF)
DAC: “
”
DAC
Digital Filter (LPF)
HPF: High Pass Filter.
(“Digital Programmable Filter”
LPF : Low Pass Filter (“Digital Programmable Filter”
)
Stereo Separation :
(“Digital Programmable Filter”
)
Gain Compensation :
EQ
Gain
(“Digital Programmable Filter”
)
(7) 5 Band EQ: Equalizer
(“Digital Programmable Filter”
(8) Volume: ALC
(“
”
“ALC”
(9) DATT:
4
(“
2”
(10) SMUTE:
Figure 24.
(1)
(2)
(3)
(4)
(5)
(6)
MS0557-J-06
)
)
)
)
2011/06
- 32 -
[AK4646]
PMADL
PMADR
PMDAC
DAFIL
bit
1
1
0
0
x
1
1
0
bit
1
0
1
0
x
1
0
1
bit
x
x
x
1
1
1
1
1
bit
LOOP
bit
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
Figure 24
SW
SW1
SW2
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
Figure
Figure 25
Figure 26
Figure 27
(x: Don’t Care)
Table 21.
LPF bit, HPF bit, FIL3 bit, EQ0
bit, EQ1 bit, EQ2 bit, EQ3 bit, EQ4 bit, EQ5 bit, ACL1 bit, ALC2 bit
ADC
DAC
2nd Order
1st Order
HPF
LPF
SMUTE
Stereo
Separation
1st Order
SMUTE
5 Band
EQ
ALC
(Volume)
(Default)
“0” Data
HPF
DAC
Gain
Compensation
DATT
Figure 25.
ADC
“0”
DATT
ALC
(Volume)
5 Band
EQ
Gain
Compensation
Stereo
Separation
1st Order
1st Order
LPF
HPF
Figure 26.
ADC
DAC
2nd Order
1st Order
HPF
LPF
SMUTE
Stereo
Separation
Gain
Compensation
5 Band
EQ
ALC
(Volume)
DATT
Figure 27.
MS0557-J-06
2011/06
- 33 -
[AK4646]
■ Digital Programmable Filter
(1) High Pass Filter (HPF)
HPF
F1B13-0 bits
2
HPF
0dB
“0”
1
2
HPF bit
HPF
HPF
2
ON/OFF
HPF
HPFAD bit = HPF bit = “0”
F1A13-0 bits
ADC
HPF HPFAD bit
OFF
PMADCL = PMADR = PMDAC bit =
fs:
fc:
(Note 36)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
1 + Bz −1
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
1
LPF
F2A13-0 bits
F2B13-0 bits
LPF OFF
0dB
PMADCL = PMADR = PMDAC bit = “0”
LPF bit
ON/OFF
LPF bit = “0”
fs:
fc:
(Note 36)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
MS0557-J-06
2011/06
- 34 -
[AK4646]
(3)
(FIL3)
F3A13-0, F3B13-0 bits
F3AS bit = “1”
Low Pass Filter (LPF)
OFF
PMADCL = PMADR = PMDAC bit = “0”
1) FIL3
FIL3
FIL3 bit
0dB
3D
F3AS bit = “0”
ON/OFF
High Pass Filter (HPF)
FIL3 bit = “0”
HPF
fs:
fc:
f:
K:
[dB] (0dB ≥ K ≥ -10dB)
(Note 36)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
A = 10K/20 x
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
2) FIL3
1 + Bz −1
LPF
fs:
fc:
f:
K:
[dB] (0dB ≥ K ≥ -10dB)
(Note 36)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
MS0557-J-06
2011/06
- 35 -
[AK4646]
(4)
F
Equalizer (EQ0)
(0dB/+12dB/+24dB)
EQ0
E0A15-0 bits, E0B13-0 bits, E0C15-0 bits
GN1-0 bits (Table 22)
EQ0
EQ0 bit
ON/OFF
EQ0 OFF
0dB
0dB
EQ0
EQ0 bit = “0”
PMADCL = PMADR = PMDAC bit = “0”
fs:
fc1:
fc2:
f:
K:
[dB] (
+12dB
)
(Note 36)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
,
B=
1 − 1 / tan (πfc1/fs)
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 28. EQ0
GN1
GN0
0
0
0
1
1
x
Table 22. Gain
Gain
0dB
(default)
+12dB
+24dB
(x: Don’t care)
MS0557-J-06
2011/06
- 36 -
[AK4646]
(5) 5
Equalizer
Equalizer
5
Equalizer
5
(EQ1, EQ2, EQ3, EQ4, EQ5)
EQ1 bit, EQ2 bit, EQ3 bit, EQ4 bit, EQ5 bit ON/OFF
Equalizer OFF
0dB
EQ1
E1A15-0 bits,
E1B15-0 bits, E1C15-0 bits
EQ2
E2A15-0 bits, E2B15-0 bits, E2C15-0 bits
EQ3
E3A15-0
bits, E3B15-0 bits, E3C15-0 bits
EQ4
E4A15-0 bits, E4B15-0 bits, E4C15-0 bits
EQ5
E5A15-0 bits, E5B15-0 bits, E5C15-0 bits
EQ
EQx bit “0”
PMADCL = PMADR = PMDAC bit = “0”
fs:
fo1 ~ fo5:
fb1 ~ fb5:
K1 ~ K5 :
3dB
( -1 ≤ Kn < 3 )
(Note 36)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
tan (πfbn/fs)
An = Kn x
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
H(z) = 1 + h1(z) + h2(z) + h3(z) + h4(z) + h5(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
fon / fs < 0.497
K(
)
“-1”
Equalizer
2
Note 36. [
X=(
)x2
X
2
(2
)
]
13
(2
)
MSB
MS0557-J-06
2011/06
- 37 -
[AK4646]
■ ALC
ALC
ALC
Lch
Rch
PMADR bit = “1”)
DAFIL bit = “0”
(PMADL bit = PMADR bit = “0”)
DAFIL bit = “1”
ALC1 bit
ALC
ON/OFF
ALC2 bit
Note 37.
VOL
Note 38.
Note 39.
ALC bit
REF
1.
IVL
ADC
Lch
Rch
ALC
(PMADL bit = “1”
ADC
ALC
ON/OFF
IVR
OVL
ALC1 bit
IREF
OVR
ALC2 bit
OREF
ALC
ALC
Lch, Rch
LMAT1-0 bit
L/R
(Table 24)
)
ZELMN bit = “0”(
ZTM1-0 bit
(
: 1/fs)
VOL
1 Step(L/R
ALC bit
LMTH1
0
0
1
1
(Table 25)
) FS
VOL
VOL
(
: 1/fs)
1 step
ALC
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALC1
0
0
1
1
FS
ALC
“0”
LMAT0
L/R
LFST bit = “1”
LMTH0 ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 23. ALC
LMAT1
(Table 23)
VOL
ALC
)
LMAT1-0 bit
ZELMN bit = “1”(
ALC
VOL (L/R
)
ATT
ALC1 Output ALC1 Output
≥ LMTH
≥ FS
0
1
0
1
Table 24. ALC
1
2
2
1
(default)
1
2
4
2
ATT
MS0557-J-06
ALC1 Output
≥ FS + 6dB
ALC1 Output
≥ FS + 12dB
1
2
4
4
(x: Don’t care)
1
2
8
8
(default)
2011/06
- 38 -
[AK4646]
ZTM1
ZTM0
0
0
1
1
0
1
0
1
8kHz
16ms
32ms
64ms
128ms
128/fs
256/fs
512/fs
1024/fs
Table 25. ALC
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
(default)
ALC
2.
WTM2-0
(Table 26)
(Table 23)
ALC
(Table 28)
ZTM1-0
(Table 25)
RGAIN1-0 bit
(Table 27)
VOL (L/R
)
WTM2-0
WTM2-0
ZTM1-0
ALC
ALC
VOL
VOL
VOL
32H
30H
ALC
ALC
ALC
ZTM1-0
RGAIN1-0 bit = “01”(2 steps)
0.75dB (0.375dB x 2)
VOL
ALC
(REF
)
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
FR bit = “0”
(
)
RFST1-0 bits
(Table 30) FR bit = “1”
WTM2
WTM1
WTM0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RGAIN1
0
0
1
1
128/fs
256/fs
512/fs
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
Table 26. ALC
RGAIN0
0
1
0
1
Table 27. ALC
ALC
8kHz
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
2048ms
16kHz
8ms
16ms
32ms
64ms
128ms
256ms
512ms
1024ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
MS0557-J-06
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
46.4ms
92.9ms
185.8ms
371.5ms
(default)
(default)
2011/06
- 39 -
[AK4646]
IREF7-0bits
F1H
F0H
EFH
:
E1H
:
92H
91H
90H
:
2H
1H
0H
Table 28.
OREF5-0bits
3CH
3BH
3AH
:
28H
:
25H
24H
23H
:
2H
1H
0H
Table 29.
RFST1 bit
0
0
1
1
Table 30.
GAIN (0dB)
+36.0
+35.625
+35.25
:
+30.0
:
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
ALC
GAIN (0dB)
+36.0
+34.5
+33.0
:
+6.0
:
+1.5
0.0
-1.5
:
-51.0
-52.5
-54.0
ALC
RFST0 bit
0
1
0
1
MS0557-J-06
Step
0.375dB
(default)
Step
1.5dB
(default)
(default)
4
8
16
N/A
(FR bit = “0” )
2011/06
- 40 -
[AK4646]
3.
ALC
VOL7-0 bits
ALC
VOL7-0 bits
VOL7-0bits
GAIN (0dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 31. VOL7-0 bits
4.
ALC
Table 32
Table 33
ALC
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
IREF7-0
IVL7-0,
IVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC1
Gain of IVOL
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
fs=44.1kHz
Data
Operation
01
−4.1dBFS
0
Enable
11
23.2ms
001
32ms
100
46.4ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
00
1
00
00
1
(
1 step
ON
1 step
4 times
Enable
)
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Limiter ATT step
Fast Limiter Operation
Recovery GAIN step
Fast Recovery Speed
ALC enable
Table 32. ALC
MS0557-J-06
2011/06
- 41 -
[AK4646]
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
Data
01
0
01
Gain of VOL
Limiter ATT step
Fast Limiter Operation
Recovery GAIN step
Fast Recovery Speed
ALC enable
Table 33. ALC
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
100
46.4ms
28H
+6dB
28H
+6dB
91H
0dB
91H
0dB
00
1
00
00
1
(
1 step
ON
1 step
4 times
Enable
)
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
ALC
ALC
(ALC1 = ALC2 bits = “0”)
ALC1=ALC2 bits = “0”
ALC
ALL=“0”
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (IREF7-0)
(2) Addr=08H, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=28H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=21H
ALC Operation
Note : WR : Write
Figure 29. ALC
MS0557-J-06
2011/06
- 42 -
[AK4646]
■
(
Rch ADC
ALC1 bit = “0”
Lch
1.
2.
)
(PMADL bit = “1”
ALC
ALC
PMADR bit = “1”)
(
DAFIL bit = “0”
)
(ZTM1-0, LMTH
)
ALC
3.
IVL7-0, IVR7-0 bits
IVL7-0, IVR7-0 bits
IVL7-0 bits
ZTM1-0 bit
Lch , Rch
Lch , Rch
PMADL = PMADR bits = “0”
= “1”
ADC
IVL7-0, IVR7-0 bits
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
Table 34.
(Table 34)
IVOLC bit = “0”
IVOLC bit = “1”
L/R
PMADL bit = “1” or PMADR bit
IVOL
GAIN (dB)
+36.0
+35.625
+35.25
:
+30.375
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
MS0557-J-06
Step
0.375dB
(default)
2011/06
- 43 -
[AK4646]
■
(
Lch Rch
bit = “0”
ADC
)
PMADL bit = PMADR bit = “1”
ALC
DVOLC bit = “0”
OVOLC bit = “1”
L/R
DAFIL bit = “1”
)
Table 35
OVL7-0, OVR7-0 bits
OVL7-0 bits
ZTM1-0 bits
ALC2
(
OVL7-0 bits, OVR7-0 bits
Lch , Rch
Lch , Rch
OVL7-0 bits
OVR7-0 bits
F1H
F0H
EFH
:
92H
91H
90H
:
2H
1H
0H
Table 35.
GAIN (0dB)
Step
+36.0
+35.625
+35.25
:
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
0.375dB
(default)
OVL7-0 bits, OVR7-0 bits
■
2
4
Lch
Rch
DATT1-0 bits
Table 36
DATT1-0bits
0H
1H
2H
3H
Table 36.
GAIN (0dB)
0.0
-6.0
-12.0
-18.1
Step
(default)
6.0dB
2
MS0557-J-06
2011/06
- 44 -
[AK4646]
■
3
IIR
(tc=50/15μs
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bit
)
(Table 37)
DEM1
DEM0
0
0
0
1
1
0
1
1
Table 37.
Mode
44.1kHz
OFF
48kHz
32kHz
(default)
■
DAC
SMUTE bit “1”
SMUTE bit “0”
SMUTE bit
256/fs (5.8msec@fs=44.1kHz)
−∞ (“0”)
−∞
−∞
256/fs (5.8msec@fs=44.1kHz)
256/fs (5.8msec@fs=44.1kHz)
0dB
0dB
S M U T E bit
256/fs
0dB
256/fs
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 30. Soft Mute Function
(1) 256/fs (5.8msec@fs=44.1kHz)
−∞ (“0”)
(2)
(GD)
(3)
256/fs (5.8msec@fs=44.1kHz)
0dB
MS0557-J-06
2011/06
- 45 -
[AK4646]
■
:
BEEPS bit
PMBP bit = “1”
BEEPL bit “1”
”1”
MIN pin
Ri
Ri = 20kΩ
(typ)
Table 38, Table 39
Ri
Ri
BEEPL
MIN
LOUT/ROUT pin
BEEPS
SPP/SPN pin
Figure 7. Block Diagram of MIN pin
LOVL1-0 bits
00
01
10
11
Table 38. Ri = 20kΩ
MIN Æ LOUT/ROUT
0dB
+2dB
+4dB
+6dB
MIN
Æ LOUT/ROUT
(default)
MIN Æ SPP/SPN
ALC2 bit = “0”
ALC2 bit = “1”
00
+4.6dB
+6.6dB
01
+6.6dB
+8.6dB
10
+8.6dB
+10.6dB
11
+10.6dB
+12.6dB
Table 39. Ri = 20kΩ
MIN
Æ
(typ)
SPKG1-0 bits
MS0557-J-06
(default)
(typ)
2011/06
- 46 -
[AK4646]
■
(LOUT, ROUT pin)
DAC Lch, Rch
LOUT, ROUT pin
OFF
LOUT, ROUT pin VCOM
min. 10kΩ
PMLO bit = LOPS bit = “0”
100kΩ (typ)
LOPS bit = “1”
bit = “1”
PMLO bit
ON/OFF
ON/OFF
Figure 32
C
20kΩ
C=1μF
300ms
PMLO bit = “1”
LOPS bit = “0”
DACL bit
DACL bit
“1”
“0”
AVSS
LOPS
LOVL bit
“DACL”
“LOVL”
LOUT pin
DAC
ROUT pin
Figure 31.
LOPS
0
1
PMLO
0
1
0
1
Table 40.
Mode
LOUT/ROUT pin
Pull-down to AVSS
(default)
Fall down to AVSS
Rise up to VCOM
(x: Don’t care)
LOVL1-0 bits
00
01
10
11
Table 41.
Gain
0dB
+2dB
+4dB
+6dB
LOUT
ROUT
(default)
1μF
220Ω
20kΩ
Figure 32.
(
MS0557-J-06
)
2011/06
- 47 -
[AK4646]
[
(
)]
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
(
Figure 33.
(1)
(2)
ON
LOPS bit = “1”
PMLO bit = “1”
LOUT, ROUT pin
(3) LOUT, ROUT pin
(4)
(5)
ON
)
C=1μF
200ms (max 300ms)
LOPS bit = “0”
C=1μF
200ms (max 300ms)
LOPS bit = “0”
LOPS bit = “1”
PMLO bit =“0”
LOUT, ROUT pin
(6) LOUT, ROUT pin
MS0557-J-06
2011/06
- 48 -
[AK4646]
■
8Ω
SVDD
2.2V ~ 4.0V
SVDD = 2.2 ~ 3.6V
Note 20. 38HFigure 34
SPP, SPN pin
(min)
8Ω
30pF
(max)
Load Impedance
Load Capacitance
10Ω
Table 42.
DAC
BTL
AVDD
SPKG1-0 bits
00
01
10
11
1kHz
[(L+R)/2]
SPKG1-0 bits
SPKG1-0 bits
ALC2 bit = “0”
ALC2 bit = “1”
+4.6dB
+6.6dB
+6.6dB
+8.6dB
+8.6dB
+10.6dB
+10.6dB
+12.6dB
Table 43. SPK-Amp
SPKG1-0 bits
SPK-Amp
ALC2 bit = “0”
00
01
10
11
3.37Vpp
4.23Vpp (Note 40)
5.33Vpp (Note 40)
6.71Vpp (Note 40)
Note 40.
SPK-Amp
50Ω (Note 20)
3μF (Note 20)
(default)
(DAC
=0dBFS)
ALC2 bit = “1”
(LMTH1-0 bits = “00”)
3.17Vpp
4.00Vpp
5.04Vpp (Note 40)
6.33Vpp (Note 40)
DAC
OVOL
0dBFS
DAC
4.0Vpp
Table 44. SPK-Amp
MS0557-J-06
2011/06
- 49 -
[AK4646]
(10Ω
Figure 34
Figure 34
)
SPP pin, SPN pin
GND
92% ≤
SVDD
Ex) SVDD = 3.8V
(Figure 34 ZD)
: 3.5V ≤ ZD ≤ 4.1V
3.9V(Min 3.7V, Max
≤ SVDD+0.3V
4.1V)
ZD
SPK-Amp
SPP
≥10Ω
SPN
≥10Ω
ZD
Figure 34. SPK
(
)
MS0557-J-06
2011/06
- 50 -
[AK4646]
Power-up/down
PMSPK bit
PMSPK bit “1”
SPPSN bit “0”
SPP pin Hi-Z SPN pin SVDD/2
PDN pin
“L”
PMSPK
0
“H”
SPP pin
SPPSN
x
0
1
Table 45
1
Hi-Z
PMSPK bit “0”
SPP, SPN pin
Hi-Z
PMSPK bit “1”
SPP, SPN pin
SPN pin SVDD/2
Power-down (PMSPK bit=“0”)
Mode
SPP
Hi-Z
Hi-Z
SPN
Hi-Z
SVDD/2
(default)
(x: Don’t care)
PMSPK bit
SPPSN bit
>1ms
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
SVDD/2
SVDD/2
Hi-Z
Figure 35. Power-up/Power-down Timing for Speaker-Amp
MS0557-J-06
2011/06
- 51 -
[AK4646]
■
3
I/F pin (CSN, CCLK, CDTIO)
I/F
Read/Write, Register address (MSB first, 7bits) Control Data
Output Data (MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↑”
8bit
CCLK “↓”
(
A0 bit
) CDTI pin
D7-D0
READ bit = “1”
READ bit = “0”
8bit
CCLK “↓”
CDTI pin
Hi-Z(
)
CSN “↑”
CDTI pin Hi-Z
CCLK
5MHz (max)
PDN pin= “L”
Note 41.
00H~11H
12H
7FH
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
“H” or “L”
CDTIO “H” or “L”
“H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 36.
MS0557-J-06
2011/06
- 52 -
[AK4646]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Output Volume Control
ALC Mode Control 3
Rch Input Volume Control
ALC LEVEL
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select 1
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
Reserved
Reserved
Reserved
Reserved
Reserved
Rch Output Volume Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
0
0
SPPSN
DAFIL
PLL3
PS1
0
LFST
REF7
D6
PMVCM
0
BEEPS
LOPS
PLL2
PS0
WTM2
ALC2
REF6
D5
PMBP
0
DACS
MGAIN1
PLL1
FS3
ZTM1
ALC1
REF5
D4
PMSPK
0
DACL
SPKG1
PLL0
0
ZTM0
ZELMN
REF4
D3
PMLO
M/S
0
SPKG0
BCKO
0
WTM1
LMAT1
REF3
D2
PMDAC
0
PMMP
BEEPL
0
FS2
WTM0
LMAT0
REF2
D1
0
MCKO
D0
PMADL
PMPLL
MGAIN2
MGAIN0
LOVL1
DIF1
FS1
RFST1
RGAIN0
REF1
LOVL0
DIF0
FS0
RFST0
LMTH0
REF0
IVL7
IVL6
IVL5
IVL4
IVL3
IVL2
IVL1
IVL0
OVL7
RGAIN1
IVR7
VOL7
READ
0
0
GN1
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
F1A7
0
F1B7
0
0
0
0
0
0
OVR7
0
0
0
0
0
0
F2A7
0
F2B7
0
OVL6
LMTH1
IVR6
VOL6
LOOP
0
0
GN0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
F1A6
0
F1B6
0
0
0
0
0
0
OVR6
0
0
0
0
0
0
F2A6
0
F2B6
0
OVL5
OREF5
IVR5
VOL5
SMUTE
0
0
LPF
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
F1A5
F1A13
F1B5
F1B13
0
0
0
0
0
OVR5
0
0
0
0
0
0
F2A5
F2A13
F2B5
F2B13
OVL4
OREF4
IVR4
VOL4
OVOLC
FR
MDIF2
HPF
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
F1A4
F1A12
F1B4
F1B12
0
0
0
0
0
OVR4
0
0
0
0
0
0
F2A4
F2A12
F2B4
F2B12
OVL3
OREF3
IVR3
VOL3
DATT1
IVOLC
MDIF1
EQ0
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
F1A3
F1A11
F1B3
F1B11
0
0
0
0
0
OVR3
0
0
0
0
0
0
F2A3
F2A11
F2B3
F2B11
OVL2
OREF2
IVR2
VOL2
DATT0
0
INR
FIL3
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
F1A2
F1A10
F1B2
F1B10
0
0
0
0
0
OVR2
0
0
0
0
0
0
F2A2
F2A10
F2B2
F2B10
OVL1
OREF1
IVR1
VOL1
DEM1
0
INL
0
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
F1A1
F1A9
F1B1
F1B9
0
0
0
0
0
OVR1
0
0
0
0
0
0
F2A1
F2A9
F2B1
F2B9
OVL0
OREF0
IVR0
VOL0
DEM0
0
PMADR
HPFAD
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
F1A0
F1A8
F1B0
F1B8
0
0
0
0
0
OVR0
0
0
0
0
0
0
F2A0
F2A8
F2B0
F2B8
MS0557-J-06
2011/06
- 53 -
[AK4646]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
Note 42. PDN pin “L”
Note 43. “0”
Note 44.
26H 2FH
Note 45.
0DH
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
12H
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
“1”
24H 32H
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
7FH
MS0557-J-06
2011/06
- 54 -
[AK4646]
■
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
0
R
0
PMADL: MIC-Amp Lch, ADC Lch
0: Power down (default)
1: Power up
PMADR bit
PMADL
D6
D5
PMBP
R/W
0
PMVCM
R/W
0
“0”
D4
PMSPK
R/W
0
D3
PMLO
R/W
0
D2
PMDAC
R/W
0
“1”
D1
0
R
0
D0
PMADL
R/W
0
(1059/[email protected])
ADC
PMDAC: DAC
0: Power down (default)
1: Power up
PMLO:
0: Power down (default)
1: Power up
PMSPK:
0: Power down (default)
1: Power up
PMBP:
0: Power down (default)
1: Power up
PMDAC bit = “1”
PMBP bit = “1”
BEEPL, BEEPS bit
MIN pin
PMVCM: VCOM
0: Power down (default)
1: Power up
PMVCM bit “1”
00H, 01H, 02H, 10H
“0”
MCKO bit
PMVCM bit
“0”
ON/OFF (“1”/”0”)
PDN pin
“L”
00H, 01H, 02H, 10H
ADC
MCKO bit
DAC
ADC
MS0557-J-06
“0”
DAC
2011/06
- 55 -
[AK4646]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
M/S
R/W
0
D2
0
R
0
D4
DACL
R/W
0
D3
0
R
0
D2
PMMP
R/W
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL
0: EXT Mode and Power down (default)
1: PLL Mode and Power up
MCKO: MCKO
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
M/S: Master / Slave Mode
0: Slave Mode (default)
1: Master Mode
Addr
02H
Register Name
Signal Select 1
R/W
Default
MGAIN2-0:
MGAIN1 bit 03H
D7
SPPSN
R/W
0
D6
BEEPS
R/W
0
D5
DACS
R/W
0
D1
D0
MGAIN2
MGAIN0
R/W
0
R/W
1
(Table 19)
D5 bit
PMMP: MPWR pin
0: Power down: Hi-Z (default)
1: Power up
DACL: DAC
0: OFF (default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
LOUT, ROUT pins AVSS
DACS: DAC
0: OFF (default)
1: ON
“1” DAC
BEEPS: MIN pin
0: OFF (default)
1: ON
“1” MIN pin
SPPSN:
0: Power Save Mode (default)
1: Normal Operation
“0”
PMSPK bit =“1”
PMSPK bit = “0”
SPP pin
MS0557-J-06
Hi-Z SPN pin SVDD/2
PDN pin = “L”
2011/06
- 56 -
[AK4646]
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
DAFIL
R/W
0
D6
LOPS
R/W
0
D5
MGAIN1
R/W
0
D4
SPKG1
R/W
0
D3
SPKG0
R/W
0
D2
BEEPL
R/W
0
D1
LOVL1
R/W
0
D0
LOVL0
R/W
0
(Table 41)
LOVL1-0 :
Default: 00(0dB)
MIN
BEEPL:
0: OFF (default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
LOUT, ROUT pins AVSS
(Table 43)
SPKG1-0:
(Table 19)
MGAIN1:
LOPS:
0: Normal Operation (default)
1: Power Save Mode
PMADR bit = “1”
DAFIL: PMADL bit = “1”
0: ADC/
(default)
1: DAC/
DAFIL bit = “1”
“L”
Addr
04H
PMDAC bit = “1”
Register Name
Mode Control 1
R/W
Default
DIF1-0:
Default: “10” (
D7
PLL3
R/W
0
Register Name
Mode Control 2
R/W
Default
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO
R/W
0
D2
0
R
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D4
0
R
0
D3
0
R
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
(Table 10)
(Table 4)
D7
PS1
R/W
0
D6
PS0
R/W
0
D5
FS3
R/W
0
MCKI
PLL
PS1-0: MCKO
Default: “00”(256fs)
SDTO pin
(Table 16)
(Table 5, Table 6)
FS3-0:
PMADL bit, PMADR bit
)
PLL3-0: PLL
Default: “0000” (LRCK pin)
Addr
05H
D6
PLL2
R/W
0
BICK
BCKO:
Filter/ALC
EXT
(Table 11)
MCKI
(Table 9)
MS0557-J-06
2011/06
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[AK4646]
Addr
06H
Register Name
Timer Select
R/W
Default
D7
0
R
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
D1
D0
LMTH0
R/W
0
(Table 26)
WTM2-0: ALC
ALC
“000” (128/fs)
(Table 25)
ZTM1-0: ALC
ALC
“00” (128/fs)
RFST1-0: ALC
Default: “00”(4
Addr
07H
(Table 30)
)
Register Name
ALC Mode Control 1
R/W
Default
D7
LFST
R/W
0
LMTH1-0: ALC
Default: “00”
LMTH1 bit 0BH
RGAIN1-0: ALC
Default: “00”
RGAIN1 bit 0BH
D5
ALC1
R/W
0
D4
ZELMN
R/W
0
/
RGAIN0
R/W
0
(Table 23)
D6 bit
(Table 27)
D7 bit
ATT
LMAT1-0: ALC
Default: “00”
D6
ALC2
R/W
0
(Table 24)
ZELMN: ALC
0: Enable (default)
1: Disable
ALC1:
0:
1:
ALC
ALC Disable (default)
ALC Enable
ALC2:
0:
1:
ALC
ALC Disable (default)
ALC Enable
LFST: FS
0:
1: ALC
ALC
Volume
FS
OVOL
(default)
(1/fs)
MS0557-J-06
2011/06
- 58 -
[AK4646]
Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
IREF7
R/W
1
D6
IREF6
R/W
1
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
1
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
R/W
Default
D7
OVL7
OVR7
R/W
1
D6
OVL6
OVR6
R/W
0
OVL7-0, OVR7-0:
Default: “91H” (0dB)
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D5
IVL5
IVR5
R/W
1
D7
RGAIN1
R/W
0
R/W
Default
VOL7-0: ALC
D1
IREF1
R/W
0
D0
IREF0
R/W
1
D3
IVL3
IVR3
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
0
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
1
D6
LMTH1
R/W
0
D5
OREF5
R/W
1
D4
OREF4
R/W
0
D3
OREF3
R/W
1
D2
OREF2
R/W
0
D1
OREF1
R/W
0
D0
OREF0
R/W
0
D1
VOL1
R
-
D0
VOL0
R
-
0.375dB step, 50 Level (Table 29)
/
(Table 23)
(Table 27)
RGAIN1: ALC
ALC Volume
D2
IREF2
R/W
0
(Table 35)
LMTH1: ALC
Register Name
D4
IVL4
IVR4
R/W
0
D5
OVL5
OVR5
R/W
0
OREF5-0:
ALC
Default: “28H” (+6.0dB)
Addr
0DH
D3
IREF3
R/W
0
; 0.375dB step, 242 Level (Table 34)
IVL7-0, IVR7-0:
Default: “E1H” (+30.0dB)
Addr
0AH
25H
D4
IREF4
R/W
0
0.375dB step, 242 Level (Table 28)
IREF7-0: ALC
Default: “E1H” (+30.0dB)
Addr
09H
0CH
D5
IREF5
R/W
1
D7
VOL7
R
-
D6
VOL6
R
-
D5
VOL5
R
-
; 0.375dB step, 242 Level
MS0557-J-06
D4
VOL4
R
-
D3
VOL3
R
-
D2
VOL2
R
-
(Table 31)
2011/06
- 59 -
[AK4646]
Addr
0EH
Register Name
Mode Control 3
R/W
Default
D7
READ
R/W
0
D5
SMUTE
R/W
0
D4
OVOLC
R/W
1
D3
DATT1
R/W
0
D2
DATT0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
D3
IVOLC
R/W
1
D2
0
R
0
D1
0
R
0
D0
0
R
0
(Table 37)
DEM1-0:
Default: “01” (OFF)
2; 6dB step, 4 Level (Table 36)
DATT1-0:
Default: “00H” (0.0dB)
OVOLC:
0: Independent
1: Dependent (default)
OVOLC bit = “1”
OVR7-0 bit OVL7-0 bit
D6
LOOP
R/W
0
OVL7-0 bit
SMUTE:
0: Normal Operation (default)
1: DAC outputs soft-muted
LOOP:
0: SDTI → DAC (default)
1: SDTO → DAC
READ:
0: Disable (default)
1: Enable
Addr
0FH
Register Name
Mode Control 4
R/W
Default
IVOLC: IVOL
0: Independent
1: Dependent (default)
IVOLC bit = “1”
D7
0
R
0
D6
0
R
0
D5
0
R
0
IVL7-0 bit
D4
FR
R/W
0
IVOL
IVR7-0 bit IVL7-0 bit
FR: ALC
0: Enable (default)
1: Disable
MS0557-J-06
2011/06
- 60 -
[AK4646]
Addr
10H
Register Name
Power Management 3
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
MDIF2
R/W
0
D3
MDIF1
R/W
0
D2
INR
R/W
0
D1
INL
R/W
0
D0
PMADR
R/W
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
EQ0
R/W
0
D2
FIL3
R/W
0
D1
0
R
0
D0
HPFAD
R/W
1
PMADR: MIC-Amp Rch, ADC Rch
0: Power down (default)
1: Power up
INL: ADC Lch
0: LIN1 pin (default)
1: LIN2 pin
INR: ADC Rch
0: RIN1 pin (default)
1: RIN2 pin
MDIF1: ADC Lch
0:
(LIN1/LIN2 pin: Default)
1:
(IN1+/IN1− pin)
MDIF2: ADC Rch
0:
(RIN1/RIN2 pin: Default)
1:
(IN2+/IN2− pin)
Addr
11H
Register Name
Digital Filter Select 1
R/W
Default
D7
GN1
R/W
0
(
HPADF: ADC
0: OFF
1: ON (default)
HPFAD bit = “1”
HPFAD
FIL3:
0: OFF (default)
1: ON
FIL3 bit = “1”
EQ0 :
0: OFF (default)
1: ON
EQ0 bit = “1”
EQ0
1
D6
GN0
R/W
0
)
HPF
F1A13-0, F1B13-0 bit
(0dB)
HPFAD bit = “0”
FIL3
F3A13-0, F3B13-0 bit
(EQ0)
E0A15-0, E0B13-0, E-C15-0 bit
(0dB)
2
HPF:
0: OFF (default)
1: ON
HPF bit = “1”
1
EQ0 bit = “0”
HPF
F1A13-0, F1B13-0 bit
HPF bit = “0”
HPF
(0dB)
MS0557-J-06
2011/06
- 61 -
[AK4646]
LPF: LPF
0: OFF (default)
1: ON
LPF bit = “1”
F2A13-0, F2B13-0 bit
LPF bit = “0”
LPF
(0dB)
GN1-0: Gain
Default: “00” (0dB)
Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
(Table 22)
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
W
0
FIL3
F3A13-0, F3B13-0:
Default: “0000H”
F3AS:
0: HPF (Default)
1: LPF
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
W
0
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
W
0
Register Name
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
R/W
Default
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
W
0
D2
F1A2
F1A10
F1B2
F1B10
W
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
(14bit x 2)
FIL3
(16bit x 2 + 14bit x 1)
E0A15-0, E0B13-0, E0C15-C0:
Default: “0000H”
Addr
1CH
1DH
1EH
1FH
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
W
0
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
F1A5
F1A13
F1B5
F1B13
W
D4
F1A4
F1A12
F1B4
F1B12
W
D3
F1A3
F1A11
F1B3
F1B11
W
F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
(14bit x 2)
F1A13-0, F1B13-0: HPF
Default: F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
fc = 150Hz@fs=44.1kHz
Addr
2CH
2DH
2EH
2FH
Register Name
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
R/W
Default
F2A13-0, F2B13-0: LPF
Default: “0000H”
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
(14bit x 2)
MS0557-J-06
2011/06
- 62 -
[AK4646]
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
EQ1: Equalizer 1
0: Disable (default)
1: Enable
EQ1 bit = “1”
EQ1
E1A15-0, E1B15-0, E1C15-0 bit
(0dB)
EQ1 bit = “0”
EQ2: Equalizer 2
0: Disable (default)
1: Enable
EQ2 bit = “1”
EQ2
E2A15-0, E2B15-0, E2C15-0 bit
(0dB)
EQ2 bit = “0”
EQ3: Equalizer 3
0: Disable (default)
1: Enable
EQ3 bit = “1”
EQ3
E3A15-0, E3B15-0, E3C15-0 bit
(0dB)
EQ3 bit = “0”
EQ4: Equalizer 4
0: Disable (default)
1: Enable
EQ4 bit = “1”
EQ4
E4A15-0, E4B15-0, E4C15-0 bit
(0dB)
EQ4 bit = “0”
EQ5: Equalizer 5
0: Disable (default)
1: Enable
EQ5 bit = “1”
EQ5
E5A15-0, E5B15-0, E5C15-0 bit
(0dB)
EQ5 bit = “0”
MS0557-J-06
D0
EQ1
R/W
0
2011/06
- 63 -
[AK4646]
Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1
Default: “0000H”
(16bit x3)
E2A15-0, E2B15-0, E2C15-0: Equalizer 2
Default: “0000H”
(16bit x3)
E3A15-0, E3B15-0, E3C15-0: Equalizer 3
Default: “0000H”
(16bit x3)
E4A15-0, E4B15-0, E4C15-0: Equalizer 4
Default: “0000H”
(16bit x3)
E5A15-0, E5B15-0, E5C15-0: Equalizer 5
Default: “0000H”
(16bit x3)
MS0557-J-06
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
2011/06
- 64 -
[AK4646]
Figure 37
(AKD4646)
Speaker
10u
ZD2
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Requi red
Line Out
200
Mono In
External MIC
1u
1u
23
22
21
20
19
18
17
NC
SVSS
SVDD
SPP
SPN
MCKO
MCKI
R2
24
NC
20k
20k
200
R1
0.1u
ZD1
10
Power Supply
2.2 ∼ 3.6V
0.1u
25 NC
DVSS
16
26 ROUT
DVDD
15
27 LOUT
BICK
14
DSP
28 MIN
AK4646
LRCK
13
29 RIN2
Top View
SDTO
12
30 LIN2
SDTI
11
31 LIN1
CDTIO 10
32 RIN1
CCLK
NC
PDN
CSN
6
7
8
VCOC
5
AVDD
4
9
μP
Rp
AVSS
3
2.2u
0.1u
VCOM
2
MPWR
1
0.1u
2.2k
2.2k
2.2k
2.2k
Internal MIC
Cp
Analog Ground
:
- AK4646
- EXT
- PLL
-
Digital Ground
AVSS, DVSS, SVSS
(PMPLL bit = “0”)
VCOC pin
(PMPLL bit = “1”)
Cp Rp Table 4
SPP, SPN pin
10Ω
M/S bit “1”
AK4646
AK4646 LRCK, BICK pin 100kΩ
LRCK, BICK pin
Figure 37.
MS0557-J-06
2011/06
- 65 -
[AK4646]
1.
AVDD, DVDD, SVDD
AVDD, DVDD, SVDD
AVSS, DVSS, SVSS
PC
2.
2.2μF
VCOM
0.1μF
AVSS
VCOM pin
VCOM pin
3.
MIN
0.0636 x AVDD Vpp (typ)
(0.5 x AVDD)
0.636 x AVDD Vpp (typ)
fc=1/(2πRC)
AK4646
DC
AVSS
AVDD
4.
DAC
8000H (@16bit)
2’s
0000H (@16bit)
0.5 x AVDD (typ)
MS0557-J-06
7FFFH (@16bit)
VCOM
SVDD/2
VCOM
2011/06
- 66 -
[AK4646]
■
DAC Power-up
ADC
1. PLL
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 38. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
AK4646
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms (max)
(6) PLL
BICK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
(1)
MS0557-J-06
PLL
2011/06
- 67 -
[AK4646]
2. PLL
(LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 39. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
AK4646
150ns
“L”
(2)
DIF1-0, FS3-0, PLL3-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPLL bit “0” Æ “1”
PLL
(LRCK or BICK pin)
PLL
LRCK PLL
2ms (max)
(5) PLL
(1)
MS0557-J-06
PLL
160ms (max), BICK
PLL
2011/06
- 68 -
[AK4646]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 40. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
AK4646
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms (max)
(6) PLL
MCKO pin
(7)
MCKO pin
(8) MCKO
BICK, LRCK
(1)
MS0557-J-06
PLL
2011/06
- 69 -
[AK4646]
4.
(
)
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 1024fs
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:27H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 41. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
AK4646
150ns
(2)
DIF1-0, FS1-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, LRCK, BICK
(1)
MS0557-J-06
“L”
2011/06
- 70 -
[AK4646]
■
(
)
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL Master Mode
Audio I/F Format:MSB justified (ADC & DAC)
Pre MIC AMP:+20dB
Sampling Frequency:44.1KHz
MIC Power On
ALC setting:Refer to Figrure 23
ALC1 bit=“1”
1,111
(1)
MIC Control
(1) Addr:05H, Data:27H
001
(Addr:02H, D2-0)
101
(2) Addr:02H, Data:05H
(2)
ALC Control 1
00H
(Addr:06H)
3CH
(3) Addr:06H, Data:3CH
E1H
(4) Addr:08H, Data:E1H
(3)
ALC Control 2
E1H
(Addr:08H)
(4)
(5) Addr:0BH, Data:28H
ALC Control 3
28H
(Addr:0BH)
28H
(6) Addr:07H, Data:21H
(5)
ALC Control 4
00H
(Addr:07H)
21H
01H
(6)
ALC State
(9)
ALC Disable
ALC Enable
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
ALC Disable
Recording
PMADL/R bit
(Addr:00H&10H, D0)
1059 / fs
(8)
(7)
ADC Internal
State
Power Down
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
Initialize Normal State Power Down
(9) Addr:07H, Data:01H
Figure 42. MIC Input Recording Sequence
<
>
fs=44.1kHz
”
ALC
ALC
“Figure 29. ALC
(1)
(FS3-0 bits)
PLL
PLL
(7)
ADC
(2)
(
02H)
(3) ALC Timer (
06H)
(4) ALC IREF (
08H)
(5) LMTH1, RGAIN1 bits
(
0BH)
(6) LMTH0, RGAIN0, LMAT1-0, ALC1 bits
(
07H)
(7)
ADC
: PMADL = PMADR bits = “0” → “1”
ADC
1059/fs=24ms@fs=44.1kHz
ALC
(IVL/R7-0 bits)
(+30dB)
“1”
(8)
HPF
PMVCM bit =
PMMP bit = “1”
AC
30k(typ)
4
ADC Power-up
ADC
: PMADL = PMADR bits = “1” → “0”
ADC
ALC Disable
ALC
(ALC bit = “0”)
ADC
(PMADL = PMADR bits = “0”)
PMADL = PMADR bits = “0”
(IVL/R7-0 bits)
(9) ALC Disable: ALC1 bit = “1” → “0”
MS0557-J-06
2011/06
- 71 -
[AK4646]
■
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
1,111
Example:
(1)
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC: Enable
(11)
DACS bit
(Addr:02H, D3)
(1) Addr:05H, Data:27H
(2)
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:0BH)
00
01
(2) Addr:02H, Data:20H
(3)
00H
(3) Addr:03H, Data:08H
3CH
(4)
28H
(4) Addr:06H, Data:3CH
28H
(5)
ALC2 bit
(Addr:07H, D6)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(5) Addr:0BH, Data:28H
0
X
(6)
(6) Addr:07H, Data:40H
91H
91H
(7) Addr:0AH & 0DH, Data:91H
(7)
(12)
PMDAC bit
(8) Addr:00H, Data:74H
(Addr:00H, D2)
PMBP bit
(9) Addr:02H, Data:A0H
(Addr:00H, D5)
(8)
PMSPK bit
Playback
(Addr:00H, D4)
(9)
(10) Addr:02H, Data:20H
SPPSN bit
(Addr:02H, D7)
(10)
SPP pin
Hi-Z
Normal Output
(11) Addr:02H, Data:00H
Hi-Z
(12) Addr:00H, Data:40H
SPN pin
Hi-Z
SVDD/2 Normal Output SVDD/2
Hi-Z
Figure 43. Speaker-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
PLL
PLL
(5) DAC
(2) DAC Æ SPK-Amp
: DACS bit = “0” Æ “1”
(3) SPK-Amp
: SPKG1-0 bits = “00” → “01”
(4) ALC Timer (
06H)
(5) ALC REF , LMTH1, RGAIN1 bits
(
0BH)
(6) LMTH0, RGAIN0, LMAT1-0, ALC2 bits
(
07H)
(7)
(
0AH&0DH)
OVOLC bit = “1”(default)
OVL7-0bits (0AH) Lch
Rch
DAC
Default (0dB)
(PMADL bit = “1”
PMADR bit = “1”)
DAFIL bit = “0”
DAC ALC/OVL7-0
(8) DAC, MIN-Amp
: PMDAC = PMBP = PMSPK bits = “0” → “1”
DAC
(PMDAC bit = “0” → “1”)
67/fs = 1.52ms@fs=44.1kHz
67/fs = 1.52ms@fs=44.1kHz
(9)
: SPPSN bit = “0” → “1”
(9)
MIN pin
MIN-Amp
SPK-Amp
Enable
e.g. R=20kΩ, C=0.1μF
:
5τ = 10ms
(10)
: SPPSN bit = “1” → “0”
(11) DAC Æ SPK-Amp
Disable: DACS bit = “1” Æ “0”
(12) DAC, MIN-Amp
: PMDAC = PMBP = PMSPK bits = “1” → “0”
MS0557-J-06
2011/06
- 72 -
[AK4646]
■
Mono
Example:
Clocks can be stopped.
CLOCK
(1) Addr:00H, Data:70H
PMBP bit
(Addr:00H, D5)
(1)
(5)
(2) Addr:02H, Data:60H
PMSPK bit
(Addr:00H, D4)
DACS bit
(Addr:02H, D5)
(3) Addr:02H, Data:E0H
" 0" or " 1"
0
(2)
(6)
BEEPS bit
Mono Signal Output
(Addr:02H, D6)
(3)
SPPSN bit
(4) Addr:02H, Data:60H
(Addr:02H, D7)
(4)
SPP pin
SPN pin
Hi-Z
Hi-Z
Normal Output
SVDD/2
Normal Output
Hi-Z
SVDD/2
(5) Addr:00H, Data:40H
Hi-Z
(6) Addr:02H, Data:00H
Figure 44. “MIN-Amp Æ Speaker-Amp” Output Sequence
<
>
“MIN-Amp Æ SPK-Amp”
: PMBP = PMSPK bits = “0” → “1”
(1) MIN-Amp
(2) DAC Æ SPK-Amp
Disable: DACS bit = “0”
MIN Æ SPK-Amp
Enable: BEEPS bit = “0” → “1”
(3)
: SPPSN bit = “0” → “1”
(3)
MIN pin
MIN-Amp
SPK-Amp
Enable
e.g. R=20kΩ, C=0.1μF
:
5τ = 10ms
(4)
: SPPSN bit = “1” → “0”
(5) MIN-Amp
: PMBP = PMSPK bits = “1” → “0”
(6) MIN Æ SPK-Amp
Disable: BEEPS bit = “1” → “0”
MS0557-J-06
2011/06
- 73 -
[AK4646]
■
FS3-0 bits
(Addr:05H, D5&D2-0)
Example:
1,111
0,000
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”
(1)
(9)
DACL bit
(2)
(Addr:02H, D4)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(1) Addr:05H, Data:27H
91H
(2) Addr:02H, Data:10H
91H
(3) Addr:0AH&0DH, Data:91H
(3)
LOPS bit
(4) Addr:03H, Data:40H
(Addr:03H, D6)
(4)
(6)
(7)
(10)
(5) Addr:00H, Data:6CH
PMDAC bit
(Addr:00H, D2)
(6) Addr:03H, Data:00H
PMBP bit
Playback
(Addr:00H, D5)
(5)
(8)
(7) Addr:03H, Data:40H
PMLO bit
(Addr:00H, D3)
>300 ms
(8) Addr:00H, Data:40H
LOUT pin
ROUT pin
>300 ms
Normal Output
(9) Addr:02H, Data:00H
(10) Addr:03H, Data:00H
Figure 45. Stereo Lineout Sequence
<
>
(1)
(FS3-0 bits)
PLL
(5) DAC
(2) DAC Æ
: DACL bit = “0” Æ “1”
(3)
(
0AH&0DH)
DVOLC bit = “1”(default)
OVL7-0bits (0AH) Lch
Rch
(PMADL bit = “1”
PMADR bit = “1”)
DAFIL bit = “0”
(4)
(5) DAC, MIN-Amp
DAC
(PMDAC bit = “0” → “1”)
67/fs = 1.52ms@fs=44.1kHz
PMLO bit = “1” LOUT, ROUT pins
300ms
(6)
LOUT, ROUT pins
(7)
(8) DAC, MIN-Amp
LOUT, ROUT pins
(9) DAC Æ
(10)
LOUT, ROUT pins
DAC ALC/OVL7-0
: LOPS bit = “0” Æ “1”
: PMDAC = PMBP = PMLO bits = “0” → “1”
67/fs = 1.52ms@fs=44.1kHz
C = 1μF
max.
: LOPS bit = “1” Æ “0”
LOUT, ROUT pins
: LOPS bit: “0” Æ “1”
: PMDAC = PMBP = PMLO bits = “1” → “0”
C = 1μF
max. 300ms
Disable: DACL bit = “1” Æ “0”
: LOPS bit = “1” Æ “0”
MS0557-J-06
2011/06
- 74 -
[AK4646]
■
DAC
ADC
1. PLL
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"0" or "1"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 46. Clock Stopping Sequence (1)
<
>
(1) PLL
(2) MCKO
(3)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
2. PLL
(LRCK, BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 47. Clock Stopping Sequence (2)
<
>
(1) PLL
(2)
: PMPLL bit = “1” → “0”
MS0557-J-06
2011/06
- 75 -
[AK4646]
3. PLL
(MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 48. Clock Stopping Sequence (3)
<
>
(1) PLL
MCKO
(2)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
4.
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 49. Clock Stopping Sequence (4)
<
>
(1)
■
1μA)
PMVCM bit = “0”
PDN pin = “L”
MS0557-J-06
(typ.
(typ. 1μA)
2011/06
- 76 -
[AK4646]
(AK4646EN)
32pin QFN (Unit: mm)
5.00 ± 0.10
0.40 ± 0.10
4.75 ± 0.10
24
17
16
4.75 ± 0.10
B
3.5
5.00 ± 0.10
25
9
32
1
1
3.5
0.50
+0.07
-0.05
32
C0.42
8
A
0.23
Exposed
Pad
0.85 ± 0.05
0.10 M AB
0.08 C
:
0.04
0.01+- 0.01
0.20
C
(Exposed Pad)
■
:
:
:
MS0557-J-06
2011/06
- 77 -
[AK4646]
(AK4646EZ)
32pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.1
17
24
0.40 ± 0.10
25
2.4 ± 0.1
4.0 ± 0.1
16
A
Exposed
Pad
32
9
0.45 ± 0.10
8
1
0.22 ± 0.05
B
0.18 ± 0.05
0.05 M
C0.3
PIN #1 ID
0.4
:
0.65 MAX
0.00 MIN
0.05 MAX
0.08
(Exposed Pad)
70°C
■
:
:
:
MS0557-J-06
2011/06
- 78 -
[AK4646]
(AK4646EN)
AKM
AK4646
XXXXX
1
XXXXX : Date code identifier (5 )
(AK4646EZ)
4646
XXXX
1
XXXX : Date code identifier (4 )
MS0557-J-06
2011/06
- 79 -
[AK4646]
Date (YY/MM/DD)
06/10/30
06/11/27
Revision
00
01
Reason
Page
Contents
27
:
<
PDN pin
“L”
<
PDN pin =
PDN pin = L
07/05/14
02
72,73
BEEP pin → MIN pin
BEEP-Amp → MIN-Amp
11
SPKG1-0 = “01”
Output Voltage
S/(N+D)
14
10/01/07
03
39, 40
53, 60
10/08/19
04
7
11/01/19
05
9
L
150ns
Speaker-Amp Characteristics
240 W
250mW
240 W
250mW
1.19xAVDD(typ) 1.21xADVV(typ)
Note 16
Control Interface Timing
CSN “↓” to CCLK “↑” → CSN Edge to CCLK “↑”
CCLK “↑” to CSN “↑” → CCLK “↑” to CSN Edge
FR bit
ALC
AK4646EZ
AVDD – SVDD
11/06/22
06
26
: 0.8V (max)
Note 18
:
“DAC -0.5dBFS
”
SPKG1-0 bits = “00”
“Vout=0.94 x AVDD” → “0.96 x AVDD”
SPKG1-0 bits = “10”
“Vout=2.05 x AVDD” → “1.52 x AVDD”
SPKG1-0 bits = “11”
“Vout=2.58 x AVDD” → “1.92 x AVDD”
■ EXT Master Mode
Table 13
(MCKI Input Frequency)
Mode 2: 256fs → 512fs
Mode 3: 512fs → 256fs
MS0557-J-06
2011/06
- 80 -
[AK4646]
z
z
z
z
z
z
MS0557-J-06
2011/06
- 81 -