[AK4121A] AK4121A Asynchronous Sample Rate Converter 8kHz ∼ 96kHz AK4121A 32kHz, 44.1kHz, 48kHz, 96kHz PLL DVD (FSI): 8kHz ∼ 96kHz (FSO): 32kHz, 44.1kHz, 48kHz, 96kHz : FSO/FSI = 0.33 ∼ 6 THD+N: –113dB I/F : 24/20/16 I2S PLL : 256/384/512/768fso : 32k/44.1k/48kHz SRC : VDD: 3.0 ∼ 3.6V, TVDD: 3.0 ∼ 5.5V (for input tolerant) Ta: –40 ∼ 85°C PDN DEM0 DEM1 SMUTE TVDD VDD DVSS (MCLK) SDTI ILRCK Serial Audio I/F IBICK De-em filter Sample Rate Converter soft mute Serial Audio I/F SDTO OLRCK OBICK CMODE2 AVSS CMODE1 PLL CMODE0 FILT IDIF2 IDIF1 IDIF0 ODIF1 MS0337-J-06 ODIF0 2010/04 -1- [AK4121A] ■ AK4121AVF AKD4121A −40 ∼ +85°C AK4121A 24pin VSOP (0.65mm pitch) ■ FILT 1 24 VDD AVSS 2 23 DVSS PDN 3 22 TVDD SMUTE 4 21 MCLK DEM0 5 20 OLRCK DEM1 6 19 OBICK ILRCK 7 18 SDTO IBICK 8 17 ODIF1 SDTI 9 16 ODIF0 IDIF0 10 15 CMODE2 IDIF1 11 14 CMODE1 IDIF2 12 13 CMODE0 Top View ■ AK4121 AK4121A (FSI) MS0337-J-06 AK4121 2010/04 -2- [AK4121A] No. 1 2 FILT AVSS I/O O I 3 PDN I 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SMUTE DEM0 DEM1 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK MCLK TVDD DVSS VDD I I I I I I I I I I I I I I O I/O I/O I I I I Function PLL & “L” #0 #1 Input Input Input Input Input #0 #1 #2 #0 #1 #2 Output Output #0 #1 Output Output Output , 3.3 ~ 5V , 3.3V MS0337-J-06 2010/04 -3- [AK4121A] (AVSS=DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: VDD TVDD ΔGND IIN VIN Ta Tstg −0.3 −0.3 4.6 6.0 0.3 ±10 TVDD+0.3 85 150 V V V mA V °C °C Core Input Buffer |AVSS-DVSS| (Note 1) Input Current, Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature Note 1. −0.3 −40 −65 : (AVSS=DVSS=0V; Note 2) Parameter Power Supplies: Core Input Buffer Symbol min typ max Units VDD TVDD 3.0 VDD 3.3 5 3.6 5.5 V V Note 2. SRC (Ta=−40∼85°C; VDD=3.0∼3.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Resolution 20 Input Sample Rate FSI 8 96 Output Sample Rate FSO 32 96 Dynamic Range (Input = 1kHz, −60dBFS,Note 3) 114 FSO/FSI=44.1kHz/48kHz 114 FSO/FSI=48kHz/44.1kHz 114 FSO/FSI=32kHz/48kHz 115 FSO/FSI=96kHz/32kHz 112 Worst Case (FSO/FSI=48kHz/96kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 3) 117 FSO/FSI=44.1kHz/48kHz THD+N (Input = 1kHz, 0dBFS, Note 3) −113 FSO/FSI=44.1kHz/48kHz −112 FSO/FSI=48kHz/44.1kHz −113 FSO/FSI=32kHz/48kHz −111 FSO/FSI=96kHz/32kHz −103 Worst Case (FSO/FSI=48kHz/8kHz) Ratio between Input and Output Sample Rate (FSO/FSI, Note 4, Note 5) 0.33 6 FSO/FSI Note 3. Rohde & Schwarz UPD04 Rejection Filter = wide 8192point FFT Note 4. 0.33 FSI 96kHz FSO 32kHz FSO/FSI Note 5. 6 FSI 8kHz FSO 48kHz MS0337-J-06 Units Bits kHz kHz dB dB dB dB dB dB dB dB dB dB dB - 2010/04 -4- [AK4121A] (Ta=−40∼85°C; VDD=3.0∼3.6V; TVDD=3.0~5.5V) Parameter Digital Filter Passband −0.001dB Stopband 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 0.452 ≤ FSO/FSI < 0.492 0.333 ≤ FSO/FSI < 0.452 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 0.452 ≤ FSO/FSI < 0.492 0.333 ≤ FSO/FSI < 0.452 Passband Ripple Stopband Attenuation Group Delay Note 6. (Note 6) L,R Symbol min PB PB PB PB PB PB PB PB SB SB SB SB SB SB SB SB PR SA GD 0 0 0 0 0 0 0 0 0.5417FSI 0.5021FSI 0.3965FSI 0.3643FSI 0.2974FSI 0.2732FSI 0.2510FSI 0.1822FSI LRCK typ max Units 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2245FSI 0.2003FSI 0.1781FSI 0.1092FSI kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs L,R ±0.01 96 ( 57.5 LRCK 20Bit, 20,16Bit ) DC (Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V) Parameter Symbol Power Supply Current (VDD+TVDD) Normal operation: FSI=FSO=48kHz at Slave Mode: VDD=TVDD=3.3V FSI=FSO=96kHz at Master Mode: VDD=TVDD=3.3V : VDD=TVDD=3.6V Power down: PDN = “L” (Note 7) High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−400μA) VOH Low-Level Output Voltage (Iout=400μA) VOL Input Leakage Current Iin Note 7. DVSS MS0337-J-06 min 0.7xVDD VDD−0.4 - typ max Units 10 20 40 100 0.3xVDD 0.4 ± 10 mA mA mA μA V V V V μA 10 - 2010/04 -5- [AK4121A] (Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V; CL=20pF) Parameter Symbol Master Clock Input (MCLK) Frequency fCLK Duty Cycle dCLK L/R clock for Input data (ILRCK) Frequency fs Duty Cycle Duty L/R clock for Output data (OLRCK) fs Frequency (Note 8) Duty Cycle Slave Mode Duty Master Mode Duty Audio Interface Timing Input tBCK IBICK Period tBCKL IBICK Pulse Width Low tBCKH IBICK Pulse Width High ILRCK Edge to IBICK “↑” (Note 9) tLRB ILRCK Frequency = 8kHz ~ 32kHz tLRB ILRCK Frequency = 32kHz ~ 48kHz tLRB ILRCK Frequency = 48kHz ~ 96kHz tBLR BICK “↑” to ILRCK Edge (Note 9) tSDH SDTI Hold Time from IBICK “↑” tSDS SDTI Setup Time to IBICK “↑” Output (Slave Mode) tBCK OBICK Period tBCKL OBICK Pulse Width Low tBCKH OBICK Pulse Width High tLRB OLRCK Edge to OBICK “↑” (Note 9) tBLR OBICK “↑” to OLRCK Edge (Note 9) tLRS OLRCK to SDTO (MSB) tBSD OBICK “↓” to SDTO Output (Master Mode) fBCK BICK Frequency dBCK BICK Duty tMBLR BICK “↓” to LRCK tBSD BICK “↓” to SDTO Power-down & Reset Timing tPD PDN Pulse Width (Note 10) Note 8. BYPASS mode min=8kHz Note 9. LRCK BICK Note 10. PDN pin “H” “L” MS0337-J-06 min typ max Units 8.192 40 - 36.864 60 MHz % 8 48 50 96 52 kHz % 96 52 kHz % % 32 48 50 50 ns ns ns 1/64fs 65 65 16/256fs 16/256fs 16/256fs 1/256fs + 45 1/256fs + 25 1/256fs + 15 30 30 30 30 30 ns ns ns ns ns ns ns 20 30 Hz % ns ns 1/64fs 65 65 30 30 64fs 50 −20 −20 150 ns ns ns ns ns ns ns 2010/04 -6- [AK4121A] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD 70%VDD SDTO 30%VDD tSDS tSDH VIH SDTI VIL Figure 2. Audio Interface Timing at Slave Mode MS0337-J-06 2010/04 -7- [AK4121A] LRCK 50%VDD tMBLR dBCK 50%VDD BICK tBSD 50%VDD SDTO Figure 3. Audio Interface Timing at Master Mode tPD VIH PDN VIL Figure 4. Power-down & Reset Timing Note 11. BICK Note 12. LRCK IBICK,OBICK ILRCK,OLRCK MS0337-J-06 2010/04 -8- [AK4121A] ■ Input Output ILRCK PLL MCLK SRC Mode 0 1 2 3 4 5 6 7 CMODE0/1/2 pin CMODE2 L L L L H H H H CMODE1 L L H H L L H H Output DVSS CMODE0/1/2 pin CMODE0 MCLK L 256fso (fso~96kHz) H 384fso (fso~96kHz) 512fso (fso~48kHz) L 768fso (fso~48kHz) H L Not used. Set to DVSS H L H Not used. Set to DVSS Table 1. Master/Slave control PDN=“L” Master/Slave (Output Port) Master Master Master Master Slave (Reserved) (Reserved) Master (BYPASS mode) ■ Input 5 Output 4 MSB 2’s SDTI IBICK BYPASS mode Mode 0 1 2 3 4 Mode 0 1 2 3 Note 13. 16bit IDIF2 L L L L H ODIF1 L L H H IDIF0/1/2 PDN=“L” IBICK=OBICK=64fs IDIF1 L L H H L ODIF0 L H L H OBICK=32 ODIF0/1 pin SDTO OBICK IDIF0 SDTI Format L 16bit LSB Justified H 20bit LSB Justified L 20bit MSB Justified H 20/16bit I2S Compatible L 24bit LSB Justified Table 2. Input Audio Data Formats SDTO Format 16bit LSB Justified 20bit LSB Justified 20/16bit MSB Justified (Note 13) 20/16bit I2S Compatible (Note 13) OBICK (Slave) 64fs 64fs ≥40fs or 32fs ≥40fs or 32fs IBICK (Slave) ≥32fs ≥40fs ≥40fs ≥40fs or 32fs ≥48fs OBICK (Master) 64fs 64fs 64fs 64fs Table 3. Output Audio Data Formats MS0337-J-06 2010/04 -9- [AK4121A] LRCK 0 1 12 13 14 15 16 31 0 1 12 13 14 15 16 31 0 1 0 1 BICK (64fs) SDTI 16bit Don’t care 15 0 Don’t care 15 0 Don’t care 15 0 15 0 15:MSB, 0:LSB SDTI 20bit Don’t care 19 18 17 16 19 18 16 17 19:MSB, 0:LSB Lch Data Rch Data Figure 5. 16bit/20bit LSB justified LRCK 0 1 2 18 19 20 30 31 0 1 2 18 19 20 30 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 0 1 Don’t care 19 18 0 1 20:MSB, 0:LSB Lch Data Rch Data Figure 6. 20bit MSB justified LRCK 0 1 2 3 19 20 21 31 0 1 2 3 19 20 21 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 1 0 Don’t care 19 19:MSB, 0:LSB Lch Data Rch Data Figure 7. 20bit I2S MS0337-J-06 2010/04 - 10 - [AK4121A] ■ SMUTE “H” “L” −∞ 1024OLRCK 1024OLRCK −∞ 1024OLRCK −∞ (“0”) 0dB SMUTE 0dB SMUTE 0dB Attenuation Level at SDTO -∞dB (2) (1) (1) Notes: (1) Transition time. 1024OLRCK cycles (1024/fso). (2) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and returned to 0dB by the same cycle. Figure 8. ■ IIR 3 (32kHz, 44.1kHz, 48kHz) Mode 0 1 2 3 (50/15µs ) DEM1 DEM0 De-emphasis filter L L 44.1kHz L H OFF 48kHz H L 32kHz H H Table 4. De-emphasis filter control MS0337-J-06 2010/04 - 11 - [AK4121A] ■ AK4121A (PDN) “L” PDN=“L” SDTO=“L” PDN pin “L” Table 5 “L” Case 1 External clocks (input port) don’t care (state1) (state2) don’t care SDTI don’t care (state1) (state2) don’t care External clocks (output port) don’t care (state1) (state2) don’t care PDN ta tb (1) (internal state) Power-down SDTO PLL lock & fs detection “0” data normal operation normal data PD PLL lock & fs detection “0” data normal operation Power-down normal data “0” data Case 2 External clocks (input port) (no clock) (state1) don’t care SDTI (don’t care) (state1) don’t care External clocks (output port) (don’t care) (state1) don’t care PDN (1) PLL Unlock (internal state) Power-down SDTO PLL lock & fs detection “0” data normal operation Power-down normal data “0” data Note: (1) <100ms for recommended value 2, <200ms for recommended value 1. (Figure 11) Figure 9. ta 10ms 10ms< Table 5. tb <100ms <200ms ta MS0337-J-06 tb 2010/04 - 12 - [AK4121A] ■ AK4121A 100ms ■ AK4121A Figure10 External clocks (Input port or Output port) Clocks 1 Don’t care Clocks 2 < 10msec PDN pin < 100ms (Internal state) Normal operation Power-down PLL lock & fs detection SDTO SMUTE (recommended) Att.Level Note1 Normal data Note2 Normal operation Normal data 1024/fso 1024/fso 0dB - ∞dB Figure10 Note 1. SDTI “0” Note 2. PDN pin “L” “0” SMUTE 1024/fso+100msSDTI SMUTE pin=“H” PDN pin “H” “0” Note 3. PDN pin MS0337-J-06 GD ~ ms - 13 - 2010/04 [AK4121A] ■ AVSS VDD VDD pin DVSS 10μF TVDD pin 0.1μF 0.1μF ■ PLL FILT pin (C2) 560ohm AVSS (R) 4.7μF (Figure 11) (C1) FILT pin 1.0nF AK4121A FILT R C2 C1 AVSS Parameter Recommended value 1 Recommended value 2 R 560ohm +/−8% 1.2kohm +/−8% C1 4.7μF +/−40% 2.2μF +/−40% C2 1.0nF +/−40% 2.2nF +/−40% FSI range 8k ~ 96kHz 16k ~ 96kHz Note 14. Those recommended values include temperature dependence. Figure 11. MS0337-J-06 2010/04 - 14 - [AK4121A] ■ AK4121A ILRCK Figure 12 0.01UIpp Figure 12 AK4121A Jitter Tolerance 10.00 Amplitude [UIpp] 1.00 (3) 0.10 (2) 0.01 (1) 0.00 1 10 100 1000 10000 Jitter Frequency [Hz] (1) (2) (3) (−50dB ) Note 15. 1UI (Unit Interval) ILRCK 1 FSI = 48kHz 1UI 1/48kHz = 20.8μs Figure 12. ■ ILRCK (FSI) PLL PLL AK4121 AK4121A 23%/sec MS0337-J-06 0.14%/sec 23%/sec 2010/04 - 15 - [AK4121A] Figure 13 Figure 14 + 10u 0.1u 560 4.7u +3.3V Analog 1.0n VDD FILT 0.1u AVSS DVSS PDN TVDD +3.3~5V Digital (*1) MCLK SMUTE Control DEM0 fsi DSP1 Mode setting (fix to “H” or “L”) AK4121A DEM1 OBICK ILRCK SDTO IBICK ODIF1 SDTI ODIF0 IDIF0 CMODE2 IDIF1 CMODE1 IDIF2 CMODE0 Figure 13. fso OLRCK ( DSP2 ) + 10u 0.1u 560 4.7u +3.3V Analog 1.0n VDD FILT 0.1u AVSS DVSS PDN TVDD SMUTE MCLK Control DEM0 fsi DSP1 Mode setting (fix to “H” or “L”) Figure 14. AK4121A OLRCK DEM1 OBICK ILRCK SDTO IBICK ODIF1 SDTI ODIF0 IDIF0 CMODE2 IDIF1 CMODE1 IDIF2 CMODE0 ( +3.3~5V Digital (*1) 256fso fso 64fso DSP2 : MCLK=256fso) *1. TVDD MS0337-J-06 2010/04 - 16 - [AK4121A] 24pin VSOP (Unit: mm) 1.25±0.2 *7.9±0.2 13 A 7.6±0.2 *5.6±0.2 24 12 1 0.65 0.22±0.1 0.15 +0.1 -0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 0-10° NOTE: Dimension "*" does not include mold flash. ■ : : : ( ) MS0337-J-06 2010/04 - 17 - [AK4121A] AKM AK4121AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code MS0337-J-06 2010/04 - 18 - [AK4121A] Date (YY/MM/DD) 04/08/27 07/06/05 Revision 00 01 Reason Page Contents ILRCK Edge to IBICK “↑” ILRCK=8kHz ~ 32kHz: 1/256fs+45 ILRCK=32kHz ~ 48kHz: 1/256fs+25 ILRCK=48kHz ~ 96kHz: 1/256fs+15 6 13 07/07/25 02 13 07/09/14 03 6 6 08/03/05 04 9 08/04/09 05 5 10/04/30 06 13 MS0337-J-06 ■ ■ ILRCK Edge to IBICK “↑” max ILRCK Frequency =8kHz ~ 32kHz: 16/256fs ILRCK Frequency =32kHz ~ 48kHz: 16/256fs ILRCK Frequency =48kHz ~ 96kHz: 16/256fs ILRCK Edge to IBICK “↑” Symbol tBLR→tLRB IBICK “↑” to ILRCK Edge Symbol tLRB→tBLR OLRCK Edge to OBICK “↑” Symbol tBLR→tLRB OBICK “↑” to OLRCK Edge Symbol tLRB→tBLR Note 13. DC Power Supply Current (VDD+TVDD) VDD =3.3V → VDD=TVDD=3.3V VDD= 3.6V → VDD=TVDD=3.6V ■ Note 2010/04 - 19 - [AK4121A] z z z z z z MS0337-J-06 2010/04 - 20 -