ASAHI KASEI [AKD4121A] AKD4121A AK4121A Evaluation Board Rev.0 GENERAL DESCRIPTION The AKD4121A is the evaluation board for the AK4121A, 96kHz asynchronous sample rate converter. This board has the optical connectors to interface with other digital audio equipments and serial interfaces for AKM AD/DA evaluation boards. The AKD4121A achieves quick evaluation of AK4121A Ordering guide AKD4121A --- Evaluation board for AK4121A FUNCTION Optical fiber connectors (for Digital Audio Interface. input x 1, output x 1.) 10pin Header (for AKM AD/DA evaluation board. input x 1, output x 1.) On board X’tal Oscillator (input x 1, output x 1.) 5V or 3.3V T1 48M003F JACK +3.3V REG D5V OUT IN GND JP10 3.3V JP1 IMCLK PORT1 JP11 Bypass OUT JP6 DIT-SOURCE IN IMCLK IBICK ILRCK SDTI +3.3V 3 +3.3V 10pin Header PORT2 DIR D5V JP5 SRC-MCLK D5V DIR 3 PORT3 PORT3 JP2 ~ 4 3 OMCLK OBICK OLRCK SDTO 10pin Header 3 Clock Generator DIT (AK4112B) Optical Input PORT3 +3.3V AK4121A 2 D5V PORT4 3 3 JP7~9 3 DIT (AK4114) Optical Output 2 3 SW1 PDN SW2 SMUTE SW3 fsi-DIR SW4 CMODE SW5 fso Figure 1. AKD4121A Block Diagram *Circuit diagram and PCB layout are attached at the end of this manual. <KM088800> 2007/03 -1- ASAHI KASEI [AKD4121A] Evaluation Board Manual Contents Operating Sequence --------------------------------------------------------------------------------------- p. 3 1. Jumper Setting for Power Supply: JP10(REG) 2. Power Supply Line Setting 3. DIP switch and Jumper pin Setting 4. Power-on DIP switch and Jumper pin Setting -----------------------------------------------------------------1. Setting of fsi (input fs) block -------------------------------------------------------------------------1-1. In case of using optical Input. 1-2. All clock are fed through the 10-pin port. 1-3. SDTI is fed through the 10-pin port and others are fed from the DIR(AK4112B). 2. Setting of fso (output fs) block ---------------------------------------------------------------------2-1. In case of providing clock from DIT. 2-2. In case of providing clock from 10pin PORT 2-2-1. AK4121A Master Mode. 2-2-2. AK4121A Slave Mode. 3. Bypass Mode --------------------------------------------------------------------------------------------------4. Setting of the others -------------------------------------------------------------------------------------4-1. De-emphasis filter. 4-2. Soft Mute. Jumper List p. 4 p. 4 p. 9 p.22 p.22 --------------------------------------------------------------------------------------------------- p.21 DIP switch list --------------------------------------------------------------------------------------------------- p.21 Toggle switch list --------------------------------------------------------------------------------------------- p.22 LED ---------------------------------------------------------------------------------------------------------------- p.22 Measurement Results Important Notice --------------------------------------------------------------------------------------- p.23 --------------------------------------------------------------------------------------------- p.29 Circuit diagram PCB layout <KM088800> 2007/03 -2- ASAHI KASEI [AKD4121A] Operating Sequence Please use the AKD4121A according to the following sequence. 1. Jumper Setting for Power Supply: JP10(3.3V) The JP10 (3.3V) selects power supply of the AKD4121A.(3.3V or 5V.) JACK : REG : Providing power supply voltage with 3.3V. Opticlal input is not avaible. Providing power supply voltage with 5V. (3.3V is supplied via regulator on board.) 2. Power Supply Line Setting Each supply line should be distributed directly from the power supply unit with low impedance connection. 5V or 3.3V : For power supply jack. 5V or 3.3V. (Power supply voltage is selectrd by JP10.) GND : Groung of the board. 0V. 3. DIP Switch and Jumper Pins Setting (refer next page) 4. Power-on(After power is on, SW1 should be reset by setting "L"→"H" once.) * The reset is done by SW1 during opertion. The AK4121A is powered down during SW1 is “L”.The power down state is canceld by briging the SW1 to “H”, at the same time, the AK4121A is reset. <KM088800> 2007/03 -3- ASAHI KASEI [AKD4121A] DIP switch and Jumper pin setting 1. Setting of fsi (input fs) block 1-1. Optical input(PORT2) 1-1-a. Jumper setting Parts No. Setting JP1 (don’t care) JP2 SHORT JP3 SHORT JP4 SHORT SW3-4 OFF X1 (don’t care) Table 1. Jumper Setting (Refer following figures) JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Figure 2. Jumper Setting MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 1-1-b. Audio Interface Format setting(IIS only) 1 2 3 4 5 fsi-DIR SW3 1/2MCLK Figure 3. DIP switch (SW3) setting <KM088800> 2007/03 -4- ASAHI KASEI [AKD4121A] 1-2. All clock are fed through the 10-pin port 1-2-a. Jumper setting Parts No. Setting JP1 (don’t care) JP2 OPEN JP3 OPEN JP4 OPEN SW3-4 (don’t care) X1 (don’t care) Table 2. Jumper Setting (Refer following figures) JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Figure 4. Jumper Setting 1-2-b. Audio Interface Format setting SRC:AK4121A SW3-1 SW3-2 SW3-3 DIF2 DIF1 DIF0 0 0 0 16bit, Right justified 0 0 1 20bit, Right justified 0 1 0 Left justified 2 0 1 1 IS 1 0 0 24bit, Right justified Table 3. DIP switch (SW3) setting(Refer following figures) MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 Audio Interface Format 1 2 3 4 5 1 2 3 4 5 fsi-DIR SW3 fsi-DIR SW3 1/2MCLK 16bit, Right justified 1/2MCLK 20bit, Right justified <KM088800> 2007/03 -5- 1 2 3 4 5 fsi-DIR SW3 1/2MCLK I2S MCLK Left justified DIR-CM0 MCLK 1 2 3 4 5 fsi-DIR 1/2MCLK SW3 IDIF2 IDIF1 IDIF0 DIR-CM0 IDIF2 IDIF1 IDIF0 MCLK DIR-CM0 [AKD4121A] IDIF2 IDIF1 IDIF0 ASAHI KASEI 1 2 3 4 5 fsi-DIR SW3 1/2MCLK 24bit, Right justified Figure 5. DIP switch Setting <KM088800> 2007/03 -6- ASAHI KASEI [AKD4121A] 1-3. SDTI is fed through the 10-pin port and other clocks are fed from the AK4112B. The X1(X’tal) or external clock (via PORT1) can be used as the system clock of the input block. Please remove X1 when unsed. The system clock can be selected as 256fsi or 512fsi. This clock is not used for the AK4121A directly. 1-3-a. Jumper setting Parts No. Setting OPEN: Using X’tal JP1 IN : System clock providing from 10port JP2 SHORT JP3 OPEN JP4 SHORT Table 4. DIP switch (SW3) setting(Refer following figures) JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Using X’tal setting JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Using external clock Figure 6. Jumper Setting <KM088800> 2007/03 -7- ASAHI KASEI [AKD4121A] DIP SW3 setting DIR-CM0 OCKS0 SW3-4 SW3-5 1 256fs ON 1/2 MCLK 2 512fs ON MCLK Table 5. DIR(AK4112B)’s clock setting(Refer following figures) MCLK 1 2 3 4 5 1 2 3 4 5 fsi-DIR SW3 DIR-CM0 IDIF2 IDIF1 IDIF0 MCLK DIR-CM0 X’tal / External clock (Max: 24.576MHz) IDIF2 IDIF1 IDIF0 No. fsi-DIR 1/2MCLK SW3 1/2MCLK MCLK:256fsi MCLK:512fsi Figure 7. DIP SW(SW3) setting(Refer following figures) 1-3-b Audio Interface Format setting Refer “1-2-b Refer Audio Interface Format setting” <KM088800> 2007/03 -8- ASAHI KASEI [AKD4121A] 2. Setting of fso (output fs) block 2-1. Optical Output(PORT4). Clocks are fed from AK4114 (DIT). (IIS Master Mode only.) The X2(X’tal) or external clock via PORT3 can be used as the system clock of the output block. Please remove X2 when unused. 2-1-a. Jumper setting Parts No. JP5 Setting DIT OPEN: Using X’tal on board JP6 PORT3: Clock input form PORT3 (DIR: Using clock from DIR for Bypass Mode) JP7 SHORT JP8 SHORT JP9 SHORT JP11 OPEN Table 6. Jumper setting(Refer following figures) JP5 JP8 JP6 DIT PORT3 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK JP9 JP7 OLRCK ILRCK JP11 10pin Bypass Output Using on-board X’tal JP5 JP8 JP6 DIT PORT3 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK JP9 JP7 OLRCK ILRCK JP11 10pin Bypass Using External Clock Output Figure 8. Jumper setting <KM088800> 2007/03 -9- ASAHI KASEI [AKD4121A] 2-1-b. DIP SW setting CMODE SW4 fso 1/2 MCLK SW5 CMODE SW4 256fso ODIF1 ODIF0 MCLK DEM1 DEM0 1 2 3 4 5 CMODE1 1 2 3 CMODE0 CMODE2 1 2 3 4 5 ODIF1 ODIF0 MCLK DEM1 DEM0 CMODE1 CMODE0 SW4-1 SW4-2 SW4-3 SW5-3 CMODE2 CMODE1 CMODE0 OCKS0 256fs L L L 1/2 MCLK 512fs L H L MCLK Table 7. Clock setting(Refer following figures) CMODE2 X2 or External Clock 1 2 3 fso 1/2 MCLK SW5 512fso Figure 9. DIP switch setting <KM088800> 2007/03 - 10 - ASAHI KASEI [AKD4121A] 2-2. Clocks are fed through the 10-pin port(PORT3) 2-2-1. AK4121A in Master Mode 2-2-1-a. Jumper setting Parts No. Setting JP5 PORT3 JP6 OPEN JP8 OPEN JP9 OPEN JP7 OPEN JP11 OPEN Table 8. Jumper setting(Refer following figures) JP5 JP8 JP6 DIT PORT3 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK JP9 JP7 OLRCK SDTO JP11 10pin Bypass Output Using X’tal on-board Figure 10. Jumper setting 2-2-1-b. Audio Interface Format Mod e 0 1 2 3 SW4-1 CMODE2 L L L L SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 L L 256fso (fso~96kHz) Master L H 384fso (fso~96kHz) Master H L 512fso (fso~48kHz) Master H H 768fso (fso~48kHz) Master Table 9. AK4121A System Clock setting <KM088800> 2007/03 - 11 - ASAHI KASEI SW5-2 SDTO Format OBICK (Slave) OBICK (Master) ODIF0 L 16bit LSB Justified 64fs 64fs H 20bit LSB Justified 64fs 64fs L 20bit MSB Justified 64fs ≥40fs 2 H 20bit I S Compatible 64fs ≥40fs or 32fs Table 10. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK 0 1 2 3 SW5-1 ODIF1 L L H H ODIF1 ODIF0 MCLK Mode [AKD4121A] 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 16bit, Right justified 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 I2S Left justified Figure 11. DIP switch setting <KM088800> 2007/03 - 12 - ASAHI KASEI [AKD4121A] 2-2-2. AK4121A in Slave Mode 2-2-2-a. Jumper setting Parts No. Setting JP5 PORT3 JP6 OPEN JP8 OPEN JP9 OPEN JP7 OPEN JP11 OPEN Table 11. Jumper setting(Refer following figures) JP5 JP8 JP6 DIT PORT3 PORT3 DIR SRC-MCLK OBICK DIT-SOURCE JP9 JP7 OLRCK SDTO JP11 10pin Bypass Output Using External Clock Figure 12. Jumper setting 2-2-2-b. Audio Interface Format DEM1 DEM0 CMODE1 SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 L L Not used. Set to DVSS Slave Table 12. AK4121A System Clock setting CMODE0 SW4-1 CMODE2 H CMODE2 Mod e 4 1 2 3 4 5 CMODE SW4 Figure 13. DIP switch setting <KM088800> 2007/03 - 13 - ASAHI KASEI SW5-2 SDTO Format OBICK (Slave) OBICK (Master) ODIF0 L 16bit LSB Justified 64fs 64fs H 20bit LSB Justified 64fs 64fs L 20bit MSB Justified 64fs ≥40fs H 20bit I2S Compatible 64fs ≥40fs or 32fs Table 13. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK 0 1 2 3 SW5-1 ODIF1 L L H H ODIF1 ODIF0 MCLK Mode [AKD4121A] 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 16bit, Right justified 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 I2S Left justified Figure 14. DIP switch setting <KM088800> 2007/03 - 14 - ASAHI KASEI [AKD4121A] 3. Bypass Mode In case of Bypass Mode, please set DIP switch (SW3) as follows. DEM1 DEM0 CMODE1 SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 H H Not used. Set to DVSS Master(Bypass) Table 14. AK4121A System Clock setting CMODE0 SW4-1 CMODE2 H CMODE2 Mod e 7 1 2 3 4 5 CMODE SW4 Figure 13. DIP switch setting 3-1. Setting of input block 3-1-1. Optical Input(PORT2) 3-1-1-a. Jumper setting Parts No. Setting JP1 OUT JP2 SHORT JP3 SHORT JP4 SHORT X1 (don’t care) Table 15. Jumper setting(Refer following figures) JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Figure 14. Jumper setting MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 3-1-1-b. Audio Interface Format setting (IIS only) 1 2 3 4 5 fsi-DIR SW3 1/2MCLK Figure 15. DIP switch (SW3) setting <KM088800> 2007/03 - 15 - ASAHI KASEI [AKD4121A] 3-1-2. All clock are fed through the 10-pin port 3-1-2-a. Jumper setting Parts No. Setting JP1 OUT JP2 OPEN JP3 OPEN JP4 OPEN X1 (don’t care) Table 16. Jumper setting(Refer following figures) JP1 JP2 JP3 JP4 IBICK SDTI ILRCK OUT IN IMCLK Figure 16. Jumper setting 3-1-2-b. Audio Interface Format MCLK IDIF2 IDIF1 IDIF0 MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 SW3-3 DIF0 0 1 0 1 0 DIR-CM0 SRC:AK4121A SW3-1 SW3-2 DIF2 DIF1 0 0 16bit, Right justified 0 0 20bit, Right justified 0 1 Left justified 2 0 1 IS 1 0 24bit, Right justified Table 17. DIP switch (SW3) setting Audio Interface Format 1 2 3 4 5 1 2 3 4 5 fsi-DIR SW3 fsi-DIR SW3 1/2MCLK 16bit, Right justified 1/2MCLK 20bit, Right justified <KM088800> 2007/03 - 16 - MCLK DIR-CM0 IDIF2 IDIF1 IDIF0 MCLK DIR-CM0 [AKD4121A] IDIF2 IDIF1 IDIF0 ASAHI KASEI 1 2 3 4 5 1 2 3 4 5 fsi-DIR SW3 fsi-DIR SW3 1/2MCLK I2S MCLK DIR-CM0 Left justified IDIF2 IDIF1 IDIF0 1/2MCLK 1 2 3 4 5 fsi-DIR SW3 1/2MCLK 24bit, Right justified Figure 17. DIP switch (SW3) setting <KM088800> 2007/03 - 17 - ASAHI KASEI [AKD4121A] 3-2. Setting of output block 3-2-1. Optical Output(PORT4). Clock are fed from AK4114 (DIT). (IIS Master Mode only.) 3-2-1-a. Jumper setting Parts No. JP8 JP9 JP7 JP5 JP6 JP11 X2 JP5 Setting SHORT SHORT SHORT (don’t care) DIR OPEN Remove Table 18. Jumper setting JP8 JP6 DIT PORT3 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK JP9 JP7 OLRCK ILRCK JP11 10pin Bypass (don’t care) Output Figure 18. Jumper setting DIP SW5 setting OCKS0 SW5-3 1/2 MCLK MCLK ODIF1 ODIF0 MCLK 1 2 DIP SW3 setting OCKS0 SW3-5 256fs 1/2 MCLK 512fs MCLK Table 19. DIR/DIT Clock setting X1or External Clock (PORT1) (Max: 24.576MHz) ODIF1 ODIF0 MCLK No. 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 MCLK:256fso MCLK:512fso Figure 19. DIP switch setting <KM088800> 2007/03 - 18 - ASAHI KASEI [AKD4121A] 3-2-2. Clock are fed through the 10-pin port(PORT3) 3-2-2-a. Jumper setting parts No. JP8 JP9 JP7 JP5 JP6 JP11 X2 JP5 setting OPEN OPEN OPEN (don’t care) OPEN OPEN (don’t care) Table20. Jumper setting JP8 JP6 DIT PORT3 PORT3 DIR DIT-SOURCE SRC-MCLK OBICK JP9 JP7 OLRCK ILRCK JP11 10pin Bypass (don’t care) Output Figure 20. Jumper setting 3-2-2-b. Audio Interface Format ODIF1 ODIF0 MCLK 0 1 2 3 SW5-1 SW5-2 SDTO Format OBICK (Master) ODIF1 ODIF0 L L 16bit LSB Justified 64fs L H 20bit LSB Justified 64fs H L 20bit MSB Justified 64fs H H 20bit I2S Compatible 64fs Table 21. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK Mode 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 16bit, Right justified 1 2 3 1 2 3 fso 1/2 MCLK SW5 fso 1/2 MCLK SW5 I2S Left justified Figure 21. DIP switch setting <KM088800> 2007/03 - 19 - ASAHI KASEI [AKD4121A] 4. The other setting 4-1. De-emphasis filter SW4-4 and SW4-5 control the de-emphasis filter. SW4-4 SW4-5 De-emphasis filter DEM1 DEM0 L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table22. De-emphasis filter setting Mode 0 1 2 3 4-2. Soft Mute Toggle switch SW2 controls the soft mute. SW2 Soft Mute SMUTE 0 OFF OFF 1 ON ON Table23. Soft Mute setting Mode <KM088800> 2007/03 - 20 - ASAHI KASEI [AKD4121A] Jumper List No. Jumper Name Default 10 3.3V REG 1 IMCLK IN 2, 3, 4 IBICK, ILRCK, SDTI Short 5 SRC-MCLK DIT 6 DIT-SORUCE Open 11 10 pin Bypass Output Open OBICK, OLRCK, SDTO Short 7, 8, 9 Function Power supply select for AKD4121A REG : Power supply for AKD4121A is 5V. The VDD(3.3V) of AK4121A is supplied from the regulator. JACK : Power supply for AKD4121A is 3.3V. Optical link is NOT available. MCLK select for fsi port. IN on-board X’tal(X1). OUT : external clock. Input select for fsi port. Open : PORT2 clock. Short : DIR clock. MCLK select for fso port. DIT : DIT (AK4114) clock. PORT3 : external clock. DIT-SORUCE select. Open on-board X’tal(X2). DIR : DIR(AK4112B) clock. PORT3: PORT3 clock. Bypass mode select. Short : Setting for bypass mode. Open : for other modes. Output select for fso port. Open : Use only PORT3. Not use DIT (AK4114) clock. Short : Use DIT clock. <KM088800> 2007/03 - 21 - ASAHI KASEI [AKD4121A] DIP switch list SW3(fsi-DIR) No. Switch Name 1, 2, 3 IDIF2, 1, 0 Default OFF, ON, ON (IIS) 4 DIR-CM0 OFF (Optical) 5 MCLK 1/2MCLK MCLK SW4(CMODE) No. Switch Name 1, 2, 3 CMODE2, 1, 0 4, 5 DEM1, 0 SW5(fso) No. Switch Name 1,2 ODIF1, 0 MCLK 1/2MCLK 3 Function fsi data format. Refer Table 3. DIR clock mode. ON : X’tal mode OFF : Optical mode DIR MCLK select. MCLK : 512fs 1/2MCLK : 256fs Default Function OFF, ON, OFF System clock selects. Refer Table 9, Table 12 and Table 14 (Master, 512fso) OFF, ON (off) De-emphasis control. Refer Table 12. Default ON, ON (IIS) MCLK Function fso data format. Refer Table 10. DIT MCLK select. MCLK : 512fs 1/2MCLK : 256fs Toggle switch list (SW1 and SW2) SW1 is reset switch for AK4121A, AK4112B(DIR) and AK4114(DIT). Set to “H” during Normal operation. Bring to “L” once after the power is supplied. SW2 is SMUTE control switch. Refer Table 23. LED Bright when ERF pin of AK4112B goes to “H”. This indicates the UNLOCK state, etc. (Refer AK4112B datasheet). <KM088800> 2007/03 - 22 - ASAHI KASEI [AKD4121A] MEASUREMENT RESULTS [Measurement Conditions] Measurement unit VDD TVDD Input Data Output Data Interface Parameter THD+N DR DR : : : : : : Audio Precision System Two Cascade 3.3V 5V 44.1kHz, 20bit, I2S 48kHz; 20bit, I2S Optical fiber Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB Measurement filter fs/2 fs/2 fs/2, A-weighted Results −113.5 dB 115.2 dB 117.6 dB <KM088800> 2007/03 - 23 - ASAHI KASEI [AKD4121A] AK4121 SRC FFT (fsi=44.1kHz, fso=48kHz; fin=1kHz, 0dBFS input) AK4121A FFT points 16384, Avg.=8, Window=Equiripple AKM +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz AK4121 SRC FFT (fsi=44.1kHz, fso=48kHz; fsi=1kHz, -60dBFS input) AK4121A FFT points 16384, Avg.=8, Window=Equiripple AKM +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz <KM088800> 2007/03 - 24 - ASAHI KASEI [AKD4121A] AK4121A AK4121 SRC THD+N vs. Input Frequency (fsi=44.1kHz, fso=48kHz; 0dBFS input) AKM -90 -92.5 -95 -97.5 -100 -102.5 -105 d B F S -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz AK4121A AK4121 SRC THD+N vs. Input Frequency (fsi=44.1kHz, fso=48kHz; -60dBFS input) AKM -90 -92.5 -95 -97.5 -100 -102.5 -105 d B F S -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 100 200 500 1k 2k 5k Hz <KM088800> 2007/03 - 25 - ASAHI KASEI [AKD4121A] AK4121 SRC THD+N vs. Input Level (fsi=44.1kHz, fso=48kHz; fin=1kHz) AK4121A AKM -100 -102 -104 -106 -108 -110 -112 d B F S -114 -116 -118 -120 -122 -124 -126 -128 -130 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS AKM AK4121A AK4121 SRC Linearity (fsi=44.1kHz, fso=48kHz; fin=1kHz) +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS <KM088800> 2007/03 - 26 - ASAHI KASEI [AKD4121A] AKM AK4121 SR C Frequency Response (fsi=44.1kHz, fso=48kHz, 0dBFS input) AK4121A -0.15 -0.16 -0.17 -0.18 -0.19 d B F S -0.2 -0.21 -0.22 -0.23 -0.24 -0.25 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k Hz AK4121A AK4121 Frequency Response (Blue:fsi=48kHz, Red:fsi=96kHz) VDD=3.3V, TVDD=5.0V, fso=48kHz -0 -1 -2 fsi=48kHz -3 -4 -5 d B F S -6 -7 fsi=96kHz -8 -9 -10 -11 -12 -13 -14 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz <KM088800> 2007/03 - 27 - ASAHI KASEI AKM [AKD4121A] AK4121A AK4121 Frequency Response (Blue:fsi=44.1kHz, Red:fsi=48kHz, Gray:fsi=96kHz) VDD=3.3V, TVDD=5.0V, fso=44.1kHz -0 -2 fsi=44.1kHz -4 -6 fsi=48kHz -8 d B F S -10 -12 -14 -16 fsi=96kHz -18 -20 -22 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz <KM088800> 2007/03 - 28 - ASAHI KASEI [AKD4121A] Revision History Date (YY/MM/DD) 07/03/22 Manual Revision KM088800 Board Revision 0 Reason Contents First Edition IMPORTANT NOTICE • These products and their specifications are subject to change without Notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM088800> 2007/03 - 29 - 5 4 3 2 1 5V or 3.3V L1 10u 3 JP10 3.3V JACK D 220k 220k IBICK ILRCK SDTI IMCLK 220k 3 IN R1 IMCLK IBICK ILRCK SDTI 1 2 3 4 5 C29 0.1u 10 9 8 7 6 + C30 47u 1 OUT IN 2 D5V + C31 47u C32 0.1u C1 0.1u 10k R31 R30 R29 D5V 100 100 100 100 GND PORT1 R21 R22 R23 R24 2 3 JP1 REG 1 1 OUT D T1 TA48M033F 2 +3V R2 +3V C2 10u short + C + C4 10u 1 DVDD CM0/CDTO 28 2 DVSS CM1/CDTI 27 3 TVDD OCKS1/CCLK 26 4 V/TX OCKS0/CSN 25 5 XTI MCKO1 24 6 XTO MCKO2 23 7 PDN DAUX 22 BICK 21 C6 open 1 2 PDN U5A C7 open U5B 3 74HC14 H 4 74HC14 8 C8 0.1u R 18k 2 SW1 PDN B AK4112B R4 1 3 L MCLK12 X1 22.5792MHz R3 10k 2 DIR-OCKS1 U1 D5V 1 C C5 0.1u D5V D1 HSU119 DIR-CM0 C3 0.1u 9 +3V C9 10u + AVDD SDTO AVSS LRCK JP2 SDTO12 IBICK JP3 LRCK12 SDTI JP4 20 C10 0.1u 10 BCK12 19 ILRCK R5 L2 47u 11 D5V C11 0.1u PORT2 6 6 5 5 GND VCC GND OUT + U5C RX1 ERF 18 470 C12 10u D5V 4 3 2 1 DIR1 5 RX2/DIF0 FS96 17 13 RX3/DIF1 P/S 16 14 RX4/DIF2 AUTO 15 SDTI B ILRCK R6 6 74HC14 12 IBICK 1k LED1 ERF D5V A A Title Size A3 Date: 5 4 3 2 AKD4121A Document Number Rev 0 AK4112B Tuesday, March 20, 2007 Sheet 1 1 of 3 5 4 3 OMCLK D PORT3 3 PORT3 OMCLK OBICK OLRCK SDTO SRC-MCLK SRC-MCLK D5V 220k 220k 220k R32 R34 DIT-MCLK R33 1 DIT 1 10PIN-PORT3 JP5 2 2 R25 R26 R27 R28 R8 100 100 100 100 10k 1 2 3 4 5 10 9 8 7 6 D JP11 1 MCLK12 10pin Bypass DIR Output (OPEN X'tal) DIR R7 JP6 +3V 2 short C13 10u DIT-SOURCE + 3 PORT3 C14 0.1u C15 + XTO X2 0.47u DIT 24.576 MHz C R9 18k RX3 AVSS RX2 TEST1 RX1 AVSS RX0 AVSS VCOM R AVDD INT1 48 47 46 45 44 43 42 41 40 39 38 37 OPEN 2 C C16 XTI 1 OPEN C17 1 2 3 4 5 6 7 8 9 10 11 12 D5V U3 AK4114 INT0 OCKS0/CSN OCKS1/CCLK CM1/CDTI CM0/CDTO PDN XTI XTO DAUX MCKO2 BICK SDTO 36 35 34 33 32 31 30 29 28 27 26 25 DIT-OCKS1 D5V PDN XTI XTO TVDD DVSS TX0 TX1 BOUT COUT UOUT VOUT DVDD DVSS MCKO1 LRCK +3V IPS0/RX4 AVSS DIF0/RX5 TEST2 DIF1/RX6 AVSS DIF2/RX7 IPS1/IIC P/SN XTL0 XTL1 VIN SDTI14 JP7 BCK14 JP8 LRCK14 JP9 SDTO SDTO OBICK OBICK OLRCK SDTO OBICK OLRCK 13 14 15 16 17 18 19 20 21 22 23 24 OLRCK B B DIT-MCLK PORT4 5 5 6 6 IN VCC IF GND TOTX176 4 3 2 1 C22 10u +3V D5V C18 10u + C20 0.1u + C19 0.1u OPT D5V R10 1k C21 0.1u A A Title Size A3 Date: 5 4 3 2 AKD4121A Document Number Rev 0 AK4114 Tuesday, March 20, 2007 Sheet 1 2 of 3 5 4 3 2 1 R11 560 1 D C25 4.7u D5V FLIT VDD 24 C26 1.0n 2 AVSS DVSS 23 U4 R12 10k PDN R13 1 3 + C23 10u C27 0.1u 3 PDN TVDD 22 D5V 4 SMUTE MCLK 21 SRC-MCLK 5 DEM0 OLRCK 20 OLRCK 6 DEM1 OBICK 19 OBICK SDTO U2D 9 ON D +3V C24 0.1u 1k OFF 8 74HC14 SW2 SMUTE 2 + DEM0 C28 1u DEM1 AK4121A ILRCK IBICK C SDTI IDIF0 IDIF1 IDIF2 7 ILRCK SDTO 18 8 IBICK ODIF1 17 9 SDTI ODIF0 16 10 IDIF0 CMODE2 15 11 IDIF1 CMODE1 14 12 IDIF2 CM0DE0 13 ODIF1 C ODIF0 CMODE2 CMODE1 CMODE0 D5V B B SW4 10 9 8 7 6 SW3 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 1 2 3 4 5 10 9 8 7 6 R43 R44 R45 R46 R47 47k 47k 47k 47k 47k CMODE2 CMODE1 CMODE0 DEM1 DEM0 ODIF1 1 ODIF0 2 CMODE2 CMODE1 CMODE0 DEM1 DEM0 MCLK SW5 6 5 4 3 fso CMODE 1/2MCLK fsi-DIR R38 R39 R40 R41 R42 1 2 3 4 5 R35 R36 R37 47k 47k 47k 47k 47k 47k 47k 47k 1/2MCLK ODIF1 ODIF0 DIT-OCKS1 IDIF2 IDIF1 IDIF0 DIR-CM0 DIR-OCKS1 A A Title Size A3 Date: 5 4 3 2 AKD4121A Document Number Rev 0 AK4121A Thursday, March 22, 2007 Sheet 1 3 of 3