[AK4103A] AK4103A 192kHz 24-Bit DIT AK4103A 192kHz IEC60958, S/PDIF, EIAJ CP1201 (DIT) AK4103A AK4103A AES3, 8 192kHz AES3, IEC60958, S/PDIF, EIAJ CP1201 CRCC & , RS422 & & 16 : 128fs, 256fs, 384fs, 512fs : / /I2S 4 TTL ( ) : 4.75 ∼ 5.25V I/F : 24 VSOP Ta: -40 ∼ 85 °C MS0251-J-01 2009/01 -1- [AK4103A] BICK SDTI C1 U1 Biphase Encoder Register V1 MUX VDD VSS TRANS BLS Prescaler Audio Serial Interface RS422 Line Driver LRCK MCLK CKS0 CKS1 DIF0 DIF1 DIF2 ■ TXP TXN FS0 FS1 CRCC Generator FS2 FS3 MS0251-J-01 PDN ANS CDTO CDTI CCLK CSN Host Serial Interface 2009/01 -2- [AK4103A] ■ AK4103AVF AKD4103A -40 ∼ +85°C 24pin VSOP (0.65mm pitch) Evaluation Board for AK4103A ■ V1 1 24 U1 TRANS 2 23 DIF2 PDN 3 22 DIF1 MCLK 4 21 DIF0 SDTI 5 20 TXP BICK 6 19 TXN LRCK 7 18 VSS FS0/CSN 8 17 VDD FS1/CDTI 9 16 CKS1 FS2/CCLK 10 15 CKS0 FS3/CDTO 11 14 BLS C1 12 13 ANS Top View ■ AK4103 Function Ambient Temperature CRCC generation by FS3-0 pins. CRCC generation by FS3-0 bits. Synchronous mode Asynchronous mode O: CRCC X: CRCC MS0251-J-01 AK4103 -10 ~ 70°C X X AK4103A -40 ~ 85°C O O 2009/01 -3- [AK4103A] No. 1 2 V1 TRANS I/O I I ( 0: 1: 3 PDN ) ( I ) & “L” ( ) TXP/N “L” 4 5 6 MCLK SDTI BICK I I I/O SDTI pin 7 LRCK 8 FS0 CSN I I AKMODE I DIF2-0 I/O L/R 0 DIF2-0 ( ) ( ) ( ) ( AK4112B ( ) ) ( 0: 9 AKM FS1 CDTI I I 1 FS2 CCLK I I 2 FS3 CDTO I O 3 12 13 C1 ANS I I 14 BLS I/O 10 11 , 1: AK4112B ( ( ( ) ) ( ) ) ( ( ) ) ) ( ( ) ) ( ( ( ) ) ) ( 0: (Asynchronous) , 1: 4 PDN pin = “L” 15 16 17 18 19 20 21 22 23 24 CKS0 CKS1 VDD VSS TXN TXP DIF0 DIF1 DIF2 U1 I I O O I I I I BLS pin 0 1 , 4.75V∼5.25V , 0V ( (Synchronous) ( “H” MS0251-J-01 ) ) “H” ( ( 0 1 2 Note 1. Note 2. ) ( ( ( ( 43kΩ (typ) ) ) ) ) ) ) 2009/01 -4- [AK4103A] (VSS=0V; Note 3) Parameter Power Supply Input Current (All pins except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 ±10 VDD+0.3 85 150 Units V mA V °C °C Note 3. : (VSS=0V; Note 3) Parameter Power Supply Symbol VDD min 4.75 typ 5.0 max 5.25 Units V : DC (Ta=25°C; VDD=4.75~5.25V) Parameter Power Supply Current (fs=108kHz, Note 4) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Except TXP/N pins: Iout=-400µA) (TXP/N pins: Iout= -8mA) Low-Level Output Voltage (Except TXP/N pins: Iout= 400µA) (TXP/N pins: Iout= 8mA) Input Leakage Current Symbol IDD VIH VIL min Note 4. 3mA(typ)@fs=48kHz, 9mA(typ)@fs=192kHz. 20mA(typ) PDN pin = “L”, TRANS pin = “H” 350μA(typ) MS0251-J-01 2.4 - typ 6 - max 15 0.8 Units mA V V VOH VOH VDD-1.0 VDD-0.8 - - V V VOL VOL Iin - - 0.4 0.6 ±10 V V μA VSS 2009/01 -5- [AK4103A] (Ta=25°C; VDD=4.75~5.25V; CL=20pF) Parameter Master Clock Timing Frequency Duty Cycle LRCK Timing Frequency Duty Cycle at Slave Mode Duty Cycle at Master Mode Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” BICK “↑” to LRCK Edge SDTI Hold Time SDTI Setup Time Master Mode BICK Frequency BICK Duty BICK “↓” to LRCK SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN “↑” to CDTO Hi-Z Power-down & Reset Timing PDN Pulse Width Note 5. Note 6. CDTO pin LRCK Symbol min fCLK dCLK fs dLCK typ max Units 3.584 40 27.648 60 MHz % 28 45 192 55 kHz % % 50 (Note 5) (Note 5) tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS fBCK dBCK tMBLR tSDH tSDS (Note 6) 36 15 15 15 15 8 8 ns ns ns ns ns ns ns 64fs 50 -20 20 20 tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 80 80 50 50 520 50 50 tPDW 150 20 45 70 Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns BICK MS0251-J-01 2009/01 -6- [AK4103A] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK = tCLKH x fCLK x 100 = tCLKL x fCLK x 100 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL ( ) LRCK 50%VDD tMBLR 50%VDD BICK tSDS tSDH VIH SDTI VIL ( MS0251-J-01 ) 2009/01 -7- [AK4103A] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDH tCDS C1 CDTI C0 * * VIH VIL Hi-Z (with pull-down resistor) CDTO WRITE/READ tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z (with pull-down resistor) CDTO WRITE VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD CDTO Hi-Z (with pull-down resistor) D7 READ D6 D5 50%VDD 1 MS0251-J-01 2009/01 -8- [AK4103A] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 READ D0 50%VDD 2 tPDW RESETN VIL & MS0251-J-01 2009/01 -9- [AK4103A] ■ AK4103A AES3, IEC60958, S/PDIF, EIAJ CP1201 CMOS (asynchronous) (synchronous) 2 “ / ” ■ PDN pin 8 BICK MCLK LRCK ■ MCLK LRCK MCLK ( DSP MCLK LRCK ( ) LRCK ) BICK LRCK (128fs x 3) MCLK CKS1 0 0 1 1 CKS0 0 1 0 1 MCLK 128fs 256fs 384fs 512fs Fs 28k-192kHz 28k-108kHz 28k-54kHz 28k-54kHz Table 1. MCLK ■ (Asynchronous) 1. (Asynchronous) ANS pin (Synchronous) ( ) “L” 16 24 4 RS422 CRCC AES3 MS0251-J-01 2009/01 - 10 - [AK4103A] 2. (Synchronous) ( ) 16 24 RS422 2-1. ( ) ANS pin = TRANS pin = “H” ( (C) ) (U) (V) (B) C,U,V C bit “H” ANS AK4112B TRANS pin = “H”, ANS pin = “L” Pin TRANS L L L H H H L H CRCC FS0/CSN pin AKMODE pin AKM “L” Modes Synchronous/Asynchronous Source for C, U and V bits Audio Routing Asynchronous mode C Pin ORed Control Register U Pin ORed Control Register V Pin ORed Control Register Normal mode (Test mode) Normal mode Audio routing mode Synchronous mode C,U and V pin Table 2. BLS C (or U,V) C(R191) C(L0) C(R0) C(L1) C(L31) C(R31) C(L32) L0 R0 L1 L31 R31 LRCK (except I2S) LRCK (I2S) SDTI R191 Figure 1. L32 (AKMODE pin = “0”) MS0251-J-01 2009/01 - 11 - [AK4103A] BLS C (or U,V) C(R191) C(L0) C(R0) C(L1) C(L31) C(R31) C(L32) LRCK SDTI (except I2S) R190 L191 R191 L0 L30 R30 L31 SDTI (I2S) L191 R191 L0 R0 R30 L31 R31 Figure 2. (AKMODE pin = “1”) ■ 2 (TRANS pin = “L”) 2BICK 0 “H” 32 ( ) (ANS pin = TRANS pin = “H”) Lch BICK I2S LRCK 1 “H” BICK Figure 3 Lch LRCK 2 (except I S) (n-1)th channel 1 nth channel 1 LRCK 2 (I S) (n-1)th channel 1 nth channel 1 BICK (1) Figure 3. “(1)” “nth channel 1” MS0251-J-01 1 2009/01 - 12 - [AK4103A] ■ C, U, V (TRANS pin = “L”) C, U, V bit ( ) Figure 4 ( LRCK 2 “0” Figure 5 ) (ANS pin=TRANS pin= “H”) CUV bit Mode 5 7 DIF mode CUV bit LRCK Mode 5 7(I2S) CUV bit Figure 6 Figure 7 BICK LRCK V bit BICK Channel1 Channel 2 BICK Channel 1 C,U,V C,U,V Previous Channel 2 C, U, V Figure 4. Normal, DIF modes 0/1/2/3/4/6 LRCK Channel 1 Channel 2 BICK Channel 1 C, U, V C,U,V Previous Channel 2 C, U, V Figure 5. Normal, DIF modes 5 and 7 (I2S) LRCK Channel 1 Channel 2 BICK C,U,V Channel 1 C, U, V Channel 2 C, U, V Figure 6. Audio routing, DIF modes 0/1/2/3/4/6 MS0251-J-01 2009/01 - 13 - [AK4103A] Channel 1 LRCK Channel 2 BICK Channel 1 C, U, V C,U,V Channel 2 C, U, V Figure 7. Audio routing, DIF modes 5 and 7 (I2S) ■ (BICK) (LRCK) LRCK L (SDTI) 3 SDTI DIF2-0 pin R DIF2-0 pin 24 16 I2S Mode 0 1 2 3 4 5 6 7 BICK OR AK4103A DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 SDTI 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S Master / Slave Slave Slave Slave Slave Slave Slave Master Master Table 3. LRCK H/L (I) H/L (I) H/L (I) H/L (I) H/L (I) L/H (I) H/L (O) L/H (O) BICK 32fs-128fs (I) 36fs-128fs (I) 40fs-128fs (I) 48fs-128fs (I) 48fs-128fs (I) 50fs-128fs (I) 64fs (O) 64fs (O) [NOTE: (I): Input, (O): Output] LRCK(i) 0 1 2 15 16 17 15 14 30 31 0 1 2 15 16 17 30 31 15 14 1 0 0 1 BICK(i) 1 0 SDTI(i) 15:MSB, 0:LSB Rch Data Lch Data Figure 8. Mode 0 MS0251-J-01 2009/01 - 14 - [AK4103A] LRCK(i) 0 1 2 13 14 15 17 16 30 31 0 1 2 13 14 15 30 31 17 16 1 0 12 13 30 31 19 18 1 0 10 11 30 31 21 20 0 1 0 1 0 1 BICK(i) 1 0 SDTI(i) 17:MSB, 0:LSB Rch Data Lch Data Figure 9. Mode 1 LRCK(i) 0 1 2 11 12 13 19 18 30 31 0 1 2 11 BICK(i) 1 0 SDTI(i) 19:MSB, 0:LSB Rch Data Lch Data Figure 10. Mode 2 LRCK(i) 0 1 8 9 10 11 30 31 23 22 21 20 1 0 0 1 8 9 23 22 BICK(i) 1 0 SDTI(i) 23:MSB, 0:LSB Rch Data Lch Data Figure 11. Mode 3 MS0251-J-01 2009/01 - 15 - [AK4103A] LRCK 0 1 2 21 22 23 21 2 1 0 30 31 0 1 2 21 22 23 21 2 1 0 30 31 0 1 BICK 23 22 23 22 23 22 SDTI(i) 23:MSB, 0:LSB Rch Data Lch Data Figure 12. Mode 4/6 Mode 4: LRCK, BICK: Input Mode 6: LRCK, BICK: Output LRCK 0 1 2 3 23 22 21 22 23 24 2 1 0 31 0 1 2 3 22 23 24 3 2 1 0 31 0 1 BICK SDTI(i) 23 22 23 23:MSB, 0:LSB Rch Data Lch Data Figure 13. Mode 5/7 Mode 5: LRCK, BICK: Input Mode 7: LRCK, BICK: Output MS0251-J-01 2009/01 - 16 - [AK4103A] ■ 3 3 3-0 0 FS3-0 pin 7-6 4 6- FS3-0 pin Sampling Frequency 44.1kHz Not Indicated 48kHz 32kHz 22.05kHz Reserved 24kHz Reserved 88.2kHz Reserved 96kHz Reserved 176.4kHz Reserved 192kHz Reserved FS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 4. ( FS[3:0] Fs 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not Defined 44.1kHz 48kHz 32kHz Not Defined Not Defined Not Defined Not Defined For vectoring 22.05kHz 88.2kHz 176.4kHz 192kHz 24kHz 96kHz Not Defined Table 5. Byte 3 Bits 3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Byte 0 Bits 7-6 00 01 10 11 00 00 00 00 00 00 00 00 00 00 00 00 ( MS0251-J-01 ) Byte 4 Bits 6-3 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 0011 0001 0010 1111 ) 2009/01 - 17 - [AK4103A] ■ TX Figure 14 192 2 32 2 0 Figure 15 1 16 8 M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub-frame Frame 191 Sub-frame Frame 0 Frame 1 Figure 14. 0 1 1 0 0 0 1 0 Figure 15. Figure 16 0-3 3 (B) 1 (M) 0 (W) 1 2 2 Table 6 27 MSB 2 0 4-27 16 28 29 24 4-11 “H” 192 0 191 192 31 191 0 0 1 30 0 4-31 3 4 L S Sync B Audio sam ple 27 28 29 30 31 M S V U C P B Figure 16. (fs) L 64 A 1 2 Preamble B M W Preceding state = 0 11101000 11100010 11100100 R B 1 Preceding state = 1 00010111 00011101 00011011 Table 6. MS0251-J-01 2009/01 - 18 - [AK4103A] ■ AK4103A RS422 ±20% 110Ω RS422 (S/PDIF) 75Ω ±20% 100Ω AES3 2∼7Vpp 110Ω 56Ω 0.5Vpp±20% 56 0.1u 330Ω Transformer TXP XLR Connector TXN Figure 17. 330 0.1u Transformer TXP RCA Phono Connector 100 TXN Figure 18. MS0251-J-01 2009/01 - 19 - [AK4103A] ■ 4 pins 4 CSN , CCLK, CDTI, CDTO 18 AK4103A AK4103A A7-0 bits C1-0 bits Figure 19 “11” R/W bit CDTI pin D7-0 bits CDTO pin C1-0 bits “1” “0” D7-0 bits CSN pin = “L” CCLK CCLK CCLK CDTO CCLK 5MHz CSN 0 1 2 3 4 5 6 * * * * * 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 20 21 CCLK CDTI WRITE C1 C0 Hi-Z (with pull-down resistor) CDTO CDTI READ CDTO R/W A7 C1 C0 * * * * * R/W A7 A6 “L” A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D1 Hi-Z (with pull-down resistor) C1-C0: R/W: *: A7-A0: D7-D0: D1 D0 D0 Hi-Z Chip Address (Fixed to “11”) READ/WRITE (0:READ, 1:WRITE) Don’t care Register Address Control Data Figure 19. μP AK4103A CSN CCLK CDTI CDTO CSN1 CCLK CDTI CDTO CSN2 AK4103A CSN CCLK CDTI CDTO Figure 20. Typical connection with μP Note: CDTO pin MS0251-J-01 2009/01 - 20 - [AK4103A] ■ Addr 00H 01H 02H 03H 04H 05H Register Name Clock/Format Control Validity/fs Control A-channel C-bit buffer for Byte 0 A-channel C-bit buffer for Byte 1 A-channel C-bit buffer for Byte 2 A-channel C-bit buffer for Byte 3 06H09H B-channel C-bit buffer for Byte 0-3 0AH0DH A-channel U-bit buffer for Byte 0-3 0EH11H B-channel U-bit buffer for Byte 0-3 D7 CRCE 0 D6 DIF2 0 D5 DIF1 0 D4 DIF0 V1 D3 CKS1 FS3 D2 CKS0 FS2 D1 MUTEN FS1 D0 RSTN FS0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 CB7 … CB31 UA7 … UA31 UB7 … UB31 … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … Table 7. … … … … CB0 … CB24 UA0 … UA24 UB0 … UB24 Notes: (1) A Lch B Rch (2) DIF2-0, CKS1-0 bits (3) 12H∼FFH (4) PDN pin = “L” OR MS0251-J-01 2009/01 - 21 - [AK4103A] ■ Addr 00H Register Name Clock/Format Control R/W Default D7 CRCE R/W 1 D6 DIF2 R/W 0 D5 DIF1 R/W 0 D4 DIF0 R/W 0 D3 CKS1 R/W 0 D2 CKS0 R/W 0 D1 MUTEN R/W 1 D0 RSTN R/W 1 RSTN: 0: TXP pin 1: “H” TXN pin BLS pin & TXP, TXN pins “L” (Default) BLS pin CKS1-0: (Table 1) Default: “00” (Mode 0: MCLK=128fs) CKS1-0 bits DIF2-0: CRCE: “H” OR (Table 3) ) OR Default: “000” (Mode 0: 16bit DIF2-0 bits CRCC 0: CRCC 1: (Default) Addr 01H “H” (Default) MUTEN: 0: 1: “L” Register Name Validity/fs Control R/W Default FS3-0: Default: “0000” ( CRCC D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 (Table 4, Table 5) “44.1kHz” D4 V1 R/W 0 D3 FS3 R/W 0 D2 FS2 R/W 0 D1 FS1 R/W 0 “ D0 FS0 R/W 0 ”) V1: 0: Valid (Default) 1: Invalid MS0251-J-01 2009/01 - 22 - [AK4103A] Addr 02H 06H Register Name A-channel C-bit buffer for Byte 0 B-channel C-bit buffer for Byte 0 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 D7 D6 D5 D4 D3 D2 D1 D0 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D7 D6 D5 D4 D3 D2 D1 D0 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 C0-7: Channel Status Byte 0 Default: “00100000” Addr 03H 07H Register Name A-channel C-bit buffer for Byte 1 B-channel C-bit buffer for Byte 1 R/W Default C8-15: Channel Status Byte 1 Default: “00000000” Addr 04H Register Name A-channel C-bit buffer for Byte 2 R/W Default CA16-23: Channel Status Byte 2 for A-channel Default: “00001000” Addr 08H Register Name B-channel C-bit buffer for Byte 2 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CB16-23: Channel Status Byte 2 for B-channel Default: “00000100” Addr 05H 09H Register Name A-channel C-bit buffer for Byte 3 B-channel C-bit buffer for Byte 3 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 C24-31: Channel Status Byte 3 Default: “01000000” MS0251-J-01 2009/01 - 23 - [AK4103A] Addr Register Name 0AH0DH A-channel U-bit buffer for Byte 0-3 0EH11H B-channel U-bit buffer for Byte 0-3 R/W Default D7 UA7 … UA31 UB7 … UB31 R/W 0 D6 … D5 … D4 … D3 … D2 … D1 … … … … … … … … … … … … … … R/W 0 … R/W 0 … R/W 0 … R/W 0 … R/W 0 … R/W 0 D0 UA0 … UA24 UB0 … UB24 R/W 0 U0-31: User Data Default: all “0” ■ CRCE DIF2-0 CKS1-0 V1 FS3-0 MUTEN RSTN Channel Status Byte0 - Bit0 - Bit1 - Bit2 - Bit3-5 - Bit6-7 Byte1 - Bit0-7 Byte2 - Bit0-3 - Bit4-7 1 000 00 0 0000 1 1 0 0 1 000 00 00000000 0000 1000 0100 Byte3 - Bit0-3 0100 - Bit4-5 00 - Bit6-7 00 User Data All zeros Table 8. CRCC 16bit, MCLK=128fs Valid fs=44.1kHz Mode 0 : General : :A :B fs=48kHz : MS0251-J-01 2009/01 - 24 - [AK4103A] 24pin VSOP (Unit: mm) *7.8±0.15 1.25±0.2 13 A 12 1 0.22 7.6±0.2 *5.6±0.2 24 +0.10 –0.05 0.65 0.15±0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ MS0251-J-01 2009/01 - 25 - [AK4103A] AKM AK4103AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code Date (YY/MM/DD) 03/07/28 09/01/09 Revision 00 01 Reason Page Contents 25 ( MS0251-J-01 ) 2009/01 - 26 - [AK4103A] • • • ( ) • • • MS0251-J-01 2009/01 - 27 -