データシート

[AK5578]
= Preliminary =
AK5578
8-Channel Differential 32-bit  ADC
1.
8kHz  768kHz
AK5578
32-bit A/D
AK5578
8
A/D
120dB
110dB
4
S/(N+D)
TDM
123dB
DSP
2.


:
 S/(N+D):
 DR, S/N:


:







:
:
:
TDM I/F:
:
8kHz  768kHz
110dB
120dB (Mono Mode: 123dB)
LPF 4
,
HPF
4.75~ 5.25V (
), 1.7~1.98V or 3.0  3.6V (
PCM
24-bit/32-bit
, I2S or TDM
DSD
DSD Native 64, 128, 256
16ch/48kHz, 8ch/96kHz, 4ch/192kHz
&
)
:
:
:
:3-wire Serial and I2C μP I/F(
)
606 mW (@AVDD=5.0V, TVDD=3.3V, fs=48kHz)
64-pin QFN
Rev. 0.2
2015/05
-1-
[AK5578]
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
3.
.................................................................................................................................................. 1
.................................................................................................................................................. 1
.................................................................................................................................................. 2
.......................................................................................................................................... 3
......................................................................................................................................... 3
............................................................................................................................ 4
............................................................................................................................................. 4
............................................................................................................................................. 5
........................................................................................................ 7
....................................................................................................................................... 8
....................................................................................................................................... 8
....................................................................................................................................... 9
..................................................................................................................................... 10
ADC
(fs = 48kHz)....................................................................................................... 10
ADC
(fs = 96kHz)....................................................................................................... 12
ADC
(fs = 192kHz)..................................................................................................... 14
ADC
(fs = 384kHz)..................................................................................................... 16
ADC
(fs = 768kHz)..................................................................................................... 17
DC
.......................................................................................................................................... 18
.......................................................................................................................... 19
................................................................................................................................ 26
........................................................................................................................................ 32
......................................................................................................................... 32
....................................................................................................................................... 32
...................................................................................................... 32
............................................................................................................................ 32
....................................................................................... 35
HPF (PCM Mode) .......................................................................................................... 47
CH Power Down & Mono Mode (PCM Mode, DSD Mode) ............................................................. 47
(PCM Mode) .................................................................................... 47
(PCM Mode , DSD Mode) .......................................................................... 48
DSD
................................................................................................................................... 48
DSD
.................................................................................................................... 49
LDO .................................................................................................................................................. 50
............................................................................................... 51
................................................................................................................. 53
........................................................................................... 53
................................................................................................................................ 57
............................................................................................................................ 57
............................................................................................................................. 60
..................................................................................................................................... 63
....................................................................................................................................... 63
............................................................................................................................ 63
....................................................................................................................................... 63
...................................................................................................................... 64
........................................................................................................................ 64
........................................................................................................................................ 65
Rev. 0.2
2015/05
-2-
[AK5578]
4.
VREFL4
VREFH4
VREFL3
VREFH3
VREFL2
VREFH2
VREFL1
VREFH1
■
TVDD
AIN1P
Delta-Sigma
Modulator
VDD18
DVSS
LDO
Voltage Reference
AIN1N
LDOE
Decimation
Filter
HPF
DIF0/DSDSEL0
DIF1/DSDSEL1
AIN2P
AIN2N
AIN3P
AIN3N
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
BICK/DCLK
LRCK/DSDOL1
TDMIN/DSDOR1
SDTO1/DSDOL2
SDTO2/DSDOR2
AIN4P
AIN4N
AIN5P
AIN5N
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
Serial Output
Interface
SDTO3/DSDOL3
SDTO4/DSDOR3
DSDOL4
DSDOR4
DP
AIN6P
AIN6N
AIN7P
AIN7N
AIN8P
AIN8N
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
TDM0
TDM1
AVDD1
AVSS1
PS/CAD0_SPI
CKS0/SDA/CDTI
CKS1/CAD0_I2C/CSN
CKS2/SCL/CCLK
CKS3/CAD1
Controller
AVDD2
I2C
DCKS/HPFE
OVF
MSN
PW0
PW1
PW2
SD/PMOD
SLOW/DCKB
TEST1
TEST2
MCLK
PDN
AVSS2
Figure 1. AK5578 Block Diagram
Rev. 0.2
2015/05
-3-
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SD/PMOD
SLOW/DCKB
CKS3/CAD1
CKS2/SCL/CCLK
CKS1/CAD0_I2C/CSN
CKS0/SDA/CDTI
OVF
DSDOR4
DSDOL4
SDTO4/DSDOR3
SDTO3/DSDOL3
SDTO2/DSDOR2
SDTO1/DSDOL2
TDMIN/DSDOR1
LRCK/DSDOL1
BICK/DCLK
[AK5578]
5.
■
DIF0/DSDSEL0
DIF1/DSDSEL1
TDM0
TDM1
PS/CAD0_SPI
I2C
DP
DCKS/HPFE
LDOE
TEST2
AIN1P
AIN1N
VREFL1
VREFH1
AIN2N
AIN2P
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
64QFN
TOP VIEW
Rev. 0.2
-432
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MSN
PW2
PW1
PW0
PDN
VDD18
DVSS
TVDD
MCLK
TEST1
AIN8P
AIN8N
VREFL4
VREFH4
AIN7N
AIN7P
Figure 2.
2015/05
[AK5578]
■
No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
AIN7P
AIN7N
VREFH4
VREFL4
AIN8N
AIN8P
TEST1
MCLK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
25
TVDD
-
26
DVSS
I
Analog Ground Pin(AIN1-4)
Analog Power Supply Pin(AIN1-4), 4.75-5.25V
Channel 3 Positive Input Pin
Channel 3 Negative Input Pin
ADC Low Level Voltage Reference Input Pin
ADC High Level Voltage Reference Input Pin
Channel 4 Negative Input Pin
Channel 4 Positive Input Pin
Channel 5 Positive Input Pin
Channel 5 Negative Input Pin
ADC High Level Voltage Reference Input Pin
ADC Low Level Voltage Reference Input Pin
Channel 6 Negative Input Pin
Channel 6 Positive Input Pin
Analog Power Supply Pin(AIN5-8), 4.75-5.25V
Analog Ground Pin(AIN5-8)
Channel 7 Positive Input Pin
Channel 7 Negative Input Pin
ADC High Level Voltage Reference Input Pin
ADC Low Level Voltage Reference Input Pin
Channel 8 Negative Input Pin
Channel 8 Positive Input Pin
TEST Enable Pin. This pin is pull down by 100kΩ internally
Master Clock Input Pin
Digital I/O Buffers and LDO Power Supply Pin
1.7~1.98V (LDOE pin= “L”) or 3.0~3.6V (LDOE pin= “H”).
Digital Ground Pin
Digital Core Power Supply Pin, 1.7-1.98V (LDOE pin= “L”)
27
VDD18
O
LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”)
28
PDN
I
29
30
31
32
PW0
PW1
PW2
MSN
I
I
I
I
33
BICK
DCLK
34
35
36
37
LRCK
I
O
O
I
DSDOL1
O
O
TDMIN
I
DSDOR1
SDTO1
DSDOL2
SDTO2
DSDOR2
O
O
O
O
O
Reset & Power Down Pin
“L”: Reset & Power down, “H” : Normal operation
Power Management Pin, Monaural/Stereo select Pin
Power Management Pin, Monaural/Stereo select Pin
Power Management Pin, Monaural/Stereo select Pin,
Master/Slave Select Pin
Audio Serial Data Clock Input Pin in PCM & Slave Mode.
This pin is pulled down by 100kΩ internally
Audio Serial Data Clock Output Pin in PCM & Master Mode
DSD Clock Output Pin in DSD Mode
Channel Clock Input Pin in PCM & Slave Mode
This pin is pulled down by 100kΩ internally
Channel Clock Output Pin in PCM & Master Mode
Audio Serial Data Output Pin for AIN1 in DSD Mode
TDM Data Input Pin in PCM Mode
This pin is pulled down by 100kΩ internally
Audio Serial Data Output Pin for AIN2 in DSD Mode
Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode
Audio Serial Data Output Pin for AIN3 in DSD Mode
Audio Serial Data Output Pin for AIN3 and AIN4 in PCM Mode
Audio Serial Data Output Pin for AIN4 in DSD Mode
Rev. 0.2
Power Down
Status
Pull Down
with 500Ω
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
L
L
L
L
2015/05
-5-
[AK5578]
No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Pin Name
SDTO3
DSDOL3
SDTO4
DSDOR3
DSDOL4
DSDOR4
OVF
CKS0
SDA
CDTI
CKS1
CAD0_I2C
CSN
CKS2
SCL
CCLK
CKS3
CAD1
SLOW
DCKB
SD
PMOD
Function
O
O
O
O
O
O
O
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
Audio Serial Data Output Pin for AIN5 and AIN6 in PCM Mode
Audio Serial Data Output Pin for AIN5 in DSD Mode
Audio Serial Data Output Pin for AIN7 and AIN8 in PCM Mode
Audio Serial Data Output Pin for AIN6 in DSD Mode
Audio Serial Data Output Pin for AIN7 in DSD Mode
Audio Serial Data Output Pin for AIN8 in DSD Mode
Analog Input Over Flow Flag Output Pin
Clock Mode Select Pin
2
Control Data I/O Pin in I C Bus Serial Control Mode
Control Data Input Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Chip Address 0 Pin in I C Bus Serial Control Mode
Chip Select Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Control Data Clock Pin in I C Bus Serial Control Mode
Control Data Clock Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Chip Address 1 Pin in I C Bus or 3-wire Serial Control Mode
Slow Roll-OFF Digital Filter Select Pin in PCM Mode
Polarity of DCLK Pin in DSD Mode
Short Delay Digital Filter Select Pin in PCM Mode
DSD Phase Modulation Mode Select Pin in DSD Mode
Audio Data Format Select Pin in PCM Mode
2
“L”: MSB justified, “H”: I S
DSD Sampling Rate Control Pin in DSD Mode
Audio Data Format Select Pin in PCM Mode
“L”: 24-bit Mode, “H”: 32-bit Mode
DSD Sampling Rate Control Pin in DSD Mode
TDM I/F Format Select Pin
* DSD
“L”
TDM I/F Format Select Pin
* DSD
“L”
Control Mode Select Pin (I2C pin = “H”)
2
“L”:I C Bus Serial Control Mode, “H” :Parallel Control Mode
Chip Address 0 Pin in 3-wire Serial Control Mode (I2C pin = “L”)
Control Mode Select Pin
“L”: 3-wire Serial Control Mode
2
“H”: I C Bus Serial Control Mode or Parallel Control Mode
DSD Mode Enable Pin
“L”: PCM Mode, “H”: DSD Mode
High Pass Filter Enable Pin
“L”: HPF Disable, “H”: HPF Enable
Master Clock Frequency Select at DSD Mode (DSD Only)
LDO Enable Pin
“L”: LDO Disable, “H”: LDO Enable
This pin is pulled down by 100kΩ internally
TEST Enable pin
Channel 1 Positive Input Pin
Channel 1 Negative Input Pin
DIF0
I
DSDSEL0
I
DIF1
I
DSDSEL1
I
TDM0
I
-
52
I/O
TDM1
I
-
-
PS
I
CAD0_SPI
I
54
I2C
I
55
DP
I
HPFE
I
DCKS
I
57
LDOE
I
58
59
60
TEST2
AIN1P
AIN1N
I
I
I
53
56
Rev. 0.2
Power Down
Status
L
L
L
L
L
L
L
Hi-z
-
-
-
-
2015/05
-6-
[AK5578]
No.
61
62
63
64
Pin Name
VREFL1
VREFH1
AIN2N
AIN2P
I/O
I
I
I
I
Function
ADC Low Level Voltage Reference Input Pin
ADC High Level Voltage Reference Input Pin
Channel 2 Negative Input Pin
Channel 2 Positive Input Pin
Power Down
Status
-
Note 1.
■
PCM Mode
Analog
Digital
AIN1~8P, AIN1~8N
VREFH1~4
VREFL1~4
TDMIN, TEST1, TEST2
SDTO1~4, DSDOL4, DSDOR4, OVF
AVDD
AVSS
DVSS
AIN1~8P, AIN1~8N
VREFH1~4
VREFL1~4
TDMIN, TDM0, TDM1, TEST1, TEST2
DSDOL1~4, DSDOR1~4, OVF
AVDD
AVSS
DVSS
DSD Mode
Analog
Digital
Note 2.
Rev. 0.2
2015/05
-7-
[AK5578]
6.
(VSS=0V; Note 3)
Parameter
(AVDD pin)
(TVDD pin)
(VDD18 pin) (Note 4)
(
)
(AIN1~8P, AIN1-8N pins)
Symbol
AVDD
TVDD
VDD18
IIN
VINA
VIND
Min.
−0.3
−0.3
−0.3
−0.3
−0.3
Max.
6.0
4.0
2.5
10
AVDD+0.3
TVDD+0.3
Ta
Ta
Tstg
−40
−40
−65
105
70
150
VSS
Note 3.
Note 4. 1.8V LDO
Unit
V
V
V
mA
V
V
°C
°C
°C
(LDOE pin= “L”) VDD18 pin
:
7.
(VSS=0V; Note 3)
Parameter
Symbol
AVDD
Min.
4.75
Typ.
5.0
Max.
5.25
Unit
V
(TVDD pin)
TVDD
1.7
1.8
1.98
V
(VDD18 pin)
(LDOE pin= “H”) (Note 7)
(TVDD pin)
VDD18
1.7
1.8
1.98
V
TVDD
VREFH
1-4
VREFL
1-4
3.0
3.3
3.6
V
4.75
5.0
5.25
V
-
AVSS
-
V
(AVDD pin)
(LDOE pin= “L”) (Note 5)
(Note 6)
Voltage
Reference
(Note 9)
“H” voltage Reference (Note 8)
“L” voltage reference
Note 3.
Note 5. LDOE pin= “L”
TVDD VDD18
AVDD TVDD
AVDD VDD18
Note 6. LDOE pin= “L”
TVDD VDD18±0.1V
Note 7. LDOE pin= “H”
LDO 1.8V
TVDD AVDD
Note 8. VREFH1~4 pin AVDD+0.1V
Note 9. VREFL1 pin
VREFL2 pin
VREFL3 pin
VREFL4 pin
{(VREFH) – (VREFL)}
Vin (Typ., @ 0dB) = 2.8  {(VREFH) – (VREFL)} / 5 [V].
AVSS
:
Rev. 0.2
2015/05
-8-
[AK5578]
8.
(
Ta= 25C; AVDD= 5.0V; TVDD= 3.3V, fs= 48kHz, BICK= 64fs;
Signal Frequency= 1kHz; 24-bit Data; Measurement frequency= 20Hz20kHz at fs= 48kHz,
40Hz40kHz at fs= 96kHz, 40Hz40kHz at fs= 192kHz)
Parameter
Min.
Typ.
Max.
Analog Input Characteristics:
Resolution
32
Input Voltage
(Note 10)
2.7
2.8
2.9
1dBFS
110
100
S/(N+D)
fs=48kHz
97
20dBFS
BW=20kHz
57
60dBFS
1dBFS
110
fs=96kHz
90
20dBFS
BW=40kHz
50
60dBFS
1dBFS
110
fs=192kHz
90
20dBFS
BW=40kHz
50
60dBFS
Dynamic Range
Stereo Mode
115
120
Mono
Mode
123
(60dBFS with A-weighted)
S/N
Stereo Mode
115
120
(A-weighted)
Mono Mode
123
Input Resistance
2.8
3.3
3.8
DSD 64fs
2
(DSD128, DSD256
Unit
bit
Vpp
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
k
)
Interchannel Isolation
(AIN1↔AIN2, AIN3↔AIN4, AIN5↔AIN6, AIN7↔AIN8)
Interchannel Gain Mismatch
Power Supply Rejection
(Note 11)
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”, LDOE pin = “H”)
AVDD
TVDD
(fs=48kHz)
TVDD
(fs=96kHz)
TVDD
(fs=192kHz)
Power Down Mode (PDN pin = “L”)
(Note 12)
AVDD+TVDD
110
120
dB
0
60
0.5
-
dB
dB
110
17
28
25
143
22
36
32
mA
mA
mA
mA
10
(n=1~8)
100
A
Note 10. ADC
(AINnP)(AINnN)
VREFHVREFL
Vin = 0.56  (VREFHmVREFLm) [Vpp]. (m=1~4)
Note 11. VREFH1~4 pin
AVDD, TVDD 1kHz, 20mVpp
Note 12.
TVDD
TVSS
Rev. 0.2
2015/05
-9-
[AK5578]
9.
■ ADC
(fs = 48kHz)
(Ta= -40  +105C; AVDD =4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.03.6V (LDOE pin= “H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 3)
(SD pin= “L”, SLOW pin= “L”)
Passband (Note 13) +0.012/0.014dB
PB
0
22.1
kHz
24.5
kHz
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
19
1/fs
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 4)
(SD pin= “L”, SLOW pin= “H”)
±0.034dB
Passband (Note 13)
PB
0
12.5
kHz
kHz
21.9
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.5
1/fs
GD
Group Delay (Note 14)
GD
7
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 5)
(SD pin= “H”, SLOW pin= “L”)
Passband (Note 13) +0.012/0.014dB
PB
0
22.1
kHz
24.4
kHz
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
5
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 6)
(SD pin= “H”,SLOW pin= “H”)
±0.034dB
Passband (Note 13)
PB
0
12.5
kHz
21.9
kHz
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
5
1/fs
Digital Filter (HPF):
Frequency Response
FR
1.0
Hz
3.0dB
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The Passband and Stopband Frequencies scale with fs.
For Example, PB (+0.012dB/0.014dB) =0.46  fs (SHARP ROLL-OFF).
For Example, PB (+0.034dB/0.034dB) =0.26  fs (SLOW ROLL-OFF).
Note 14.
ADC
SDTO Lch
MSB
+1[1/fs]
Rev. 0.2
2015/05
- 10 -
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[ dB]
[AK5578]
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[dB]
Figure 3. SHARP ROLL-OFF (fs= 48kHz)
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[ dB]
Figure 4. SLOW ROLL-OFF (fs= 48kHz)
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[dB]
Figure 5. SHORT DELAY SHARP ROLL-OFF (fs= 48kHz)
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
Figure 6. SHORT DELAY SLOW ROLL-OFF (fs=48kHz)
Rev. 0.2
2015/05
- 11 -
[AK5578]
■ ADC
(fs = 96kHz)
(Ta= -40  +105C; AVDD =4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.03.6V (LDOE pin= “H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 7)
(SD pin= “L”, SLOW pin= “L”)
44.2
Passband (Note 13) 0dB/0.06dB
0
kHz
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
19
1/fs
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 8)
(SD pin= “L”, SLOW pin= “H”)
25
Passband (Note 13) 0dB/0.074dB
0
kHz
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
7
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF (Figure 9)
(SD pin= “H”,SLOW pin= “L”)
Passband (Note 13) 0dB/0.06dB
0
44.2
kHz
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
5
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 10)
(SD pin=“H”, SLOW pin= “H”)
Passband (Note 13) 0dB/0.074dB
0
25
kHz
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
5
1/fs
Digital Filter (HPF):
Frequency Response
FR
1.0
Hz
3.0dB
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The Passband and Stopband Frequencies scale with fs.
For example, PB (0dB/0.06dB) =0.46  fs (SHARP ROLL-OFF).
For example, PB (0dB/0.074dB) =0.26  fs (SLOW ROLL-OFF).
Note 14.
ADC
SDTO Lch
MSB
+1[1/fs]
Rev. 0.2
2015/05
- 12 -
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple [dB]
[AK5578]
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[dB]
Figure 7. SHARP ROLL-OFF (fs= 96kHz)
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
Figure 8. SLOW ROLL-OFF (fs= 96kHz)
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
-60
-0.02
Gain[dB]
Ripple[dB]
Figure 9. SHORT DELAY SHARP ROLL-OFF (fs=96kHz)
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
Figure 10. SHORT DELAY SLOW ROLL-OFF (fs= 96kHz)
Rev. 0.2
2015/05
- 13 -
[AK5578]
■ ADC
(fs = 192kHz)
(Ta= -40  +105C; AVDD =4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.03.6V (LDOE pin= “H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 11)
(SD pin=“L”, SLOW pin= “L”)
83.7
Passband (Note 13) 0dB/0.04dB
0
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
15
1/fs
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 12)
(SD pin=“L”, SLOW pin= “H”)
Passband (Note 13)
0dB/0.7dB
0
31.1
kHz
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
146
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
8
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 13)
(SD pin=“H”, SLOW pin= “L”)
Passband (Note 13) 0dB/0.04dB
0
83.7
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.2
1/fs
GD
Group Delay (Note 14)
GD
6
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER (Figure 14)
(SD pin=“H”, SLOW pin= “H”)
Passband (Note 13)
0
31.1
kHz
0dB/0.7dB
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
146
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.5
1/fs
GD
Group Delay (Note 14)
GD
6
1/fs
Digital Filter (HPF):
Frequency Response
FR
1.0
Hz
3.0dB
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The Passband and Stopband Frequencies scale with fs.
For Example, PB (0dB/0.04dB) =0.436  fs (SHARP ROLL-OFF).
For Example, PB (0dB/0.7dB) =0.162  fs (SLOW ROLL-OFF).
Note 14.
ADC
SDTO Lch
MSB
+1[1/fs]
Rev. 0.2
2015/05
- 14 -
[AK5578]
0.2
10.00
0.1
0.00
0.0
-10.00
-0.1
-20.00
-30.00
-0.2
Gain[dB]
Ripple[dB]
Figure 11. SHARP ROLL-OFF (fs=192kHz)
-40.00
-0.3
-50.00
-0.4
-60.00
-0.5
-70.00
-0.6
-80.00
-0.7
-90.00
-0.8
-100.00
0
16
32
48
64
80 96 112 128 144 160 176 192
Freq[kHz]
Figure 12. SLOW ROLL-OFF (fs=192kHz)
0.2
10.00
0.1
0.00
0.0
-10.00
-0.1
-20.00
-30.00
-0.2
Gain[dB]
Ripple[dB]
Figure 13. SHORT DELAY SHARP ROLL-OFF (fs=192kHz)
-40.00
-0.3
-50.00
-0.4
-60.00
-0.5
-70.00
-0.6
-80.00
-0.7
-90.00
-0.8
-100.00
0
16
32
48
64
80 96 112 128 144 160 176 192
Freq[kHz]
Figure 14. SHORT DELAY SLOW ROLL-OFF (fs=192kHz)
Rev. 0.2
2015/05
- 15 -
[AK5578]
■ ADC
(fs = 384kHz)
(Ta= -40 ~ +105ºC; AVDD =4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.0~3.6V (LDOE pin= “H”),
VDD18= 1.7~1.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF) (Figure 15)
(SD pin = “X”, SLOW pin = “X”) * SD pin, Slow pin
Frequency Response
-0.1dB
81.75
kHz
(Note 13)
-1.0dB
114
kHz
FR
-3.0dB
137.63
kHz
-6.0dB
157.2
kHz
Stopband (Note 13)
SB
277.4
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0~ 40.0kHz
ΔGD
0
1/fs
Group Delay (Note 14)
GD
7
1/fs
Note 13. The Passband and Stopband Frequencies scale with fs.
Note 14.
ADC
SDTO Lch
MSB
+1[1/fs]
0.80
20.00
0.40
0.00
0.00
-20.00
-0.40
Gain[dB]
-60.00
-1.20
-80.00
-1.60
Gain[dB]
-40.00
-0.80
-100.00
-2.00
-120.00
-2.40
-140.00
-2.80
-3.20
-160.00
0
64
128
192
256
320
384
Freq[kHz]
Figure 15. Frequency Response (fs = 384kHz)
Rev. 0.2
2015/05
- 16 -
[AK5578]
■ ADC
(fs = 768kHz)
(Ta= -40 ~ +105ºC; AVDD =4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.0~3.6V (LDOE pin= “H”),
VDD18= 1.7~1.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF) (Figure 16)
(SD pin = “X”, SLOW pin = “X”) * SD pin, Slow pin
Frequency Response
-0.1dB
26.25
kHz
(Note 13)
-1.0dB
83.75
kHz
FR
-3.0dB
144.5
kHz
-6.0dB
203.1
kHz
Stopband (Note 13)
SB
640.3
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0~40.0kHz
ΔGD
0
1/fs
Group Delay (Note 14)
GD
5
1/fs
Note 13. The Passband and Stopband Frequencies scale with fs.
Note 14.
ADC
SDTO Lch
MSB
+1[1/fs]
0.80
20.00
0.40
0.00
0.00
-20.00
-0.40
Gain[dB]
-60.00
-1.20
-80.00
-1.60
Gain[dB]
-40.00
-0.80
-100.00
-2.00
-120.00
-2.40
-140.00
-2.80
-3.20
-160.00
0
64
128
192
256
320
384
448
512
576
640
704
768
Freq[kHz]
Figure 16. Frequency Response (fs= 768kHz)
Rev. 0.2
2015/05
- 17 -
[AK5578]
10. DC
(Ta=40~105C; AVDD=4.75~5.25V, TVDD=1.7~1.98V (LDOE pin= “L”), 3.03.6V (LDOE pin= “H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
TVDD=1.7  1.98V
VIH
80%TVDD
V
High-Level Input Voltage
(Note 15)
VIL
20%TVDD
V
Low-Level Input Voltage
(Note 15)
TVDD=3.0V  3.6V
VIH
70%TVDD
V
High-Level Input Voltage
(Note 15)
Low-Level Input Voltage
(Note 15)
VIL
30%TVDD
V
High-Level Output Voltage
(Note 16)
VOH
TVDD0.5
V
(Iout=100µA)
Low-Level Output Voltage
(Note 17)
(except SDA pin : Iout= 100µA)
VOL
0.5
V
(SDA pin, 3.0V  TVDD  3.6V: Iout= 3mA)
VOL
0.4
V
(SDA pin, 1.7V  TVDD  1.98V: Iout= 3mA)
VOL
20%TVDD
V
Input Leakage Current
Iin
10
A
Note 15. MCLK, PDN, PW0-2, MSN, BICK (Slave Mode), LRCK (Slave Mode), TDMIN, SLOW/DCKB,
SD/PMOD, CKS0/SDA (Write)/CDTI, CKS1/CAD_I2C/CSN, CKS2/SCL/CCLK, CKS3/CAD1,
DIF0/DSDSEL0, DIF1/DSDSEL1, TDM0, TDM1, PS/CAD0_SPI, I2C, DP, DCKS/HPFE, LDOE,
TEST1-2
Note 16. BICK (Master Mode)/DCLK, LRCK (Master Mode)/DSDOL1, DSDOR1, SDTO1/DSDOL2,
SDTO2/DSDOR2, SDTO3/DSDOL3, SDTO4/DSDOR3, DSDOL4, DSDOR4, SDA (Read),
OVF
Note 17. Note 16. pin
SDA
TVDD+0.3V
Rev. 0.2
2015/05
- 18 -
[AK5578]
11.
(
Ta=40+105C; AVDD= 4.75~5.25V,
TVDD=1.7~1.98V (LDOE pin= “L”), 3.03.6V (LDOE pin= “H”), VDD18= 1.71.98V (LDOE pin= “L”),
CL= 20pF)
Parameter
Symbol
Min.
Typ.
Max
Unit
Master Clock Timing (Figure 18)
fCLK
2.048
49.152
MHz
Frequency
dCLK
45
55
%
Duty Cycle
LRCK Frequency (Slave Mode) (Figure 17)
Normal Mode (TDM1-0 bits = “00”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
fsq
108
216
kHz
Quad Speed Mode
fso
384
kHz
Oct Speed Mode
fsh
768
kHz
Hex Speed Mode
Duty
45
55
%
Duty Cycle
TDM128 Mode (TDM1-0 bits = “01”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
fsq
108
216
kHz
Quad Speed Mode
tLRH
1/128fs
ns
High Time
tLRL
1/128fs
ns
Low Time
TDM256 Mode (TDM1-0 bits = “10”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
tLRH
1/256fs
ns
High time
tLRL
1/256fs
ns
Low time
TDM512 mode (TDM1-0 bits = “11”)
fsn
8
54
kHz
Normal Speed Mode
tLRH
1/512fs
ns
High Time
tLRL
1/512fs
ns
Low Time
Parameter
LRCK Frequency (Master Mode) (Figure 18)
Normal Mode (TDM1-0 bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct Speed Mode
Hex Speed Mode
Duty Cycle
TDM128 Mode (TDM1-0 bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High Time
TDM256 Mode (TDM1-0 bits = “10”)
Normal Speed Mode
Double Speed Mode
High Time
TDM512 Mode (TDM1-0 bits = “11”)
Normal Speed Mode
High Time
Symbol
Min.
fsn
fsd
fsq
fso
fsh
Duty
8
54
108
fsn
fsd
fsq
tLRH
8
54
108
fsn
fsd
tLRH
8
54
fsn
tLRH
8
Rev. 0.2
Typ.
Max.
Unit
54
108
216
kHz
kHz
kHz
kHz
kHz
%
54
108
216
kHz
kHz
kHz
ns
54
108
kHz
kHz
ns
54
kHz
ns
384
768
50
1/4fs
1/8fs
1/16fs
2015/05
- 19 -
[AK5578]
Parameter
Symbol
Audio Interface Timing (Slave Mode) (Figure 19)
Normal Mode (TDM1-0 bits = “00”)
(LDOE pin = “H”)
(8kHz fs 216kHz)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mod
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓”toSDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(LDOE pin = “L”) *
15pF
(8kHz ≤ fs ≤ 216kHz)
BICK Period
Normal Speed Mode(8kHz ≤ fs ≤ 48kHz)
Double Speed Mode(48kHz ≤ fs ≤ 96kHz)
Quad Speed Mode(96kHz ≤ fs ≤ 192kHz)
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓” to SDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(fs = 384kHz, 768kHz)
BICK Period
Oct Speed Mode
Hex Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓” to SDTO1/2/3/4
Min.
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/128fsn
1/128fsd
1/64fsq
32
32
25
25
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/128fsn
1/128fsd
1/64fsq
36
36
30
30
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fso
1/32fsh
18
18
18
18
Rev. 0.2
Typ.
Max
Unit
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
ns
ns
ns
ns
ns
ns
ns
ns
2015/05
- 20 -
[AK5578]
Parameter
Symbol
Audio Interface Timing (Slave Mode) (Figure 20)
TDM128 Mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
Quad Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM256 Mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM512 Mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup Time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
Rev. 0.2
Min.
Typ.
Max
Unit
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/512fsn
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/05
- 21 -
[AK5578]
Parameter
Symbol
Audio Interface Timing (Master Mode) (Figure 21)
Normal Mode (TDM1-0 bits = “00”)
(8kHz fs 216kHz)
BICK Period
fBCK
Normal Speed Mode
fBCK
Double Speed Mode
fBCK
Quad Speed Mod
dBCK
BICK Duty
tMBLR
BICK “↓” to LRCK Edge
tBSD
BICK “↓”to SDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(fs = 384kHz,768kHz)
BICK Period
fBCK
Oct speed Mode
fBCK
Hex speed Mode
dBCK
BICK Duty
tMBLR
BICK “↓” to LRCK Edge
tBSD
BICK “↓” to SDTO1/2/3/4
Rev. 0.2
Min.
Typ.
Max
Unit
20
20
ns
ns
ns
ns
ns
ns
5
4
ns
ns
ns
ns
ns
1/64fsn
1/64fsd
1/64fsq
50
-20
-20
1/64fso
1/64fsh
50
-5
-4
2015/05
- 22 -
[AK5578]
Parameter
Symbol
Audio Interface Timing (Master Mode) (Figure 23)
TDM128 Mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
Quad Speed Mode
tBCK
BICK Duty
dBCK
BICK “↓” to LRCK Edge
tMBLR
SDTO Setup time BICK “”
tBSS
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM256 Mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed Mode
Double Speed Mode
BICK Duty
BICK “↓” to LRCK Edge
SDTO Setup time BICK “”
SDTO Hold BICK “”
TDMIN Hold Time
TDMIN Setup Time
TDM512 Mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed Mode
BICK Duty
BICK “↓” to LRCK Edge
SDTO Setup time BICK “”
SDTO Hold BICK “”
TDMIN Hold Time
TDMIN Setup Time
tBCK
tBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
tBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
Rev. 0.2
Min.
Typ.
Max
Unit
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/128fsn
1/128fsd
1/128fsq
50
-5
5
5
5
5
1/256fsn
1/256fsd
50
-5
5
5
5
5
5
1/512fsn
50
-5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/05
- 23 -
[AK5578]
Parameter
Symbol
Min.
Audio Interface Timing (Master Mode) (Figure 24)
DSD Audio Interface Timing
(64 Mode, DSDSEL 1-0 bits = “00”)
tDCK
DCLK Period
tDCKL
144
DCLK Pulse Width Low
tDCKH
144
DCLK Pulse Width High
tDDD
-20
DCLK Edge to DSDL/R
(Note 20)
DSD Audio Interface Timing
(128 Mode, DSDSEL 1-0 bits = “01”)
tDCK
DCLK Period
tDCKL
72
DCLK Pulse Width Low
tDCKH
72
DCLK Pulse Width High
tDDD
-10
DCLK Edge to DSDL/R
(Note 20)
DSD Audio Interface Timing
(256 Mode, DSDSEL 1-0 bits = “10”)
tDCK
DCLK Period
tDCKL
36
DCLK Pulse Width Low
tDCKH
36
DCLK Pulse Width High
tDDD
-10
DCLK Edge to DSDL/R
(Note 20)
Note 18. 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs
RSTN bit
Note 19.
LRCK
BICK “”
Note 20.
DCKB= “0” default
DCLK “”
DSDL/R
DCKB= “1”
DCLK “↑”
DSDL/R
Rev. 0.2
Typ.
Max
Unit
20
ns
ns
ns
ns
10
ns
ns
ns
ns
1/64fs
1/128fs
1/256fs
10
PDN pin
ns
ns
ns
ns
tDDD
tDDD
2015/05
- 24 -
[AK5578]
Parameter
Control Interface Timing (3-Wire Serial Mode):
(Figure 26) (Figure 27)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Timing
CDTI Hold Timing
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus Mode): (Figure 28)
SCL CLOCK Frequency
Bus Free Time Between Transmissions
Start Condition Hold Tune (Prior to First Clock Pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 21)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive Load on Bus
Power Down & Reset Timing (Figure 29)
PDN Pulse Width
(Note 22)
PDN Reject Pulse Width
(Note 22)
PDN “” to SDTO1-4 valid
(Note 23)
Note 21.
300ns(SCL
)
Note 22.
PDN pin “L”
150ns
PDN pin = “L”
30ns
PDN pin= “L”
Note 23. PDN pin
LRCK
“↑”
Rev. 0.2
Symbol
Min.
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
fSCL
tBUF
tHD STA
tLow
tHIGH
tSU STA
tHD DAT
tSU DAT
tR
tF
tSU STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
tPD
tRPD
tPDV
150
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
583
400
1.0
0.3
50
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
pF
30
ns
ns
1/fs
2015/05
- 25 -
[AK5578]
■
[1]PCM Mode
1/fCLK
50%TVDD
MCLK
tdCLKH
tdCLKL
dCLK=tdCLKHfs100
or
tdCLKLfs100
1/fs
50%TVDD
LRCK
tLRH
tLRL
tBCK
Duty=tLRHfs100
or
tLRLfs100
VIH
BICK
VIL
tBCKH
tBCKL
Figure 17 Clock Timing (Slave Mode)
1/fCLK
50%TVDD
MCLK
tCLKH
tCLKL
dCLK=tCLKHfCLK100
or
tCLKLfCLK100
1/fs
VOH
50%TVDD
LRCK
Duty=tLRHfs100
tLRH
1/fBCK
50%TVDD
BICK
tBCKH
tBCKL
dBCK=tBCKHfBCK100
or
tBCKLfBCK100
Figure 18 Clock Timing (Master Mode)
Rev. 0.2
2015/05
- 26 -
[AK5578]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO1/2/3/4
50%TVDD
Figure 19 Audio Interface Timing (Normal Mode & Slave Mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSS
tBSH
SDTO1/2/3/4
50%TVDD
tSDS
tSDH
VIH
TDMIN
VIL
Figure 20 Audio Interface Timing (TDM Mode & Slave Mode)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSD
50%TVDD
SDTO1/2/3/4
Figure 21 Audio Interface Timing (Normal Mode & Master Mode, 8kHz fs
Rev. 0.2
216kHz)
2015/05
- 27 -
[AK5578]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO1/2/3/4
Figure 22 Audio Interface Timing (Normal Mode & Master Mode, fs= 384kHz, 768kHz)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO1/2/3/4
tSDS
tSDH
VIH
TDMIN
VIL
Figure 23 Audio Interface Timing (TDM Mode & Master Mode)
Rev. 0.2
2015/05
- 28 -
[AK5578]
[2] DSD Mode
tDCK
tDCKL
tDCKH
VOH
DCLK
VOL
tDDD
VOH
DSDOL1-4
DSDOR1-4
VOL
Figure 24. Audio Serial Interface Timing (Normal Mode, DCKB bit= “0” or DCKB pin= “L”)
tDCK
tDCKL
tDCKH
VOH
DCLK
VOL
tDDD
tDDD
VOH
DSDOL1-4
DSDOR1-4
VOL
Figure 25. Audio Serial Interface Timing (Phase Modulation Mode, DCKB bit= “0” or DCKB pin= “L”)
Rev. 0.2
2015/05
- 29 -
[AK5578]
[3] 3-Wire Serial Interface
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 26. WRITE Command Input Timing (3-wire Serial Mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 27. WRITE Data Input Timing (3-wire Serial Mode)
Rev. 0.2
2015/05
- 30 -
[AK5578]
[4]I2C Interface
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 28. I2C Bus Mode Timing
[5] Power-down Timing
tPD
VIH
PDN
VIL
tRP
tPDV
SDTO1/2/3/4
50%TVDD
Figure 29 Power-down & Reset Timing
Rev. 0.2
2015/05
- 31 -
[AK5578]
12.
■
AK5578
TVDD (3.3V)
TVDD
1.8V
LDO
1.8V
1.8V
LDOE pin = “H” LDO
LDOE pin= “L”
VDD18 pin
LDOE pin = “L”
1.8V
■
AK5578 PCM
DP bit
RSTN bit= “0”
PCM
DSD
PCM/DSD
PW8~1 bit = “00H”
2~3/fs
MCLK, BICK, LRCK
)
MCLK
DSD
DSD
DP pin
PW2 pin=PW1 pin=PW0 pin= “L”
SDTO1-4
PCM
DCLK, DSDOL1-4, DSDOR1-4
PCM
(
DSD
0.5
DP pin
DP bit
Interface
L
0
PCM
H
1
DSD
Table 1 PCM/DSD Mode Control
■
PCM
BICK,
PCM
MCLK
LRCK
LRCK
AK5578
MCLK
fs
BICK
LRCK
BICK pin
LRCK
pin
AK5578
MSN pin
MCLK, BICK, LRCK
MCLK
MSN pin= “H”
DSD
LRCK, BICK
MSN= “L”
MCLK
DSD
■
[1] PCM
PCM
fs
Table 2, Table 3, Table 4
fs
MCLK
AK5578
MCLK, BICK, LRCK
MCLK
MCLK
(Table 5)
CKS3-0 pin
LRCK
PDN pin
PW2 pin = PW1 pin = PW0 pin = “L”
“0”
LRCK
RSTN bit =
PW8~1 bit = “00H”
Rev. 0.2
2015/05
- 32 -
[AK5578]
32fs
48fs
64fs
96fs
128fs
MCLK
192fs
32kHz
N/A
N/A
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
192kHz
N/A
N/A
N/A
N/A
24.576
MHz
384kHz
N/A
N/A
36.864
MHz
768kHz
24.576
MHz
36.864
MHz
24.576
MHz
49.152
MHz
N/A
fs
256fs
8.192
MHz
12.288
MHz
24.576
MHz
384fs
12.288
MHz
18.432
MHz
36.864
MHz
512fs
16.384
MHz
24.576
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
N/A
N/A
N/A
36.864
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not Available)
Table 2 System Clock Example (Slave Mode)
fs
32fs
48fs
64fs
96fs
32kHz
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
192kHz
N/A
N/a
N/A
N/A
384kHz
768kHz
24.576 36.864
MHz
MHz
24.576 36.864 49.152
N/A
MHz
MHz
MHz
N/A
N/A
MCLK
128fs
192fs
256fs
384fs
512fs
8.192 12.288 16.384
N/A
N/A
MHz
MHz
MHz
12.288 18.432 24.576
N/A
N/A
MHz
MHz
MHz
24.576 36.864
N/A
N/A
N/A
MHz
MHz
24.576 36.864
N/A
N/A
N/A
MHz
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not Available)
Table 3 System Clock Example (Master Mode)
fs
MCLK
192fs
256fs
32fs
48fs
64fs
96fs
128fs
32kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
192kHz
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
768kHz
24.576 36.864
MHz
MHz
24.576 36.864
MHz
MHz
NA
N/A
24.576 36.864
MHz
MHz
384fs
24.576 36.864
MHz
MHz
512fs
16.384
MHz
24.576
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not Available)
Table 4 System Clock Example (Auto Mode)
Rev. 0.2
2015/05
- 33 -
[AK5578]
CKS3
pin(bit)
CKS2
pin(bit)
CKS1
pin(bit)
L(0)
L(0)
L(0)
L(0)
L(0)
L(0)
L(0)
L(0)
H(1)
L(0)
L(0)
H(1)
L(0)
H(1)
L(0)
L(0)
H(1)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
H(1)
L(0)
L(0)
H(1)
L(0)
L(0)
H(1)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
H(1)
H(1)
H(1)
H(1)
CKS0
pin(bit)
M/S pin
L
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
H
L
L(0)
H
L
H(1)
Table 5 MCLK
L(0)
Rev. 0.2
MCLK
Frequency
128fs
24M
192fs
36M
256fs
12M
256fs
24M
384fs
36M
384fs
18M
512fs
24M
768fs
36M
64fs
24M
32fs
24M
96fs
36M
48fs
36M
64fs
49.1M
1024fs
32M
Quad Speed Mode
108kHz  fs  216kHz
Quad Speed Mode
108kHz  fs  216kHz
Normal Speed Mode
8kHz  fs  54kHz
Double Speed Mode
54kHz  fs  108kHz
Double Speed Mode
54kHz  fs  108kHz
Normal Speed Mode
8kHz  fs  54kHz
Normal Speed Mode
8kHz  fs  54kHz
Normal Speed Mode
8kHz  fs  54kHz
Oct Speed Mode
fs = 384kHz
Hex Speed Mode
fs = 768kHz
Oct Speed Mode
fs = 384kHz
Hex Speed Mode
fs = 768kHz
Hex Speed Mode
fs = 768kHz
Normal Speed Mode
8kHz ≤ fs ≤ 32kHz
NA
NA
Auto
8kHz  fs  216kHz
fs Range
2015/05
- 34 -
[AK5578]
[2] DSD
DSD
MCLK
MCLK
DSDOR1-4
MCLK
ON
DCLK
512fs
768fs
MCLK
(PDN pin = “L”  “H”) MCLK
DSD
64fs, 128fs, 256fs
DCLK
DSDSEL1-0 pin
DSDSEL1
pin (bit)
L(0)
L(0)
H(1)
H(1)
PCM
DCKS pin(bit)
DCKS pin (bit)
MCLK Frequency
L (0)
512fs
H (1)
768fs
Table 6. System Clock (DSD Mode)
AK5578
MCLK
DSDOL1-4
DCLK
(default)
fs
32kHz,44.1kHz, 48kHz
DSDSEL1-0 bit
(Table 7)
DSDSEL0 Frequency
Mode
pin (bit)
L(0)
64fs
H(1)
128fs
L(0)
256fs
DSD Sampling Frequency
fs=32kHz
fs=44.1kHz
fs=48kHz
2.048MHz
2.8224MHz
3.072MHz
4.096MHz
5.6448MHz
6.144MHz
8.192MHz
11.2896MHz
12.288MHz
Reserved
Reserved
Reserved
(8.192MHz)
(11.2896MHz)
(12.288MHz)
Table 7. DSD Sampling Frequency Select
H(1)
(default)
■
TDM1-0 pins(bits), DIF1-0 pins(bits), SLOW pin(bit), SD pin(bit)
[1] PCM Mode
AK5578
48
Table 9)
8kHz fs
PDN pin= “L”
TDM1-0 pins(bits), MSN pin(bit), DIF1-0 pins(bits)(Table 8,
MSB
2’s
TDM1-0bits="00"
BICK
SDTO1/2/3/4
BICK
216kHz
(TDM)
TDM256
(
SDTO2 pin
SDTO4 pin
TDM512
TDM128
4
TDM0/1 pin(bit)
TDM)
AIN1 AIN2 A/D
AIN5 AIN6 A/D
48fs
DIF1 pin(bit)
( TDM)
128fs (fs=48kHz)
SDTO1 pin
SDTO3 pin
Normal, Double, Quad
A/D
bit
24-bit
(
16-bit 48fs
24-bit/32-bit
bit
16-bit
bit
24-bit
AIN3 AIN4 A/D
AIN7 AIN8 A/D
TDM)
OCT
DIF1 pin(bit)
A/D
HEX
Rev. 0.2
BICK
BICK
BICK
BICK
BICK
32-bit
32fs, 48fs, 64fs
BICK
32fs
64fs
DIF1 pin(bit)
32fs
2015/05
- 35 -
[AK5578]
(
64fs
MCLK
bit
16-bit 48fs
pin(bit) 24-bit/32-bit
LRCK
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
TDM)
Normal, Double, Quad
bit
DIF1 pin(bit) 24-bit/32-bit
( TDM)
OCT/HEX
BICK
MCLK
32fs, 48fs, 64fs
MCLK
24-bit A/D
MCLK
64fs
A/D
(MSB Justified)
Multiplex Speed TDM1 TDM0
Mode
Mode pin(bit) pin(bit)
MSN
Pin
L
Normal
Double
Quad
L(0)
L(0)
H
Normal
L
OCT
HEX
L(0)
L(0)
H
I2S
DIF1
DIF0
SDTO
pin(bit) pin(bit)
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
*
L(0)
16-bit, MSB
2
*
H(1)
16-bit, I S
*
L(0)
24-bit, MSB
2
*
H(1)
24-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
*
L(0)
16-bit, MSB
2
*
H(1)
16-bit, I S
*
L(0)
24-bit, MSB
2
*
H(1)
24-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
H(1)
H(1)
32-bit, I2S
Table 8.
(I2S Compatible)
LRCK
Pol. I/O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
BICK
Freq.
48-128fs
48-128fs
64-128fs
64-128fs
64fs
64fs
64fs
64fs
32fs
32fs
48fs
48fs
64fs
64fs
64fs
64fs
32fs
32fs
48fs
48fs
64fs
64fs
64fs
64fs
BICK
32fs
DIF1
DIF0 pin
I/O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
MCLK
Freq.
I/O
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32fs
I
32fs
I
48fs
I
48fs
I
64fs
I
64fs
I
64fs
I
64fs
I
(Normal Mode, OCT/HEX Mode)
Rev. 0.2
2015/05
- 36 -
[AK5578]
No.
Multiplex Speed TDM1 TDM0
Mode
Mode pin(bit) pin(bit)
24
25
26
Normal
27
TDM128 Double
28
Quad
29
30
31
32
33
34
35
Normal
TDM256
Double
36
37
38
39
40
41
42
43
TDM512 Normal
44
45
46
47
MSN
pin
L
L(0)
H(1)
H
L
H(1)
L(0)
H
L
H(1)
H(1)
H
DIF1
DIF0
pin(bit) pin(bit)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
Table 9
SDTO
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
LRCK
Edg. I/O
I

I

I

I

O

O

O

O

I

I

I

I

O

O

O

O

I

I

I

I

O

O

O

O

BICK
Freq. I/O
128fs
I
128fs
I
128fs
I
128fs
I
128fs
O
128fs
O
128fs
O
128fs
O
256fs
I
256fs
I
256fs
I
256fs
I
256fs
O
256fs
O
256fs
O
256fs
O
512fs
I
512fs
I
512fs
I
512fs
I
512fs
O
512fs
O
512fs
O
512fs
O
MCLK
Freq.
I/O
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
(TDM Mode)
Rev. 0.2
2015/05
- 37 -
[AK5578]
TDM Mode
TDM512 Mode
30)
SDTO1 pin
2
AK5578
AK5578
#1
MCLK 1
Table 10
MCLK
#2
MCLK ↓ 2
MCLK BICK
BICK
MCLK
MCLK=2BICK
MCLK=BICK
Table 10
BICK
(Figure
AK5578
A/D
1024fs
512fs
↑
BICK
↓
±10ns
Figure 55
Figure 56
AK5578 #1
256fs or 512fs
MCLK
48kHz
LRCK
512fs
BICK
TDMIN
GND
SDTO1
AK5578 #2
MCLK
TDMIN
LRCK
BICK
16ch TDM
SDTO1
TDM512
Figure 30.
Rev. 0.2
2015/05
- 38 -
[AK5578]
LRCK
0
1
2
11
12
13
23
24
31
0
1
2
11
12
13
23
24
31
0
1
BICK(64fs)
SDTO1-4
1
13 12 11
23 22
0
23 22
13
23: MSB, 0: LSB
AIN1/3/5/7 Data
1
12 11
0
31
AIN2/4/6/8 Data
Figure 31 Mode 0/4 Timing (Normal Mode, Normal/Double/Quad Speed Mode, MSB Justified, 24-bit)
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO1-4
23 22
2
1
0
23 22
2
23: MSB, 0: LSB
AIN1/3/5/7 Data
1
0
AIN2/4/6/8 Data
Figure 32 Mode 1/5 Timing (Normal Mode, Normal/Double/Quad Speed Mode, I2S Compatible, 24-bit)
LRCK
0
1
2
11
12
13
20
21
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO1-4
12 11
22 20 19
31 30
1
0
31 30
22
31: MSB, 0: LSB
AIN1/3/5/7 Data
12 11
20 19
1
0
31
AIN2/4/6/8 Data
Figure 33 Mode 2/6 Timing (Normal Mode, Normal/Double/Quad Speed Mode, MSB Justified, 32-bit)
LRCK
0
1
2
3
23
24
25
26
29
30
31
0
1
2
3
23
24
25
26
29
30
31
0
1
BICK(64fs)
SDTO1-4
31 30
16 15 14
3
2
1
31: MSB, 0: LSB
AIN1/3/5/7 Data
0
31 30
16 15 14
3
2
1
0
AIN2/4/6/8 Data
Figure 34 Mode 3/7 Timing (Normal Mode, Normal/Double/Quad Speed Mode, I2S Compatible, 32-bit)
Rev. 0.2
2015/05
- 39 -
[AK5578]
32 BICK
LRCK (Master)
LRCK (Slave)
BICK (32fs)
SDTO1-4 (O)
0 15 14
9
8
7
6
1
0 15 14
9
8
7
6
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
16 BICK
16 BICK
0 15 14
Figure 35. Mode 8/16 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 16-bit)
32 BICK
LRCK (Master)
LRCK (Slave)
BICK (32fs)
SDTO1-4 (O)
0 15 14
9
8
7
6
1
0 15 14
9
8
7
6
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
16 BICK
16 BICK
0 15 14
Figure 36. Mode 9/17 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 16-bit)
48 BICK
LRCK (Master)
LRCK (Slave)
BICK (48fs)
SDTO1-4 (O)
0 23 22
13 12 11 10
1
0 23 22
13 12 11 10
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
24 BICK
24 BICK
0 23 22
Figure 37. Mode 10/18 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 24-bit)
48 BICK
LRCK (Master)
LRCK (Slave)
BICK (48fs)
SDTO1-4 (O)
0 23 22
13 12 11 10
1
0 23 22
13 12 11 10
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
24 BICK
24 BICK
0 23 22
Figure 38. Mode 11/19 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 24-bit)
Rev. 0.2
2015/05
- 40 -
[AK5578]
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
23 22
15
8
7
0
23 22
15
8
7
0
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
23 22
Figure 39. Mode 12/20 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 24-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
23 22
15
8
7
0
23 22
15
8
7
0
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
23 22
Figure 40. Mode 13/21 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 24-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
0 31 30
17 16 15 14
1
0 31 30
17 16 15 14
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
0 31 30
Figure 41. Mode 14/22 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 32-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
0 31 30
17 16 15 14
1
0 31 30
17 16 15 14
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
0 31 30
Figure 42. Mode 15/23 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 32-bit)
Rev. 0.2
2015/05
- 41 -
[AK5578]
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
23 22
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23 22
SDTO3-4 (O)
Figure 43. Mode 24/28 Timing (TDM128 Mode, MSB Justified, 24-bit)
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
SDTO3-4 (O)
Figure 44. Mode 25/29 Timing (TDM128 Mode, I2S Compatible)
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
0 31 30
SDTO3-4 (O)
Figure 45. Mode 26/30 Timing (TDM128 Mode, MSB Justified)
Rev. 0.2
2015/05
- 42 -
[AK5578]
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30
SDTO2 (O)
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
0 31 30
SDTO3-4 (O)
Figure 46. Mode 27/31 Timing (TDM128 Mode, I2S Compatible)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
SDTO2-4 (O)
Figure 47. Mode 32/36 Timing (TDM256 Mode, MSB Justified, 24-bit)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
SDTO2-4 (O)
Figure 48. Mode 33/37 Timing (TDM256 Mode, I2S Compatible, 24-bit)
Rev. 0.2
2015/05
- 43 -
[AK5578]
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
Figure 49. Mode 34/38 Timing (TDM256 Mode, MSB Justified, 32-bit)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31
SDTO2-4 (O)
Figure 50. Mode 35/39 Timing (TDM256 Mode, I2S Compatible, 32-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
23 22
0
23 33
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
23 22
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
31 30
32 BICK
Figure 51. Mode 40/44 Timing (TDM512 Mode, MSB Justified, 24-bit)
Rev. 0.2
2015/05
- 44 -
[AK5578]
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
23 22
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23
32 BICK
Figure 52. Mode 41/45 Timing (TDM512 Mode, I2S Compatible, 24-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
31 30
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0
31 30
32 BICK
Figure 53. Mode 42/46 Timing (TDM512 Mode, MSB Justified, 32-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
31 30
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0
31
32 BICK
Figure 54. Mode 43/47 Timing (TDM512 Mode, I2S Compatible, 32-bit)
Parameter
MCLK “” to BICK “↓”
BICK “↓” to MCLK“”
Symbol
Min.
tMCB
tBIM
10
10
Typ.
Max
Unit
ns
ns
Table 10 TDM Mode Clock Timing
Rev. 0.2
2015/05
- 45 -
[AK5578]
VIH
MCLK
VIL
tMCB
tBIM
VIH
B ICK
VIL
Figure 55 Audio Interface Timing (Slave Mode, TDM Mode MCLK=2×BICK)
VIH
MCLK
VIL
tMCB
tBIM
VIH
B ICK
VIL
Figure 56 Audio Interface Timing (Slave Mode, TDM Mode MCLK=BICK)
[2] DSD Mode
DSD
Master Mode
DCLK
DSDSEL1-0 pins
SDSSEL1-0 bits
64fs, 128fs, 256fs
DCLK
64fs, 128fs
Phase Modulation
PMOD pin= “H”
PMOD bit= “1” Phase Modulation
256fs
Phase Modulation
DCLK
DCKB bit
DSD Mode
PCM Mode 0.5
DCLK (64fs,128fs,256fs)
DCKB bit= “1”
DCLK (64fs,128fs,256fs)
DCKB bit= “0”
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 57. DSD Mode Timing
Rev. 0.2
2015/05
- 46 -
[AK5578]
■
HPF (PCM Mode)
AK5578
DC
HPF
HPFE pin (bit) = “H”
HPF
HPF
fc
fs=48kHz(Normal Speed Mode), 96kHz(Double Speed Mode),
192kHz(Quad Speed Mode)
1Hz
fs=384kHz
fs=768kHz
DSD
HPF
HPFE
HPF ON/OFF
PDN pin= “L”
PW2-pin=PW1-pin=PW0-pin= “L”,
RSTN bit=
“0”,
PW8~1 bit= “00H”
■ CH Power Down & Mono Mode (PCM Mode, DSD Mode)
PW0/1/2 pin
(Table 11
Mono Mode
)
Mono Mode
AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8
S/N
3dB
AIN1 AIN2
1/2
SDTO1 (DSDLO1, DSDRO1) AIN1 AIN2
AIN3 AIN4
1/2
SDTO2 (DSDOL2, DSDOR2) AIN3 AIN4
AIN4 AIN5
1/2
SDTO3 (DSDOL3, DSDOR3)
AIN4 AIN5
AIN6 AIN7
1/2
SDTO4
(DSDOL4, DSDOR4) AIN6 AIN7
PW0
pin
1
1
1
1
0
0
0
0
PW1
pin
1
1
0
0
1
1
0
0
PW2
pin
1
0
1
0
1
0
1
0
Ch1
Ch2
Ch3
Ch4
Ch5
ON
ON
ON
ON
ON
CH1+2 CH1+2 CH3+4
CH3+4
CH5+6
ON
ON
ON
ON
OFF
CH1+2 CH1+2 CH3+4
CH3+4
OFF
ON
ON
ON
ON
ON
CH1+2 CH1+2 CH3+4
CH3+4
CH5+6
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
Table 11 Channel Power & Mono Mode
3
I2C
PWn (n=1-8) bit= “0”
MONO bit= “1”
AINn
■
PW1-8 bit AIN1-8
PWn (n=1-8) bit= “1”
Mono Mode
Ch6
Ch7
Ch8
ON
CH5+6
OFF
OFF
ON
CH5+6
ON
OFF
ON
CH7+8
ON
CH7+8
OFF
OFF
ON
OFF
ON
CH7+8
ON
CH7+8
OFF
OFF
OFF
OFF
AINn
(PCM Mode)
AK5578
4
SD
L
L
H
H
SD pin(bit), SLOW pin(bit)
SLOW
L
H
L
H
Table 12
Filter
Sharp Roll-off Filter
Slow Roll-off Filter
Short Delay Sharp Roll-off Filter
Short Delay Slow Roll-off Filter
Rev. 0.2
2015/05
- 47 -
[AK5578]
■
(PCM Mode , DSD Mode)
[1]PCM Mode
AK5578
AIN1~AIN8
(0.3dBFS
OVF pin
OVF
)OVF pin
“H”
”L”
ADC
[2]DSD Mode
(
)
DSD
L1
R4
1
OVF
“H”
■ DSD
DSD
Rev. 0.2
2015/05
- 48 -
[AK5578]
■ DSD
PDN pin
Internal PDN
(1)
MCLK In
Don’t care
Internal
State
Power-Down
Don’t care
Initialize
Normal Operation
Power-Down
(2)
ADC In
(Analog)
(6)
(4)
OVF-pin
(5)
(3)
DSD Out
(Digital)
“L” (-full scale data)
abnormal data
normal data
normal data
“L” (-full scale data)
Figure 58. DSD
Notes:
(1) LDOE pin= “H”
PDN
“L”
“H”
LDO
(10ms(Max.))
LDOE pin= “L”
(1ms(Max.))
Internal PDN "1"
(2) MCLK
583/fs
(3)
(4)
(5)
(6)
Internal PDN “0”
“1”
PDN
“L”
“H”
Internal PDN
DSD
“0”
“1”
“L”(-full scale data)
OVF
“H”
DSD
OVF
“L”
Rev. 0.2
2015/05
- 49 -
[AK5578]
■ LDO
TVDD
1.7~1.98V
3.0~3.6V
TVDD
LDO ON/OFF LDOE pin
(Table 13)
LDOE
PDN
LDO
VDD18 pin
L
L
OFF
1.7~1.98V
L
H
OFF
1.7~1.98V
H
L
OFF
500 Pull Down
H
H
ON
LDO
Table 13. LDO Select Mode
[1] TVDD=1.7V~1.98V
TVDD 1.7~1.98V
TVDD
VDD18
[2] TVDD=3.0V~3.6V
TVDD 3.0~3.6V
VDD18 pin
, LDO
LDO
LDO ON/OFF
TVDD pin
1.7~1.98V
1.7~1.98V
3.0~3.6V
3.0~3.6V
(LDOE pin = “L”)
VDD18 pin
0.1V
, LDO
(LDOE pin = “H”)
LDO ON
Rev. 0.2
LDOE pin= “L”
1.7 1.98V
LDO
OFF
LDO
VDD18 pin
2015/05
- 50 -
[AK5578]
■
PDN pin
“L”
PCM Mode:
PDN pin “H”
MCLK
PDN pin
MCLK
PCM Mode
SDTO
ADC
“H”
MCLK, BICK, LRCK
LRCK
MCLK
583 ᵡ fs
2’s complement
(
578 ᵡ fs
“0”
ADC
)
DSD Mode
PDN pin
“H”
MCLK
MCLK
Power
PDN pin
(1)
VDD18 pin
(2)
Internal PDN
(3)
Internal
State
Power -down
Initialize
Normal Operation
Power -down
ADC In
(Analog)
GD
(5)
(5)
GD
(4)
(4)
ADC Out
(Digital)
“0”data
“0”data
Idle Noise
Idle Noise
(6)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
Figure 59
Notes
(1) AVDD
TVDD
(2) a. LDOE pin = “H”
b. LDOE pin = “H”
/
PDN pin 150nsec
I2C pin = “H” PS pin = “H”
LDO
Internal PDN
Internal PDN
PS pin = “L”
“L”
Parallel Mode
MCLK
MCLK
16384
MCLK
Register Mode
Rev. 0.2
2015/05
- 51 -
[AK5578]
LDO
16384
(10ms(Max.))
Internal PDN
c. LDOE pin = “L”
(3)
(4)
(5)
(1ms(Max.))
583/fs
ADC
(GD)
578/fs
“0”
Internal PDN
Figure 60. Internal PDN
Rev. 0.2
2015/05
- 52 -
[AK5578]
■
AK5578
I2C pin
I2C pin
L
L
H
H
I2C
3
PS pin
PS pin
Control Mode
L
3-wire Serial
H
3-wire Serial
L
I2C Bus
H
Parallel
Table 14. Control Mode
■
(1) 3
(I2C pin = “L”)
3
I/F pin: CSN, CCLK, CDTI
I/F
Chip
address (2-bit, C1/0), Read/Write (1-bit, “1”
, Write only), Register address (MSB first, 5-bit) Control
data (MSB first, 8-bit)
CCLK “”
“”
CSN “”
CCLK
5MHz
(Max.)
PDN pin “L”
RSTN bit “0”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
*3
*PDN pin = “L”
*CSN = “L”
CCLK
Chip Address (C1=CAD1, C0=CAD0)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 61 Control I/F Timing
“” 15
17
Rev. 0.2
2015/05
- 53 -
[AK5578]
(2) I2C
AK5578
(I2C pin = “H”
PS pin = “L”)
(max:400kHz, Ver1.0)
2
IC
(2)-1. WRITE
I2C
7-bit
2-bit
(Figure 63)
Figure 62
SCL
(Start Condition)
(Figure 68)
8-bit
IC
AK5578
IC
“H”
SDA
(R/W)
CAD1-0 pins
(Acknowledge)
“H”
5-bit
“00100”
SDA
69) R/W
“0”
2
3-bit
“0”
8-bit MSB first
R/W
“L”
(Figure
“1”
(
)
(Figure 64)
3
(Figure 65) AK5578
8-bit MSB first
(Stop Condition)
“H”
SDA
“L”
SCL
“H”
(Figure 68)
AK5578
1
“07H”
“00H”
“H”
“H”
SDA
SCL
“H” “L”
(Figure 70) SCL
“L”
SDA
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
1st byte
Sub
Address(n)
A
C
K
2nd byte
Data(n)
A
C
K
Data(n+1)
A
C
K
3rd byte
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 62. I2C
0
0
1
0
0
(CAD0 pin
Figure 63. 1
0
0
0
A4
Figure 64.
D7
D6
D5
Figure 65.
CAD1
CAD0
R/W
)
A3
A2
A1
A0
D3
D2
D1
D0
2
D4
3
Rev. 0.2
2015/05
- 54 -
[AK5578]
(2)-2. READ
R/W
“1”
AK5578
READ
“14H”
“00H”
AK5578
2
READ
(2)-2-1.
AK5578
(READ
AK5578
READ
WRITE
)
“n+1”
(R/W = “1”)
“n”
1
READ
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 66. CURRENT ADDRESS READ
(2)-2-2.
READ
(R/W bit= “1”)
WRITE
WRITE
(R/W = “0”)
AK5578
(R/W bit= “1”)
READ
AK5578
1
READ
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 67. Random Address Read
Rev. 0.2
2015/05
- 55 -
[AK5578]
SDA
SCL
S
P
start condition
stop condition
Figure 68.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 69. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 70. I2C
Rev. 0.2
2015/05
- 56 -
[AK5578]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Management1
Power Management2
Control 1
Control 2
Control 3
DSD
TEST1
TEST2
D7
PW8
0
0
0
DP
0
TST7
0
D6
PW7
0
CKS3
TDM1
0
0
TST6
0
D5
PW6
0
CKS2
TDM0
0
DCKS
TST5
0
Note 24.
0AH1FH
Note 25. RSTN bit
“0”
Note 26. PDN pin
D4
PW5
0
CKS1
0
0
0
TST4
0
D3
PW4
0
CKS0
0
0
PMOD
TST3
0
D2
PW3
0
DIF1
0
0
DCKB
TST2
0
“0”
D1
PW2
MONO
DIF0
0
SD
DSDSEL1
TST1
0
D0
PW1
RSTN
HPFE
0
SLOW
DSDSEL0
TST0
TRST
“1”
CONTROL
“L”
■
Addr Register Name
D7
D6
00H Power Management1
PW8 PW7
R/W
R/W
R/W
Default
1
1
PW8-1: Power Down control for channel 8-1
0: Power OFF
1: Power ON (default)
Addr
01H
Register Name
D7
Power Management2
0
R/W
R/W
Default
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
“0”
D6
0
R/W
0
D5
PW6
R/W
1
D4
PW5
R/W
1
D3
PW4
R/W
1
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
PW3
R/W
1
D2
0
R/W
0
D1
PW2
R/W
1
D0
PW1
R/W
1
D1
MONO
R/W
0
D0
RSTN
R/W
1
MONO: Monaural Mode
0: Stereo Mode (default)
1: MONO Mode
“1”
Addr
02H
Register Name
D7
Control 1
0
R/W
R/W
Default
0
HPFE: High Pass Filter Enable
0: High Pass Filter OFF
1: High Pass Filter ON (default)
“1”
HPF
D6
CKS3
R/W
0
D5
CKS2
R/W
0
D4
CKS1
R/W
0
D3
CKS0
R/W
0
D2
DIF1
R/W
0
D1
DIF0
R/W
0
D0
HPFE
R/W
1
ON
DIF1-0:Audio Data Interface Modes Select (Table 8, Table 9)
A/D
24-bit/32-bit
MSB justified/ I2S Compatible
CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 5)
MCLK
Rev. 0.2
2015/05
- 57 -
[AK5578]
Addr
03H
Register Name
D7
D6
D5
D4
D3
Control 2
0
TDM1
TDM0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
TDM1-0: TDM Modes Select (Table 9)
A/D
Normal, TDM128, TDM256, TDM512
Addr Register Name
D7
D6
04H DSD1
DP
0
R/W
R/W
R/W
Default
0
0
SLOW: Slow Roll-off Filter Select (Table 12)
0: Sharp Roll-off (default)
1: Slow Roll-off
Roll-OFF
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D1
SD
R/W
0
D0
0
R/W
0
D0
SLOW
R/W
0
SD: Short Delay Select (Table 12)
0: Normal Delay (default)
1: Short Delay
Group Delay
DP: DSD Mode Select
0: PCM Mode (default)
1: DSD Mode
Addr Register Name
D7
D6
05H DSD
0
0
R/W
R/W
R/W
Default
0
0
DSDSEL1-0: Select the Frequency of DCLK
00: 64fs
01: 128fs (default)
10: 256fs
11: Reserved (128fs)
D5
DCKS
R/W
0
D4
0
R/W
0
D3
D2
D1
D0
PMOD DCKB DSDSEL1 DSDSEL0
R/W
R/W
R/W
R/W
0
0
0
0
DCKB: Polarity of DCLK
0: DSD data is output from DCLK Falling Edge (default)
1: DSD data is output from DCLK Rising Edge
PMOD: DSD Phase Modulation Mode
0: Not Phase Modulation Mode (default)
1: Phase Modulation Mode
DSD
Phase Modulation Mode
DCKS: Master Clock Frequency Select at DSD Mode (DSD Only)
0: 512fs (default)
1: 768fs
Rev. 0.2
2015/05
- 58 -
[AK5578]
Addr Register Name
06H
TEST1
R/W
Default
D7
TST7
RD
0
D6
TST6
RD
0
TST7-0: Test register.
default
Addr Register Name
07H
TEST2
R/W
Default
D5
TST5
RD
0
D4
TST4
RD
0
D3
TST3
RD
0
D2
TST2
RD
0
D1
TST1
RD
0
D0
TST0
RD
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
D0
TRST
W
0
bit “0”
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
0
R/W
0
TRST: Test register. This register must be “0”.
default
bit “0”
Rev. 0.2
2015/05
- 59 -
[AK5578]
13.
(AKD5578)
AIN1+
AIN1
0.1
+
Analog 5V
10
0.1
0.1
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CKS3/CAD1
CKS2/SCL/CCLK
CKS1/CAD0_I2C/CSN
CKS0/SDA/CDTI
OVF
DSDOR4
DSDOL4
SDTO4/DSDOR3
SDTO3/DSDOL3
SDTO2/DSDOR2
SDTO1/DSDOL2
TDMIN/DSDOR1
LRCK/DSDOL1
BICK/DCLK
DIF1/DSDSEL1
MSN
PW2
PW1
PW0
PDN
VDD18
DVSS
TVDD
MCLK
TEST1
AIN8P
AIN8N
VREFL4
VREFH4
AIN7N
AIN7P
OVFFUNC/TDM0
OVFRST/TDM1
PS/CAD0_SPI
I2C
DP
HPFE/DCKS
LDOE
TEST2
AIN1P
AIN1N
VREFL1
VREFH1
AIN2N
AIN2P
AK5578
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Mode
Setting
Controller
4.7
+
0.1
10
AIN8+
AIN8
0.1
+
0.1
Digital 3.3V
Mater Clock
10
Analog 5V
AIN7
AIN7+
0.1
0.1
+
AIN6
AIN6+
Analog 5V
10
0.1
0.1
10
AIN4
AIN4+
AIN5+
AIN5
Analog 5V
Analog 5V
+
0.1
0.1
0.1
+
10
0.1
+
Analog 5V
AIN3+
AIN3
10
0.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AIN2
AIN2+
DIF0/
DSDSEL0
Controller
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
Mode
Setting
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SD/PMOD 48
SLOW/DCKB 47
Mode
Setting
fs
64fs
Figure 71
Figure 71. Typical Connection Diagram
Note 27.
Rev. 0.2
2015/05
- 60 -
[AK5578]
1.
AVDD1/2, TVDD
AVDD1/2, TVDD
AVSS1/2, DVSS
PC
2.
VREFH1-4 pin VREFL1-4 pin
VREFH1-4 pin AVDD
pin
0.1µF
VREFL1-4 pin
AVSS
VREFH1-4 pin
VREFL1-4
AK5578
VREFH1-4, VREFL1-4 pin
3.
2.8Vpp(typ)
(n=1-8)
(ADC
DC
AK5578
AVSS1/20.3V
)
AK5578
2’s
AVSS1/2
AINn+ AINn
AVDD1/2
DC
HPF
+5V
10mA
AVDD1/2+0.3V
IC
15V
Rev. 0.2
2015/05
- 61 -
[AK5578]
4.
Figure 72 AK5578
gain=-14.5dB)
Figure 72
1 (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351kHz,
JP1, 2
±14.9Vpp
(AK5578: ±2.8Vpp Typ.)
DR= 120dB, S/(N+D)= 110dB
fs=48kHz
4.7k
4.7k
Analog In
620
JP1
VP+
Vin- 68µ
+
14.9Vpp
JP1, 2
1n
3.3k
Bias
VP-
10
+
2.8Vpp
AK5578 AINn+
NJM5534
NJM5534
XLR
15n
VA+
620
10k
Bias
11k
JP2
68µ
-
+
10µ
1n
3.3k
Vin+
10
AK5578 AINn-
+
0.1µ
NJM5534
Bias
VA=+5
VP=15
2.8Vpp
Figure 72.Input Buffer example1
fin
1Hz
10Hz
Frequency
1.77dB
0.02dB
Response
Table 15. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
Frequency
0.00dB
0.00dB
0.00dB
Response
Table 16. Frequency Response of LPF
Rev. 0.2
6.144MHz
49.68dB
2015/05
- 62 -
[AK5578]
14.
■
64-pin QFN (Unit mm)
■
:
:
:
■
5578EN
XXXXXXX
1
1)
2)
3)
Pin #1 indication
Date Code : XXXXXXX (7 digits)
Marketing Code : 5578EN
Rev. 0.2
2015/05
- 63 -
[AK5578]
15.
■
TBD
AK5578EN
-40
105ºC
64-pin QFN
Rev. 0.2
2015/05
- 64 -
[AK5578]
0.
1.
2.
3.
4.
5.
RoHS
6.
7.
Rev. 0.2
2015/05
- 65 -