Data Sheet

[AK5558]
= Preliminary =
AK5558
8-Channel Differential 32-bit  ADC
1. General Description
The AK5558 is a 32-bit, 768kHz sampling, differential input A/D converter for digital audio systems. It
integrates an 8-channel A/D converter, suitable for mixers and automotive amplifier units. The AK5558
achieves 115dB dynamic range and 106dB S/(N+D) in stereo mode, and 118dB dynamic range in Mono
mode while keeping low power consumption performance. Four types of digital filters are integrated and
selectable according to the sound quality preference. The AK5558 can be easily connected to a DSP by
supporting TDM audio formats.
2. Features
 Sampling Rate: 8kHz  768kHz
 Input: Full Differential Inputs
 S/(N+D): 106dB
 DR, S/N: 115dB (Mono Mode: 118dB)
 Internal Filter: Four types of LPF, Digital HPF
 Power Supply: 4.75~ 5.5V(Analog), 1.7~1.98V or 3.0  3.6V(Digital)
 Output Format
PCM mode: 24/32-bit MSB justified, I2S or TDM
DSD mode: DSD Native 64, 128, 256
 Cascade TDM I/F: 16ch/48kHz, 8ch/96kHz, 4ch/192kHz
 Operation Mode: Master & Slave Modes
 Detection Function: Input Overflow Flag
 Serial Interface: 3-wire Serial and I2C μP I/F (Pin setting is also available)
 Power Consumption: 256mW (@AVDD=5.0V, TVDD=3.3V, fs=48kHz)
 Package: 64-pin QFN
Rev. 0.2
2015/09
-1-
[AK5558]
3. Table of Contents
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents................................................................................................................................ 2
Block Diagram..................................................................................................................................... 3
■ Block Diagram.................................................................................................................................... 3
5. Pin Configurations and Functions ...................................................................................................... 4
■ Pin Configurations ............................................................................................................................. 4
■ Pin Functions ..................................................................................................................................... 5
■ Handling of Unused Pin ..................................................................................................................... 7
6. Absolute Maximum Ratings ................................................................................................................ 8
7. Recommended Operation Conditions ................................................................................................ 8
8. Analog Characteristics ........................................................................................................................ 9
9. Filter Characteristics ......................................................................................................................... 10
■ ADC Filter Characteristics (fs= 48kHz) ........................................................................................... 10
■ ADC Filter Characteristics (fs= 96kHz) ........................................................................................... 12
■ ADC Filter Characteristics (fs= 192kHz) ......................................................................................... 14
■ ADC Filter Characteristics (fs= 384kHz) ......................................................................................... 16
■ ADC Filter Characteristics (fs= 768kHz) ......................................................................................... 17
10.
DC Characteristics ........................................................................................................................ 18
11.
Switching Characteristics .............................................................................................................. 19
■ Timing Diagram ............................................................................................................................... 26
12.
Functional Descriptions ................................................................................................................. 32
■ Digital Core Power Supply ............................................................................................................... 32
■ Output Mode .................................................................................................................................... 32
■ Master and Slave Mode ................................................................................................................... 32
■ System Clock ................................................................................................................................... 32
■ Audio Interface Format .................................................................................................................... 35
■ Digital HPF (PCM mode) ................................................................................................................. 47
■ CH Power Down & Mono Mode (PCM mode, DSD mode) ............................................................. 47
■ Digital Filter Setting (PCM mode) .................................................................................................... 47
■ Overflow Detection (PCM mode, DSD mode) ................................................................................. 48
■ DSD Output Function ....................................................................................................................... 48
■ DSD Operation Timing Example ..................................................................................................... 49
■ LDO .................................................................................................................................................. 50
■ Power Down Function/ Sequence ................................................................................................... 51
■ Operation Mode Control .................................................................................................................. 53
■ Register Control Interface ................................................................................................................ 53
■ Register Map .................................................................................................................................... 57
■ Register Definitions .......................................................................................................................... 57
13.
Recommended External Circuits .................................................................................................. 60
14.
Package......................................................................................................................................... 63
■ Outline Dimensions .......................................................................................................................... 63
■ Material & Lead Finish ..................................................................................................................... 63
■ Marking ............................................................................................................................................ 63
15.
Ordering Guide .............................................................................................................................. 64
■ Ordering Guide ................................................................................................................................ 64
IMPORTANT NOTICE ........................................................................................................................... 65
1.
2.
3.
4.
Rev. 0.2
2015/09
-2-
[AK5558]
4. Block Diagram
VREFL4
VREFH4
VREFL3
VREFH3
VREFL2
VREFH2
VREFL1
VREFH1
■ Block Diagram
TVDD
AIN1P
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
AIN5P
AIN5N
AIN6P
AIN6N
AIN7P
AIN7N
AIN8P
AIN8N
Delta-Sigma
Modulator
VDD18
DVSS
LDO
Voltage Reference
AIN1N
LDOE
Decimation
Filter
HPF
DIF0/DSDSEL0
DIF1/DSDSEL1
Delta-Sigma
Modulator
Decimation
Filter
Delta-Sigma
Modulator
Decimation
Filter
HPF
Serial Output
Interface
BICK/DCLK
LRCK/DSDOL1
TDMIN/DSDOR1
HPF
SDTO1/DSDOL2
SDTO2/DSDOR2
Delta-Sigma
Modulator
Decimation
Filter
Delta-Sigma
Modulator
Decimation
Filter
SDTO3/DSDOL3
SDTO4/DSDOL3
SDTO4/DSDOR3
HPF
DSDOL4
HPF
DSDOR4
DP
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
Delta-Sigma
Modulator
Decimation
Filter
HPF
TDM0
TDM1
AVDD1
AVSS1
PS/CAD0_SPI
CKS0/SDA/CDTI
CKS1/CAD0_I2C/CSN
CKS2/SCL/CCLK
CKS3/CAD1
Controller
AVDD2
I2C
DCKS/HPFE
OVF
MSN
PW0
PW1
PW2
SD/PMOD
SLOW/DCKB
TEST1
TEST2
MCLK
PDN
AVSS2
Figure 1. Block Diagram
Rev. 0.2
2015/09
-3-
[AK5558]
5. Pin Configurations and Functions
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SD/PMOD
SLOW/DCKB
CKS3/CAD1
CKS2/SCL/CCLK
CKS1/CAD0_I2C/CSN
CKS0/SDA/CDTI
OVF
DSDOR4
DSDOL4
SDTO4/DSDOR3
SDTO3/DSDOL3
SDTO2/DSDOR2
SDTO1/DSDOL2
TDMIN/DSDOR1
LRCK/DSDOL1
BICK/DCLK
■ Pin Configurations
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
64QFN
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MSN
PW2
PW1
PW0
PDN
VDD18
DVSS
TVDD
MCLK
TEST1
AIN8P
AIN8N
VREFL4
VREFH4
AIN7N
AIN7P
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIF0/DSDSEL0
DIF1/DSDSEL1
TDM0
TDM1
PS/CAD0_SPI
I2C
DP
DCKS/HPFE
LDOE
TEST2
AIN1P
AIN1N
VREFL1
VREFH1
AIN2N
AIN2P
Figure 2. Pin Configurations
Rev. 0.2
2015/09
-4-
[AK5558]
■ Pin Functions
No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
AIN7P
AIN7N
VREFH4
VREFL4
AIN8N
AIN8P
TEST1
MCLK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
25
TVDD
-
26
DVSS
I
Analog Ground Pin(AIN1-4)
Analog Power Supply Pin(AIN1-4), 4.5-5.5V
Channel 3 Positive Input Pin
Channel 3 Negative Input Pin
ADC Low Level Voltage Reference Input Pin
ADC High Level Voltage Reference Input Pin
Channel 4 Negative Input Pin
Channel 4 Positive Input Pin
Channel 5 Positive Input Pin
Channel 5 Negative Input Pin
ADC High Level Voltage Reference Input Pin
ADC Low Level Voltage Reference Input Pin
Channel 6 Negative Input Pin
Channel 6 Positive Input Pin
Analog Power Supply Pin(AIN5-8), 4.5-5.5V
Analog Ground Pin(AIN5-8)
Channel 7 Positive Input Pin
Channel 7 Negative Input Pin
ADC High Level Voltage Reference Input Pin
ADC Low Level Voltage Reference Input Pin
Channel 8 Negative Input Pin
Channel 8 Positive Input Pin
TEST Enable Pin. This pin is pull down by 100kΩ internally
Master Clock Input Pin
Digital I/O Buffers and LDO Power Supply Pin
1.7~1.98V (LDOE pin= “L”) or 3.0~3.6V (LDOE pin= “H”).
Digital Ground Pin
Digital Core Power Supply Pin, 1.7-1.98V (LDOE pin= “L”)
27
VDD18
O
LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”)
28
PDN
I
29
30
31
32
PW0
PW1
PW2
MSN
I
I
I
I
33
BICK
DCLK
34
35
36
37
LRCK
I
O
O
I
DSDOL1
O
O
TDMIN
I
DSDOR1
SDTO1
DSDOL2
SDTO2
DSDOR2
O
O
O
O
O
Reset & Power Down Pin
“L”: Reset & Power down, “H” : Normal operation
Power Management Pin, Monaural/Stereo select Pin
Power Management Pin, Monaural/Stereo select Pin
Power Management Pin, Monaural/Stereo select Pin,
Master/Slave Select Pin
Audio Serial Data Clock Input Pin in PCM & Slave Mode.
This pin is pulled down by 100kΩ internally
Audio Serial Data Clock Output Pin in PCM & Master Mode
DSD Clock Output Pin in DSD Mode
Channel Clock Input Pin in PCM & Slave Mode
This pin is pulled down by 100kΩ internally
Channel Clock Output Pin in PCM & Master Mode
Audio Serial Data Output Pin for AIN1 in DSD Mode
TDM Data Input Pin in PCM Mode
This pin is pulled down by 100kΩ internally
Audio Serial Data Output Pin for AIN2 in DSD Mode
Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode
Audio Serial Data Output Pin for AIN3 in DSD Mode
Audio Serial Data Output Pin for AIN3 and AIN4 in PCM Mode
Audio Serial Data Output Pin for AIN4 in DSD Mode
Rev. 0.2
Power Down
Status
Pull Down
with 500Ω
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
L
L
L
L
2015/09
-5-
[AK5558]
No.
38
39
40
41
42
43
44
45
46
47
48
Pin Name
I/O
Function
SDTO3
DSDOL3
SDTO4
DSDOR3
DSDOL4
DSDOR4
OVF
CKS0
SDA
CDTI
CKS1
CAD0_I2C
CSN
CKS2
SCL
CCLK
CKS3
CAD1
SLOW
DCKB
SD
PMOD
O
O
O
O
O
O
O
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
Audio Serial Data Output Pin for AIN5 and AIN6 in PCM Mode
Audio Serial Data Output Pin for AIN5 in DSD Mode
Audio Serial Data Output Pin for AIN7 and AIN8 in PCM Mode
Audio Serial Data Output Pin for AIN6 in DSD Mode
Audio Serial Data Output Pin for AIN7 in DSD Mode
Audio Serial Data Output Pin for AIN8 in DSD Mode
Analog Input Over Flow Flag Output Pin
Clock Mode Select Pin
2
Control Data I/O Pin in I C Bus Serial Control Mode
Control Data Input Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Chip Address 0 Pin in I C Bus Serial Control Mode
Chip Select Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Control Data Clock Pin in I C Bus Serial Control Mode
Control Data Clock Pin in 3-wire Serial Control Mode
Clock Mode Select Pin
2
Chip Address 1 Pin in I C Bus or 3-wire Serial Control Mode
Slow Roll-OFF Digital Filter Select Pin in PCM Mode
Polarity of DCLK Pin in DSD Mode
Short Delay Digital Filter Select Pin in PCM Mode
DSD Phase Modulation Mode Select Pin in DSD Mode
Audio Data Format Select Pin in PCM Mode
2
“L”: MSB justified, “H”: I S
DSD Sampling Rate Control Pin in DSD Mode
Audio Data Format Select Pin in PCM Mode
“L”: 24-bit Mode, “H”: 32-bit Mode
DSD Sampling Rate Control Pin in DSD Mode
TDM I/F Format Select Pin
* This pin must be fixed to “L” when using DSD mode.
TDM I/F Format Select Pin
* This pin must be fixed to “L” when using DSD mode.
Control Mode Select Pin (I2C pin = “H”)
2
“L”:I C Bus Serial Control Mode, “H” :Parallel Control Mode
Chip Address 0 Pin in 3-wire Serial Control Mode (I2C pin =
“L”)
Control Mode Select Pin
“L”: 3-wire Serial Control Mode
2
“H”: I C Bus Serial Control Mode or Parallel Control Mode
DSD Mode Enable Pin
“L”: PCM Mode, “H”: DSD Mode
High Pass Filter Enable Pin
“L”: HPF Disable, “H”: HPF Enable
Master Clock Frequency Select at DSD Mode (DSD Only)
LDO Enable Pin
“L”: LDO Disable, “H”: LDO Enable
This pin is pulled down by 100kΩ internally
TEST Enable pin
Channel 1 Positive Input Pin
Channel 1 Negative Input Pin
DIF0
I
DSDSEL0
I
DIF1
I
DSDSEL1
I
51
TDM0
I
52
TDM1
I
PS
I
CAD0_SPI
I
54
I2C
I
55
DP
I
HPFE
I
DCKS
I
57
LDOE
I
58
59
60
TEST2
AIN1P
AIN1N
I
I
I
49
50
53
56
Rev. 0.2
Power Down
Status
L
L
L
L
L
L
L
Hi-z
-
-
-
2015/09
-6-
[AK5558]
No.
Pin Name
61
62
63
64
VREFL1
VREFH1
AIN2N
AIN2P
I/O
I
I
I
I
Function
ADC Low Level Voltage Reference Input Pin
ADC High Level Voltage Reference Input Pin
Channel 2 Negative Input Pin
Channel 2 Positive Input Pin
Power Down
Status
-
Note 1. All digital input pins must not be allowed to float.
■ Handling of Unused Pin
The unused I/O pins should be connected appropriately.
1. PCM Mode
Classification
Analog
Digital
Pin Name
AIN1~8P, AIN1-8N
VREFH1-4
VREFL1-4
TDMIN, TEST1, TEST2
SDTO1-4, DSDOL4, DSDOR4, OVF
Setting
Open
Connect to AVDD
Connect to AVSS
Connect to DVSS
Open
2. DSD Mode
Classification
Analog
Digital
Pin Name
AIN1-8P, AIN1-8N
VREFH1-4
VREFL1-4
TDMIN, TDM0, TDM1, TEST1, TEST2
DSDOL1-4, DSDOR1-4, OVF
Setting
Open
Connect to AVDD
Connect to AVSS
Connect to DVSS
Open
Note 2. Unused channels must be powered down.
Rev. 0.2
2015/09
-7-
[AK5558]
6. Absolute Maximum Ratings
(VSS=0V; Note 3)
Parameter
Symbol
Power
Analog (AVDD pin)
AVDD
Supplies:
Digital Interface (TVDD pin)
TVDD
Digital Core (VDD18 pin)(Note 4)
VDD18
Min.
Max.
Unit
−0.3
−0.3
−0.3
6.0
4.0
2.5
V
V
V
Input Current (Any Pin Except Supplies)
IIN
mA
10
Analog Input Voltage (AIN1-8P, AIN1-8N pins)
VINA
−0.3
AVDD+0.3
V
Digital Input Voltage
VIND
−0.3
TVDD+0.3
V
Ambient Temperature (Power applied)
When the back tab is connected to VSS
Ta
−40
105
C
When the back tab is open
Ta
−40
70
C
Storage Temperature
Tstg
−65
150
C
Note 3. All voltages with respect to ground.
Note 4. The 1.8V LDO is off (LDOE pin = “L”) and an external power is supplied to the VDD18 pin.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operation Conditions
(VSS=0V; Note 3)
Parameter
Analog (AVDD pin)
Power
Supplies
(LDOE pin= “L”) (Note 5)
Digital Interface (TVDD pin) (Note 6)
Digital Core (VDD18 pin)
(LDOE pin= “H”) (Note 7)
Digital Interface (TVDD pin)
Symbol
AVDD
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
TVDD
VDD18
1.7
1.7
1.8
1.8
1.98
1.98
V
V
TVDD
3.0
3.3
3.6
V
Voltage
“H” voltage Reference (Note 8)
VREFH1-4
4.5
5.0
5.5
V
Reference
“L” voltage reference
VREFL1-4
AVSS
V
(Note 11)
Note 3. All voltages with respect to ground.
Note 5. TVDD must be powered up before VDD18 when the LDOE pin = “L”. The power up sequence
between AVDD and TVDD or AVDD and VDD18 is not critical.
Note 6. TVDD must not exceed VDD18±0.1V when LDOE pin= “L”.
Note 7. When LDOE pin = “H”, the internal LDO supplies 1.8V (typ). The power up sequences between
AVDD and TVDD is not critical.
Note 8. VREFH1-4 pin must not exceed AVDD+0.1V.
Note 9. VREFL1-4 pins must be connected to AVSS.
Analog Input Voltage is proportional to {(VREFH) – (VREFL)}.
Vin (typ, @ 0dB) = 2.8  {(VREFH) – (VREFL)} / 5 [V].
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
Rev. 0.2
2015/09
-8-
[AK5558]
8. Analog Characteristics
(Ta=25C; AVDD=5.0V; TVDD=3.3V, fs=48kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24-bit
Data; Measurement frequency=20Hz20kHz at fs=48kHz, 40Hz40kHz at fs=96kHz, 40Hz40kHz at
fs=192kHz, unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Analog Input Characteristics:
Resolution
32
Bit
Input Voltage
(Note 10)
PCM Mode
Vpp
2.7
2.8
2.9
DSD Mode
Vpp
±1.4
1dBFS
100
106
dB
S/(N+D)
fs=48kHz
20dBFS
92
dB
BW=20kHz
60dBFS
52
dB
1dBFS
106
dB
fs=96kHz
20dBFS
89
dB
BW=40kHz
60dBFS
49
dB
1dBFS
106
dB
fs=192kHz
20dBFS
89
dB
BW=40kHz
60dBFS
49
dB
Dynamic Range
110
115
Stereo Mode
dB
(60dBFS with A-weighted)
118
Mono Mode
S/N
110
115
Stereo Mode
dB
(A-weighted)
118
Mono Mode
Input Resistance
These values will be doubled in DSD 64fs mode.
7.8
9.1
10.4
k
(Values in DSD128 or DSD256 modes are as shown here)
Interchannel Isolation
110
120
dB
(AIN1AIN2, AIN3AIN4, AIN5AIN6, AIN7AIN8)
Interchannel Gain Mismatch
0
0.5
dB
Power Supply Rejection
(Note 11)
60
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”, LDOE pin = “H”)
AVDD
40
52
mA
TVDD
(fs=48kHz)
17
22
mA
TVDD
(fs=96kHz)
28
36
mA
TVDD
(fs=192kHz)
25
32
mA
Power down mode (PDN pin = “L”)
(Note 12)
AVDD+TVDD
10
100
A
Note 10. This value is (AINnP)(AINnN) that the ADC output becomes full-scale (n=1-8). Input voltage is
proportional to VREFHVREFL.
Vin = 0.56  (VREFHmVREFLm) [Vpp]. (m=1-4)
Note 11. PSRR is applied to AVDD, TVDD with 1kHz, 20mVpp sine wave. The VREFH1~4 pins are held
to the same voltage.
Note 12. All digital inputs are fixed to TVDD or TVSS.
“
Rev. 0.2
2015/09
-9-
[AK5558]
9. Filter Characteristics
■ ADC Filter Characteristics (fs= 48kHz)
(Ta= -40  +105C; AVDD =4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 3)
(SD pin=“L”, SLOW pin=“L”)
Passband (Note 13)
PB
0
kHz
22.1
+0.012/0.014dB
kHz
24.5
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
19
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 4)
(SD pin=“L”, SLOW pin=“H”)
±0.034dB
Passband (Note 13)
PB
0
12.5
kHz
21.9
kHz
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.5
1/fs
GD
Group Delay (Note 14)
GD
7
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 5)
(SD pin=“H”, SLOW pin=”L”)
Passband (Note 13)
PB
0
22.1
kHz
+0.012/0.014dB
24.4
kHz
6.0dB
Stopband (Note 13)
SB
27.8
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 6)
(SD pin=“H”, SLOW pin=“H”)
±0.034dB
Passband (Note 13)
PB
0
12.5
kHz
21.9
kHz
6.0dB
Stopband (Note 13)
SB
36.5
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 20.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
5
1/fs
Digital Filter (HPF):
3.0dB
Frequency Response
1.0
Hz
FR
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The passband and stopband frequencies scale with fs.
For example, PB (+0.012dB/0.014dB) =0.46  fs (SHARP ROLL-OFF).
For example, PB (+0.034dB/0.034dB) =0.26  fs (SLOW ROLL-OFF).
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at
maximum when outputting data via audio interfaces.
Rev. 0.2
2015/09
- 10 -
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[ dB]
[AK5558]
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[dB]
Figure 3. SHARP ROLL-OFF (fs=48kHz)
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[ dB]
Figure 4. SLOW ROLL-OFF (fs=48kHz)
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[dB]
Figure 5. SHORT DELAY SHARP ROLL-OFF (fs=48kHz)
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
4
8
12
16
20 24 28
Freq[kHz]
32
36
40
44
48
Figure 6. SHORT DELAY SLOW ROLL-OFF (fs=48kHz)
Rev. 0.2
2015/09
- 11 -
[AK5558]
■ ADC Filter Characteristics (fs= 96kHz)
(Ta= -40  +105C; AVDD =4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin= “H”),
VDD18= 1.71.98V (LDOE pin= “L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 7)
(SD pin=“L”, SLOW pin= “L”)
44.2
Passband (Note 13)
0dB/0.06dB
0
kHz
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
19
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 8)
(SD pin=“L”, SLOW pin= “H”)
25
Passband (Note 13)
0dB/0.074dB
0
kHz
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
7
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF (Figure 9)
(SD pin=“H”, SLOW pin= “L”)
Passband (Note 13)
0
44.2
kHz
0dB/0.06dB
PB
48.7
kHz
6.0dB
Stopband (Note 13)
SB
55.6
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 10)
(SD pin=“H”, SLOW pin= “H”)
Passband (Note 13)
0
25
kHz
0dB/0.074dB
PB
43.7
kHz
6.0dB
Stopband (Note 13)
SB
73
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
2.6
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5
Digital Filter (HPF):
3.0dB
Frequency Response
1.0
Hz
FR
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The passband and stopband frequencies scale with fs.
For example, PB (0dB/0.06dB) =0.46  fs (SHARP ROLL-OFF).
For example, PB (0dB/0.074dB) =0.26  fs (SLOW ROLL-OFF).
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at
maximum when outputting data via audio interfaces.
Rev. 0.2
2015/09
- 12 -
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple [dB]
[AK5558]
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[dB]
Figure 7. SHARP ROLL-OFF (fs=96kHz)
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
Figure 8. SLOW ROLL-OFF (fs=96kHz)
0.05
10
0.04
0
0.03
-10
0.02
-20
-30
0.01
-40
0
-50
-0.01
Gain[dB]
Ripple[dB]
Figure 9. SHORT DELAY SHARP ROLL-OFF (fs=96kHz)
-60
-0.02
-70
-0.03
-80
-0.04
-90
-0.05
-100
0
8
16
24
32
40 48 56
Freq[kHz]
64
72
80
88
96
Figure 10. SHORT DELAY SLOW ROLL-OFF (fs=96kHz)
Rev. 0.2
2015/09
- 13 -
[AK5558]
■ ADC Filter Characteristics (fs= 192kHz)
(Ta= -40  +105C; AVDD =4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin=“L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 11)
(SD pin=“L”, SLOW pin=“L”)
83.7
Passband (Note 13) 0dB/0.04dB
0
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
15
Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 12)
(SD pin=“L”, SLOW pin=“H”)
Passband (Note 13) 0dB/0.7dB
0
31.1
kHz
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
146
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
8
1/fs
Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 13)
(SD pin=“H”, SLOW pin=“L”)
Passband (Note 13) 0dB/0.04dB
0
83.7
kHz
PB
100.1
kHz
6.0dB
Stopband (Note 13)
SB
122.9
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.2
1/fs
GD
Group Delay (Note 14)
GD
1/fs
6
Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER (Figure 14)
(SD pin=“H”, SLOW pin=“H”)
Passband (Note 13) 0dB/0.7dB
0
31.1
kHz
PB
75.2
kHz
6.0dB
Stopband (Note 13)
SB
146
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0.5
1/fs
GD
Group Delay (Note 14)
GD
6
1/fs
Digital Filter (HPF):
3.0dB
Frequency Response
1.0
Hz
FR
2.5
Hz
0.5dB
(Note 13)
6.5
Hz
0.1dB
Note 13. The passband and stopband frequencies scale with fs.
For example, PB (0dB/0.04dB) =0.436  fs (SHARP ROLL-OFF).
For example, PB (0dB/0.7dB) =0.162  fs (SLOW ROLL-OFF).
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at
maximum when outputting data via audio interfaces.
Rev. 0.2
2015/09
- 14 -
[AK5558]
0.2
10.00
0.1
0.00
0.0
-10.00
-0.1
-20.00
-30.00
-0.2
-40.00
-0.3
-50.00
-0.4
Gain[dB]
Ripple[dB]
Figure 11. SHARP ROLL-OFF (fs=192kHz)
-60.00
-0.5
-70.00
-0.6
-80.00
-0.7
-90.00
-0.8
-100.00
0
16
32
48
64
80 96 112 128 144 160 176 192
Freq[kHz]
Figure 12. SLOW ROLL-OFF (fs=192kHz)
0.2
10.00
0.1
0.00
0.0
-10.00
-0.1
-20.00
-30.00
-0.2
-40.00
-0.3
-50.00
-0.4
Gain[dB]
Ripple[dB]
Figure 13. SHORT DELAY SHARP ROLL-OFF (fs=192kHz)
-60.00
-0.5
-70.00
-0.6
-80.00
-0.7
-90.00
-0.8
-100.00
0
16
32
48
64
80 96 112 128 144 160 176 192
Freq[kHz]
Figure 14. SHORT DELAY SLOW ROLL-OFF (fs=192kHz)
Rev. 0.2
2015/09
- 15 -
[AK5558]
■ ADC Filter Characteristics (fs= 384kHz)
(Ta= -40  +105C; AVDD =4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin=“L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF) (Figure 15)
(SD pin=“X”, SLOW pin=“X”) * It does not depend on the SD pin and SLOW pin.
Frequency
-0.1dB
81.75
kHz
Response
-1.0dB
114
kHz
(Note 13)
FR
-3.0dB
137.63
kHz
-6.0dB
157.2
kHz
Stopband (Note 13)
SB
277.4
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
7
Note 13. The passband and stopband frequencies scale with fs.
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at
maximum when outputting data via audio interfaces.
0.80
20.00
0.40
0.00
0.00
-20.00
-0.40
-40.00
-60.00
-1.20
-80.00
Gain[dB]
Gain[dB]
-0.80
-1.60
-100.00
-2.00
-120.00
-2.40
-140.00
-2.80
-3.20
-160.00
0
64
128
192
256
320
384
Freq[kHz]
Figure 15. Frequency Response (fs = 384kHz)
Rev. 0.2
2015/09
- 16 -
[AK5558]
■ ADC Filter Characteristics (fs= 768kHz)
(Ta= -40  +105C; AVDD =4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin=“L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter (Decimation LPF) (Figure 16)
(SD pin=“X”, SLOW pin=“X”) * It does not depend on the SD pin and SLOW pin.
Frequency Response
-0.1dB
26.25
kHz
(Note 13)
-1.0dB
83.75
kHz
FR
-3.0dB
144.5
kHz
-6.0dB
203.1
kHz
Stopband (Note 13)
SB
640.3
kHz
Stopband Attenuation
SA
85
dB
Group Delay Distortion 0 ~ 40.0kHz
0
1/fs
GD
Group Delay (Note 14)
GD
1/fs
5
Note 13. The passband and stopband frequencies scale with fs.
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at
maximum when outputting data via audio interfaces.
0.80
20.00
0.40
0.00
0.00
-20.00
-0.40
-40.00
-60.00
-1.20
-80.00
Gain[dB]
Gain[dB]
-0.80
-1.60
-100.00
-2.00
-120.00
-2.40
-140.00
-2.80
-3.20
-160.00
0
64
128
192
256
320
384
448
512
576
640
704
768
Freq[kHz]
Figure 16. Frequency Response (fs = 768kHz)
Rev. 0.2
2015/09
- 17 -
[AK5558]
10. DC Characteristics
(Ta=40~105C; AVDD=4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin=“L”))
Parameter
Symbol
Min.
Typ.
Max.
Unit
TVDD=1.7  1.98V
VIH
80%TVDD
V
High-Level Input Voltage
(Note 15)
VIL
20%TVDD
V
Low-Level Input Voltage
(Note 15)
TVDD=3.0V  3.6V
High-Level Input Voltage
(Note 15)
VIH
70%TVDD
V
Low-Level Input Voltage
(Note 15)
VIL
30%TVDD
V
High-Level Output Voltage
(Note 16)
VOH
TVDD0.5
V
(Iout=100µA)
Low-Level Output Voltage
(Note 17)
(except SDA pin: Iout= 100µA)
VOL
0.5
V
(SDA pin, 3.0V  TVDD  3.6V: Iout= 3mA)
VOL
0.4
V
(SDA pin, 1.7V  TVDD  1.98V: Iout= 3mA)
VOL
20%TVDD
V
Input Leakage Current
Iin
10
A
Note 15. MCLK, PDN, PW0-2, MSN, BICK (Slave Mode), LRCK (Slave Mode), TDMIN, SLOW/DCKB,
SD/PMOD, CKS0/SDA (Write)/CDTI, CKS1/CAD0_I2C/CSN, CKS2/SCL/CCLK, CKS3/CAD1,
DIF0/DSDSEL0, DIF1/DSDSEL1, TDM0, TDM1, PSN/CAD0_SPI, I2C, DP, HPFE/DCKS,
LDOE, TEST1-2
Note 16. BICK (Master Mode)/DCLK, LRCK (Master Mode)/DSDOL1, DSDOR1, SDTO1/DSDOL2,
SDTO2/DSDOR2, SDTO3/DSDOL3, SDTO4/DSDOR3, DSDOL4, DSDOR4, SDA (Read),
OVF
Note 17. The external pull-up resistors at the SDA pin and pins shown in Note 16 should be connected to
TVDD+0.3V or less.
Rev. 0.2
2015/09
- 18 -
[AK5558]
11. Switching Characteristics
(Ta=40+105C; AVDD=4.5~5.5V, TVDD=1.7~1.98V (LDOE pin=“L”), 3.03.6V (LDOE pin=“H”),
VDD18= 1.71.98V (LDOE pin = “L”), CL=20pF, unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max
Unit
Master Clock Timing (Figure 18)
fCLK
2.048
49.152
MHz
Frequency
dCLK
45
55
%
Duty Cycle
LRCK Frequency (Slave Mode) (Figure 17)
Normal Mode (TDM1-0 bits = “00”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
fsq
108
216
kHz
Quad Speed Mode
fso
384
kHz
Oct Speed Mode
fsh
768
kHz
Hex Speed Mode
Duty
45
55
%
Duty Cycle
TDM128 Mode (TDM1-0 bits = “01”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
fsq
108
216
kHz
Quad Speed Mode
tLRH
1/128fs
ns
High Time
tLRL
1/128fs
ns
Low Time
TDM256 Mode (TDM1-0 bits = “10”)
fsn
8
54
kHz
Normal Speed Mode
fsd
54
108
kHz
Double Speed Mode
tLRH
1/256fs
ns
High time
tLRL
1/256fs
ns
Low time
TDM512 mode (TDM1-0 bits = “11”)
fsn
8
54
kHz
Normal Speed Mode
tLRH
1/512fs
ns
High Time
tLRL
1/512fs
ns
Low Time
Parameter
LRCK Frequency (Master Mode) (Figure 18)
Normal Mode (TDM1-0 bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct Speed Mode
Hex Speed Mode
Duty Cycle
TDM128 Mode (TDM1-0 bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High Time
TDM256 Mode (TDM1-0 bits = “10”)
Normal Speed Mode
Double Speed Mode
High Time
TDM512 Mode (TDM1-0 bits = “11”)
Normal Speed Mode
High Time
Symbol
Min.
fsn
fsd
fsq
fso
fsh
Duty
8
54
108
fsn
fsd
fsq
tLRH
8
54
108
fsn
fsd
tLRH
8
54
fsn
tLRH
8
Rev. 0.2
Typ.
Max.
Unit
54
108
216
kHz
kHz
kHz
kHz
kHz
%
54
108
216
kHz
kHz
kHz
ns
54
108
kHz
kHz
ns
54
kHz
ns
384
768
50
1/4fs
1/8fs
1/16fs
2015/09
- 19 -
[AK5558]
Parameter
Symbol
Audio Interface Timing (Slave Mode) (Figure 19)
Normal Mode (TDM1-0 bits = “00”)
(LDOE pin = “H”)
(8kHz ≤ fs ≤ 216kHz)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mod
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓”toSDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(LDOE pin = “L”) *CL=15pF or less.
(8kHz ≤ fs ≤ 216kHz)
BICK Period
Normal Speed Mode(8kHz ≤ fs ≤ 48kHz)
Double Speed Mode(48kHz ≤ fs ≤ 96kHz)
Quad Speed Mode(96kHz ≤ fs ≤ 192kHz)
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓” to SDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(fs = 384kHz, 768kHz)
BICK Period
Oct Speed Mode
Hex Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “”
(Note 19)
BICK “” to LRCK Edge
(Note 19)
LRCK to SDTO (MSB) (Except I2S Mode)
BICK “↓” to SDTO1/2/3/4
Min.
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/128fsn
1/128fsd
1/64fsq
32
32
25
25
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/128fsn
1/128fsd
1/64fsq
36
36
30
30
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fso
1/32fsh
18
18
18
18
Rev. 0.2
Typ.
Max
Unit
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
ns
ns
ns
ns
ns
ns
ns
ns
2015/09
- 20 -
[AK5558]
Parameter
Symbol
Audio Interface Timing (Slave Mode) (Figure 20)
TDM128 Mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
Quad Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM256 Mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM512 Mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed Mode
tBCK
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
LRCK Edge to BICK “”
(Note 19)
tLRB
tBLR
BICK “” to LRCK Edge
(Note 19)
tBSS
SDTO Setup Time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
Rev. 0.2
Min.
Typ.
Max
Unit
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/512fsn
14
14
14
14
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/09
- 21 -
[AK5558]
Parameter
Symbol
Audio Interface Timing (Master Mode) (Figure 21)
Normal Mode (TDM1-0 bits = “00”)
(8kHz ≤ fs ≤ 216kHz)
BICK Period
fBCK
Normal Speed Mode
fBCK
Double Speed Mode
fBCK
Quad Speed Mod
dBCK
BICK Duty
tMBLR
BICK “↓” to LRCK Edge
tBSD
BICK “↓”to SDTO1/2/3/4
Normal Mode (TDM1-0 bits = “00”)
(fs = 384kHz,768kHz)
BICK Period
fBCK
Oct speed Mode
fBCK
Hex speed Mode
dBCK
BICK Duty
tMBLR
BICK “↓” to LRCK Edge
tBSD
BICK “↓” to SDTO1/2/3/4
Rev. 0.2
Min.
Typ.
Max
Unit
20
20
ns
ns
ns
ns
ns
ns
5
4
ns
ns
ns
ns
ns
1/64fsn
1/64fsd
1/64fsq
50
-20
-20
1/64fso
1/64fsh
50
-5
-4
2015/09
- 22 -
[AK5558]
Parameter
Symbol
Audio Interface Timing (Master Mode) (Figure 23)
TDM128 Mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
Quad Speed Mode
tBCK
BICK Duty
dBCK
BICK “↓” to LRCK Edge
tMBLR
SDTO Setup time BICK “”
tBSS
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM256 Mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed Mode
tBCK
Double Speed Mode
tBCK
BICK Duty
dBCK
BICK “↓” to LRCK Edge
tMBLR
tBSS
SDTO Setup time BICK “”
tBSH
SDTO Hold BICK “”
tSDH
TDMIN Hold Time
tSDS
TDMIN Setup Time
TDM512 Mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed Mode
BICK Duty
BICK “↓” to LRCK Edge
SDTO Setup time BICK “”
SDTO Hold BICK “”
TDMIN Hold Time
TDMIN Setup Time
tBCK
dBCK
tMBLR
tBSS
tBSH
tSDH
tSDS
Rev. 0.2
Min.
Typ.
Max
Unit
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/128fsn
1/128fsd
1/128fsq
50
-5
5
5
5
5
1/256fsn
1/256fsd
50
-5
5
5
5
5
5
1/512fsn
50
-5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/09
- 23 -
[AK5558]
Parameter
Symbol
Min.
Typ.
Max.
Unit
Audio Interface Timing (Master Mode) (Figure 24)
DSD Audio Interface Timing
(64 Mode, DSDSEL 1-0 bits = “00”)
tDCK
1/64fs
ns
DCLK Period
tDCKL
144
ns
DCLK Pulse Width Low
tDCKH
144
ns
DCLK Pulse Width High
tDDD
-20
20
ns
DCLK Edge to DSDL/R (Note 20)
DSD Audio Interface Timing
(128 Mode, DSDSEL 1-0 bits = “01”)
tDCK
1/128fs
ns
DCLK Period
tDCKL
72
ns
DCLK Pulse Width Low
tDCKH
72
ns
DCLK Pulse Width High
tDDD
-10
10
ns
DCLK Edge to DSDL/R (Note 20)
DSD Audio Interface Timing
(256 Mode, DSDSEL 1-0 bits = “10”)
tDCK
1/256fs
ns
DCLK Period
tDCKL
36
ns
DCLK Pulse Width Low
tDCKH
36
ns
DCLK Pulse Width High
tDDD
-10
10
ns
DCLK Edge to DSDL/R (Note 20)
Note 18. When the 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5558 should be
reset by the PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. DSD data transmitting device must meet this time.
tDDD is defined from a falling edge of DCLK “↓” to a DSDL/R edge when DCKB bit = “0” and it
is defined from a rising edge of DCLK “↑” to a DSDL/R edge when DCKB bit = “1”.
Rev. 0.2
2015/09
- 24 -
[AK5558]
Parameter
Symbol
Min.
Typ.
Max. Unit
Control Interface Timing (3-Wire Serial Mode):
(Figure 26) (Figure 27)
tCCK
200
ns
CCLK Period
tCCKL
80
ns
CCLK Pulse Width Low
tCCKH
80
ns
Pulse Width High
tCDS
40
ns
CDTI Setup Timing
tCDH
40
ns
CDTI Hold Timing
tCSW
150
ns
CSN “H” Time
tCSS
50
ns
CSN “↓” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
2
Control Interface Timing (I C Bus Mode): (Figure 28)
fSCL
400
kHz
SCL CLOCK Frequency
tBUF
1.3
µs
Bus Free Time Between Transmissions
tHD STA
0.6
µs
Start Condition Hold Tune (Prior to First Clock Pulse)
tLow
1.3
µs
Clock Low Time
tHIGH
0.6
µs
Clock High Time
tSU STA
0.6
µs
Setup Time for Repeated Start Condition
tHD
DAT
0
µs
SDA Hold Time from SCL Falling (Note 21)
tSU DAT
0.1
µs
SDA Setup Time from SCL Rising
tR
1.0
µs
Rise Time of Both SDA and SCL Lines
tF
0.3
µs
Fall Time of Both SDA and SCL Lines
tSU STO
0.6
µs
Setup Time for Stop Condition
tSP
0
50
ns
Pulse Width of Spike Noise Suppressed by Input Filter
Cb
400
pF
Capacitive Load on Bus
Power Down & Reset Timing (Figure 29)
PDN Pulse Width
(Note 22)
tPD
150
ns
PDN Reject Pulse Width
(Note 22)
tRPD
30
ns
tPDV
583
1/fs
PDN “” to SDTO1-4 valid
(Note 23)
Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 22. The AK5558 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held
“L” for more than 150ns for a certain reset. The AK5558 is not reset by the “L” pulse less than
30ns.
Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Rev. 0.2
2015/09
- 25 -
[AK5558]
■ Timing Diagram
[1] PCM Mode
1/fCLK
50%TVDD
MCLK
tdCLKH
tdCLKL
dCLK=tdCLKHfs100
or
tdCLKLfs100
1/fs
50%TVDD
LRCK
tLRH
tLRL
tBCK
Duty=tLRHfs100
or
tLRLfs100
VIH
BICK
VIL
tBCKH
tBCKL
Figure 17. Clock Timing (Slave mode)
1/fCLK
50%TVDD
MCLK
tCLKH
tCLKL
dCLK=tCLKHfCLK100
or
tCLKLfCLK100
1/fs
VOH
50%TVDD
LRCK
Duty=tLRHfs100
tLRH
1/fBCK
50%TVDD
BICK
tBCKH
tBCKL
dBCK=tBCKHfBCK100
or
tBCKLfBCK100
Figure 18. Clock Timing (Master mode)
Rev. 0.2
2015/09
- 26 -
[AK5558]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO1/2/3/4
50%TVDD
Figure 19. Audio Interface Timing (Normal mode & Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSS
tBSH
SDTO1/2/3/4
50%TVDD
tSDS
tSDH
VIH
TDMIN
VIL
Figure 20. Audio Interface Timing (TDM mode & Slave mode)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSD
50%TVDD
SDTO1/2/3/4
Figure 21. Audio Interface Timing (Normal mode & Master mode, 8kHz≤fs≤216kHz)
Rev. 0.2
2015/09
- 27 -
[AK5558]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO1/2/3/4
Figure 22. Audio Interface Timing (Normal mode & Master mode, fs=384kHz, 768kHz)
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSS
tBSH
50%TVDD
SDTO1/2/3/4
tSDS
tSDH
VIH
TDMIN
VIL
Figure 23. Audio Interface Timing (TDM mode & Master mode)
Rev. 0.2
2015/09
- 28 -
[AK5558]
[2] DSD Mode
tDCK
tDCKL
tDCKH
VOH
DCLK
VOL
tDDD
VOH
DSDOL1-4
DSDOR1-4
VOL
Figure 24. Audio Serial Interface Timing (Normal Mode, DCKB bit= “0” or DCKB pin= “L”)
tDCK
tDCKL
tDCKH
VOH
DCLK
VOL
tDDD
tDDD
VOH
DSDOL1-4
DSDOR1-4
VOL
Figure 25. Audio Serial Interface Timing (Phase Modulation Mode, DCKB bit= “0” or DCKB pin= “L”)
Rev. 0.2
2015/09
- 29 -
[AK5558]
[3] 3-Wire Serial Interface
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 26. WRITE Command Input Timing (3-wire Serial Mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 27. WRITE Data Input Timing (3-wire Serial Mode)
Rev. 0.2
2015/09
- 30 -
[AK5558]
[4] I2C Interface
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
Start
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 28. I2C Bus Mode Timing
[5] Power-down Timing
tPD
VIH
PDN
VIL
tPDV
SDTO1/2/3/4
tRP
D
50%TVDD
Figure 29. Power-down & Reset Timing
Rev. 0.2
2015/09
- 31 -
[AK5558]
12. Functional Descriptions
■ Digital Core Power Supply
The digital core of the AK5558 is operates off of a 1.8V power supply. Normally, this voltage is generated
by the internal LDO from TVDD (3.3V) for digital interface. The internal LDO will be powered up by setting
the LDOE pin = “H”. Set the LDOE pin to “L” and supply a 1.8V power to the VDD18 pin externally when
a 1.8V is used as TVDD.
■ Output Mode
The AK5558 is able to output either PCM or DSD data. The DP pin or DP bit select the output mode. Set
the PW2 pin = PW1 pin = PW0 pin = “L” or RSTN bit = “0” or PW8-1 bits = “00H” to reset all channels
when changing the PCM/DSD mode. It takes 2~3/fs to output a normal data after releasing the reset
when changing the output mode. The AK5558 outputs PCM data from the SDTO1-4 pins by MCLK, BICK
and LRCK inputs in PCM mode (slave mode).
DSD clock and data are output from the DCLK, DSDOL1-4 and DSDOR1-4 pins by MCLK input in DSD
mode. The output gain in DSD mode will be half value of the PCM mode. If a large signal that the DSD
output exceeds this value is input, the output data will not be correct.
DP pin
DP bit
Interface
L
0
PCM
H
1
DSD
Table 1. PCM/DSD Mode Control
■ Master and Slave Mode
The AK5558 requires a master clock (MCLK), an audio serial data clock (BICK) and an output channel
clock (LRCK) in PCM mode. In this case, the LRCK frequency will be the sampling frequency.
Both master and slave modes are available in PCM mode. In master mode, the AK5558 internally
generates BICK and LRCK clocks from MCLK inputs and outputs them from the BICK pin and the LRCK
pin. MCLK must be synchronized with BICK and LRCK but the phase is not important. The MSN pin
controls master/slave mode. The AK5558 is in master mode when the MSN pin = “H” and in slave mode
when the MSN pin = “L”.
The AK5558 requires a master clock (MCLK) in DSD mode. Slave mode is not available in DSD mode,
only master mode is supported.
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK5558, are MCLK, BICK and LRCK in PCM
mode. MCLK frequency is determined automatically based on LRCK frequency, according to the
operation mode. Table 2, Table 3 and Table 4 show MCLK frequencies correspond to the normal audio
rate. Set the frequency ratio between Sampling frequency and MCLK by the CKS3-0 pins (Table 5).
The AK5558 integrates a phase detection circuit for LRCK. If the internal timing becomes out of
synchronization in slave mode, the AK5558 is reset automatically and the phase is resynchronized. If
more than two devices are synchronized, the AK5558 must be reset by the PDN pin once when changing
the clock frequency, clock mode or audio interface format. The frequency of operation clock and clock
mode should be changed while all channels are reset by setting PW2 pin = PW1 pin = “L”, RSTN bit = “0”
or PW8-1 bits = “00H”. A stable clock must be supplied after releasing the reset.
Rev. 0.2
2015/09
- 32 -
[AK5558]
32fs
48fs
64fs
96fs
128fs
MCLK
192fs
32kHz
N/A
N/A
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
192kHz
N/A
N/A
N/A
N/A
24.576
MHz
384kHz
N/A
N/A
36.864
MHz
768kHz
24.576
MHz
36.864
MHz
24.576
MHz
49.152
MHz
N/A
fs
256fs
8.192
MHz
12.288
MHz
24.576
MHz
384fs
12.288
MHz
18.432
MHz
36.864
MHz
512fs
16.384
MHz
24.576
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
N/A
N/A
N/A
36.864
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not Available)
Table 2 System Clock Example (Slave Mode)
32fs
48fs
64fs
96fs
128fs
MCLK
192fs
32kHz
N/A
N/A
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
192kHz
N/A
N/a
N/A
N/A
24.576
MHz
384kHz
N/A
N/A
36.864
MHz
768kHz
24.576
MHz
36.864
MHz
24.576
MHz
49.152
MHz
N/A
fs
256fs
8.192
MHz
12.288
MHz
24.576
MHz
384fs
12.288
MHz
18.432
MHz
36.864
MHz
512fs
16.384
MHz
24.576
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
N/A
N/A
N/A
36.864
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not available)
Table 3. System Clock Example (Master Mode)
32fs
48fs
64fs
96fs
128fs
MCLK
192fs
256fs
384fs
32kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
48kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
96kHz
N/A
N/A
N/A
N/A
N/A
N/A
24.576
MHz
192kHz
N/A
N/a
N/A
N/A
24.576
MHz
36.864
MHz
384kHz
N/A
N/A
24.576
MHz
36.864
MHz
N/A
768kHz
24.576
MHz
36.864
MHz
N/A
N/A
N/A
fs
512fs
16.384
MHz
24.576
MHz
768fs
24.576
MHz
36.864
MHz
1024fs
32.768
MHz
36.864
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not available)
Table 4. System Clock Example (Auto Mode)
Rev. 0.2
2015/09
- 33 -
[AK5558]
CKS3
pin(bit)
CKS2 CKS1 CKS0
pin(bit) pin(bit) pin(bit)
L(0)
L(0)
L(0)
L(0)
L(0)
L(0)
L(0)
H(1)
L(0)
L(0)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
L(0)
L(0)
L(0)
H(1)
L(0)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
H(1)
H(1)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
L(0)
H(1)
L(0)
H(1)
H(1)
H(1)
H(1)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
H(1)
H(1)
L(0)
H(1)
H(1)
H(1)
H(1)
M/S
pin
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
-
MCLK
Frequency
128fs
24M
192fs
36M
256fs
12M
256fs
24M
384fs
36M
384fs
18M
512fs
24M
768fs
36M
64fs
24M
32fs
24M
96fs
36M
48fs
36M
64fs
49.1M
1024fs
32M
Quad Speed Mode
108kHz  fs  216kHz
Quad Speed Mode
108kHz  fs  216kHz
Normal Speed Mode
8kHz  fs  54kHz
Double Speed Mode
54kHz  fs  108kHz
Double Speed Mode
54kHz  fs  108kHz
Normal Speed Mode
8kHz  fs  54kHz
Normal Speed Mode
8kHz  fs  54kHz
Normal Speed Mode
8kHz  fs  54kHz
Oct Speed Mode
fs = 384kHz
Hex Speed Mode
fs = 768kHz
Oct Speed Mode
fs = 384kHz
Hex Speed Mode
fs = 768kHz
Hex Speed Mode
fs = 768kHz
Normal Speed Mode
8kHz ≤ fs ≤ 32kHz
NA
NA
Auto
8KHz  fs  216kHz
fs Range
Table 5. MCLK Frequency
Rev. 0.2
2015/09
- 34 -
[AK5558]
[2] DSD Mode
The AK5558 only supports master mode in DSD mode. The external clock, which is required to operate
the AK5558, is MCLK in DSD mode. In this mode, necessary MCLK frequencies are the same as PCM
mode. The AK5558 generates DCLK from MCLK inputs and DSD data outputs (DSDOL1-4 and
DSDOR1-4) are synchronized with DCLK.
The necessary MCLK frequencies are 512fs and 768fs (fs=32kHz, 44.1kHz, 48kHz). MCLK frequency
can be changed by the DCKS pin (bit). After exiting reset (PDN pin = “L” → “H”) upon power-up, the
AK5558 is in power-down state until MCLK is input.
DCKS pin (bit)
MCLK Frequency
L(0)
512fs
H(1)
768fs
Table 6. System Clock (DSD Mode)
(default)
The AK5558 supports 64fs, 128fs and 256fs DSD sampling frequencies (fs= 32kHz 44.1kHz, 48kHz).
DSDSEL1-0 pins (bits) control this setting (Table 7).
DSDSEL1
pin (bit)
L(0)
L(0)
H(1)
DSDSEL0
pin (bit)
L(0)
H(1)
L(0)
H(1)
H(1)
Frequency
Mode
64fs
128fs
256fs
DSD Sampling Frequency
fs=32kHz
fs=44.1kHz
fs=48kHz
2.048MHz
2.8224MHz
3.072MHz
4.096MHz
5.6448MHz
6.144MHz
8.192MHz
11.2896MHz
12.288MHz
Reserved
Reserved
Reserved
(8.192MHz)
(11.2896MHz) (12.288MHz)
Table 7. DSD Sampling Frequency Select
(default)
■ Audio Interface Format
TDM1-0 pins(bits), DIF1-0 pins(bits), SLOW pin(bit) and SD pin(bit) settings should be changed when
the PDN pin= “L”.
[1] PCM Mode
48 types of audio interface format can be selected by the TDM1-0 pins (bits), MSN pin and DIF1-0 pins
(bits) (Table 8, Table 9). In all formats the serial data is MSB-first, 2's complement format. If 8kHz ≤ fs ≤
216kHz and TDM1-0 bits= “00”, the SDTO1/2/3/4 is clocked out on the falling edge of BICK. In other
conditions, the data is clocked out on the rising edge of BICK.
Audio interface format is distinguished in four types: Normal mode, TDM128 mode, TDM256 mode and
TDM512 mode are available. The TDM1-0 pins (bits) select these modes.
In Normal mode (non TDM), AIN1 and AIN2 A/D converted data is output from the SDTO1 pin, AIN3 and
AIN4 A/D converted data is output from the SDTO2 pin, AIN5 and AIN6 A/D data is output from the
SDTO3 pin and AIN7 and AIN8 A/D data is output from the SDTO4 pin.
The BICK frequency must be in the rage from 48fs to 128fs (fs=48kHz) in slave mode if the audio
interface format is in Normal mode (non TDM) and the interface speed is in Normal, Double or Quad
mode. Bit length of A/D data is 24-bit or 32-bit and it is selected by the DIF1 pin (bit).
The BICK frequency must be set to 32fs, 48fs or 64fs in slave mode if the audio interface format is in
Normal mode (non TDM) and the interface speed is in OCT mode. Bit length of A/D data is determined by
BICK frequency regardless of the DIF1 pin (bit). It is 16-bit when the BICK frequency is 32fs and 24-bit
when the BICK frequency is 48fs. When the BICK frequency is 64fs, A/D data can be selected between
24-bit and 32-bit by the DIF1 pin (bit). The BICK frequency must be 32fs when the audio interface speed
is in HEX mode. In this case, bit length will be 16-bit.
Rev. 0.2
2015/09
- 35 -
[AK5558]
The BICK frequency will be 64fs in master mode if the audio interface format is in Normal mode (non
TDM) and the interface speed is Normal, Double or Quad mode. Data bit length can be selected from
24-bit and 32-bit by the DIF1 pin (bit).
The BICK frequency will be synchronized with the MCLK frequency in master mode if the audio interface
format is in Normal mode (non TDM) and the interface speed is OCT/HEX mode. The MCLK frequency
must be 32fs, 48fs or 64fs. The bit length of A/D data is 16-bit when the MCLK frequency is 32fs, 24-bit
when the MCLK frequency is 48fs and 24-bit or 32-bit can be selected by the DIF1 pin (bit) when the
MCLK frequency is 64fs.
The DIF0 pin selects the A/D data format between MSB justified and I2C Compatible.
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Multiplex Speed TDM1 TDM0
Mode
Mode pin(bit) pin(bit)
MSN
Pin
L
Normal
Double
Quad
L(0)
L(0)
H
Normal
L
OCT
HEX
L(0)
L(0)
H
DIF1
DIF0
SDTO
pin(bit) pin(bit)
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
*
L(0)
16-bit, MSB
2
*
H(1)
16-bit, I S
*
L(0)
24-bit, MSB
2
*
H(1)
24-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
2
H(1)
H(1)
32-bit, I S
*
L(0)
16-bit, MSB
2
*
H(1)
16-bit, I S
*
L(0)
24-bit, MSB
2
*
H(1)
24-bit, I S
L(0)
L(0)
24-bit, MSB
2
L(0)
H(1)
24-bit, I S
H(1)
L(0)
32-bit, MSB
H(1)
H(1)
32-bit, I2S
LRCK
Pol. I/O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
H/L I
L/H I
H/L I
L/H I
H/L O
L/H O
H/L O
L/H O
BICK
Freq.
48-128fs
48-128fs
64-128fs
64-128fs
64fs
64fs
64fs
64fs
32fs
32fs
48fs
48fs
64fs
64fs
64fs
64fs
32fs
32fs
48fs
48fs
64fs
64fs
64fs
64fs
I/O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
MCLK
Freq.
I/O
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32-96fs
I
32fs
I
32fs
I
48fs
I
48fs
I
64fs
I
64fs
I
64fs
I
64fs
I
Table 8. Audio Interface Format (Normal Mode, OCT/HEX Mode)
Rev. 0.2
2015/09
- 36 -
[AK5558]
No.
Multiplex Speed TDM1 TDM0
Mode
Mode pin(bit) pin(bit)
24
25
26
Normal
27
TDM128 Double
28
Quad
29
30
31
32
33
34
35
Normal
TDM256
Double
36
37
38
39
40
41
42
43
TDM512 Normal
44
45
46
47
MSN
pin
L
L(0)
H(1)
H
L
H(1)
L(0)
H
L
H(1)
H(1)
H
DIF1
DIF0
pin(bit) pin(bit)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
L(0)
L(0)
L(0)
H(1)
H(1)
L(0)
H(1)
H(1)
SDTO
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
24-bit, MSB
2
24-bit, I S
32-bit, MSB
2
32-bit, I S
LRCK
Edg. I/O
I

I

I

I

O

O

O

O

I

I

I

I

O

O

O

O

I

I

I

I

O

O

O

O

BICK
Freq. I/O
128fs
I
128fs
I
128fs
I
128fs
I
128fs
O
128fs
O
128fs
O
128fs
O
256fs
I
256fs
I
256fs
I
256fs
I
256fs
O
256fs
O
256fs
O
256fs
O
512fs
I
512fs
I
512fs
I
512fs
I
512fs
O
512fs
O
512fs
O
512fs
O
MCLK
Freq.
I/O
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
128-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
256-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
512-1024fs I
Table 9. Audio Interface Format (TDM Mode)
Rev. 0.2
2015/09
- 37 -
[AK5558]
Cascade Connection in TDM Mode
The AK5558 supports cascade connection of two devices in TDM512 mode. Figure 30 shows a
connection example. All A/D converted data of connected AK5558 are output from the SDTO1 pin of the
second AK5558 by cascade connection.
When using multiple devices in slave mode on cascade connection, internal operation timing of each
device may differ for one MCLK cycle depending on MCLK and BICK input timings. To prevent this timing
difference, BICK “↓” should be more than ± 10ns from MCLK “↑” as shown in Table 10.
To realize this timing, BICK divided by two should be input on a falling edge of MCLK as shown in Figure
55 when MCLK=2xBICK (normal speed 1024fs mode). When MCLK=BICK (normal speed 512fs mode),
MCLK and BICK should be input in-phase as shown in Figure 56 to satisfy the timing shown in Table 10.
256fs or 512fs
AK5558 #1
MCLK
48kHz
LRCK
512fs
BICK
TDMIN
GND
SDTO1
AK5558 #2
MCLK
TDMIN
LRCK
BICK
16ch TDM
SDTO1
TDM512
Figure 30. Cascade Connection
Rev. 0.2
2015/09
- 38 -
[AK5558]
LRCK
0
1
2
11
12
13
23
24
31
0
1
2
11
12
13
23
24
31
0
1
BICK(64fs)
SDTO1-4
1
13 12 11
23 22
0
23 22
13
23: MSB, 0: LSB
AIN1/3/5/7 Data
1
12 11
0
31
AIN2/4/6/8 Data
Figure 31. Mode 0/4 Timing (Normal Mode, Normal/Double/Quad Speed Mode, MSB Justified, 24-bit)
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO1-4
23 22
2
1
0
23 22
2
23: MSB, 0: LSB
AIN1/3/5/7 Data
1
0
AIN2/4/6/8 Data
Figure 32. Mode 1/5 Timing (Normal Mode, Normal/Double/Quad Speed Mode, I2S Compatible, 24-bit)
LRCK
0
1
2
11
12
13
20
21
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO1-4
12 11
22 20 19
31 30
1
0
31 30
22
31: MSB, 0: LSB
AIN1/3/5/7 Data
12 11
20 19
1
0
31
AIN2/4/6/8 Data
Figure 33. Mode 2/6 Timing (Normal Mode, Normal/Double/Quad Speed Mode, MSB Justified, 32-bit)
LRCK
0
1
2
3
23
24
25
26
29
30
31
0
1
2
3
23
24
25
26
29
30
31
0
1
BICK(64fs)
SDTO1-4
31 30
16 15 14
3
2
1
31: MSB, 0: LSB
AIN1/3/5/7 Data
0
31 30
16 15 14
3
2
1
0
AIN2/4/6/8 Data
Figure 34. Mode 3/7 Timing (Normal Mode, Normal/Double/Quad Speed Mode, I2S Compatible, 32-bit)
Rev. 0.2
2015/09
- 39 -
[AK5558]
32 BICK
LRCK (Master)
LRCK (Slave)
BICK (32fs)
SDTO1-4 (O)
0 15 14
9
8
7
6
1
0 15 14
9
8
7
6
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
16 BICK
16 BICK
0 15 14
Figure 35. Mode 8/16 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 16-bit)
32 BICK
LRCK (Master)
LRCK (Slave)
BICK (32fs)
SDTO1-4 (O)
0 15 14
9
8
7
6
1
0 15 14
9
8
7
6
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
16 BICK
16 BICK
0 15 14
Figure 36. Mode 9/17 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 16-bit)
48 BICK
LRCK (Master)
LRCK (Slave)
BICK (48fs)
SDTO1-4 (O)
0 23 22
13 12 11 10
1
0 23 22
13 12 11 10
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
24 BICK
24 BICK
0 23 22
Figure 37. Mode 10/18 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 24-bit)
48 BICK
LRCK (Master)
LRCK (Slave)
BICK (48fs)
SDTO1-4 (O)
0 23 22
13 12 11 10
1
0 23 22
13 12 11 10
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
24 BICK
24 BICK
0 23 22
Figure 38. Mode 11/19 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 24-bit)
Rev. 0.2
2015/09
- 40 -
[AK5558]
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
23 22
15
8
7
0
23 22
15
8
7
0
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
23 22
Figure 39. Mode 12/20 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 24-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
23 22
15
8
7
0
23 22
15
8
7
0
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
23 22
Figure 40. Mode 13/21 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 24-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
0 31 30
17 16 15 14
1
0 31 30
17 16 15 14
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
0 31 30
Figure 41. Mode 14/22 Timing (Normal Mode, OCT/HEX Speed Mode, MSB Justified, 32-bit)
64 BICK
LRCK (Master)
LRCK (Slave)
BICK (64fs)
SDTO1-4 (O)
0 31 30
17 16 15 14
1
0 31 30
17 16 15 14
1
AIN1/3/5/7 Data
AIN2/4/6/8 Data
32 BICK
32 BICK
0 31 30
Figure 42. Mode 15/23 Timing (Normal Mode, OCT/HEX Speed Mode, I2S Compatible, 32-bit)
Rev. 0.2
2015/09
- 41 -
[AK5558]
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
23 22
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23 22
SDTO3-4 (O)
Figure 43. Mode 24/28 Timing (TDM128 Mode, MSB Justified, 24-bit)
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
SDTO3-4 (O)
Figure 44. Mode 25/29 Timing (TDM128 Mode, I2S Compatible)
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
SDTO2 (O)
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
0 31 30
SDTO3-4 (O)
Figure 45. Mode 26/30 Timing (TDM128 Mode, MSB Justified)
Rev. 0.2
2015/09
- 42 -
[AK5558]
128 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30
SDTO2 (O)
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
0 31 30
SDTO3-4 (O)
Figure 46. Mode 27/31 Timing (TDM128 Mode, I2S Compatible)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
SDTO2-4 (O)
Figure 47. Mode 32/36 Timing (TDM256 Mode, MSB Justified, 24-bit)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
SDTO2-4 (O)
Figure 48. Mode 33/37 Timing (TDM256 Mode, I2S Compatible, 24-bit)
Rev. 0.2
2015/09
- 43 -
[AK5558]
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
Figure 49. Mode 34/38 Timing (TDM256 Mode, MSB Justified, 32-bit)
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31
SDTO2-4 (O)
Figure 50. Mode 35/39 Timing (TDM256 Mode, I2S Compatible, 32-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
23 22
0
23 33
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
23 22
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
32 BICK
23 22
0
31 30
32 BICK
Figure 51. Mode 40/44 Timing (TDM512 Mode, MSB Justified, 24-bit)
Rev. 0.2
2015/09
- 44 -
[AK5558]
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
23 22
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23 22
32 BICK
0
23
32 BICK
Figure 52. Mode 41/45 Timing (TDM512 Mode, I2S Compatible, 24-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
31 30
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0
31 30
32 BICK
Figure 53. Mode 42/46 Timing (TDM512 Mode, MSB Justified, 32-bit)
512 BICK
LRCK (Master)
LRCK (Slave)
BICK (512fs)
SDTO1 (O)
0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31
#2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 #2 Data 7 #2 Data 8 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SDTO2-4 (O)
TDMIN (I)
31 30
(#1 SDTO1)
#1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 #1 Data 7 #1 Data 8
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0 31 30
32 BICK
1 0
31
32 BICK
Figure 54. Mode 43/47 Timing (TDM512 Mode, I2S Compatible, 32-bit)
Parameter
MCLK “” to BICK “↓”
BICK “↓” to MCLK“”
Symbol
Min.
tMCB
tBIM
10
10
Typ.
Max
Unit
ns
ns
Table 10. TDM Mode Clock Timing
Rev. 0.2
2015/09
- 45 -
[AK5558]
VIH
MCLK
VIL
tMCB
tBIM
VIH
BICK
VIL
Figure 55. Audio Interface Timing (Slave Mode, TDM Mode MCLK=2×BICK)
VIH
MCLK
VIL
tMCB
tBIM
VIH
BICK
VIL
Figure 56. Audio Interface Timing (Slave Mode, TDM Mode MCLK=BICK)
[2] DSD Mode
DSD output is available only when the AK5558 is in Master Mode.
The DCLK frequency can be selected from 64fs, 128fs and 256fs by setting the DSDSEL1-0 pins (bits).
The AK5558 enters Phase Modulation mode by setting PMOD pin = “H” or PMOD bit = “1”.
It does not support Phase Modulation mode when the DCLK frequency is 256fs. DCKB bit controls DCLK
polarity. If a large signal that exceeds the input voltage range is input, the data output will not be correct.
DCLK (64fs,128fs,256fs)
DCKB bit=”1”
DCLK (64fs,128fs,256fs)
DCKB bit=”0”
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 57. DSD Mode Timing
Rev. 0.2
2015/09
- 46 -
[AK5558]
■ Digital HPF (PCM mode)
The AK5558 has a digital high-pass filter for DC offset cancellation. The digital high-pass filter is enabled
by setting the HPFE pin (bit) = “H”. The cut-off frequency of the high-pass filter is fixed 1.0Hz when
fs=48kHz (Normal Speed Mode), 96kHz (Double Speed Mode) or 192kHz (Quad Speed Mode). The
high-pass filter is not available in fs=384kHz mode, fs=768kHz mode and DSD mode. So that the setting
of the HPFE pin is ignored. The high pass-filter setting should be changed when the PDN pin = “L”, PW2
pin= PW1 pin= PW0 pin= “L”, RSTN bit = “0” or PW8~1 bits = “00H”.
■ CH Power Down & Mono Mode (PCM mode, DSD mode)
The PW0-2 pins control the input channel power-down and Mono mode setting in parallel mode (Table
11). The power consumption of the device can be improved by setting unused channels to power-down
state. In this case, the channel circuit that is powered down will be rest.
In Mono mode, dynamic range and S/N performance can be improved about 3dB by inputting the same
analog signal to AIN1 and AIN2, AIN3 and AIN4, AIN5 and AIN6, and AIN7 and AIN8. In this mode, AIN1
and AIN2 channel data are summed digitally and output from the SDTO1 (DSDLO1 and DSDRO1) by
dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and
output from the SDTO2 (DSDLO2 and DSDRO2) by dividing into half amplitude. AIN5 and AIN6 channel
data are summed digitally and output from the SDTO3 (DSDLO3 and DSDRO3) by dividing into half
amplitude. AIN6 and AIN7 channel data are summed digitally and output from the SDTO4 (DSDLO4 and
DSDRO4) by dividing into half amplitude.
PW0
pin
1
1
1
1
0
0
0
0
PW1
pin
1
1
0
0
1
1
0
0
PW2
pin
1
0
1
0
1
0
1
0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
ON
ON
ON
ON
ON
ON
CH1+2 CH1+2 CH3+4
CH3+4
CH5+6
CH5+6
ON
ON
ON
ON
OFF
OFF
CH1+2 CH1+2 CH3+4
CH3+4
OFF
OFF
ON
ON
ON
ON
ON
ON
CH1+2 CH1+2 CH3+4
CH3+4
CH5+6
CH5+6
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
Table 11. Channel Power & Mono Mode Setting
Ch7
Ch8
ON
CH7+8
ON
CH7+8
OFF
OFF
ON
OFF
ON
CH7+8
ON
CH7+8
OFF
OFF
OFF
OFF
In 3-wire serial mode or I2C mode, PW1-8 bits control the power of AIN1-8 channels. AINn channel is
powered down when PWn bit = “0” (n=1-8) and AINn channel is in normal operation when PWn bit = “1”.
All channels are set to Mono mode by setting MONO bit = “1”.
■ Digital Filter Setting (PCM mode)
The AK5558 has four types of digital filters and they can be selected by SD pin (bit) and SLOW pin (bit).
SD
pin (bit)
L (0)
L (0)
H (1)
H (1)
SLOW
Filter
pin (bit)
L (0)
Sharp Roll-off Filter
H (1)
Slow Roll-off Filter
L (0)
Short Delay Sharp Roll-off Filter
H (1)
Short Delay Slow Roll-off Filter
Table 12. Digital Filter Setting
Rev. 0.2
2015/09
- 47 -
[AK5558]
■ Overflow Detection (PCM mode, DSD mode)
[1]PCM Mode
The AK5558 has an overflow detect function for the analog input. The OVF pin outputs “H” if one of AIN1
- AIN8 channel overflows (more than 0.3dBFS). The OVF pin returns to “L” when analog input overflows
are resolved. The OVF output for overflowed analog input has the same group delay as the ADC.
[2]DSD Mode
Overflow Detection (Error Detection Function)
The AK5558 outputs overflow flag when detecting overflow status at modulator for DSD output signal
generation. The OVF pin goes to “H” when overflow is detected at one of the L1 ~ R4 channels.
■ DSD Output Function
DSD output is only available when the AK5558 is in master mode.
Rev. 0.2
2015/09
- 48 -
[AK5558]
■ DSD Operation Timing Example
PDN pin
Internal PDN
(1)
MCLK In
Don’t care
Internal
State
Power-Down
Don’t care
Initialize
Normal Operation
Power-Down
(2)
ADC In
(Analog)
(6)
(4)
OVF-pin
(5)
(3)
DSD Out
(Digital)
“L” (-full scale data)
normal data
abnormal data
normal data
“L” (-full scale data)
Figure 58. DSD Operation Timing
Notes:
(1) The internal LDO is powered up by setting the PDN pin to “H” from “L” during the LDOE pin= “H”.
Internal power down signal (internal PDN) changes “0” → “1” in 10ms (max.) after the shutdown
switch is ON following internal oscillator is counting up.
Internal shutdown switch is ON and internal power down signal (internal PDN) changes “0” → “1” in
1ms (max.) by setting the PDN pin to “H” from “L” during the LDOE pin = “L”.
Register writings become available when the internal PDN changes to “1”.
(2) Internal core circuit is powered up and Initialization starts by MCLK input.
Initialization operation will be completed in 583/fs.
(3) DSD output pins output “L” (-full scale data) during power down and initializing operation.
(4) The OVF pin outputs “H” when an excessive signal is input and overflow is detected at internal
modulator.
(5) In the case above (4), the DSD output data will not be correct.
(6) The OVF pin returns to “L” when the input signal settled to a normal state and overflow status of the
internal modulator is resolved.
Rev. 0.2
2015/09
- 49 -
[AK5558]
■ LDO
The voltage range of TVDD is from 1.7 to 1.98V or from 3.0 to 3.6V. Set ON/OFF of the LDO by the LDOE
pin according to TVDD voltage (Table 13).
The internal LDO is switched ON/OFF depending on TVDD voltage range.
LDOE
PDN
LDO
VDD18 pin
L
L
H
H
L
H
L
H
OFF
OFF
OFF
ON
External Power Input 1.7~1.98V
External Power Input 1.7~1.98V
Pulled Down by 500 internally
LDO Voltage Output
Table 13. LDO Select Mode
Additional Voltage Range to
TVDD pin
1.7~1.98V
1.7~1.98V
3.0~3.6V
3.0~3.6V
[1] TVDD=1.7V~1.98V, LDO is OFF (LDOE pin = “L”)
The internal LDO does not work properly when the TVDD voltage range is from 1.7 to 1.98V. Set the
LDOE pin to “L” to switch OFF the LDO. A 1.7 ~ 1.98V is supplied from the VDD18 pin for internal logic
circuits. The voltage difference between TVDD and VDD18 must be ±0.1V or less.
[2] TVDD=3.0V~3.6V, LDO is ON (LDOE pin = “H”)
The internal LDO should be ON when the TVDD voltage range is from 3.0 to 3.6V. It will be the power
supply for the internal logic circuit. The VDD18 pin will be a connection terminal for a stabilization
capacitor. It is not possible to supply the power to external circuits from the VDD18 pin.
Rev. 0.2
2015/09
- 50 -
[AK5558]
■ Power Down Function/ Sequence
The AK5558 enters power-down mode by setting the PDN pin to “L”. Digital filters are reset at the same
time.
PCM Mode:
In slave mode, system reset is released by inputting MCLK, BICK and LRCK after setting the PDN pin
to “H”. The AK5558 detects a rising edge of MCLK first, and then exits power-down mode by a rising
edge of LRCK.
In master mode, system reset is released by inputting MCLK after setting the PDN pin to “H”. The
AK5558 exits power-down mode by a rising edge of MCLK. Initialization cycle starts when power-down
mode is released in PCM mode. Therefore, the output data of SDTO will be valid in 583x fs after exiting
power-down mode in slave mode, it will be valid in 578 x fs after exiting power-down mode in master
mode. During initialization, the ADC digital outputs of both channels are in 2’s complement format and
forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of
initialization (This settling takes approximately the group delay time).
DSD Mode
In master mode, system reset is released by inputting MCLK after setting the PDN pin to “H”. The
AK5558 exits power-down mode by a rising edge of MCLK.
Power
PDN pin
(1)
VDD18 pin
(2)
Internal PDN
(3)
Internal
State
Power -down
Initialize
Normal Operation
Power -down
ADC In
(Analog)
GD
(5)
(5)
GD
(4)
(4)
ADC Out
(Digital)
“0”data
Idle Noise
“0”data
Idle Noise
(6)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
Figure 59. Power-Up/Down Sequence Example
Notes:
(1) The PDN pin should be held to “L” for more than 150nsec after AVDD and TVDD are powered up.
(2) a. LDEO pin = “H”, I2C pin = “H” and PS pin = “H” (Parallel Mode):
The internal LDO is powered up by releasing power-down mode. The internal circuits will be
powered up after the shutdown switch is ON in the end of MCLK counter and internal PDN is
released. The internal PDN is released by toggling MCLK for 16384times or more. Therefore,
MCLK input is necessary in this mode.
Rev. 0.2
2015/09
- 51 -
[AK5558]
b. LDOE pin = “H” and PSN pin = “L” (Register Mode):
The internal LDO is powered up by releasing power-down mode. The internal circuits will be
powered up in 10ms (max.) after the shutdown switch is ON in the end of counter by the internal
oscillator. The internal PDN is released by toggling internal oscillator clock for 16384 times or
more.
c. LDOE pin = “L”:
The internal shutdown switch is ON after power up. The internal circuits will be powered up in 1ms
(max.) after the shutdown switch is ON.
During this period, digital output and digital in/output pins may output an instantaneous pulse (max.
1us). Therefore, referring the output of digital pins and data transmission with a device on the same
3-wire serial/I2C bus as the AK5558 should be avoided in this period to prevent system errors.
(3) Initialization cycle is 583/fs in slave mode and 578/fs in master mode.
(4) The ADC output data is “0” during initialization cycle and power-down mode.
(5) The digital output corresponding to analog input has group delay (GD).
Internal PDN Release Sequence
Figure 60. Internal PDN Release Sequence
Rev. 0.2
2015/09
- 52 -
[AK5558]
■ Operation Mode Control
Operation modes of the AK5558 are set by pins or registers. In parallel mode, the operation mode is set
by pin and register settings are invalid. Therefor the functions that needs register settings are not
available in parallel mode. For register accessing, 3-wire serial and I2C bus communications are
available. This control mode of the AK5558 is selected by the I2C pin and the PSN pin.
I2C pin
L
L
H
H
PSN pin
Control Mode
L
3-wire Serial
H
3-wire Serial
L
I2C Bus
H
Parallel
Table 14. Control Mode
■ Register Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI).
The data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to “1”, Write only),
Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked
in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data
is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max).
The internal registers are initialized by setting the PDN pin = “L”. In serial mode, an internal timing
circuit is reset by setting RSTN bit = “0” but register values are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1=CAD1, C0=CAD0)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 61. Control I/F Timing
* The AK5558 does not support read commands in 3-wire serial control mode.
* When the AK5558 is in power down mode (PDN pin = “L”), a writing into the control registers is
prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more
during CSN is “L”.
Rev. 0.2
2015/09
- 53 -
[AK5558]
(2) I2C-bus Control Mode (I2C pin = “H” and PS pin = “L”)
The AK5558 supports the fast-mode I2C-bus (max: 400kHz, Ver1.0).
(2)-1. WRITE Operations
Figure 62 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 68). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1-0 (device address bits). This bits identifies the
specific device on the bus. The hard-wired input pins (CAD1-0 pins) set these device address bit (Figure
63). If the slave address matches that of the AK5558, the AK5558 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the
SDA line (HIGH) during the acknowledge clock pulse (Figure 69). R/W bit = “1” indicates that the read
operation is to be executed. “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5558. The format is MSB first, and
those most significant 3-bits are fixed to zeros (Figure 64). The data after the second byte contains
control data. The format is MSB first, 8bits (Figure 65). The AK5558 generates an acknowledge after
each byte is received. Data transfer is always terminated by a STOP condition generated by the master.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 68).
The AK5558 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK5558 generates an acknowledge and awaits the next data. The master can transmit more than
one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each
data packet the internal 6-bit address counter is incremented by one, and the next data is automatically
taken into the next address. If the address exceeds “07H” prior to generating a stop condition, the
address counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW (Figure 70) except
for the START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
1st byte
Sub
Address(n)
A
C
K
2nd byte
Data(n)
A
C
K
Data(n+1)
A
C
K
3rd byte
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 62. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
A1
A0
D1
D0
(CAD0 and CAD1 are set by pins)
Figure 63. The First Byte
0
0
0
A4
A3
A2
Figure 64. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 65. Byte Structure After The Second Byte
Rev. 0.2
2015/09
- 54 -
[AK5558]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5558. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “07H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK5558 supports two basic read operations: Current Address Read and Random Address Read.
(2)-2-1. Current Address Read
The AK5558 contains an internal address counter that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK5558 generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK5558 ceases transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 66. Current Address Read
(2)-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit =“1”. The AK5558 then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK5558 ceases transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 67. Random Address Read
Rev. 0.2
2015/09
- 55 -
[AK5558]
SDA
SCL
S
P
start condition
stop condition
Figure 68. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 69. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 70. Bit Transfer on the I2C-Bus
Rev. 0.2
2015/09
- 56 -
[AK5558]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Management1
Power Management2
Control 1
Control 2
Control 3
DSD
TEST1
TEST2
D7
PW8
0
0
0
DP
0
TST7
0
D6
PW7
0
CKS3
TDM1
0
0
TST6
0
D5
PW6
0
CKS2
TDM0
0
DCKS
TST5
0
D4
PW5
0
CKS1
0
0
0
TST4
0
D3
PW4
0
CKS0
0
0
PMOD
TST3
0
D2
PW3
0
DIF1
0
0
DCKB
TST2
0
D1
PW2
MONO
DIF0
0
SD
DSDSEL1
TST1
0
D0
PW1
RSTN
HPFE
0
SLOW
DSDSEL0
TST0
TRST
Note 24. Data must not be written into addresses from “08H” to “1FH”.
Note 25. The bits indicated as “0” must contain a “0” value. When RSTN bit is set to “0”, the internal digital
filter and the control block are reset but the register values are not initialized.
Note 26. When the PDN pin is set to “L”, all registers are initialized to their default values.
■ Register Definitions
Addr
00H
Register Name
D7
D6
Power Management1
PW8
PW7
R/W
R/W
R/W
Default
1
1
PW8-1: Power Down control for channel 8-1
0: power OFF
1: power ON (default)
D5
PW6
R/W
1
D4
PW5
R/W
1
Addr
01H
Register Name
D7
D6
D5
D4
Power Management2
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
Internal clock timings are reset but registers are not reset.
D3
PW4
R/W
1
D2
PW3
R/W
1
D1
PW2
R/W
1
D0
PW1
R/W
1
D3
0
R/W
0
D2
0
R/W
0
D1
MONO
R/W
0
D0
RSTN
R/W
1
D3
CKS0
R/W
0
D2
DIF1
R/W
0
D1
DIF0
R/W
0
D0
HPFE
R/W
1
MONO: Monaural Mode
0: Stereo mode (default)
1: MONO mode
When this bit is “1”, all channels enter monaural mode.
Addr
02H
Register Name
D7
D6
D5
D4
Control 1
0
CKS3 CKS2 CKS1
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
HPFE: High Pass Filter Enable
0: High Pass Filter OFF
1: High Pass Filter ON (default)
When this bit is “1”, digital HPFs for all channels are ON.
DIF1-0: Audio Data Interface Modes Select (Table 8, Table 9)
Select A/D data bit length (24-bit/32-bit) and the format (MSB justified/ I2S Compatible)
CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 5)
Select Sampling Speed and MCLK frequency.
Rev. 0.2
2015/09
- 57 -
[AK5558]
Addr
03H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
0
TDM1 TDM0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
TDM1-0: TDM Modes Select (Table 9)
Select the A/D data output mode from Normal, TDM128, TDM256 and TDM512 modes.
Addr
04H
Register Name
D7
D6
D5
Control 3
DP
0
0
R/W
R/W
R/W
R/W
Default
0
0
0
SLOW: Slow Roll-off Filter Select (Table 12)
0: Sharp Roll-off (default)
1: Slow Roll-off
Select Roll-off characteristic of the digital filter.
SD:
Short Delay Select (Table 12)
0: Normal Delay (default)
1: Short Delay
Select group delay of the digital filter.
DP:
DSD Mode Select
0: PCM Mode (default)
1: DSD Mode
Select Output Mode.
Addr Register Name
D7
D6
05H DSD
0
0
R/W
R/W
R/W
Default
0
0
DSDSEL1-0: Select the Frequency of DCLK
00: 64fs (default)
01: 128fs
10: 256fs
11: Reserved (128fs)
D5
DCKS
R/W
0
D4
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D3
PMOD
R/W
0
D2
0
R/W
0
D1
SD
R/W
0
D0
SLOW
R/W
0
D2
D1
D0
DCKB DSDSEL1 DSDSEL0
R/W
R/W
R/W
0
0
0
DCKB: Polarity of DCLK
0: DSD data is output from DCLK Falling Edge (default)
1: DSD data is output from DCLK Rising Edge
PMOD: DSD Phase Modulation Mode
0: Not Phase Modulation Mode (default)
1: Phase Modulation Mode
DSD Output Phase Modulation Mode Enable
DCKS: Master Clock Frequency Select at DSD Mode (DSD Only)
0: 512fs (default)
1: 768fs
Rev. 0.2
2015/09
- 58 -
[AK5558]
Addr
06H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
TEST 1
TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0
R/W
RD
RD
RD
RD
RD
RD
RD
RD
Default
0
0
0
0
0
0
0
0
TST7-0: Test register.
This register must be used as the default setting. Normal operation is not guaranteed if all bits
are not “0”.
Addr
07H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
TEST 2
0
0
0
0
0
0
0
TRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Default
0
0
0
0
0
0
0
0
TRST: Test register.
This register must be “0”.
This register must be used as the default setting. Normal operation is not guaranteed if all bits
are not “0”.
Rev. 0.2
2015/09
- 59 -
[AK5558]
AIN1+
AIN1
Analog 5V
0.1
+
0.1
0.1
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CKS3/CAD1
CKS2/SCL/CCLK
CKS1/CAD0_I2C/CSN
CKS0/SDA/CDTI
OVF
DSDOR4
DSDOL4
SDTO4/DSDOR3
SDTO3/DSDOL3
SDTO2/DSDOR2
SDTO1/DSDOL2
TDMIN/DSDOR1
LRCK/DSDOL1
BICK/DCLK
DIF1/DSDSEL1
MSN
PW2
PW1
PW0
PDN
VDD18
DVSS
TVDD
MCLK
TEST1
AIN8P
AIN8N
VREFL4
VREFH4
AIN7N
AIN7P
OVFFUNC/TDM0
OVFRST/TDM1
PS/CAD0_SPI
I2C
DP
HPFE/DCKS
LDOE
TEST2
AIN1P
AIN1N
VREFL1
VREFH1
AIN2N
AIN2P
AK5558
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Mode
Setting
Controller
4.7
+
0.1
10
AIN8+
AIN8
0.1
+
0.1
Digital 3.3V
Mater Clock
10
Analog 5V
AIN7
AIN7+
0.1
0.1
+
AIN6
AIN6+
Analog 5V
10
0.1
0.1
10
AIN4
AIN4+
AIN5+
AIN5
Analog 5V
Analog 5V
+
0.1
0.1
0.1
+
10
0.1
+
Analog 5V
AIN3+
AIN3
10
0.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AIN2
AIN2+
10
DIF0/
DSDSEL0
Controller
AVSS1
AVDD1
AIN3P
AIN3N
VREFL2
VREFH2
AIN4N
AIN4P
AIN5P
AIN5N
VREFH3
VREFL3
AIN6N
AIN6P
AVDD2
AVSS2
Mode
Setting
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SD/PMOD 48
SLOW/DCKB 47
Mode
Setting
fs
64fs
13. Recommended External Circuits
Figure 71 shows recommended external connection. An evaluation board (AKD5558) is available for fast
evaluation as well as suggestions for peripheral circuitry.
Figure 71. Typical Connection Diagram
Note 27. All digital input pins must not be allowed to float.
Rev. 0.2
2015/09
- 60 -
[AK5558]
1. Grounding and Power Supply Decoupling
The AK5558 requires careful attention to power supply and grounding arrangements. Normally AVDD
1/2 and TVDD are supplied from analog supply of the system. The power-up sequence between
AVDD1/2 and TVDD are not critical when AVDD1/2 and TVDD are supplied separately. DVSS and
AVSS1/2 must be connected to the same analog ground plane. System analog ground and digital
ground should be wired separately and connected together as close as possible to where the supplies
are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as
near as possible to the supply pin.
2. Reference Voltage
The differential voltage between the VREFH1-4 pin and the VREFL1-4 pin sets the full-scale analog
output range. The VREFL1/2/3/4 pin is normally connected to the analog ground. VREFH1-4 and
VREFL1-4 should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to
eliminate the effects of high frequency noise. All digital signals, especially clocks, should be kept away
from the VREFH1-4 and VREFL1-4 pins in order to avoid unwanted noise coupling into the AK5558.
3. Analog Inputs
The Analog input signal is differentially supplied into the modulator via the AINn+ and the AINn- pins (n=
1-8). The input voltage is the difference between the ALINn+ and ALINn- pins (n= 1-8). The full scale
signal on each pin is nominally ±2.8V (typ). A voltage from AVSS1/2 to AVDD1/2 can be input to the
AK5558. The output code format is two’s complement. The internal HPF removes DC offset (including
DC offset by the ADC itself).
The AK5558 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of
AVDD1/2+0.3V and lower limit of AVSS1/2 -0.3V and any current beyond 10mA for the analog input pins
should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must
be protected from signals at or beyond these limits. Use caution especially when using ±15V for other
analog circuits in the system.
Rev. 0.2
2015/09
- 61 -
[AK5558]
4. External Analog Circuit Examples
Figure 72 shows an input buffer circuit example 1. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351 kHz,
gain= -14.5dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2
for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-14.9Vpp (AK5558:
+/-2.8 Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=115dB,
S/(N+D)=106dB.
4.7k
4.7k
Analog In
620
JP1
VP+
Vin- 68µ
+
14.9Vpp
Bias
VP-
1n
3.3k
10
+
2.8Vpp
AK5558 AINn+
NJM5534
NJM5534
XLR
15n
VA+
620
10k
Bias
11k
JP2
68µ
-
+
10µ
1n
3.3k
Vin+
0.1µ
10
AK5558 AINn-
+
NJM5534
Bias
VA=+5V
VP=15V
2.8Vpp
Figure 72. Input Buffer Example1
fin
1Hz
10Hz
Frequency Response
1.77dB
0.02dB
Table 15. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
Frequency Response
0.00dB
0.00dB
0.00dB
Table 16. Frequency Response of LPF
Rev. 0.2
6.144MHz
49.68dB
2015/09
- 62 -
[AK5558]
14. Package
■ Outline Dimensions
64-pin QFN (Unit mm)
9.00±0.15
A
0.40±0.10
8.75
B
64
49
48
48
1
33
16
6.15
8.75
9.00±0.15
1
64
49
16
33
32
17
0.10
M AB
0.25
+0.05
-0.07
.60
C0
X
MA
32
0.50
17
6.15
+0.15
S
0.85 -0.05
+0.03
-0.02
0.08
0.02
0.20
S
■ Material & Lead Finish
Package molding compound: Epoxy resin
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
■ Marking
5558VN
XXXXXXX
1
1)
2)
3)
Pin #1 indication
Date Code : XXXXXXX (7 digits)
Marketing Code : 5558VN
Rev. 0.2
2015/09
- 63 -
[AK5558]
15. Ordering Guide
■ Ordering Guide
TBD
AK5558VN
-40~105ºC
64-pin QFN
Rev. 0.2
2015/09
- 64 -
[AK5558]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
Rev. 0.2
2015/09
- 65 -