New Features for Solving HSD Challenges with ADS 2013 What is Jitter Amplification and Why Should I Care Fangyi Rao “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 1 Outline • What is Jitter Amplification • Mechanism of Jitter Amplification in Clock Channels • Impacts on Link Analyses • Summary “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 2 What is Jitter Amplification: a RJ Example channel ISI + RJout RJin 2 2 2 σ tot = σ ISI + σ RJ ,out σRJ,in : input RJ RMS σtot : total RMS of output jitter σISI : output ISI RMS σRJ,out : output RJ RMS • ISI is measured with zero input jitter. • RJout is induced by RJin. When RJ is small, σRJ,out is proportional to σRJ,in Jitter Amplification σRJ,out > σRJ,in “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 3 What is Jitter Amplification (cont’d) • Same amplification happens to other jitter components including duty-cycle-distortion (DCD) and sinusoidal jitter (SJ) • DCD : output peak-to-peak DCD > input peak-to-peak DCD • SJ : output SJ amplitude > input SJ amplitude • Jitter is amplified even when the channel is linear, passive and noiseless • As we will show later, amplification is caused by channel loss • The effect arises from lower attenuation at the jitter lower sideband (LSB) than at the signal carrier (which is at a higher frequency compared to jitter LSB) 0 frequency ω0−ω ω0 ω+ω0 LSB carrier USB “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 4 Observations on DCD and RJ in Clock Channels: Intel EPEPS 2006 • Two 15-inch passive clock channels at 6.4Gbps and 9.6Gbps • One with 100 ohm (matched) backplane, the other with 81 ohm (mismatched) backplane • Benefits of studying clock channels: ISI=0 due to periodic 1010 clock pattern • Output jitter is entirely induced by input jitter • Amplification can be measured directly from output jitter without having to subtract ISI S. Chaudhuri, W. Anderson, J. McCall, and S. Dabrai, “Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s,” Proc. IEEE 15th Topical Meeting on Electric Performance of Electronic Packaging, Scottsdale, AZ, Oct. 2006, pp. 21-24. “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 5 Observations on DCD and RJ in Clock Channels: Intel EPEPS 2006 (cont’d) DCD RJ Amplification increases with data rate S. Chaudhuri, W. Anderson, J. McCall, and S. Dabrai, “Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s,” Proc. IEEE 15th Topical Meeting on Electric Performance of Electronic Packaging, Scottsdale, AZ, Oct. 2006, pp. 21-24. “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 6 Observations on DCD and RJ in Clock Channels: Rambus EPEPS 2007 24-inch PCB clock channel at data rates up to 12G measurement simulation 8, 16, and 24-inch PCB clock channels at data rates between 2 and 6G simulation • DCD and RJ amplifications scale uniquely with loss • Indicates a link between the effect and channel loss C. Madden, S. Chang, D. Oh and C. Yuan, “Jitter Amplification Considerations for PCB Clock Channel Design,” IEEE 16th Topical Meeting on Electr. Performance Electron. Packag., Atlanta, GA, pp. 135-138, Oct. 2007. “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 7 Observations on RJ in Data Channel: Agilent DesignCon 2010 • Simulations on a passive data channel at 1, 3, and 5G with PRBS31 • Step 1: turn off input jitter, run 106 bits and measure output jitter RMS, which is σISI • Step 2: turn on input RJ, run 106 bits and measure output jitter RMS, which is σtot • Step 3: extract output RJ RMS by σRJ,out2 = σtot2 - σISI2 • Step 4: RJ amplification factor = σRJ,out / σRJ,in F. Rao, V. Borich, H. Abebe and M. Yan, “Rigorous modeling of transmit jitter for accurate and efficient statistical eye simulation,” IEC DesignCon, Feb. 2010. “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 8 Observations on SJ, DCD and RJ in Clock Channel: Agilent EPEPS 2012 • Simulate 106 bits on 4 passive clock channels with different losses • Each channel is simulated at different data rates up to 16G • SJ amplification (ASJ,out / ASJ,in) is found to increase exponentially with SJ frequency • DCD and RJ scale uniquely with loss (Insertion loss is measured at fundamental) F. Rao and S. Hindi, “Frequency domain analysis of jitter amplification in clock channels,” Proc. IEEE 21th Topical Meeting on Electric Performance of Electronic Packaging, Tempe, AZ, Oct. 2012, pp. 51-54. http://cp.literature.agilent.com/litweb/pdf/5991-1255EN.pdf “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 9 Outline • What is Jitter Amplification • Mechanism of Jitter Amplification in Clock Channels • Impacts on Link Analyses • Summary “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 10 Sinusoidal Wave Representation of Clock Signal • Periodicity of 1010 clock pattern completely eliminates ISI • Output jitter is induced solely by input jitter • High order harmonics are heavily attenuated in lossy channel • Repeated 1010 clock signal can be approximated by a sinusoidal wave • Jitter can be represented by phase modulation vin vin t t vin (t ) = A cos[ω0t + θ 0 + φ (t )] ≈ A j (ω0t +θ 0 ) [e + jφ (t )e j (ω0t +θ 0 ) ] + complex conjugate 2 ω0: fundamental frequency, half of data rate φ: phase modulation that represents jitter “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 11 Sinusoidal Jitter Amplification • Input signal with SJ at ω φ (t ) = φ (ω )e jωt + φ (ω )* e − jωt Ae jθ 0 jω0t vin = [e + jφ (ω )e j (ω +ω0 ) t + jφ (ω )* e j ( −ω +ω0 ) t ] + c.c 2 • Output signal carrier USB LSB Ae jθ 0 vout (t ) = [ H (ω0 )e jω0t + jH (ω + ω0 )φ (ω )e j (ω +ω0 )t + jH (−ω + ω0 )φ (ω )* e j ( −ω +ω0 )t ] + c.c 2 Ae jθ0 H (ω + ω0 ) H (−ω + ω0 ) φ (ω )e j (ω +ω0 )t + j = H (ω0 )[e jω0t + j φ (ω )* e j ( −ω +ω0 )t ] + c.c 2 H (ω0 ) H (ω0 ) carrier USB LSB 0 frequency • H(ω) decays exponentially with ω in lossy channel • LSB is attenuated less than the carrier is by a factor of H(ω0-ω)/H(ω0) • A gain of PM is induced at the channel output, leading to jitter amplification ω0−ω ω0 ω+ω0 LSB carrier USB “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 12 Sinusoidal Jitter Amplification (cont’d) • Output signal AM PM vout (t ) ≈ A | H (ω0 ) | exp[ − Imψ + (t )] cos[ω0t + jθ 0 + j∠H (ω0 ) + j Reψ + (t )] ψ + (t ) = H (ω + ω0 ) H ( −ω + ω0 ) φ (ω )e jωt + φ (ω )* e − jωt H (ω0 ) H (ω0 ) • AM and PM are induced at output by input SJ, causing impairments in time and voltage • Output SJ φout (t ) = Reψ + (t ) = H (ω + ω0 ) H (ω − ω0 ) + | φ (ω ) | cos[ωt + ∠φ (ω ) + γ ] H (ω0 ) H (−ω0 ) SJ transfer function/amplification factor: amplitude ratio between output and input SJ FSJ (ω ) = 1 H (ω + ω0 ) H (ω − ω0 ) + 2 H (ω0 ) H (−ω0 ) • Jitter amplification is the result of smaller loss in LSB than in fundamental • When reflection is small, H(ω) can be replaced by forward S-parameters “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 13 DCD Amplification • DCD is a special case of SJ at ω=ω0 DCD amplification factor FDCD = H (0) 1 H (2ω 0 ) + 2 H (ω 0 ) H (−ω 0 ) • At ω=ω0, LSB becomes a DC shift • Output = DC + Fundamental + Higher orders harmonics (negligible under loss) • Signal is shifted vertically by DC, causing imbalance between 1-bit and 0-bit cycles, i.e. DCD • DC shift is proportional to H(0), which is always around 0dB regardless the loss • Fundamental is proportional to H(ω0) • The larger the loss at ω0, the smaller the fundamental amplitude, and the larger the DCD “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 14 Random Jitter Amplification Input RJ: assume white noise with flat power spectral density ω0 < φ (t ) 2 >= ∫ dωC = 2Cω 0 −ω0 Output RJ ω0 < φ out (t ) 2 >= 2C ∫ dω FSJ (ω ) 2 0 RJ amplification factor: RMS ratio between output and input RJ < φout (t ) 2 > 1 FRJ = = < φ (t ) 2 > 4ω0 ∫ ω0 0 H (ω + ω0 ) H (ω − ω0 ) dω + H (ω0 ) H (−ω0 ) 2 “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 15 Comparison with Square Wave Formulation • Input clock signal is modeled by square wave. Jitter is applied to transitions. τin • Output signal is computed with superposition of step response R(t) vout (t ) = ∑ R(t − lT − τ l =even in l ∑ R(t − mT − τ )− in m ) m =odd • Output jitter is measured from crossing time shift ∑ (−1) h(nT + t − mT )τ = ∑ (−1) h(nT + t − mT ) m in m d τ nout m td: channel delay m d h(t): dR/dt or impulse response. FT[h]=H(ω) m • For input SJ τmin = Λcos(ωmT), DTFT yields τ nout = Λ 2 ∑ H (ω + kω )e ∑ H ( kω ) e j (ω + k ω 0 ) t d 0 0 j ( ω + kω0 ) t d 0 k = odd k = odd ∑ H (ω + kω )e ∑ H (kω )e jkω0 t d e jωnT + c.c = Λ k =odd jkω0t d cos(ωnT + α ) 0 k =odd “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 16 Comparison with Square Wave Formulation (cont’d) SJ amplification factor ∑ H (ω + kω )e ∑ H (kω )e j (ω + kω0 ) td 0 FSJ (ω ) = k =odd jkω0t d 0 k = odd • Converge to sinusoidal wave result after neglecting higher order harmonics and using phase delay of H at ω0 for td FSJ (ω ) = 1 H (ω + ω 0 ) H (ω − ω 0 ) + 2 H (ω 0 ) H (−ω 0 ) “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 17 Scaling of DCD and RJ Amplification with Loss • Channel loss model H (ω ) = exp(−k | ω | − jω t d ) SJ amplification factor for ω < ω0 e − kω + e kω FSJ (ω ) = ≥1 2 • Jitter is amplified at all frequencies below ω0. FSJ grows exponentially with frequency. DCD and RJ amplifications FDCD e − kω0 + e kω0 = 2 e 2 kω0 − e −2 kω0 1 + FRJ = 8kω0 2 • FDCD and FRJ grow exponentially with data rate DCD and RJ scaling with loss FDCD = cosh [ln 10⋅ | D (ω 0 ) | / 20 ] FRJ = 5 ln 10 1 sinh | D (ω 0 ) | + ln 10⋅ | D (ω 0 ) | 10 2 ( D(ω0 ) = 20 log10 | H (ω0 ) |) “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 18 Comparison with Simulations • 4 single-ended channels with different losses • Input clock signal is modeled by square wave with jitter applied at transitions • Output signal is computed with linear superposition • 1 million bits per simulation Insertion loss “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 19 SJ • Channel 2 at 10Gbps with input SJ amp = 5ps and frequency = 0.5, 2 and 3GHz Simulated output eyes Simulated output jitter distributions “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 20 SJ (cont’d) FSJ in channel 1 at 10Gbps and channel 2 at 10 and 20Gbps Theory 1 FSJ (ω ) = 1 S 21(ω + ω0 ) S 21(ω − ω0 ) + 2 S 21(ω0 ) S 21(−ω0 ) Theory 2 (loss approx.) FSJ (ω ) = e − kω + ekω 2 • Two theoretical predictions with S(2,1) and with loss model (k is extracted from insertion loss slope) agree with simulations • Loss model is shown to be a good approximation in these channels • FSJ grows exponentially with jitter frequency • FSJ is insensitive to data rate, as predicted by the loss model “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 21 DCD FDCD in channels 1 and 2 Theory 1 FDCD = 1 S 21(2ω0 ) S 21(0) + 2 S 21(ω0 ) S 21(−ω 0 ) Theory 2 (loss approx.) FDCD = e− kω0 + ekω0 2 “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 22 RJ Simulated output jitter distribution of channel 1 at 8, 12 and 16Gbps with 1ps input RJ FRJ in channels 1 and 2 Theory 1 FRJ = 1 4ω0 ∫ ω0 0 S 21(ω + ω0 ) S 21(ω − ω0 ) dω + S 21(ω0 ) S 21( −ω0 ) 2 Theory 2 (loss approx.) e 2 kω0 − e −2 kω0 1 FRJ = + 8kω0 2 “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 23 DCD and RJ Amplification Scaling with Loss • All 4 channels, each at difference data rates up to 16Gbps (Insertion loss is measured at fundamental) Scaling Theory FDCD = cosh [ln 10⋅ | D (ω 0 ) | / 20] FRJ = 5 ln 10 1 sinh | D (ω 0 ) | + ln 10⋅ | D (ω 0 ) | 10 2 “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 24 Outline • What is Jitter Amplification • Mechanism of Jitter Amplification in Clock Channels • Impacts on Link Analyses • Summary “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 25 Physical Model of Tx Jitter Tx jitter must be applied to the stimulus input to the channel in both bit-by-bit (time-domain) and statistical simulations i th pulse 0 t r (i ) τ r (i ) 1 1 0 nr (i )T n f (i )T t f (i ) 0 1 1 0 0 Ideal edge τ f (i ) t r (i ) = nr (i ) ⋅ T + τ r (i ) t f (i) = n f (i) ⋅ T + τ f (i ) τ r (i ) = η rRJ (i ) + ASJ cos[ω SJ nr (i )T ] + (−1) n (i ) DCD r τ f (i ) = η RJ f (i ) + ASJ cos[ω SJ n f (i )T ] + ( −1) n f (i ) DCD RJ, SJ and DCD are advanced jitter parameters in AMI extension, which are supported in ADS2012.08 “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 26 Physical Model of Tx Jitter (cont’d) Adding Tx jitter in post-processing by convolving Tx jitter PDF with ISI PDF, like in the StatEye approach, will miss jitter amplification, thus underestimate jitter at channel output Tx RJ example Timing bathtub at channel output Voltage bathtub at channel output Statistical simulation with Tx jitter applied to input 106 bits time-domain simulation with Tx jitter applied to input Add Tx jitter in post-processing “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 27 Summary • Jitter is amplified by channel loss • It occurs even when the channel is linear, passive and noiseless • Amplification arise from smaller attenuation in jitter LSB than in the fundamental • In lossy clock channels, jitter is amplified at any jitter frequency below Nyquist • The effect grows exponentially with jitter frequency and data rate • DCD and RJ amplifications scale uniquely with loss in clock channel • Tx jitter must be applied in input stimulus when simulating link performance in order to capture the amplification effect “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 28 Reference 1. S. Chaudhuri, W. Anderson, J. McCall, and S. Dabrai, “Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s,” Proc. IEEE 15th Topical Meeting on Electric Performance of Electronic Packaging, Scottsdale, AZ, Oct. 2006, pp. 21-24. 2. C. Madden, S. Chang, D. Oh and C. Yuan, “Jitter Amplification Considerations for PCB Clock Channel Design,” IEEE 16th Topical Meeting on Electr. Performance Electron. Packag., Atlanta, GA, pp. 135-138, Oct. 2007. 3. F. Rao, V. Borich, H. Abebe and M. Yan, “Rigorous modeling of transmit jitter for accurate and efficient statistical eye simulation,” IEC DesignCon, Feb. 2010. 4. F. Rao and S. Hindi, “Frequency domain analysis of jitter amplification in clock channels,” Proc. IEEE 21th Topical Meeting on Electric Performance of Electronic Packaging, Tempe, AZ, Oct. 2012. pp. 51-54. http://cp.literature.agilent.com/litweb/pdf/5991-1255EN.pdf “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 29 Thank you “New Features for Solving HSD Challenges with ADS 2013” Copyright © 2013 Agilent Technologies 30