Post Layout EM Simulation for Signal Integrity Verification 1 Agenda • Introduction to Fast Channel Simulation for Pre Layout Design • Introduction to SAS Specifications • Post Layout Extraction and Simulation of SAS/SATA Board & Backplane • Eye Diagram Simulation with Transmit Equalization • Receive Equalization at 6 Gbps using ADS2009 Update 1 Post Layout Simulation in ADS 2 Channel System Architecture • Basic components: transmitter, channel, receiver and crosstalk • Rise and fall edges of each bit are modulated by various jitters Post Layout Simulation in ADS 3 Eye Diagram and BER • Eye opening is determined by jitter and crosstalk. Post Layout Simulation in ADS 4 Different Jitter Type • Inter-symbol-interference (ISI): caused by channel dispersion. ISI • Duty-cycle-distortion (DCD) ideal edge 1 0 1 1 DCD 0 t • Periodic jitter (PJ): due to modulation (AM, PM & FM), power switching and period EMI source. • Random jitter (RJ) in Tx • RJ in Rx sample time Post Layout Simulation in ADS 5 Crosstalk • Crosstalk is caused by coupling between forward and crosstalk channels. Xtlk channel coupling Tx channel Output • Synchronous crosstalk: relative signal phase between Xtlk & Tx is fixed • Asynchronous crosstalk: signal phase is random relative to Tx Post Layout Simulation in ADS 6 Tx Emphasis main cursor pre-cursor t post-cursor Vout (t ) = L + a−1Vin (t + ∆ ) + a0Vin (t ) + a1Vin (t − ∆ ) + a2Vin (t − 2∆ ) + L Before emphasis After emphasis Post Layout Simulation in ADS 7 Rx Equalizer • Feed-forward-equalizer (FFE) Vout (t ) = a0Vin (t ) + a1Vin (t − T ) + a2Vin (t − 2T ) + L • Continue-time-equalizer (CTE): pole-zero ( s − z1 )( s − z 2 ) L H ( s) = A ( s − p1 )( s − p1 ) L Before EQ After EQ Post Layout Simulation in ADS 8 Challenges in Signal Integrity Simulation • Extremely low BER. • Reliable statistics require samples of millions of bits. Regular transient simulation is impractical. • Account for different types of jitter: ISI, DCD, PJ & RJ. • Tx and Rx equalizers. • Effects of crosstalk channels. • Optimization of channel and equalizer. Post Layout Simulation in ADS 9 ADS Channel Simulator: An Integrated Solution for SI Designs EyeDiff_Probe EyeDiff V+ TX_CLK Tx Driver Via1 2 Rx Amp TL1 Ref TXN_NEAR S4P SNP1 RX_INN Via2 Metal-1 TX2 Dielectric-1 Metal-2 Metal-i : T[i], COND[i], TYPE[i] Dielectric-i : ER[i], H[i], TAND[i] RXP RX_INP 4 1 3 TX_CLKB V- ML2CTL_V CLin1 TXP_NEAR blah blah_1 ModelType=MW RXN TL2 RX1 Subst1 Post Layout Simulation in ADS 10 Simulation Technologies: Superposition in LTI Systems • Response of single bit. • Response of multiple bits. Superposition ISI Post Layout Simulation in ADS 11 Simulation Techniques • Assume LTI system. • Channel characterization: run transient to calculate step response S(t) of Tx channel and each Xtlk channel. • Include Tx and Rx equalizers in S(t). • Bit-by-bit superposition of pulse response of Tx and Xtlk bits. vout (t ) = ∑ [ STx (t − tri ) − STx (t − tf i )] + ∑ [ S Xtlk (t − trj ) − S Xtlk (t − tf j )] i j • ISI is included in superposition. • Rise time tr and fall time tf are modulated by DCD, PJ and RJ. Post Layout Simulation in ADS 12 Asynchronous Crosstalk Phase between TX and Xtlk is random vout = vTx + v Xtlk1 + v Xtlk 2 pout (v, t ) = pTx (v, t ) ∗ p Xtlk 1 (v) ∗ p Xtlk 2 (v) (convolve over v) • Average Xtlk PDF over UI • Convolve Tx PDF with averaged Xtlk PDF Rx Random Jitter • Rx jitter smears sample time • Equivalent to averaging PDF with Gaussian kernel along time axis p out (v, t ) = ∫ p in (v, t + τ ) g σ (τ ) dτ = pin (v, t ) ∗ g σ (t ) (convolve over t ) Post Layout Simulation in ADS 13 SAS-2 Specifications The SAS-2 6Gb/s Rx/ Tx requirements assumption Data Rate Transmitter 6Gb/s Differential Amplitude mV(p-p) 800 –1200 Return loss dB < 6a at 3GHz Recommenced Rise/Fall time 20-80% ps Differential impedance Ohm 100Ohm +/-15% DJ UI < 0.15 RJ, CDF level 1e-15 UI < 0.15 Transmitter- Equalizer 1-tap post cursor de-emphasis with gain dB > 30 < 6dB Receiver Return loss dB Differential impedance Ohm Equalized eye amplitude TJ, CDF level 1e-15 UI <6a 100 +/-15%b mV(p-p) > 100 < 0.6 Rx-Equalizer DFE with number of taps (or equivalent in performance FIR filter) - 5 Adaptability Yes Limit for the sum of DFE taps for Tx =1Vpp, absolute value Vpp 0.263 Post Layout Simulation in ADS 14 Compliance Mask Specifications Post Layout Simulation in ADS 15 Challenges for Post Layout Simulation • Complex multilayer board • Long trace lengths (typically 3” to 17” or more) • 4 to 40 layer stack-up • Multiple power and ground planes • Complex via structures • Long via stubs • Crosstalk and impedance mismatch • EM Simulation • Accuracy • Time and memory requirement Post Layout Simulation in ADS 16 SAS/SATA Channel Plug in Unit Connector Backplane Post Layout Simulation in ADS 17 SAS/SATA Channel Backplane Differential Trace – Layer 12 10043546-101LF 10039851-101LF FCI FCI Vitesse VSC7157-02 expander (U12) Drive_2_TX Backplane Differential Trace – Layer 12 Drive_2_RX PIU Left Side Via Transition PIU Right Side Via Transition Backplane Left Side Via Transition Backplane Right Side Via Transition Post Layout Simulation in ADS 18 Plug in Unit Card Critical net Extraction DRIVE_12_C_TX_P DRIVE_12_C_TX_N DRIVE_12_C_RX_P DRIVE_12_C_RX_N Post Layout Simulation in ADS 19 Allegro/APD to ADS Flow APD/Allegro Momentum Export Setup Select Critical Nets or Entire Layout Cookie-cut Power and Ground Planes Portion Import in ADS Layout Create Ports Ground Ref Port Adjustments if required Select Stackup Layers Export to ADS Layout Verify Layout using 3-D Preview and Simulate Post Layout Simulation in ADS 20 Page 20 Export Setting • Default settings – Fine setting A – Fine setting B – Medium setting – Coarse setting • User defined settings – Change in arc resolution – Bring signal via as is and convert gnd via to rectangular – Remove non-functional pads – ... Post Layout Simulation in ADS 21 Page 21 Simulation Methodology For board/backplane post layout analysis take advantage of board layout properties EMDS Board File Board File Critical nets Extraction using Allegro DFI Critical nets Extraction using Allegro DFI with stack-up limited between PWR/GND planes ADS Import EMDS Crop Via Portion ADS Import Momentum RF Run EMDS Crop Diff pair portion Run Momentum RF Post Layout Simulation in ADS 22 What is Momentum? • Method of Moments simulator for restricted 3D passive circuits • Frequency Domain • Uses precomputed Green’s functions for faster EM simulations than full 3D simulators can achieve • Layout driven (accepts arbitrary geometry) • Visualization of current and far-field patterns • Layout Components for ADS schematic • Co-simulation/Co-optimization with circuits/systems Post Layout Simulation in ADS 23 Application Overview • 3D Circuit Components - LTCC - Embedded passives • Packages and Interconnects • Circuit- System3DEM Co-simulation Post Layout Simulation in ADS 24 EMDS-G2 Technology Finite Element Method (FEM) ¾ Generate mesh of triangles on ports and tetrahedrons in 3D space ¾ Compute Port modes and use as excitation for 3D structure ¾ Approximate electric field over each tetrahedron with a second-order polynomial containing unknown coefficients ¾ Solve resulting matrix to determine values for the polynomial coefficients ¾ Derive S-parameters Post Layout Simulation in ADS 25 PIU Left Side Via Simulation Positive Pwr/Gnd were converted to slot layers Post Layout Simulation in ADS 26 Left Side Via -3D Preview PIU Left Side Via using Momentum MW Mode Simulation Post Layout Simulation in ADS 27 EMDS Simulation of PIU Left Side Via Comparison of simulation results EMDS Plot Momentum Plot Post Layout Simulation in ADS 28 Comparison on Via Simulation Results EMDS Momentum MW Momentum RF RF mode provide good performance Momentum MW mode or EMDS is essential Post Layout Simulation in ADS 29 Drive_12_TX Nets Differential pair brought in with stack up reduced to top ground Post Layout Simulation in ADS 30 Drive_12_TX Nets – Simulation Results 0 -20 -40 -60 -80 0 2 4 6 8 10 12 14 16 18 20 Post Layout Simulation in ADS 31 Drive_12_RX : Receive Nets The differential pair was limited to upper power plane. The Bottom layer was an open substrate Allegro DFI Setup can be used to limit differential pair stack up between top and bottom gnd planes Post Layout Simulation in ADS 32 Drive_12_RX Net Simulation Results 0 -20 -40 -60 -80 0 2 4 6 8 10 12 14 16 18 20 Post Layout Simulation in ADS 33 EDOB Right Side Via Post Layout Simulation in ADS 34 Connector Models Connector S-parameter files were provided Post Layout Simulation in ADS 35 Backplane Simulation Backplane trace Right side via Left side via Post Layout Simulation in ADS 36 Layout Modifications for Via Simulation • Select all • Using Edit > Modify >Crop • Select a rectangular window around differential via with adjacent ground via Number of layers : 32 (dielectric+ conductor+pwr/gnd) Negative planes : No Number of Pwr/Gnd planes : 8 Post Layout Simulation in ADS 37 Backplane Left Side Via Models Signal Via Gnd Via Post Layout Simulation in ADS 38 Converting Positive Layers to Slot Layers Boolean operation is used to convert finite Pwr/Gnd planes in slot layers Provide speed advantage for Momentum simulation and overcome any resonance due to finite power ground planes shapes Modify stack up for slot layers ADS2009 Update will provide automatic conversion from +ve to –ve planes Post Layout Simulation in ADS 39 Comparison of Two Models Finite PWR/GND Plane Metallization PWR/GND Plane Modeled as Slot Layer Post Layout Simulation in ADS 40 Simulation Statistics Notice that the non-functional have been removed from all other layers except two signal layers Post Layout Simulation in ADS 41 Left Side Backplane Via Simulation Results Slot layer view of the structure Momentum S-parameter plots Post Layout Simulation in ADS 42 Backplane Differential Trace – Layer 12 Via portion at both end were cut out and simulated separately. The traces were imported by limiting the differential pair within adjacent PWR/GND planes Post Layout Simulation in ADS 43 Backplane Differential Trace Simulation- Layer 12 Mesh Frequency : 20 GHz Edge Mesh : ON Post Layout Simulation in ADS 44 Backplane Differential Trace – Layer 14 Via portion at both end were cut out and simulated separately. The traces were imported by limiting the differential pair within adjacent PWR/GND planes Post Layout Simulation in ADS 45 Backplane Differential Trace – Layer 14 Simulation Results Mesh Frequency : 20 GHz Edge Mesh : ON Mesh Density : 20 C/W Post Layout Simulation in ADS 46 Right Side Backplane Via Extraction and 3 D Preview Non Functional PADS were removed Post Layout Simulation in ADS 47 Right Side Via Simulation- Results Insertion Loss Plots Post Layout Simulation in ADS 48 Complete Channel Model Post Layout Simulation in ADS 49 Channel Model- S Parameter Simulation 0 -10 dB(S(2,2)) dB(S(1,1)) dB(S(4,3)) dB(S(1,2)) -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 12 14 16 18 20 freq, GHz Post Layout Simulation in ADS 50 Eye Diagram Simulation @ 3Gbps Post Layout Simulation in ADS 51 Eye Diagram Simulation @ 3Gbps with 3.5 dB De-emphasis Eye diagram acceptable with 3.5 dB TX de-emphasis Post Layout Simulation in ADS 52 Eye Diagram Simulation @ 6Gbps Transmit de-emphasis may be required to open eye Post Layout Simulation in ADS 53 Eye Diagram Simulation @ 6Gbps with 3.5 dB De-emphasis Post Layout Simulation in ADS 54 ADS 2009 Update 1 55 What’s New in ADS2009 Update 1? • Decision Feed Back Equalization • Ability to auto generate optimized tap coefficient for FFE and DFE • Adaptive Equalization for FFE and DFE utilizing LMS,RLS, ZF • Arbitrary eye mask display and automatic positioning within eye diagram • Statistical simulator Integrated within Channel Simulator Post Layout Simulation in ADS 56 SAS/SATA Channel @ 6Gbps with Optimized FFE/DFE Equalized receiver utilizing: FFE: 1 precursor 2 post cursor DFE: 3 Tap DFE Optimized coefficients are auto generated and can be stored in a file Numerous ways to define/calculate tap coefficients Post Layout Simulation in ADS 57 Standard Mask Definition •Convenient eye mask display •Flexible specification format compatible with Agilent scopes •Browse and select any arbitrary mask file and preview •Mask is automatically position within eye diagram across timing and amplitude axis Sample Eye Mask Post Layout Simulation in ADS 58 Statistical Eye Contours and Bathtub @ 6Gbps SAS/SATA Eye diagram and Bathtub plots Post Layout Simulation in ADS 59 Channel Simulator Updates Statistical analysis option in the Channel Simulator for fast simulation down to very low BER Agilent’s proprietary technology extends StatEye principles Contour at given BER Height at BER ChannelSim ChannelSim ChannelSim1 NumberOfBits=1000 ToleranceMode=Auto EnforcePassivity=yes Width at BER Post Layout Simulation in ADS 60 Summary • Discussed channel simulation requirements • Established an efficient high data rate post layout extraction flow • Introduced channel simulation and how if could be using for post layout verifications • Introduced new capabilities of ADS2009 Update 1 for channel analysis Post Layout Simulation in ADS 61