Plextek RFI

Plextek RFI
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Plextek RFI
www.plextekRFI.com
Our expertise is your advantage
Plextek RFI
www.plextekRFI.com
Our expertise is your advantage
Plextek RF
RFIIntegration
Design of a 100W, X-band GaN PA
Using Discrete Transistor Die
Stuart Glynn, Liam Devlin, Graham Pearson
[email protected]
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Introduction
• Solid-state PA covering 10.5 to 11.5GHz
• Psat > 100W
• Small signal gain > 23dB
• Design based on discrete GaN transistor die (Cree, 0.25µm,
40V bias)
– Power levels available from 50Ω matched MMICs require
combination of too many parts
– Packaged X-band power transistors are pre-matched for specific
bands
– Discrete die allow a very compact implementation and flexibility of
operating band
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Transistor Selection
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• Available die, all 18GHz devices from Cree’s 40V, 0.25µm,
GaN on SiC Process
CGHV1J006D
CGHV1J025D
CGHV1J070D
Output Power
6W
25W
70W
Die Width
0.84mm
1.92mm
4.80mm
Electrical Die Width
at 11GHz (in air)
11.1°
25.3°
63.4°
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Transistor Performance Analysis
• Initial device performance analysis undertaken to determine:
– Matching topologies
– Requirements to ensure unconditional stability
– Trade off in Psat and PAE
– Initial estimate of thermal performance
• Useful application note available from Agilent at:
– http://cp.literature.agilent.com/litweb/pdf/5991-4154EN.pdf
• Corresponding workspace available free of charge from
Agilent at:
– http://bit.ly/1jZ2eYT
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Transistor Performance Analysis
• Standard Cree two-port large signal model in ADS
Selected quiescent bias point: 50mA/mm
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Transistor Performance Analysis
• Distributed model based on Cree 0.25µm process PDK in ADS
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Single Transistor – Stability
• At 11GHz the transistor die is not unconditionally stable, gate
resistance is required to ensure unconditional stability:
– Bare die, no gate resistance
– Bare die with 0.4Ω series gate resistance
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Transistor Performance Analysis
• Distributed model based on Cree 0.25µm process PDK in ADS
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Second Harmonic Termination
Best case
termination
Worst case
termination
Design
target at
22GHz
Centre of Smith
Chart is 5.0 +j0.0 Ω
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Third Harmonic Termination
Best case
termination
Worst case
termination
Design
target at
33GHz
Centre of Smith
Chart is 5.0 +j0.0 Ω
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Transistor Performance Analysis
• Re-sweeping fundamental load with updated harmonic
terminations
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Thermal Considerations
• Thermal Conductivity of SiC, Gold and GaAs at Room Temperature
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Material
Thermal Conductivity
(W/°C.cm)
SiC
4.30
Gold (Au)
3.17
GaAs
0.46
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Thermal Considerations
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• Variation of Thermal Conductivity of SiC and GaAs with Temperature
5
0.5
0.45
4
0.4
3.5
0.35
3
0.3
2.5
0.25
2
0.2
1.5
0.15
1
0.1
0.5
GaAs Thermal Conductivity (W/degC.cm)
SiC Thermal Conductivity (W/degC.cm)
4.5
SiC
GaAs
0.05
0
0
0
50
100
150
200
250
300
Temperature (degC)
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Channel Temperature
• Quiescent and Psat
– Standard Cree model,
tcase=85°C
– Quiescent bias 50mA/mm
– Ideal source and load
matches at 11GHz.
– Input power at 11GHz
swept from -20dBm to
35dBm.
– Junction temperature is
122.4°C under quiescent
conditions and150.4°C at
5dB compression.
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Output Stage Topology
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• Selected device has Psat of 25W
• Allowing for combiner, matching and bias network losses we
assume the use of 6 transistors
• Balanced topology with each branch driving 3 power-combined
transistors:
3
Vgg
Input
Matching
Network
W
A
Y
RF i/p
Gate Bias
Tee
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S
P
L
I
T
T
E
R
Input
Matching
Network
Input
Matching
Network
Output
Matching
Network
Output
Matching
Network
Output
Matching
Network
3
W
A
Y
C
O
M
B
I
N
E
R
Vdd
Drain
Bias Tee
RF o/p
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Implementation of 3-Transistor Block
• Design of bias-tees
• Design of input and output matching
• Single transistor performance
– Small signal performance
– Large signal performance
• Performance of 3 transistor block
– Small signal performance
– Large signal performance
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Gate Bias Tee Design
Substrate is 30 thou
RT/duroid 6002 with
2oz copper
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Gate Bias Tee – S-parameters
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EM Analysis
• Essential for accurate prediction of performance at
microwave/mm-wave frequencies
• Momentum 2.5D EM simulator integral to ADS
• Optimisation of layout required after EM simulation to account
for proximity and discontinuity effects
• More details of how to do this can be found in the Plextek RFI
video tutorial “Designing mm-wave integrated filters using
Agilent ADS”
– http://www.youtube.com/watch?v=PnkGkb3q3Qo
– Full technical tutorial video library:
• http://www.plextekrfi.com/publications/video-tutorials.html
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Drain Bias Tee Design
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•
Design of Output Matching
Target Load Impedance at 11GHz:
(2.59 + j7.0)Ω
•
Impedance presented by output match:
(2.27 + j7.21)Ω at 11GHz
Centre of Smith
Chart : 5.0 +j0.0Ω
Z = (2.27 +j7.21)Ω at 11GHz
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Z = 50Ω
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•
Design of Output Matching
Target Load Impedance at 22GHz:
(0.38 + j18.65)Ω
•
Impedance presented by output match:
(0.12 + j18.94)Ω at 22GHz
•
Target Load Impedance at 33GHz:
(0.83 + j28.33)Ω
•
Impedance presented by output match:
(0.1 + j30.15)Ω at 33GHz
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Centre of Smith
Chart : 5.0 +j0.0Ω
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Design of Input Matching
•
Target Source Impedance at 11GHz:
(1.0 + j0.0)Ω
•
Impedance presented by input match:
(1.6 + j0.06)Ω at 11GHz; includes series
gate resistance for stability
Centre of Smith
Chart : 5.0 +j0.0Ω
Z = 50Ω
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Z = (1.6 +j0.06)Ω at 11GHz
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Single Transistor – Small Signal
• Includes gate and drain bias tees
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Single Transistor – Large Signal
• Large Signal Performance at 5dB Compression (Psat is
≈23.4W). Includes gate and drain bias tees:
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ADS Schematic
• Of 3-transistor block:
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Loop Stability Analysis
Loop Gain dB
= 20log10 (vout/vin)
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Loop Stability Analysis
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Loop Stability Analysis
• Improving loop stability – adding balancing resistors:
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Lp
Lp
Rb
Rb
Lp
Lp
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Loop Stability Analysis
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Small Signal Performance
• Of 3-transistor block:
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Large Signal Performance
• Of 3-transistor block at 5dB Compression (Psat is ≈ 69W):
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Balanced Combination
• Two 3-transistor blocks are power combined with Branch Line
couplers (ADS schematic):
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Balanced Output Stage
• Small Signal Performance:
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Balanced Output Stage
• Large Signal Performance at 5dB Compression (Psat is
≈125W):
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Balanced Output Stage
• Large Signal Performance at 4dB Compression (Pout is
≈110W):
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Sizing of Driver Stage
• Selecting the optimum size of the driver stage:
Parameter at
11GHz
Balanced
Output Stage
3-Transistor
Block
Dual Transistor
Single
Transistor
Gain (dB)
13.6
13.6
13.6
13.8
P-5dB (dBm)
51.2
48.3
46.8
43.9
Input Referred
P-5dB (dBm)
42.6
39.7
38.2
35.1
P-1dB (dBm)
41.2
38.2
36.4
33.5
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Driver Stage
• Schematic – Driver stage uses two 25W amplifiers in a
balanced configuration:
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Driver stage
• Small Signal Performance:
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Driver Stage
• Large Signal Performance at 2dB Compression (Pout is
≈11.3W):
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Complete Two-stage PA
• Small Signal Performance:
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Complete Two-stage PA
• Large Signal Performance at 6dB Compression (Psat is
≈110W):
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Gain Compression Characteristics
• Compression of each stage and complete PA at 11GHz:
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Complete Two-stage PA
• Output Spectrum at P-6dB, 11GHz
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Complete Two-stage PA
• Second Harmonic Rejection (compared to fundamental),
29dBm Input Power, 10GHz to 12GHz
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Complete Two-stage PA
• Performance variation with changing load:
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Complete Two-stage PA
• Performance variation with changing load:
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Complete Two-stage PA
• Performance variation with changing load:
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Summary/Conclusions
• Design and simulation of a 100W, X-band PA module
presented
• Based on 0.25µm gate length, bare die transistors from Cree
• Uses mixed bare die/SMT assembly with thin film matching
components
• Six transistors (CGHV1J025D) used in the output stage and
two in the input stage
• Final simulation shows a Psat of 110W at 6dB compression
across 10.5 to 11.5GHz
• Small signal gain is 26.8dB with input and output return losses
of > 22dB
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