1.125Gb Low Latency DRAM III (LLDRAM III

Preliminary
GS4303T18/36GN
180-Pin BGA
Commercial Temp
Industrial Temp
1.125Gb Low Latency DRAM III (LLDRAM III)
Common I/O Burst of 2, POD I/O
Up to 600 MHz
1.5 V VDD
2.5 V VEXT
1.2 V or 1.0 V VDDQ
Features
Introduction
• 32Mb x 36 and 64Mb x 18 organizations available
• Up to 600 MHz DDR operation (1.2 Gb/s/pin data rate)
• 600 MT/s peak transaction rate (in millions per second)
• 43.2 Gb/s peak data bandwidth (x36 @ 1.2 Gb/s)
• Common I/O DDR Data Bus
• Multiplexed DDR Address Bus (2 beats in 1 cycle)
• Burst of 2 Read and Write operations
• 8 bank architecture
• Reduced Random Cycle Time (tRC = 13.3 ns at 600 MHz)
• Configurable Random Cycle Time, Read Latency, and Write
Latency
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data Mask capability for Write commands
• Differential input clock (CK, CK)
• Differential input data clocks (DK, DK)
• Free-running output clocks (QK, QK) tightly aligned to
output data, for source-synchronous operation
• On-chip PLL aligns output data and output clocks to CK
• Read Data Valid signal (QVLD)
• 32 ms refresh (256K refresh commands—32K per bank—
must be issued every 32 ms, equating to one every 122 ns)
• Auto Refresh and Overlapped Refresh capability
• Loopback Mode for address and control de-skew training
• Configurable output driver impedance
• On-die input termination with configurable impedance
• Mirror Function for easy clam-shell application
• 1.5 V VDD, 2.5 V VEXT, 1.2 V or 1.0 V VDDQ
• 1.2 V or 1.0 V POD I/O, with optional Data Inversion for
reduced I/O power and SSO noise
• IEEE 1149.1 JTAG interface
• 180-pin, 14 mm x 18.5mm, 1 mm ball pitch, 6/6 RoHScompliant BGA package
• Commercial and Industrial Temperature Range support
Commercial (0° ≤ TC ≤ +95°C)
Industrial (–40° ≤ TC ≤ +95°C)
The GSI Technology 1.125Gb Low Latency DRAM-III
(LLDRAM III) is a high speed memory device designed for
high transaction rate data processing typically found in
networking and telecommunications applications. The 8-bank
architecture and low tRC allows access rates formerly only
found in SRAMs.
Rev: 1.05 9/2014
Read and Write data transfers always occur in bursts of 2.
Addresses are synchronous DDR signals that are latched on
both crossing edges of CK & CK that occur in a given cycle.
1 clock cycle (i.e., 2 DDR beats) are required to load the entire
address for a Read or Write operation.
The control signals used to input commands to the device are
synchronous SDR signals that are latched on the first crossing
edge of CK & CK that occurs in a given cycle (i.e., on the
positive edge of CK and the negative edge of CK).
Input data are synchronous DDR signals that are latched on
both crossing edges of DK & DK that occur in a given cycle.
1 clock cycle (i.e., 2 DDR beats) are required to load all of the
input data associated with a Write operation.
Output data are DDR signals that are driven out twice per clock
cycle. 1 clock cycle (i.e., 2 DDR beats) are required to drive
out all of the output data associated with a Read operation.
Free-running QK & QK output clocks are closely aligned to
output data, and enable reliable source-synchronous operation.
A special “Loopback Mode” is available for per-pin address
and control de-skew timing training.
1/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
64Mb x 18 Pin Assignments (Top View)
1
2
3
4
5
A
TMS
VDD
TCK
VDDQ
B
VSS
DNU,
VSS
VSS
C
QVLD
VDDQ
D
VSS
E
6
7
8
9
10
11
12
13
VSS
VSS
VDDQ
VEXT
VDD
QK0
DQ6
VDD
VDD
DNU,
VSS
VSS
DQ8
VSS
DNU,
VSS
VDDQ
DQ4
DNU,
VSS
VDDQ
DQ7
VDDQ
QK0
DNU,
VSS
VSS
DQ2
VSS
VSS
DNU,
VSS
VSS
DQ5
VSS
DNU,
VSS
VDDQ
DNU,
VSS
VDDQ
DQ0
DNU,
VSS
VDDQ
DQ1
VDDQ
DQ3
F
VSS
DQINV0
VSS
A12
VSS
VSS
A13
VSS
DNU,
VSS
VSS
G
VDD
VDDQ
A10
VDDQ
A8
A7
VDDQ
A11
VDDQ
VDD
H
VSS
RST
VSS
A6
VSS
VSS
A5
VSS
DM
VSS
J
MF
VDDQ
DK0
VSS
VDD
CK
VSS
DNU,
VSS
VDDQ
LBK
K
VREF
VSS
DK0
VDDQ
VDD
CK
VDDQ
DNU,
VSS
VSS
VREF
L
TRST
CS
VSS
A4
VSS
VSS
A3
VSS
WE
VSS
M
VDD
VDDQ
DPR
VDDQ
A2
REF
VDDQ
A9
VDDQ
VDD
N
VSS
DQINV1
VSS
A0
VSS
VSS
A1
VSS
DNU,
VSS
VSS
P
DNU,
VSS
VDDQ
DNU,
VSS
VDDQ
DQ9
DNU,
VSS
VDDQ
DQ10
VDDQ
DQ12
R
VSS
DNU,
VSS
VSS
DQ11
VSS
VSS
DNU,
VSS
VSS
DQ14
VSS
T
QK1
VDDQ
DNU,
VSS
VDDQ
DQ13
DNU,
VSS
VDDQ
DQ16
VDDQ
TDO
U
VSS
DNU,
VSS
VSS
DQ15
VDD
VDD
DNU,
VSS
VSS
DQ17
VSS
V
QK1
VDD
ZQ
VDDQ
VSS
VSS
VDDQ
VEXT
VDD
TDI
180p BGA—14 mm x 18.5 mm Body Size—1 mm Ball Pitch
Rev: 1.05 9/2014
2/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
32Mb x 36 Pin Assignments (Top View)
1
2
3
4
5
A
TMS
VDD
TCK
VDDQ
B
VSS
DQ9
VSS
C
QVLD
VDDQ
D
VSS
E
6
7
8
9
10
11
12
13
VSS
VSS
VDDQ
VEXT
VDD
QK0
DQ6
VDD
VDD
DQ11
VSS
DQ8
VSS
DQ10
VDDQ
DQ4
DQ13
VDDQ
DQ7
VDDQ
QK0
DQ12
VSS
DQ2
VSS
VSS
DQ15
VSS
DQ5
VSS
DQ16
VDDQ
DQ14
VDDQ
DQ0
DQ17
VDDQ
DQ1
VDDQ
DQ3
F
VSS
DQINV0
VSS
A12
VSS
VSS
A13
VSS
DQINV1
VSS
G
VDD
VDDQ
A10
VDDQ
A8
A7
VDDQ
A11
VDDQ
VDD
H
VSS
RST
VSS
A6
VSS
VSS
A5
VSS
DM
VSS
J
MF
VDDQ
DK0
VSS
VDD
CK
VSS
DK1
VDDQ
LBK
K
VREF
VSS
DK0
VDDQ
VDD
CK
VDDQ
DK1
VSS
VREF
L
TRST
CS
VSS
A4
VSS
VSS
A3
VSS
WE
VSS
M
VDD
VDDQ
DPR
VDDQ
A2
REF
VDDQ
A9
VDDQ
VDD
N
VSS
DQINV2
VSS
A0
VSS
VSS
A1
VSS
DQINV3
VSS
P
DQ35
VDDQ
DQ34
VDDQ
DQ18
DQ33
VDDQ
DQ19
VDDQ
DQ21
R
VSS
DQ32
VSS
DQ20
VSS
VSS
DQ31
VSS
DQ23
VSS
T
QK1
VDDQ
DQ30
VDDQ
DQ22
DQ29
VDDQ
DQ25
VDDQ
TDO
U
VSS
DQ28
VSS
DQ24
VDD
VDD
DQ27
VSS
DQ26
VSS
V
QK1
VDD
ZQ
VDDQ
VSS
VSS
VDDQ
VEXT
VDD
TDI
180p BGA—14 mm x 18.5 mm Body Size—1 mm Ball Pitch
Rev: 1.05 9/2014
3/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
1. Pin Description
Symbol
Direction I/O Type Freq MHz
CK, CK
DK[1:0],
DK[1:0]
A[13:0]
Input
Input
Input
HSIO
HSIO
HSIO
Description
600
Input Clock—Differential input clocks used to latch address and control inputs. CK
is ideally 180º out of phase with CK.
600
Input Data Clock—Differential input clocks used to latch data inputs during Write
operations. DKn is ideally 180º out of phase with DKn.
x36 devices: DK0 & DK0 latch DQ[17:0], DQINV[1:0], DM.
DK1 & DK1 latch DQ[35:18], DQINV[3:2].
x18 devices: DK0 & DK0 latch DQ[17:0], DQINV[1:0], DM.
DK1 & DK1 are unused.
600 DDR
Address Inputs—Multiplexed address bus, including bank select bits, latched by
CK & CK.
Note: A12 is unused in x36 devices. A13 is unused in all devices, and reserved for
future use.
CS
Input
HSIO
600 SDR
Chip Select—Control input latched by CK & CK that enables the command
decoder when asserted Low and disables it when deasserted High. When the
command decoder is disabled, new commands are ignored, but internal operations
continue.
WE
Input
HSIO
600 SDR
Write Enable—Control input latched by CK & CK. When CS is asserted Low, WE
and REF define the command to be executed.
REF
Input
HSIO
600 SDR
Refresh Enable—Control input latched by CK & CK. When CS is asserted Low,
WE and REF define the command to be executed.
600 SDR
Dual Port Refresh—Control input latched by CK & CK. When Overlapped Refresh
is selected and DPR is asserted Low, Overlapped Refresh commands are
executed, potentially in parallel with Read and Write commands depending on the
states of CS, WE, and REF.
Note: Pin should be tied to VDDQ if Overlapped Refresh is not utilized.
600 DDR
Data Input / Output—Bi-directional data bus latched by DKn & DKn during Write
operations, and driven and aligned with QKn & QKn during Read operations.
Note: DQ[35:18] are unused in x18 devices, and in a High-Z state.
600 DDR
Data Inversion Input / Output—Bi-directional data bits that indicate the inversion
states of their associated DQ data bytes during Read and Write operations. Like the
DQs, they are latched by DKn & DKn during Write operations, and driven and
aligned with QKn & QKn during Read operations.
DQINV0 is associated with data byte DQ[8:0].
DQINV1 is associated with data byte DQ[17:9].
DQINV2 is associated with data byte DQ[26:18].
DQINV3 is associated with data byte DQ[35:27].
Note: DQINV[3:2] are unused in x18 devices, and in a High-Z state.
DPR
DQ[35:0]
DQINV[3:0]
Rev: 1.05 9/2014
Input
I/O
I/O
HSIO
HSIO
HSIO
4/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
1. Pin Description (Continued)
Symbol
Direction I/O Type Freq MHz
Description
DM
Input
HSIO
600 DDR
Input Data Mask—Latched by DK0 & DK0 during Write operations. Disables
writing of the corresponding data value when asserted High.
Note: Pin should be tied to VSS if the Input Data Mask feature is not utilized.
QVLD
Output
HSIO
600 SDR
Output Data Valid—Driven High and aligned with QKn & QKn during Read
operations in order to indicate the presence of valid output data.
Output Data Clocks—QKn and QKn are opposite polarity, free-running output data
clocks. They are edge-aligned with output data during Read operations.
x36 devices: QK0 & QK0 align with DQ[17:0], DQINV[1:0].
QK1 & QK1 align with DQ[35:18], DQINV[3:2].
x18 devices: QK0 & QK0 align with DQ[8:0], DQINV0.
QK1 & QK1 align with DQ[17:9], DQINV1.
QK[1:0],
Output
HSIO
600 DDR
RST
Input
HSIO
(no ODT)
—
Master Reset—Asynchronous input that resets the device when asserted Low.
LBK
Input
HSIO
(no ODT)
—
Loopback Mode Enable—Asynchronous input that enables address and control
pin de-skew training when asserted Low.
MF
Input
HSIO
(no ODT)
DC
Mirror Function—Causes “mirroring” of certain pins, as described in Section 2.13.
ZQ
Analog
—
—
Impedance Control—Used for output driver impedance and input termination
impedance control. Must be tied to VSS through a high-precision resistor (RQ).
TCK
Input
HSIO
(no ODT)
—
JTAG Clock—Must be tied to VSS if the JTAG function is unused.
TRST
Input
HSIO
(no ODT)
—
JTAG Reset—Must be tied to VSS if the JTAG function is unused.
TMS
Input
HSIO
(no ODT)
—
JTAG Mode Select—May be left unconnected if the JTAG function is unused.
TDI
Input
HSIO
(no ODT)
—
JTAG Data Input—May be left unconnected if the JTAG function is unused.
TDO
Output
HSIO
—
JTAG Data Output—May be left unconnected if the JTAG function is unused.
VDD
Power
—
—
Power Supply—1.5 V nominally.
VEXT
Power
—
—
Power Supply—2.5 V nominally.
VDDQ
Power
—
—
I/O Power Supply—1.2 V or 1.0 V nominally.
VREF
Ref
—
—
Input Reference Voltage—0.7 * VDDQ nominally.
VSS
Ground
—
—
Ground
DNU, VSS
-
—
—
Do Not Use—Must be left unconnected, or tied to VSS.
DNU, VDDQ
-
—
—
Do Not Use—Must be left unconnected, or tied to VDDQ.
QK[1:0]
Note: “HSIO” indicates a single-ended, high-side-terminated I/O interface. It is similar in character to POD18 (1.8 V VDDQ) and
POD15 (1.5 V VDDQ) standards, except that VDDQ is either 1.2 V or 1.0 V. It is expected that 1.2 V HSIO will be similar to future
POD12 standard, and 1.0 V HSIO will be similar to future POD10 standard.
Rev: 1.05 9/2014
5/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
2. Functional Description
2.1 Interface Overview
The primary LLDRAM III interface consists of unidirectional command and address buses and a bidirectional data bus. This type
of data bus is often referred to as “Common I/O” or “CIO”. See Section 1 for a complete list of device pins.
The command bus is single data rate (SDR) and consists of 3 control signals CS, WE, and REF that are used to initiate Read, Write,
Auto Refresh, and MRS commands, plus a 4th control signal DPR that can be used to initiate Overlapped Refresh commands in
parallel with Read and Write commands. The address bus is double data rate (DDR) and consists of 14 multiplexed address signals
A[13:0]. Both the command bus and address bus are latched by the differential clock pair CK and CK. Read and Write commands
can be issued at a rate of once every CK cycle.
The data interface is a double-data rate (DDR) interface that transfers 36 bits of data on each clock edge in x36 devices, and 18 bits
of data on each clock edge in x18 devices. In x36 devices, the data interface includes 36 data I/O signals DQ[35:0] plus 4 data
inversion I/O signals DQINV[3:0]. In x18 devices, the data interface includes 18 data I/O signals DQ[17:0] plus 2 data inversion
I/O signals DQINV[1:0]. Additionally, the data interface in all devices includes a DDR data mask input signal DM, and two
differential input clock pairs DK[1:0] and DK[1:0] that latch the write data (DQ) and write data inversion (DQINV) inputs during
Write operations. The LLDRAM III outputs two differential clock pairs QK[1:0] and QK[1:0] that are associated with the read data
(DQ), read data inversion (DQINV), and read data valid (QVLD) outputs during Read operations. Because the data bus is
bidirectional, idle cycles are required to implement data bus turn-around as described in Section 2.12.
2.2 Clocking
There are three groups of clock signals: two input clock groups CK/CK and DK[1:0]/DK[1:0], and one output clock group
QK[1:0]/QK[1:0].
The CK/CK clock is associated with address and control inputs. It is used to latch A[13:0], CS, WE, REF, and DPR, and must
nominally be centered in those inputs’ signal valid windows. It is also the input clock to the on-chip PLL.
The DK[1:0]/DK[1:0] clocks are associated with write data inputs. During Write operations in all devices, DK0/DK0 is used to
latch DQ[17:0], DQINV[1:0], and DM, and must nominally be centered in those inputs’ signal valid windows. During Write
operations in x36 devices, DK1/DK1 is used to latch DQ[35:18] and DQINV[3:2], and must nominally be centered in those inputs’
signal valid windows.
The DK[1:0]/DK[1:0] clocks must meet the specified tCKDK skew requirement with respect to the CK/CK clock in order to ensure
proper timing relationship between write address/command and write data, and to enable proper data bus turn-around.
The QK[1:0]/QK[1:0] clocks are associated with read data outputs. During Read operations in x36 devices, QK0/QK0 is edgealigned with DQ[17:0], DQINV[1:0], and QVLD, and QK1/QK1 is edge-aligned with the DQ[35:18] and DQINV[3:2] signals.
During Read operations in x18 devices, QK0/QK0 is edge aligned with DQ[8:0], DQINV0, and QVLD, and QK1/QK1 is edgealigned with DQ[17:9] and DQINV1.
The QK[1:0]/QK[1:0] clocks meet the specified tCKQK skew requirement with respect to the CK/CK clock in order to ensure
proper timing relationship between read address/command and read data, and to enable proper data bus turn-around.
The QK[1:0]/QK[1:0] clocks are free-running, including when RST = 0; when RST = 0, the QK[1:0]/QK[1:0] clocks echo the
CK/CK clock.
Rev: 1.05 9/2014
6/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
2.3 Address Bus
The address bus is a multiplexed DDR bus in which some of the address bits (in the first beat) are used to specify the bank being
accessed. One clock cycle (2 beats) are required to load the address associated with a Read or Write command. One clock cycle
(1 beat) is required to load the bank address associated with an Auto Refresh command. Two clock cycles (2 beats) are required to
select a particular MRS register, and to load data into the selected MRS register, during an MRS command.
Address Bit Encoding
Command
Device
x36
Read or Write
x18
Auto Refresh
all
MRS
all
Beat A13 A12 A11 A10 A9
A8
A7
A6
0
X
X
1
X
X
0
X
1
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
X
A5
A4
A3
Address
A2
A1
A0
Bank Address
Address
Address
Bank Address
Address
X
X
X
MRS Register Data
Bank Address
MRS Register #
MRS Register Data
Notes:
1. “X” indicates the input value is a don’t care.
2. Overlapped Refresh commands do not utilize the address bus at all. See Section 2.9 for more information.
3. A12 is only used in x18 devices. It is unused in x36 devices.
4. A13 is reserved for future expansion. It is unused in these devices. See Section 2.13 for more information.
2.4 Command Encoding
The LLDRAM III supports five types of command cycles:
1.
2.
3.
4.
5.
The NOP command must be used in any cycle where no other commands are requested.
The READ command is used to initiate a Read operation of burst length 2.
The WRITE command is used to initiate a Write operation of burst length 2.
The REFRESH command is used to initiate a Refresh operation on a particular bank of memory.
The MRS command is used to configure the device following a reset.
The Refresh command comes in two varieties: “Auto Refresh” and “Overlapped Refresh”. See Section 2.9 for more information.
The command encoding and its state diagram have two different forms depending on whether Auto or Overlapped Refresh is
selected. They are more complex when Overlapped Refresh is selected because such Refresh commands may overlap with Read
and Write commands, and because they utilize an additional control input DPR.
Rev: 1.05 9/2014
7/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Command Encoding when Auto Refresh is selected
Command
CS
WE
REF
LBK
RST
Length
(cycles)
Description
NOP
1
X
X
1
1
1
No operation
Read
0
1
1
1
1
1
Read
Write
0
0
1
1
1
1
Write
Refresh
0
1
0
1
1
1
Auto Refresh
MRS
0
0
0
1
1
2
Mode Register Set
NOP
1
X
X
1
1
-
No operation
NOP
0
X
X
1
1
-
No operation
—
Loopback
X
X
X
0
1
-
Loopback Mode
—
Reset
X
X
X
X
0
-
Reset
State
IDLE
MRS
Note1:
1. “X” indicates the input value is a don’t care.
2. Grey-shaded entries are considered illegal operations; they are included in the table for the sake of completeness, but for compatibility reasons they should not be used.
Command Encoding State Diagram when Auto Refresh is selected
Read
NOP
IDLE
MRS
Refresh
Write
NOP
MRS
Rev: 1.05 9/2014
8/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Command Encoding when Overlapped Refresh is selected
Command
CS
WE
REF
DPR
LBK
RST
Length
(cycles)
Description
NOP
1
X
X
1
1
1
1
No operation
Refresh
1
X
X
0
1
1
4
Overlapped Refresh
Read
0
1
1
1
1
1
1
Read
Read + Refresh
0
1
1
0
1
1
1/4
Read and Overlapped
Refresh
Write
0
0
1
1
1
1
1
Write
Write + Refresh
0
0
1
0
1
1
1/4
Write and Overlapped
Refresh
MRS
0
0
0
1
1
1
2
Mode Register Set
MRS
0
0
0
0
1
1
2
Mode Register Set
NOP
0
1
0
X
1
1
1
No operation
NOP*
1
X
X
X*
1
1
-
No operation
Read*
0
1
1
X*
1
1
1
Read (overlapped)
Write*
0
0
1
X*
1
1
1
Write (overlapped)
NOP*
0
X
0
X*
1
1
-
No operation
NOP
1
X
X
1
1
1
-
No operation
NOP
1
X
X
0
1
1
-
No operation
NOP
0
X
X
X
1
1
-
No operation
—
Loopback
X
X
X
X
0
1
-
Loopback Mode
—
Reset
X
X
X
X
X
0
-
Reset
State
IDLE
OR1, OR2, OR3
MRS
Notes:
1. “X” indicates the input value is a don’t care.
2. The entries marked with an asterisk “*” indicated that the state of DPR is ignored for the purposes of command decoding (the pin is used for
conveying the bank number during this cycle).
3. Grey-shaded entries are considered illegal operations; they are included in the table for the sake of completeness, but for compatibility reasons they should not be used.
4. Overlapped Refresh commands cannot be initiated in the 1st or 2nd command cycles of MRS commands (DPR is ignored in both cycles).
That is, they cannot overlap with MRS commands, they can only overlap with Read and Write commands.
Rev: 1.05 9/2014
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Preliminary
GS4303T18/36GN
Command Encoding State Diagram when Overlapped Refresh is selected
Read
NOP
Read + Refresh
Read*
Read*
Read*
Refresh
NOP*
NOP*
NOP*
IDLE
Write + Refresh
MRS
OR1*
Write*
OR2*
OR3*
Write*
Write*
IDLE
IDLE
IDLE
Write
NOP
MRS
2.5 Command Cycles
Read, Write, Auto Refresh, and MRS commands are initiated by driving CS Low at the rising edge of CK, while simultaneously
driving WE, REF, and A[13:0] to the states appropriate to the desired command. Overlapped Refresh commands are initiated by
driving DPR Low at the rising edge of CK, and can be initiated simultaneously with Read and Write commands. NOP commands
are initiated by driving CS High at the rising edge of CK, in which case the simultaneous states of WE, REF, and A[13:0] are a
“don’t care”.
• Read and Write commands are initiated in a single cycle.
• Auto Refresh commands are initiated in a single cycle.
• Overlapped Refresh commands are initiated over 4 cycles.
• MRS commands are initiated over 2 cycles.
• NOP commands are initiated in a single cycle.
2.6 Write Data Cycles
The DQ, DQINV, and DM signals associated with a Write command are received by the LLDRAM III in a DDR burst of 2
sequence, starting on the rising edge of DK that is offset WL clock cycles from the rising edge of CK corresponding to the first
cycle in which the Write command was initiated. This delay of WL cycles (which is always equal to RL+1) is intended to minimize
the number of NOP commands needed for data bus turn-around during Read-to-Write command transitions.
2.7 Read Data Cycles
The DQ and DQINV signals associated with a Read command are driven by the LLDRAM III in a DDR burst of 2 sequence,
starting from the rising edge of CK that is offset RL clock cycles from the rising edge of CK corresponding to the first cycle in
which the Read command was initiated. This delay of RL cycles is equal to the delay required for the internal logic and memory
within the LLDRAM III to read data and make it available on the bus.
Rev: 1.05 9/2014
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Preliminary
GS4303T18/36GN
2.8 Read and Write Command Protocol
The following figures illustrate Read and Write command sequences.
Read Command Sequence
tRC
0
1
2
3
RL-1
RL
RL+1
RL+2
CK
A
A0 A1
WE, REF
CS
QK
R0 R1
DQ. DQINV
QVLD
Write Command Sequence
tRC
0
1
2
3
WL-1
WL
WL+1 WL+2
CK
A
A0 A1
REF
CS, WE
DK
DQ. DQINV, DM
Rev: 1.05 9/2014
W0 W1
11/50
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Preliminary
GS4303T18/36GN
The following diagram shows an example of a sequence of 2 Read, 2 Write, and 2 Read commands, with the following configuration:
• Speed Configuration #3: tRC = 8, tRL = 12, tWL = 13.
• Data Inversion is enabled (DI=1).
Some observations of this sequence are:
• One NOP is inserted between READ2 and WRITE1 to allow for Read-to-Write bus turn-around.
• Three NOPs are inserted between WRITE2 and READ3 to allow for Write-to-Read bus turn-around.
• Because tRC = 8, READ3 may access the same bank as READ1; however, none of READ2, WRITE1, or WRITE2 may access
the same bank as READ1.
Read / Write / Read Command Sequence
Command
RD1 RD2 NOP WR1 WR2 3 NOPs
RD3 RD4
tRC = 8 (RD1)
Cycle #
0
1
2
3
4
5
8
9
tRL=12 (RD1)
tWL=13 (WR1)
tRL=12 (RD3)
12
16
20
13
17
21
CK
CS
WE
REF
RD1 RD2
Data Data
12 13
A
WR1 WR2
Data Data
16 17
RD3 RD4
Data Data
20 21
DK
QK
DQ, DQINV
QVLD
Rev: 1.05 9/2014
12/50
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Preliminary
GS4303T18/36GN
2.9 Refresh Commands
Refresh operations are initiated to the LLDRAM III memory array via the Refresh command. Each Refresh command causes a
single refresh operation to occur on the bank specified in the command.
The minimum data retention time is 32ms over the specified temperature range. Each bank must receive 32,768 Refresh commands
every 32ms in order to ensure proper data retention. Consequently, a Refresh command must be initiated at an average rate of one
every ~122ns.
The Refresh command comes in two varieties: “Auto Refresh” and “Overlapped Refresh”. The Refresh Mode (RM) bit in the MRS
registers selects between Auto (RM=0) and Overlapped (RM=1) Refresh.
Auto Refresh
When Auto Refresh is utilized, it cannot overlap with Read and Write commands because it uses the address pins to input the
refresh bank address. Consequently, Auto Refresh consumes a portion of the available command bandwidth (~1.4%, at 600 MHz).
Auto Refresh Command Sequence
tRC
0
1
CK
A
BANK
WE
CS, REF
Overlapped Refresh
When Overlapped Refresh is utilized, it can overlap with Read and Write commands because it does not use the address pins to
input the refresh bank address. Rather, it uses the DPR pin to serially input the refresh bank address in the 3 cycles immediately
after the command is initiated (starting with the LSB of the bank address, and concluding with the MSB of the bank address).
Consequently, it is possible to design a system in which refresh consumes no command bandwidth.
Overlapped Refresh commands can be initiated during idle cycles, and in the same cycle as Read or Write commands. They cannot
be initiated in either cycle of MRS commands.
After the Overlapped Refresh command has been initiated in a particular cycle, the state of the DPR pin is ignored for the next 3
cycles for the purposes of command decoding, in order to allow subsequent Read or Write commands to be initiated while the
refresh bank address is serially input on the DPR pin.
Note: The DPR pin should be tied (or constantly driven) High in applications that do not utilize Overlapped Refresh.
Rev: 1.05 9/2014
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Preliminary
GS4303T18/36GN
Overlapped Refresh Command Sequence
tRC
0
1
2
3
B0
B1
B2
4
CK
DPR
(See note)
Note: tRC for Overlapped Refresh begins 3 cycles after the start of the command
Overlapped Refresh with Read Commands
tRC
0
1
2
3
4
5
6
CK
A
A0
A1
A0
A1
A0
A1
A0
B0
DPR
A1
B1
A0
A1
B2
REF
WE
CS
Read
Read +
Overlapped Refresh
Read
Read
Read
(See note)
NOP
Note: tRC for Overlapped Refresh begins 3 cycles after the start of the command
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Preliminary
GS4303T18/36GN
2.10 Data Mask
During Write operations, the DM pin can be used to prevent (i.e., “mask”) data from being written to the memory array. It is a DDR
input that, during Write operations, is sampled on both edges of DK0/DK0 (twice in one cycle) simultaneously with the input data
that is sampled on both edges of DK0/DK0 and DK1/DK1. When DM is sampled Low on a particular clock edge, all of the
concurrently-sampled input data is written to the memory array. When DM is sampled High on a particular clock edge, all of the
concurrently-sampled input data is ignored, and no update to the memory array is made.
The DM pin is ignored in all other circumstances. Consequently, it can be tied (or constantly driven) Low in applications where no
data masking is required, i.e., where both beats of input data always are to be written to the memory array.
When the Auto-DM Function (ADM) bit is set (to 1) in the MRS registers, the DM pin is ignored. Instead, during Write operations,
the device responds as if the DM pin were sampled Low only on the clock edge specified by the value of the two Auto-DM Pattern
(DMP) bits in the MRS registers. Specifically, when ADM=1:
DMP = 00: only the 1st beat of input data is written to the memory array.
DMP = 01: only the 2nd beat of input data is written to the memory array.
DMP = 10: not applicable in burst-of-2 devices.
DMP = 11: not applicable in burst-of-2 devices.
2.11 Data Inversion
Because the nominal design for POD I/O signals is high-side termination to VDDQ, signals driven High will consume less power
than those driven Low. Consequently, in order to reduce I/O current (and simultaneous switching noise), these devices support Data
Inversion, where all 9 bits of any given 9-bit data byte are inverted before transmission if the data byte contains more 0s than 1s; in
this way, more 1s than 0s are always transmitted on each data byte. To accomplish this, one data inversion bit (DQINV) is utilized
per 9-bit data byte (DQ), to indicate if the data byte has been inverted or not during transmission.
In order to support this feature, an extra bit in the memory array is used to store the state of each DQINV bit transmitted during Write
operations (and to retrieve the state of each DQINV bit transmitted during Read operations). In essence, the DQINV bits are
functionally identical to DQ bits, with respect to how they are stored/retrieved during Write/Read operations. Consequently, the
DQINV bits don’t necessarily have to be used for Data Inversion - they can be used simply as additional DQ data bits, if desired.
When the DQINV bits are used for Data Inversion, during Write operations the controller determines if a particular DQ byte should
be inverted or not during transmission. If it inverts the DQ byte, it drives the associated DQINV bit High during transmission;
otherwise, it drives it Low. And during Read operations, the LLDRAM III simply returns the DQ and DQINV bit states that were
stored during the previous Write operation. In this way, no more than five bits of each 10-bit data group (nine DQs plus one DQINV)
will be driven Low at any given time, and no more than five bits of each 10-bit data group will switch states in the same direction
at any given time.
Data Inversion can be enabled and disabled via the Data Inversion (DI) bit in the MRS registers. When it is enabled (DI=1), the
DQINV bits are stored and retrieved during Write and Read operations, as discussed above. When it is disabled, the DQINV bits
are ignored during Write operations (i.e. not stored in the memory array), and are driven High during Read operations.
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Preliminary
GS4303T18/36GN
2.12 Data Bus Turn-Around
Because the DQ and DQINV pins are bidirectional, care must be taken to ensure that the LLDRAM III and its controller do not
drive these pins simultaneously. In order to help facilitate this in an efficient manner, a rapid DQ and DQINV turn-off time is
implemented in the LLDRAM III.
The actual bus turn-around time depends on many system parameters, including burst length (2, in this case), read latency (RL),
write latency (WL), pre-amble, post-amble, controller I/O timing, LLDRAM I/O timing, and PCB delays; and the system must
ensure that neither the LLDRAM III, nor the controller drives the bus during that time. This is accomplished by inserting a
sufficient number of NOP commands between each Read-to-Write and Write-to-Read command transition. Additional NOP
commands may be required to allow settling of the bus in order to insure no adverse effect on I/O timing.
Note that a Refresh command can be used in place of a NOP command to effect the insertion of an idle cycle on the data bus.
2.13 Clam-Shell Support (Mirror Function)
In order to support clam-shell mounting on the system board, the pin-out of the LLDRAM III is designed so that most pins that
overlap when devices are clam-shelled are functionally interchangeable. A few pins require their function to be swapped, however.
The Mirror Function (MF) pin causes the pin assignment to be modified to effect those pin swaps. In order to support proper signal
integrity, package trace lengths for mirrored pins are matched to within +/- 0.1mm.
Due to the mirroring of A12 and A13, an input buffer is implemented on both the F4 pin (A12 when MF=0, A13 when MF=1) and
the F10 pin (A13 when MF=0, A12 when MF=1), even though A13 is not utilized in these devices. In these devices, whichever pin
is defined as A13 (depending on the state of MF) is ignored; it can be unconnected, or driven high or low.
Pins Affected by the MF Pin
Rev: 1.05 9/2014
Pin
MF=0
MF=1
N4
A0
A1
N10
A1
A0
L4
A4
A3
L10
A3
A4
M5
A2
REF
M9
REF
A2
L2
CS
WE
L12
WE
CS
H10
A5
A6
H4
A6
A5
F4
A12
A13
F10
A13
A12
M11
A9
DPR
M3
DPR
A9
H2
RST
DM
H12
DM
RST
16/50
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Preliminary
GS4303T18/36GN
2.14 Random Cycle Time / Read Latency / Write Latency Configuration
The relationship between Clock Cycle Time (tCK) and Random Cycle Time (tRC), Read Latency (tRL), and Write Latency (tWL) is
user-configurable via the three Speed Configuration (C[2:0]) bits in the MRS registers. The table below lists the available
configurations in these devices, and the clock frequencies supported for each setting.
Speed Configuration Table
Parameter
Condition
Random Cycle Time (tRC)
Read Latency (tRL)
Write Latency (tWL)
Valid Frequency Range
Configuration #
Units
2
3
—
7
8
DI = 0
9
10
DI = 1
11
12
DI = 0
10
11
DI = 1
12
13
-600 Speed Bin
526 ~ 400
600 ~ 400
-500 Speed Bin
434 ~ 400
500 ~ 400
cycles
cycles
cycles
MHz
Notes:
1. Write Latency is equal to Read Latency plus one in each configuration to help minimize data bus turn-around time.
2. Read Latency and Write Latency increase by two cycles when Data Inversion is enabled.
2.15 PLL Enable / Disable
The PLL bit in the MRS registers is used to enable and disable the on-chip PLL. The default setting of the bit is “low” = “disabled”.
When the bit is set “high” via an MRS command, the PLL requires a time period of tPLL to synchronize before QK, DQ, and
QVLD output timing with respect to CK meets specification, and Read commands can be issued.
The PLL must be “reset” (i.e., disabled and then re-enabled) whenever nominal tCK or nominal VDD is changed. The following
steps should be followed to reset the PLL:
1.
2.
3.
4.
Issue an MRS command to Register #1 (“001”), to set the PLL bit “low” and thereby disable the PLL.
Wait at least 24 cycles.
Issue another MRS command to Register #1, to set the PLL bit back “high” again and thereby re-enable the PLL.
Wait at least tPLL before issuing a Read command, to allow sufficient time for the PLL to re-synchronize.
Note that tCK or VDD can be changed before step 1 or during step 2, either one.
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Preliminary
GS4303T18/36GN
3. Initialization
Prior to functional use, the LLDRAM III must first be initialized and configured. The steps described in Section 3 will ensure that
the internal logic has been properly reset, and that functional timing parameters have been configured.
Initialization Flow
Power on
Reset chip and
configure
impedances
Deskew
Required?
No
Yes
Address / Control
Deskew
(Loopback Mode)
Enable PLL
and other modes
(MRS command)
Enable PLL
and other modes
(MRS command)
Read Data
Deskew
Write Data
Deskew
Set modes
(MRS commands)
Normal operation
Yes
Rev: 1.05 9/2014
New Deskew
Required?
No
18/50
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Preliminary
GS4303T18/36GN
Initialization Sequence
CK
RST
LBK
CS
WE
Note: Refresh should be performed on a regular basis, if
data retention is required during an initialization sequence.
REF
A
DK
DQ, DQINV, DM
Reset
Address / Control
Deskew
PLL Init
and Config
Read Data Path Deskew
Write data at
Read data at
full speed
full speed
using Auto-DM
Write Data Path Deskew
Write data at
Read data at
full speed
full speed
3.1 Power-on
There are no restriction on the power-up sequence of the VDD, VEXT, and VDDQ power supplies. The system may bring them up in
any order.
3.2 Reset
Before the LLDRAM III can be configured, it must be reset properly in order to ensure that it is in a known and functional state
regardless of any power-on anomalies and power supply ramp rates. In order to reset the device, the RST pin must be asserted Low
for at least 200μs, during which time the device logic is reset to a known state, and input termination and output impedance are
configured via the DQ pins (see Section 3.3).
All MRS register bits are reset to their default values whenever RST is asserted Low. Consequently (and amongst other effects),
the assertion of RST disables the on-chip PLL, since the default state of the PLL bit in the MRS registers is “0”, and “0” means
“PLL disabled”.
Terminator and driver impedance calibration circuits are disabled while RST is asserted Low.
Memory array content is not guaranteed to be retained when the device is reset.
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Preliminary
GS4303T18/36GN
3.3 Initial Impedance Settings
During the reset sequence, the DQ pins are used to configure input termination and output impedance via the use of a Reset
Register, as indicated in the table below. When RST is asserted Low, the logic values on the DQ pins pass through the Reset
Register (it functions as a latch) and continuously update their corresponding positions in the MRS registers. When RST is
subsequently de-asserted High, the logic values on the DQ pins at that time are latched into the Reset Register, and a final update to
the corresponding positions in the MRS registers takes place. Before, during, and after the reset sequence, the state of the MRS
register bits determine the state and strengths of the terminator and driver impedances. The impedances are continuously calibrated
while the input clock is toggling.
The meaning of the bits in the Reset Register (as indicated by the Cell ID in the table) is the same as the corresponding bits in the
MRS registers, although their positions in the Reset Register are unrelated to their positions in the MRS registers.
Data Inversion is disabled during reset regardless of the state of the DI bit in the MRS registers. That is, the DQINV pins are
ignored during reset, and the sampled values of the DQ pins are non-inverted when stored in the Reset Register.
Reset Register Impedance Control Assignments
Pins
U12
T11
U4
R12
T5
P13
R4
P11
P5
B12
C11
B4
D12
C5
E13
D4
E11
E5
DQ (x18)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DQ (x36)
26
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
0
Reset Register
MSB -> LSB
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ODT
QD
QU
IM
KD
Cell ID
KU
CD
CU
DD
DU
Reset Sequence
CK
0
1
0
1
RST
DQ
CS, WE, REF
DK
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Preliminary
GS4303T18/36GN
3.4 Per-Bit Deskew Training Sequence
The LLDRAM III provides support that allows a memory controller to deskew signals for high speed operation. If per-bit deskew
is desired, the memory controller must provide the actual deskew functionality. Per-pin deskew is normally performed after the
RST pin is deasserted, but may be performed at any time without affecting memory array content. Furthermore, resetting the device
does not necessarily affect the skew characteristics of the device pins; therefore, the deskew training sequence does not necessarily
have to be repeated each time the device is reset.
Per-pin deskew training is anticipated to be implemented in three phases:
1.
2.
3.
Deskew of the address, control, and input data clock pins:
Deskew of the read data path:
Deskew of the write data path:
A, CS, WE, REF, DPR, and DK with respect to CK.
DQ, DQINV, and QVLD with respect to QK.
DQ, DQINV, and DM with respect to DK.
Phase 1—Address, control and input data clock deskew using Loopback Mode
The first phase of the per-pin training sequence, deskew of the address, control, and input data clock pins, is facilitated by the use
of the device’s “Loopback Mode” available via the LBK pin. When LBK is asserted Low, A, CS, WE, REF, DPR, and DK input
pins are looped back to DQ output pins, as defined in the table below.
Input-to-Output Pin Mapping during Loopback Mode
x36 device
Input Pin
Output Pin
Input Signal
x18 device
MF=0
MF=1
Output
Signal
Input Signal
MF=0
MF=1
Output
SIgnal
F4
B4
A12
A13
DQ6
A12
A13
DQ6
F10
B12
A13
A12
DQ8
A13
A12
DQ8
G3
D4
A10
A10
DQ2
A10
A10
DQ2
G11
D12
A11
A11
DQ5
A11
A11
DQ5
G5
C5
A8
A8
DQ4
A8
A8
DQ4
G9
C11
A7
A7
DQ7
A7
A7
DQ7
H4
E5
A6
A5
DQ0
A6
A5
DQ0
H10
E13
A5
A6
DQ3
A5
A6
DQ3
J1, K1
E11
DK0, DK0
DK0, DK0
DQ1
DK0, DK0
DK0, DK0
DQ1
J11, K11
E3
DK1, DK1
DK1, DK1
DQ14
DNU, VSS
DNU, VSS
DNU, VSS
L2
R4
CS
WE
DQ20
CS
WE
DQ11
L12
P13
WE
CS
DQ21
WE
CS
DQ12
L4
P5
A4
A3
DQ18
A4
A3
DQ9
L10
P11
A3
A4
DQ19
A3
A4
DQ10
M3
N2
DPR
A9
DQINV2
DPR
A9
DQINV1
M11
R12
A9
DPR
DQ23
A9
DPR
DQ14
M5
T5
A2
REF
DQ22
A2
REF
DQ13
M9
T11
REF
A2
DQ25
REF
A2
DQ16
N4
U4
A0
A1
DQ24
A0
A1
DQ15
N10
U12
A1
A0
DQ26
A1
A0
DQ17
Note: DK0/DK0 and DK1/DK1 have differential receivers, the output of which is used as the signal being looped back.
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Preliminary
GS4303T18/36GN
Each looped-back input pin is sampled on both the rising and falling edges of CK. The value driven on the corresponding output
pin at the rising edge of QK is the value of the input pin sampled on the rising edge of CK. The value driven on the corresponding
output pin at the falling edge of QK is the inverted value of the input pin sampled on the falling edge of CK.
When Loopback Mode is enabled, the delay from when an input pin is first sampled to when the looped-back value first appears on
the corresponding DQ output pin is 5 CK cycles.
After LBK is asserted Low, the memory controller should wait at least 16 CK cycles before beginning the deskew training
sequence (i.e., before toggling input pins and expecting valid output results 5 CK cycles later).
While LBK is asserted Low, Data Inversion is disabled regardless of the state of the DI bit in the MRS registers.
While LBK is asserted Low, the DQ output pins corresponding to unused input pins will still meet AC timing specifications, but
may have arbitrary, non-constant states.
While LBK is asserted Low, the device ignores any apparent commands presented on the CS, WE, and REF pins, and performs
self-refresh operations to prevent loss of data during extended periods of deskew training. In order to ensure that Read, Write,
Refresh, and MRS commands are not inadvertently received during entry and exit from deskew training, they should not be
initiated for at least 16 CK cycles before LBK is asserted Low, and for at least 16 CK cycles after LBK is deasserted High.
If LBK is asserted Low when the on-chip PLL is disabled, then the PLL remains disabled throughout Loopback Mode. If LBK is
asserted Low when the on-chip PLL is enabled, then the PLL is temporarily bypassed throughout Loopback Mode. Consequently,
during Loopback Mode the phase of the QK output clock is undefined with respect to the CK input clock (and the tCD output
timing parameter comes into effect); however, QK to DQ timing will still meet specification. Note that after LBK is deasserted
High, the PLL will return to the same state (enabled or disabled) it was in before LBK was asserted Low.
Loopback Mode Deskew Training Sequence
tLBKL
Wait 16 cycles
1 ...
... 16
0
1
2
3
4
5
6
7
8
CK
A, CS, WE, REF, DPR, DK
LBK
tCD
QK
DQ
After address, control, and input data clock deskew has been completed and the LBK pin has been deasserted High, the second and
third phases of the per-pin training sequence—read data path deskew and write data path deskew—can then be performed.
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Preliminary
GS4303T18/36GN
Phase 2—Read data path deskew using Auto-DM-controlled Write commands and normal Read commands
Before read data path deskew begins, an MRS command should be issued to enable the PLL (via the PLL bit in the MRS registers).
Note that after it has been enabled, the PLL requires a time period of tPLL to synchronize, during which time QK, DQ, and QVLD
output timing with respect to CK is unspecified. Additionally, Refresh commands should continue to be issued to the device while
the PLL is synchronizing in order to ensure proper retention of data.
Read data path deskew requires that training patterns be written to the memory array. In order to facilitate the loading of complex
data patterns into the memory array using non-deskewed DQ inputs, the LLDRAM III supports an “Auto-DM” capability enabled
via the Auto-DM Function (ADM) bit and Auto-DM Pattern (DMP) bits in the MRS registers. The Auto-DM feature enables the
memory controller to initiate Write commands by using the (previously deskewed) address, control, and data clock inputs in
normal fashion, and by maintaining a constant data pattern on the non-deskewed DQ inputs for both data beats. The Auto-DM
Pattern bits determine which one of the two input data beats is written to the memory array. Consequently, Auto-DM-controlled
Write commands can be used to load complex data patterns into the memory array reliably.
Once written to the memory, these data patterns can then be read out using normal Read commands to effect any desired pattern on
the DQ bus. This permits the system to deskew the DQ, DQINV, and QVLD signals with respect to the QK clocks.
Phase 3—Write data path deskew using normal Write and Read commands
After read data path deskew has been completed, write data path deskew can then be performed by issuing normal Write and Read
commands to the device, and using the (previously deskewed) read data path to determine whether or not write data was correctly
received by the device. This permits the system to deskew the DQ, DQINV, and DM signals with respect to the DK clocks.
3.5 Configuration (MRS Commands and MRS Registers)
The MRS command is used to configure the LLDRAM III. Configuration is used to specify the following parameters:
• Speed configuration of Random Cycle Time (tRC), Read Latency (tRL), and Write Latency (tWL), in number of clock cycles.
• Select DQ, DQINV, QK, QK, QVLD driver pull-up and pull-down impedances.
• Select DQ, DQINV, DM, DK, DK, A, CS, WE, REF, DPR, CK, CK terminator pull-up and pull-down impedances.
• Enable/freeze dynamic PVT compensation of driver and terminator impedances.
• Enable/disable PLL.
• Enable/disable Data Inversion.
• Select Refresh Mode—Auto Refresh or Overlapped Refresh.
• Enable/disable Auto-DM, and select Auto-DM modes.
The MRS command can be used to write registers using SDR timing on the A[6:0] address inputs, although A6 is not, in fact,
utilized for MRS in these devices. The actual address pins used depend on the value of the Mirror Function (MF) pin.
Because an MRS command may change register values that significantly affect the behavior of the device, no Read, Write, or
Refresh commands should be initiated for at least 24 CK cycles before and after an MRS command is initiated.
MRS Sequence
0
CK
A
A0
1
2
A2
CS, WE, REF
Rev: 1.05 9/2014
23/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
MRS Configuration Register Bit Assignments
Beat 0
Beat 2
Pins (MF=0)
H4
H10
L4
L10
M5
N10
N4
H4
H10
L4
L10
M5
N10
N4
Pins (MF=1)
H10
H4
L10
L4
M9
N4
N10
H10
H4
L10
L4
M9
N4
N10
Address
A6
A5
A4
A3
A2
A1
A0
A6
A5
A4
A3
A2
A1
A0
Address Bit Field
Register Data
Register #
Register Data
Active
X
Configuration
0
0
0
X
0
DI
FZ
RM
Active
X
DMP
ADM
0
0
1
X
0
0
0
0
Active
X
KU
ODT
0
1
0
X
CD
CU
Active
X
QD
QU
IM
0
1
1
X
DD
DU
X
0
0
0
1
0
0
X
0
0
0
X
0
0
0
1
0
1
X
0
0
X
0
0
0
1
1
0
X
0
X
0
0
0
1
1
1
X
0
Reserved
BL
0
PLL
KD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MRS Configuration Bit Definitions
Speed Configuration
Burst Length
BL
Clock Cycles
Config #
C2
C1
C0
DI
0
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
4
1
5
6
tRC
tRL
tWL
Refresh Mode
Operation
RM
Operation
0
0
Reserved—not supported
0
Auto Refresh Mode (default)
not supported
0
1
2 Beats (default)
1
Overlapped Refresh Mode
0
not supported
1
0
Reserved—not supported
0
7
9
10
1
1
Reserved—not supported
1
0
8
10
11
0
0
0
not supported
Auto-DM Function
1
0
1
0
not supported
ADM
Operation
1
1
0
0
not supported
0
Disabled (default)
7
1
1
1
0
not supported
1
Enabled
0
0
0
0
1
not supported
1
0
0
1
1
not supported
2
0
1
0
1
7
11
12
3
0
1
1
1
8
12
13
4
1
0
0
1
5
1
0
1
6
1
1
0
7
1
1
1
Rev: 1.05 9/2014
Impedance Freeze
FZ
Operation
0
Update active (default)
1
Update frozen
Data Inversion
Auto-DM Pattern
DMP
Pattern #
00
01
10
11
not supported
DM Beat 0
0
1
1
1
1
not supported
DM Beat 1
1
0
1
1
1
not supported
1
not supported
Note: When ADM=0, DMP=Don’t Care.
24/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DI
Operation
0
Disabled (default)
1
Enabled
PLL Control
PLL
Operation
0
Disabled / Reset (default)
1
Enabled
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
MRS Input Termination Impedance Bit Definitions
Pins
Data Input ODT—Up
ODT
DQ, DQINV,
DM,
DK0, DK0,
DK1, DK1
Pins
DU
Pins
ODT
DD
Div
200Ω 240Ω RQ value
1
X
X
Off
-
-
1
X
X
Off
-
-
1
1
Off
-
-
X
1
1
Off
-
-
(Default)
0
1
0
1
200Ω 240Ω
0
1
0
1
-
-
(Not supported)
0
0
1
1/2
100Ω 120Ω
0
0
1
1/2
-
-
(Not supported)
0
0
0
1/4
50Ω
0
0
0
1/4
-
-
(Not supported)
60Ω
(Default)
Address & Control Input ODT—Up
CU
Div
Address & Control Input ODT—Down
200Ω 240Ω RQ value
ODT
CD
Div
200Ω 240Ω RQ value
1
X
X
Off
-
-
1
X
X
Off
-
-
X
1
1
Off
-
-
X
1
1
Off
-
-
(Default)
0
1
0
1
200Ω 240Ω
0
1
0
1
-
-
(Not supported)
0
0
1
1/2
100Ω 120Ω
0
0
1
1/2
-
-
(Not supported)
0
0
0
1/4
50Ω
0
0
0
1/4
-
-
(Not supported)
Div
200Ω 240Ω RQ value
60Ω
(Default)
Clock Input ODT—Up
ODT
CK, CK
200Ω 240Ω RQ value
X
ODT
A,
CS, WE, REF,
DPR
Data Input ODT—Down
Div
KU
Clock Input ODT—Down
ODT
KD
Div
200Ω 240Ω RQ value
1
X
X
Off
-
-
1
X
X
Off
-
-
X
1
1
Off
-
-
X
1
1
Off
-
-
(Default)
0
1
0
1
200Ω 240Ω
0
1
0
1
-
-
(Not supported)
0
0
1
1/2
100Ω 120Ω
0
0
1
1/2
-
-
(Not supported)
0
0
0
1/4
50Ω
0
0
0
1/4
-
-
(Not supported)
60Ω
(Default)
MRS Output Driver Impedance Bit Definitions
Pins
DQ, DQINV,
QK0, QK0,
QK1, QK1,
QVLD
Output Driver Impedance—Up
Output Driver Impedance—Down
IM
QU
Div
200Ω 240Ω RQ value
IM
QD
Div
200Ω 240Ω RQ value
0
1
1/4
50Ω
0
1
1/4
50Ω
1
X
Off
60Ω* 60Ω* (Ignores RQ)
1
X
Off
40Ω* 40Ω* (Ignores RQ)
0
0
1/6
33Ω
0
0
1/6
33Ω
60Ω
(Default)
40Ω
Note: 60Ω* = 60Ω no PVT compensation
60Ω
40Ω
(Default)
Note: 40Ω* = 40Ω no PVT compensation
Note: All MRS register bits are reset to their default values at power-up, and whenever RST is asserted Low.
Rev: 1.05 9/2014
25/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4. Electrical Specifications
4.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Supply Voltage
VDD
-0.3 to +1.95
V
Supply Voltage
VEXT
-0.3 to +2.8
V
I/O Supply Voltage
VDDQ
-0.3 to +1.55
V
Input Voltage
VIN
-0.3 to VDDQ + 0.3 (1.55 V max)
V
Max Junction Temperature
TJ
105
°C
Storage Temperature
TSTG
-55 to 125
°C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to the Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time
may affect reliability of this component.
4.2 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
VDD
1.4
1.5
1.6
V
Supply Voltage
VEXT
2.3
2.5
2.7
V
I/O Supply Voltage (1.2 V POD I/O)
VDDQ
1.15
1.2
1.25
V
I/O Supply Voltage (1.0 V POD I/O)
VDDQ
0.95
1.0
1.05
V
Junction Temperature (Commercial)
TJ
0
—
100
°C
Junction Temperature (Industrial)
TJ
-40
—
100
°C
Case Temperature (Commercial)
TC
0
—
95
°C
Case Temperature (Industrial)
TC
-40
—
95
°C
Notes:
1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
2. Maximum operating case temperature, TC, is measured in the center of the package.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4. Both junction and case temperature specifications must be satisfied.
Rev: 1.05 9/2014
26/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4.3 I/O DC Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Units
Notes
Input Reference Voltage
VREF (DC)
0.69 * VDDQ
0.7 * VDDQ
0.71 * VDDQ
V
1
Input High Voltage
VIH (DC)
VREF + ΔV
VDDQ
VDDQ + 0.3
V
2
Input Low Voltage
VIL (DC)
–0.3
0.4 * VDDQ
VREF – ΔV
V
2,3
Input Clock Voltage
VIN (DC)
–0.3
—
VDDQ + 0.3
V
Input Clock Differential Voltage
VDIF (DC)
0.2
—
VDDQ + 0.6
V
Output High Voltage
VOH (DC)
VDDQ – 0.025
VDDQ
—
V
Output Low Voltage
VOL (DC)
—
0.4 * VDDQ
—
V
3
Output Impedance High
ZOH
—
60
—
Ω
4
Output Impedance Low
ZOL
—
40
—
Ω
4
Input Impedance High
ZIH
—
60
—
Ω
4
Notes:
1. Peak-to-peak AC noise on VREF must not exceed ± 2% of VDDQ (DC).
2. “ΔV” equals 80m V when VDDQ = 1.2 V (nominal), and 70m V when VDDQ = 1.0 V (nominal).
3. Parameter applies when ZOL = 40 Ω and ZIH = 60 Ω.
4. Programmable via ZQ and Reset/MRS.
4.4 I/O AC Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Units
Notes
Input High Voltage
VIH (AC)
VREF + ΔV
—
VDDQ + 0.3
V
1, 2, 3
Input Low Voltage
VIL (AC)
–0.3
—
VREF – ΔV
V
1, 2, 3
Input Clock Voltage
VIN (AC)
–0.3
—
VDDQ + 0.3
V
1, 2
Input Clock Differential Voltage
VDIF (AC)
0.2
—
VDDQ + 0.6
V
Input Clock Crossing Voltage
VX (AC)
0.6 * VDDQ
0.7 * VDDQ
0.8 * VDDQ
V
4
Notes:
1. VIH (AC) max, VIL (AC) min, and VIN (AC) min/max apply for pulse widths less than one-quarter of the cycle time.
2. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
3. “ΔV” equals 150m V when VDDQ = 1.2 V (nominal), and 130m V when VDDQ = 1.0 V (nominal).
4. Parameter applies when ZOL = 40 Ω and ZOH = ZIH = 60 Ω.
Rev: 1.05 9/2014
27/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4.5 I/O Capacitance
(TA = 25°C, f = 1 MHz)
Parameter
Symbol
Min
Max
Units
Notes
Clock Input Capacitance
CKIN
—
1
pF
1, 2
Input Capacitance
CIN
—
1
pF
1, 3
Output, I/O, and Other Capacitance
COUT
—
1.5
pF
1, 4
Capacitance delta between differential clock inputs
CDKIN
—
0.15
pF
1, 2
Capacitance delta between address and control inputs
CDIN
—
0.2
pF
1, 3
Capacitance delta between DQs
CDDQ
—
0.2
pF
1
Notes:
1. Parameters are tested at VIN = VOUT = 0 V. They do not include package capacitance.
2. Parameters apply to CK, CK, DK, DK.
3. Parameters apply to A, CS, WE, REF.
4. Parameters apply to QK, QK, DQ, DQINV, QVLD, DM.
4.6 Package Thermal Impedances
Package
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
BGA
TBD
TBD
TBD
TBD
TBD
4.7 Leakage Currents
Parameter
Symbol
Min
Max
Units
Notes
Input Leakage Current
ILI
—
50
μA
1
Output Leakage Current
ILO
—
50
μA
2
I/O Leakage Current
ILIO
—
50
μA
1, 2
Notes:
1. Parameters apply when ODT is disabled.
2. Parameters apply when the output driver is disabled (i.e., in a High-Z state).
Rev: 1.05 9/2014
28/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4.8 Standby and Operating Currents
Parameter
Symbol
Max
Test Conditions
600 MHz 500 MHz
VDD
Standby Current
ISB1
tCK = Idle.
All banks idle, no inputs toggling.
VDDQ
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
VEXT
VDD
Active Standby
Current
ISB2
CS = High, NOP commands only.
Half address / data transitions once every 4 cycles.
VDDQ
VEXT
VDD
Operating Current
IDD2
Sequential read / write.
Sequential bank access.
Continuous address / data (once, for 2 cycles, per tRC).
VDDQ
VEXT
Auto Refresh
Current
(Distributed)
IAREF2
VDD
Sequential refresh.
Sequential bank access.
Stable address.
Continuous data.
VDDQ
VEXT
Auto Refresh
Current
(Burst)
IAREF1
VDD
Continuous refresh.
Cyclic bank access.
Stable address.
Continuous data.
VDDQ
VEXT
VDD
Overlapped
Refresh Current
(with Write)
IOREFW
Continuous refresh overlapped with continuous write.
Cyclic bank access.
Continuous address / data.
VDDQ
VEXT
Rev: 1.05 9/2014
29/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Units
mA
mA
mA
mA
mA
mA
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4.8 Standby and Operating Currents (Continued)
Parameter
Symbol
Max
Test Conditions
600 MHz 500 MHz
VDD
Overlapped
Refresh Current
(with Read)
IOREFR
Continuous refresh overlapped with continuous read.
Cyclic bank access.
Continuous address / data.
VDDQ
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
x36
T.B.D
T.B.D
x18
T.B.D
T.B.D
T.B.D
T.B.D
VEXT
VDD
Operating Burst
Write Current
IDD4W
Continuous write.
Cyclic bank access.
Continuous address / data.
VDDQ
VEXT
VDD
Operating Burst
Read Current
IDD4R
Continuous read.
Cyclic bank access.
Continuous address / data.
VDDQ
VEXT
Units
mA
mA
mA
Standby and Operating Current Notes:
1. IDD parameters are tested after the device is properly initialized and is operating at worst-case temperature and voltage specifications.
2. IDD parameters are specified with Data Inversion and ODT enabled (@ default impedance).
3. Definitions of IDD Conditions:
3a. Low:
VIN ≤ VIL(AC) (max).
3b. High:
VIN > VIH(AC) (min).
3c. Continuous data:
one quarter of the data bits (including the data inversion bits) change from Low to High, and one quarter
of the data bits change from High to Low, every half clock cycle (twice per clock).
3d. Continuous address:
half of the non-bank address bits change between High and Low every half clock cycle (twice per clock).
3e. Stable address:
all of the non-bank address bits remain fixed High.
3f. Sequential read / write:
alternating Read and Write commands, one command every tRC.
3g. Sequential refresh:
one Refresh command every tRC.
3h. Continuous read:
one Read command every cycle.
3i. Continuous write:
one Write command every cycle.
3j. Continuous refresh:
one Refresh command every cycle for Auto Refresh commands;
one Refresh command every 4 cycles for Overlapped Refresh commands.
3k. Sequential bank access: the bank address increments by one every tRC.
3l. Cyclic bank access:
the bank address increments by one for each command; that is,
once every cycle for Read and Write commands;
once every cycle for Auto Refresh commands;
once every 4 cycles for Overlapped Refresh commands.
Rev: 1.05 9/2014
30/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
4.9 Programmable Impedance Control
The LLDRAM III includes programmable driver impedance control of all output and bidirectional pins (except for the JTAG TDO
pin), as well as programmable termination impedance control of all input and bidirectional pins (except for the RST, LBK, and MF
pins, and the JTAG TCK, TMS, TDI, and TRST pins). See Section 3.5 for a complete list of input, output, and bidirectional pins
affected, and the programmable impedance control available for those pins.
The impedance control affects both High and Low drive strengths, as well as the high-side termination impedance. The impedance
is controlled via a precision resistor connected between the ZQ and VSS pins. The nominal value of the precision (1%) resistor is
240 Ω, with a supported range of 200 Ω to 240 Ω.
The output impedance accuracy is within 15% of the programmed value, with the linearity measured at the points described in the
Impedance Test Parameters table below.
Normally, driver and terminator impedances are continuously adjusted to compensate for temperature and voltage fluctuations in
the system, such that only minor instantaneous variations in the impedances occur. However, when the FZ bit in the MRS registers
is set (to 1), then driver and terminator impedances are “frozen” at their current values.
If the IM bit in the MRS registers is set (to 1), then driver impedance has a nominal value that is independent of the value of the RQ
resistor connected to the ZQ pin. In this mode, the ZQ pin is ignored, and driver impedance is not PVT-compensated.
Impedance Test Parameters (VDDQ = 1.2 V nominal)
Parameter
Symbol
Min
Typ
Max
Units
Output High Voltage with forced IOH = -(VDDQ – 1.02 V) / ZOH
VOH
0.867
1.02
1.173
V
Output High Voltage with forced IOH = -(VDDQ – 0.84 V) / ZOH
VOH
0.714
0.84
0.966
V
Output Low Voltage with forced IOL = 0.84 V / ZOL
VOL
0.714
0.84
0.966
V
Output Low Voltage with forced IOL = 0.66 V / ZOL
VOL
0.561
0.66
0.759
V
Parameter
Symbol
Min
Typ
Max
Units
Output High Voltage with forced IOH = -(VDDQ – 0.85 V) / ZOH
VOH
0.723
0.85
0.977
V
Output High Voltage with forced IOH = -(VDDQ – 0.7 V) / ZOH
VOH
0.595
0.7
0.805
V
Output Low Voltage with forced IOL = 0.7 V / ZOL
VOL
0.595
0.7
0.805
V
Output Low Voltage with forced IOL = 0.55 V / ZOL
VOL
0.468
0.55
0.632
V
Impedance Test Parameters (VDDQ = 1.0 V nominal)
Rev: 1.05 9/2014
31/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
5. Interface AC Timing
5.1 AC Timing Waveforms
Standard bus timing waveforms for address, command, and data are illustrated in the following diagrams. All timing is measured
to/from the crossing point on differential clocks and to/from the VREF crossing point on single-ended signals.
Address / Command Input Timing Waveforms
tCK
tCKH
CK
tCKL
CK
tAS
tAH
tAS
tAH
A
tASH, tAPW
tCS
tASH, tAPW
tCH
CS, WE, REF, DPR
tCSH, tCPW
Data Input Timing Waveforms
CK
CK
tCKDK
tCK
tCKH
DK
tCKL
DK
tIS
tIH
tIS
tIH
DQ, DQINV, DM
tISH, tIPW
tISH, tIPW
Output Driver Enable / Disable Timing Waveforms
CK
CK
tQON
tQOFF
DQ, DQINV
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Preliminary
GS4303T18/36GN
Data Output Timing Waveforms
CK
CK
tCKQK
tCK
tQKH
QK
tQKL
QK
tQKQ0, tQKQ1, tQKQ
tQKQ0, tQKQ1, tQKQ
tQH0, tQH1, tQH
tQH0, tQH1, tQH
DQ, DQINV
tQKQV
QVLD
tQVH
Reset Timing Waveforms
CK
tRSS
tRSH
RST
tRDS
tRDH
DQ
CS, LBK
Note: The clock must be within specification and all other chip inputs must be driven to legal values throughout
the tRSS period.
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Preliminary
GS4303T18/36GN
5.2 AC Timing Specifications
Parameter
Symbol
-600
Min
-500
Max
Min
Max
1.66
2.50
2.00
2.50
1.90
2.50
2.30
2.50
Units
Notes
Input Clock Specifications
CK, DK Clock Period (Speed Config #3)
CK, DK Clock Period (Speed Config #2)
tCK
ns
CK, DK High Time
tCKH
0.45*
—
0.45*
—
tCK (avg)
CK, DK Low Time
tCKL
0.45*
—
0.45*
—
tCK (avg)
CK, DK Period Jitter
tJIT (per)
-0.07
0.07
-0.07
0.07
ns
CK, DK Cycle-to-Cycle Jitter
tJIT (cc)
—
0.14
—
0.14
ns
tCKDK
-0.26
0.26
-0.32
0.32
ns
tPLL
—
20
—
20
μs
CK to DK Skew
Time for PLL to synchronize after its enabled
Input Setup and Hold Specifications
2~3
A to CK Setup Time
tAS
0.17
—
0.20
—
ns
4
CK to A Hold Time
tAH
0.17
—
0.20
—
ns
5
A Input Pulse Width
tAPW
0.25
—
0.30
—
ns
6
A Input Setup / Hold Window
tASH
0.20
—
0.24
—
ns
7
CS, WE, REF, DPR to CK Setup Time
tCS
0.24
—
0.28
—
ns
4
CK to CS, WE, REF, DPR Hold Time
tCH
0.24
—
0.28
—
ns
5
CS, WE, REF, DPR Input Pulse Width
tCPW
0.50
—
0.60
—
ns
6
CS, WE, REF, DPR Input Setup / Hold Window
tCSH
0.40
—
0.48
—
ns
7
DQ, DQINV, DM to DK Setup Time
tIS
0.17
—
0.20
—
ns
4
DK to DQ, DQINV, DM Hold Time
tIH
0.17
—
0.20
—
ns
5
DQ, DQINV, DM Input Pulse Width
tIPW
0.25
—
0.30
—
ns
6
DQ, DQINV, DM Input Setup / Hold Window
tISH
0.20
—
0.24
—
ns
7
Output Timing Specifications
8
Output Rise Time
tRISE
2
5
2
5
V/ns
Output Fall Time
tFALL
2
5
2
5
V/ns
CK to QK Skew
tCKQK
-0.40
0.40
-0.48
0.48
ns
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
5.2 AC Timing Specifications (Continued)
Parameter
-600
Symbol
-500
Min
Max
Min
Max
Units
Notes
9
Additional tRL Delay
tCD
—
5
—
5
ns
QK High Time
tQKH
0.45*
—
0.45*
—
tCK (avg)
QK Low Time
tQKL
0.45*
—
0.45*
—
tCK (avg)
QK0 to DQ[17:0], DQINV[1:0] (x36) or
DQ[8:0], DQINV0 (x18)
tQKQ0
—
0.13
—
0.15
ns
QK0 to DQ[17:0], DQINV[1:0] (x36) or
DQ[8:0], DQINV0 (x18)
tQH0
0.40*
—
0.40*
—
tCK (avg)
QK1 to DQ[35:18], DQINV[3:2] (x36) or
DQ[17:9], DQINV1 (x18)
tQKQ1
—
0.13
—
0.15
ns
QK1 to DQ[35:18], DQINV[3:2] (x36) or
DQ[17:9], DQINV1 (x18)
tQH1
0.40*
—
0.40*
—
tCK (avg)
Any QK to any DQ, DQINV
tQKQ
—
0.20
—
0.24
ns
Any QK to any DQ, DQINV
tQH
0.35*
—
0.35*
—
tCK (avg)
Any QK to QVLD
tQKQV
—
0.20
—
0.24
ns
Any QK to QVLD
tQVH
0.85*
—
0.85*
—
tCK (avg)
QK to DQ, DQINV driver & ODT enable (on)
tQON
—
0.13
—
0.15
ns
QK to DQ, DQINV driver & ODT disable (off)
tQOFF
-0.10 *
tCK (avg)
0.13
-0.10 *
tCK (avg)
0.15
ns
Reset Specifications
RST Pulse Width
tRSS
200
—
200
—
μs
DQ to RST deasserted High Setup Time
tRDS
1000
—
1000
—
cycles
RST deasserted High to DQ Hold Time
tRDH
5
—
5
—
cycles
RST deasserted High to LBK, CS, or DPR
asserted Low
tRSH
400000
—
400000
—
cycles
Loopback Mode Specifications
NOP Commands before LBK asserted Low
tLBKD1
16
—
16
—
cycles
Deskew Training start after LBK asserted Low
tLBKD2
16
—
16
—
cycles
NOP Commands after LBK deasserted High
tLBKD3
16
—
16
—
cycles
MRS Command Specifications
Read, Write, or Refresh command start, or LBK
deasserted High, to MRS command start
tMRD1
24
—
24
—
cycles
MRS command start to Read, Write, or Refresh
command start, or to LBK asserted Low
tMRD2
24
—
24
—
cycles
Rev: 1.05 9/2014
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
AC Timing Specification Notes:
1. tCK (avg) is the value of tCK averaged over 200 clock cycles.
2. All input setup and hold timing assumes input rise and fall times of 2V/ns.
3. Each synchronous input register has a fundamental setup time requirement “FST” and a fundamental hold time requirement “FHT” with
respect to the register’s input clock. When added together, they define the fundamental setup/hold window “FSHW” for the register. Each
synchronous input register also has a fundamental pulse width (i.e., signal valid) requirement “FPW” that is typically greater than FSHW.
4. Each Input Setup spec “t_S” in the table above represents the minimum setup time that is guaranteed (by manufacturing test) to work for
every input in a particular signal group. It is determined by the maximum FST across all inputs in a particular signal group.
5. Each Input Hold spec “t_H” in the table above represents the minimum hold time that is guaranteed (by manufacturing test) to work for every
input in a particular signal group. It is determined by the maximum FHT across all inputs in a particular signal group.
6. Each Input Pulse Width spec “t_PW” in the table above represents the minimum pulse width that is guaranteed (by device characterization)
to work for every input in a particular signal group. It is determined by the maximum FPW across all inputs in a particular signal group.
7. Each Input Setup / Hold Window spec “t_SH” in the table above is determined by the maximum FSHW across all inputs in a particular signal
group. It is based on electrical simulations. It is used for deskew timing budgeting, and cannot be directly measured without performing
deskew training.
8. All output timing assumes the AC Test Output Load illustrated in the figure below.
9. tCD applies during Loopback Mode and when the PLL is disabled.
AC Test Output Load
VDDQ
60 Ω
Output
50Ω
2 pF
Rev: 1.05 9/2014
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
6. JTAG Specification
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a subset of IEEE std. 1149.1 functions.
This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.),
LLDRAM III, other components, and the printed circuit board. In conformance with a subset of the IEEE standard, these devices
contain a TAP Controller and multiple TAP Registers consisting of one Instruction Register and multiple Data Registers.
The TAP consists of the following five signals:
Pin
Pin Name
I/O
On-Chip PU / PD
Description
TCK
Test Clock
I
Pull-down
Induces (clocks) TAP Controller state transitions.
TRST
Test Reset
I
Pull-down
Asynchronously resets the TAP Controller when Low.
TMS
Test Mode Select
I
Pull-up
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TDI
Test Data In
I
Pull-up
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
TDO
Test Data Out
O
—
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
Concurrent TAP and Normal Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST, CLAMP, and HIGH-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the LLDRAM III. TRST should also be tied Low. TMS and
TDI should either be tied High through a pull-up resistor or left unconnected. TDO should be left unconnected.
6.1 JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VTIH
VREF + 0.15
VDDQ + 0.3
V
1
JTAG Input Low Voltage
VTIL
–0.3
VREF – 0.15
V
1
JTAG Output High Voltage
VTOH
VDDQ – 0.2
—
V
2, 3
JTAG Output Low Voltage
VTOL
—
0.2
V
2, 4
Notes:
1. Parameters apply to TCK, TMS, TDI and TRST.
2. Parameters apply to TDO.
3. ITOH = –2.0 mA.
4. ITOL = 2.0 mA.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
6.2 JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTHTH
20
—
ns
TCK High Pulse Width
tTHTL
10
—
ns
TCK Low Pulse Width
tTLTH
10
—
ns
TMS Setup Time
tMVTH
5
—
ns
TMS Hold Time
tTHMX
5
—
ns
TDI Setup Time
tDVTH
5
—
ns
TDI Hold Time
tTHDX
5
—
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
5
—
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
5
—
ns
TCK Low to TDO Valid
tTLQV
—
10
ns
TCK Low to TDO Hold
tTLQX
0
—
ns
TRST Low Pulse Width
tTRSTW
100
—
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
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Preliminary
GS4303T18/36GN
6.3 TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of three ways:
1. At power up.
2. When a logic 0 is applied to TRST.
3. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
6.4 TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR—8 bits)
The Instruction Register stores the various TAP Instructions supported by the LLDRAM III. It is loaded with the IDCODE
instruction at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 8 bits wide, and is encoded as follows:
Code
(7:0)
Instruction
Description
EXTEST
Loads the logic states of all signals composing the LLDRAM III I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between TDI
and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with all output signals (DQ, DQINV,
QVLD, QK, QK) directly to their corresponding output pins. However, newly loaded Boundary Scan Register
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
See the Boundary Scan Register description for more information.
0010 0001
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the TAP
Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the TAP
Controller is in the Shift-DR state.
See the ID Register description for more information.
0000 0101
SAMPLE /
PRELOAD
Loads the logic states of all signals composing the LLDRAM III I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between TDI
and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
CLAMP
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and inserts
the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with all output signals (DQ, DQINV,
QVLD, QK, QK) directly to their corresponding output pins.
See the Bypass Register description for more information.
0000 0011
HIGH-Z
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and inserts
the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
Also forces all output drivers (DQ, DQINV, QVLD, QK, QK) to a High-Z state.
See the Bypass Register description for more information.
1111 1111
BYPASS
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and inserts
the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
All Others
PRIVATE
The remaining instructions are reserved for manufacturer use only.
0000 0000
0000 0111
Bit 0 is the LSB of the Instruction Register, and Bit 7 is the MSB. When the Instruction Register is selected, TDI serially shifts data
into the MSB, and the LSB serially shifts data out through TDO.
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Preliminary
GS4303T18/36GN
Bypass Register (DR—1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR—32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the ShiftDR state.
The ID Register is 32 bits wide, and is encoded as follows:
Device
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
x18
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
x36
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR—113 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the LLDRAM III (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the LLDRAM III I/O ring when the EXTEST or SAMPLE / PRELOAD instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST or
SAMPLE / PRELOAD instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the LLDRAM III outputs (DQ, DQINV, QVLD, QK,
QK) are driven directly to the corresponding LLDRAM III output pins when the EXTEST instruction is selected. However, after
the EXTEST instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the
Shift-DR state does not appear at the output pins until the TAP Controller has reached the Update-DR state.
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© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order Assignments
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 0 is the LSB and Bit 112 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Note: In the following tables:
• Pins labeled “DNU0” correspond to “DNU, VSS” pins in the pinouts.
• Pins labeled “DNU1” correspond to “DNU, VDDQ” pins in the pinouts.
• Pins labeled “name1_name2” (e.g., “CS_WE”) are those subject to the mirror function, where “name1” is the MF=0 pin name,
and “name2” is the MF=1 pin name.
Boundary Scan Register Bit Order, x18
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
J3
K3
L2
L4
M5
M3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
DK0
DK0
CS_WE
A4_A3
A2_REF
DPR_A9
*
DQINV1
A0_A1
*
DQ9
*
DNU0(1)
*
DNU0(2)
*
DNU0(3)
*
DQ11
*
DQ13
*
DNU0(4)
QK1
*
DNU0(5)
*
DQ15
QK1
*
DQ17
*
input
input
input
input
input
input
control
bidir
input
control
bidir
control
internal
control
internal
control
internal
control
bidir
control
bidir
control
internal
output2
control
internal
control
bidir
output2
control
bidir
control
X
X
X
X
X
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
0
X
0
X
X
0
X
0
N2
N4
P5
P3
P1
R2
R4
T5
T3
T1
U2
U4
V1
U12
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Ctrl Cell Ctrl Value Ctrl State
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6
0
Z
9
0
Z
17
0
Z
19
0
Z
26
0
Z
29
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order, x18 (Continued)
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
U10
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
DNU0(6)
*
DNU0(7)
*
DQ16
*
DQ14
*
DNU0(8)
*
DNU0(9)
*
DQ10
*
DQ12
*
DNU0(10)
A1_A0
REF_A2
A9_DPR
WE_CS
A3_A4
CK
DNU0(11)
LBK
DNU0(12)
CK
A5_A6
DM_RST
A11
A7
A13_A12
*
DNU0(13)
*
DQ3
*
DQ1
*
DNU0(14)
*
DNU0(15)
internal
control
internal
control
bidir
control
bidir
control
internal
control
internal
control
bidir
control
bidir
control
internal
input
input
input
input
input
input
internal
input
internal
input
input
input
input
input
input
control
internal
control
bidir
control
bidir
control
internal
control
internal
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
X
0
X
0
X
0
X
0
X
T9
T11
R12
R10
P9
P11
P13
N12
N10
M9
M11
L12
L10
K9
K11
J13
J11
J9
H10
H12
G11
G9
F10
F12
E13
E11
E9
D10
Rev: 1.05 9/2014
Ctrl Cell Ctrl Value Ctrl State
43/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
35
0
Z
37
0
Z
43
0
Z
45
0
Z
66
0
Z
68
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order, x18 (Continued)
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
*
DQ5
QK0
*
DQ7
*
DNU0(16)
*
DNU0(17)
*
DQ8
QK0
*
DQ6
*
DNU0(18)
QVLD
*
DNU0(19)
*
DQ4
*
DQ2
*
DNU0(20)
*
DNU0(21)
*
DNU0(22)
*
DQ0
A12_A13
*
DQINV0
A10
A8
A6_A5
RST_DM
MF
control
bidir
output2
control
bidir
control
internal
control
internal
control
bidir
output2
control
bidir
control
internal
output2
control
internal
control
bidir
control
bidir
control
internal
control
internal
control
internal
control
bidir
input
control
bidir
input
input
input
input
input
0
X
X
0
X
0
X
0
X
0
X
X
0
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
0
X
X
X
X
X
X
D12
C13
C11
C9
B10
B12
A13
B4
B2
C1
C3
C5
D4
D2
E1
E3
E5
F4
F2
G3
G5
H4
H2
J1
Rev: 1.05 9/2014
Ctrl Cell Ctrl Value Ctrl State
44/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
74
0
Z
77
0
Z
83
0
Z
86
0
Z
93
0
Z
95
0
Z
103
0
Z
106
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order, x36
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
J3
K3
L2
L4
M5
M3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
DK0
DK0
CS_WE
A4_A3
A2_REF
DPR_A9
*
DQINV2
A0_A1
*
DQ18
*
DQ34
*
DQ35
*
DQ32
*
DQ20
*
DQ22
*
DQ30
QK1
*
DQ28
*
DQ24
QK1
*
DQ26
*
DQ27
*
DQ29
*
DQ25
*
DQ23
*
DQ31
input
input
input
input
input
input
control
bidir
input
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
output2
control
bidir
control
bidir
output2
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
X
X
X
X
X
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
0
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
N2
N4
P5
P3
P1
R2
R4
T5
T3
T1
U2
U4
V1
U12
U10
T9
T11
R12
R10
Rev: 1.05 9/2014
Ctrl Cell Ctrl Value Ctrl State
45/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6
0
Z
9
0
Z
11
0
Z
13
0
Z
15
0
Z
17
0
Z
19
0
Z
21
0
Z
24
0
Z
26
0
Z
29
0
Z
31
0
Z
33
0
Z
35
0
Z
37
0
Z
39
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order, x36 (Continued)
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
*
DQ33
*
DQ19
*
DQ21
*
DQINV3
A1_A0
REF_A2
A9_DPR
WE_CS
A3_A4
CK
DK1
LBK
DK1
CK
A5_A6
DM_RST
A11
A7
DNU1(1)
*
DQINV1
*
DQ3
*
DQ1
*
DQ17
*
DQ15
*
DQ5
QK0
*
DQ7
*
DQ13
*
DQ11
control
bidir
control
bidir
control
bidir
control
bidir
input
input
input
input
input
input
input
input
input
input
input
input
internal
internal
internal
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
output2
control
bidir
control
bidir
control
bidir
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
X
0
X
0
X
0
X
0
X
0
X
X
0
X
0
X
0
X
P9
P11
P13
N12
N10
M9
M11
L12
L10
K9
K11
J13
J11
J9
H10
H12
G11
G9
F10
F12
E13
E11
E9
D10
D12
C13
C11
C9
B10
Rev: 1.05 9/2014
Ctrl Cell Ctrl Value Ctrl State
46/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
41
0
Z
43
0
Z
45
0
Z
47
0
Z
64
0
Z
66
0
Z
68
0
Z
70
0
Z
72
0
Z
74
0
Z
77
0
Z
79
0
Z
81
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
Boundary Scan Register Bit Order, x36 (Continued)
Pin
Cell #
Cell Type
Pin Name
Type
Safe Bit
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
BC_2
BC_7
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_2
BC_7
BC_1
BC_2
BC_7
BC_1
BC_1
BC_1
BC_1
BC_1
*
DQ8
QK0
*
DQ6
*
DQ9
QVLD
*
DQ10
*
DQ4
*
DQ2
*
DQ12
*
DQ16
*
DQ14
*
DQ0
DNU1(2)
*
DQINV0
A10
A8
A6_A5
RST_DM
MF
control
bidir
output2
control
bidir
control
bidir
output2
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
control
bidir
internal
control
bidir
input
input
input
input
input
0
X
X
0
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
0
X
X
X
X
X
X
B12
A13
B4
B2
C1
C3
C5
D4
D2
E1
E3
E5
F4
F2
G3
G5
H4
H2
J1
Rev: 1.05 9/2014
Ctrl Cell Ctrl Value Ctrl State
47/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
83
0
Z
86
0
Z
88
0
Z
91
0
Z
93
0
Z
95
0
Z
97
0
Z
99
0
Z
101
0
Z
103
0
Z
106
0
Z
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
7. Package Dimensions—180p BGA
A1 Corner
5.42
5.42
Note: All dimensions in millimeters.
6.23
10°
// 0.10 S
S
0.738
6.23
13.6
1.208
Ø0.6
Seating Plane
0.17
0.10 S
(E-Pin, 5x)
0.47
R0.2 (4x)
Ø0.61
(180x)
Ø0.15 M
Ø0.08 M
SAB
S
A1 Corner
0.218
1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1
1.0
18.1
18.5
Pitch 1.0 * 17 = 17
15.2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
0.52
A
2.68
0.2 S A
1.0
Pitch 1.0 * 12 = 12
14.0
0.2 S B
B
Rev: 1.05 9/2014
48/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
8. Ordering Information—GSI LLDRAM III
Org
Part Number
Type
Package
Max Speed
Temp
64Mb x 18
GS4303T18GN-600
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
600 MHz
C
64Mb x 18
GS4303T18GN-500
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
500 MHz
C
32Mb x 36
GS4303T36GN-600
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
600 MHz
C
32Mb x 36
GS4303T36GN-500
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
500 MHz
C
64Mb x 18
GS4303T18GN-600I
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
600 MHz
I
64Mb x 18
GS4303T18GN-500I
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
500 MHz
I
32Mb x 36
GS4303T36GN-600I
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
600 MHz
I
32Mb x 36
GS4303T36GN-500I
Common I/O Burst of 2
RoHS-compliant 180-pin BGA
500 MHz
I
Note:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS4303TH20GN-600T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.05 9/2014
49/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology
Preliminary
GS4303T18/36GN
9. Datasheet Revision History
Rev. Code
Types of Changes
Format or Content
GS4303Txx_r1
—
• Creation of initial datasheet.
GS4303Txx_r1.01
Content
• Updated package drawing.
GS4303Txx_r1.02
Content
• Corrected VX specs in I/O AC Electrical Specifications.
GS4303Txx_r1.03
Content
• Updated package drawing.
GS4303Txx_r1.04
Content
• Updated Data Inversion description.
• Updated Standby and Operating Current measurement conditions, and
added IDDQ specifications.
GS4303Txx_r1.05
Content
• Updated the Initial Impedance Settings description.
Rev: 1.05 9/2014
Revisions
50/50
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology