Preliminary GS82582T19/37GE-450/400/375/333 288Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features 450 MHz–333 MHz 1.8 V VDD 1.8 V or 1.5 V I/O SRAMs. The GS82582T19/37GE SigmaDDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid pin (QVLD) Support • IEEE 1149.1 JTAG-compliant Boundary Scan • RoHS-compliant 165-bump BGA package Clocking and Addressing Schemes The GS82582T19/37GE SigmaDDR-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a SigmaDDR-II+ B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a SigmaDDR-II+ B2 RAM is always one address pin less than the advertised index depth (e.g., the 16M x 18 has an 8M addressable index). SigmaDDR™ Family Overview The GS82582T19/37GE are built in compliance with the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) Parameter Synopsis Rev: 1.03 7/2015 -450 -400 -375 -333 tKHKH 2.2 ns 2.5 ns 2.66 ns 3.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 1/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 16M x 18 SigmaDDR-II+ SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W BW1 K SA LD SA SA CQ B NC DQ9 NC SA SA K BW0 SA NC NC DQ8 C NC NC NC VSS SA NC SA VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA QVLD SA SA NC NC DQ0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Note: BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17. Rev: 1.03 7/2015 2/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 8M x 36 SigmaDDR-II+ SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W BW2 K BW1 LD SA SA CQ B NC DQ27 DQ18 SA BW3 K BW0 SA SA NC DQ8 C NC NC DQ28 VSS SA NC SA VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Note: BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35. Rev: 1.03 7/2015 3/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read Input High: Read Low: Write BW0–BW3 Synchronous Byte Writes Input Active Low LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — MCL Must Connect Low — — DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active Low CQ Output Echo Clock Output — CQ Output Echo Clock Output — VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 V or 1.5 V Nominal VSS Power Supply: Ground Supply — QVLD Q Valid Output Output — ODT On-Die Termination Input Active High NC No Connect — — Notes: 1. NC = Not Connected to die or any other pin 2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. K and K cannot be set to VREF voltage. Rev: 1.03 7/2015 4/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Background Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations Read and write operations are "Burst" operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in the timing diagrams.This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted. Deselect Cycles Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations. SigmaDDR-II+ Burst of 2 SRAM Read Cycles The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. SigmaDDR-II+ Burst of 2 SRAM Write Cycles The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures data in on the next rising edge of K, for a total of two transfers per address load. Special Functions Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Rev: 1.03 7/2015 5/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 3 D0–D8 Byte 4 D9–D17 Written Unchanged Unchanged Written Beat 1 Beat 2 Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Rev: 1.03 7/2015 6/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaDDR-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Input Termination Impedance Control These SigmaDDR-II+ SRAMs are supplied with programmable input termination on Data (DQ), Byte Write (BW), and Clock (K, K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left floating–the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175 and 250. Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner as for driver impedance (see above). Notes: 1. When ODT = 1, Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating currents being higher. 2. When ODT = 1, DQ input termination is enabled during Write and NOP operations, and disabled during Read operations. Specifically, DQ input termination is disabled 0.5 cycles before the SRAM enables its DQ drivers and starts driving valid Read Data, and remains disabled until 0.5 cycles after the SRAM stops driving valid Read Data and disables its DQ drivers; DQ input termination is enabled at all other times. Consequently, the SRAM Controller should disable its DQ input termination, enable its DQ drivers, and drive DQ inputs (High or Low) during Write and NOP operations. And, it should enable its DQ input termination and disable its DQ drivers during Read operations. Care should be taken during Write or NOP -> Read transitions, and during Read -> NOP transitions, to minimize the time during which one device (SRAM or SRAM Controller) has enabled its DQ input termination while the other device has not yet enabled its DQ driver. Otherwise, the input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a metastable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating currents being higher. Rev: 1.03 7/2015 7/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Power-Up Initialization After power-up, stable input clocks must be applied to the device for 20 s prior to issuing read and write commands. See the tKInit timing parameter in the AC Electrical Characteristics section. Note: The tKInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048) must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock properly before issuing read and write commands). However, tKInit is greater than tKLock, even at the slowest permitted cycle time of 8.4 ns (2048*8.4 ns = 17.2 s). Consequently, the 20 s associated with tKInit is sufficient to cover the tKLock requirement at power-up if the Doff pin is driven High prior to the start of the 20 s period. Also, tKInit only needs to be met once, immediately after power-up, whereas tKLock must be met any time the DLL is disabled/reset (whether by toggling Doff Low or by stopping K clocks for > 30 ns). Rev: 1.03 7/2015 8/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table DQ Kn LD 1 R/W Operation A+0 A+1 X Hi-Z / * Hi-Z / * Deselect 0 0 D@Kn+1 D@Kn+1 Write 0 1 Q@Kn+2 Q@Kn+2 Read Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”. 2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations. 3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations. 4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP and Write commands, 2.0 cycles after the command is sampled. 5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.0 cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the state of the DQ input termination. See the Input Termination Impedance Control section for more information. Burst of 2 Byte Write Clock Truth Table BW BW Current Operation D D K (tn + 1) K (tn + 1½) K (tn) K (tn +1 ) K (tn + 1½) T T Write Dx stored if BWn = 0 in both data transfers D1 D2 T F Write Dx stored if BWn = 0 in 1st data transfer only D1 X F T Write Dx stored if BWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.03 7/2015 9/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 x36 Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Data In Don’t Care Don’t Care Don’t Care 1 0 1 1 Don’t Care Data In Don’t Care Don’t Care 0 0 1 1 Data In Data In Don’t Care Don’t Care 1 1 0 1 Don’t Care Don’t Care Data In Don’t Care 0 1 0 1 Data In Don’t Care Data In Don’t Care 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Data In Data In Data In Don’t Care 1 1 1 0 Don’t Care Don’t Care Don’t Care Data In 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Don’t Care Data In Don’t Care Data In 0 0 1 0 Data In Data In Don’t Care Data In 1 1 0 0 Don’t Care Don’t Care Data In Data In 0 1 0 0 Data In Don’t Care Data In Data In 1 0 0 0 Don’t Care Data In Data In Data In 0 0 0 0 Data In Data In Data In Data In x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In Rev: 1.03 7/2015 10/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 2.9 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 ( 2.9 V max.) V VTIN Input Voltage (TCK, TMS, TDI) –0.5 to VDDQ +0.5 ( 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 oC TSTG Storage Temperature –55 to 125 oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.4 — VDD V Reference Voltage VREF VDDQ/2 – 0.05 — VDDQ/2 + 0.05 V Note:. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Junction Temperature (Commercial Range Versions) TJ 0 25 85 C Junction Temperature (Industrial Range Versions)* TJ –40 25 100 C Note: * The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.03 7/2015 11/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Thermal Impedance Package Test PCB Substrate JA (C°/W) Airflow = 0 m/s JA (C°/W) Airflow = 1 m/s JA (C°/W) Airflow = 2 m/s JB (C°/W) JC (C°/W) 165 BGA 4-layer 16.10 13.69 12.73 6.54 2.08 Notes: 1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. Please refer to JEDEC standard JESD51-6. 3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes Input Reference Voltage VREF VDDQ /2 – 0.05 VDDQ /2 + 0.05 V – Input High Voltage VIH1 VREF + 0.1 VDDQ + 0.3 V 1 Input Low Voltage VIL1 –0.3 VREF – 0.1 V 1 Input High Voltage VIH2 0.7 * VDDQ VDDQ + 0.3 V 2,3 Input Low Voltage VIL2 –0.3 0.3 * VDDQ V 2,3 Notes: 1. Parameters apply to K, K, SA, DQ, R/W, LD, BW during normal operation and JTAG boundary scan testing. 2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing. 3. Parameters apply to ZQ during JTAG boundary scan testing only. HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes Input Reference Voltage VREF VDDQ /2 – 0.08 VDDQ /2 + 0.08 V – Input High Voltage VIH1 VREF + 0.2 VDDQ + 0.5 V 1,2,3 Input Low Voltage VIL1 –0.5 VREF – 0.2 V 1,2,3 Input High Voltage VIH2 VDDQ – 0.2 VDDQ + 0.5 V 4,5 Input Low Voltage VIL2 –0.5 0.2 V 4,5 Notes: 1. VIH(MAX) and VIL(MIN) apply for pulse widths less than one-quarter of the cycle time. 2. Input rise and fall times myust be a minimum of 1 V/ns, and within 10% of each other. 3. Parameters apply to K, K, SA, DQ, R/W, LD, BW during normal operation and JTAG boundary scan testing. 4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing. 5. Parameters apply to ZQ during JTAG boundary scan testing only. Rev: 1.03 7/2015 12/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Clock Capacitance CCLK — 5 6 pF Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level 1.25 Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level .75 Output reference level 0.75 V Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ 50 RQ = 250 (HSTL I/O) VREF = 0.75 V VT = 0.75 V Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IILDOFF VIN = 0 to VDD –20 uA 2 uA ODT IILODT VIN = 0 to VDD –2 uA 20 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Rev: 1.03 7/2015 13/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175 RQ 350 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175 RQ 350. 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V 4. 0RQ 5. IOH = –1.0 mA 6. IOL = 1.0 mA Rev: 1.03 7/2015 14/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Operating Currents -450 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR Standby Current (NOP): DDR -400 -375 -333 0° to 70°C –40° to 85°C 0° to 70°C –40° to 85°C 0° to 70°C –40° to 85°C 0° to 70°C –40° to 85°C Notes VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min TBD TBD TBD TBD TBD TBD TBD TBD 2, 3 ISB1 Device deselected, IOUT = 0 mA, f = Max, All Inputs 0.2 V or VDD – 0.2 V TBD TBD TBD TBD TBD TBD TBD TBD 2, 4 Notes: 1. Power measured with output pins floating. 2. Minimum cycle, IOUT = 0 mA 3. Operating current is calculated with 50% read cycles and 50% write cycles. 4. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.03 7/2015 15/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Symbol -450 -400 -375 -333 Min Max Min Max Min Max Min Max Units Parameter Notes AC Electrical Characteristics Clock K, K Clock Cycle Time tKHKH 2.2 8.4 2.5 8.4 2.66 8.4 3.0 8.4 ns tK Variable tKVar — 0.15 — 0.2 — 0.2 — 0.2 ns K, K Clock High Pulse Width tKHKL 0.4 — 0.4 — 0.4 — 0.4 — cycle K, K Clock Low Pulse Width tKLKH 0.4 — 0.4 — 0.4 — 0.4 — cycle K to K High tKHKH 0.94 — 1.06 — 1.13 — 1.28 — ns K to K High tKHKH 0.94 — 1.06 — 1.13 — 1.28 — ns DLL Lock Time tKLock 2048 — 2048 — 2048 — 2048 — cycle K Static to DLL reset tKReset 30 — 30 — 30 — 30 — ns tKInit 20 — 20 — 20 — 20 — s K, K Clock High to Data Output Valid tKHQV — 0.45 — 0.45 — 0.45 — 0.45 ns K, K Clock High to Data Output Hold tKHQX –0.45 — –0.45 — –0.45 — –0.45 — ns K, K Clock High to Echo Clock Valid tKHCQV — 0.37 — 0.45 — 0.45 — 0.45 ns K, K Clock High to Echo Clock Hold tKHCQX –0.37 — –0.45 — –0.45 — –0.45 — ns CQ, CQ High Output Valid tCQHQV — 0.15 — 0.2 — 0.2 — 0.25 ns CQ, CQ High Output Hold tCQHQX –0.15 — –0.2 — –0.2 — –0.25 — ns tQVLD –0.15 0.15 –0.2 0.2 -0.2 0.2 –0.25 0.25 ns tCQHCQH tCQHCQH 0.85 — 1.0 — 1.08 — 1.25 — ns K Clock High to Data Output High-Z tKHQZ — 0.45 — 0.45 — 0.45 — 0.45 ns K Clock High to Data Output Low-Z tKHQX1 –0.45 — –0.45 — –0.45 — –0.45 — ns tAVKH 0.275 — 0.4 — 0.4 — 0.4 — ns 1 tIVKH 0.275 — 0.4 — 0.4 — 0.4 — ns 2 tIVKH 0.22 — 0.28 — 0.28 — 0.28 — ns 3 tDVKH 0.22 — 0.28 — 0.28 — 0.28 — ns tKHAX 0.275 — 0.4 — 0.4 — 0.4 — ns K, K Clock Initialization 4 5 6 Output Times CQ, CQ High to QLVD CQ Phase Distortion Setup Times Address Input Setup Time Control Input Setup Time (R/W, LD) Control Input Setup Time (BWX) Data Input Setup Time Hold Times Address Input Hold Time 1 Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R/W, LD. 3. Control signals are BW0, BW1 and (BW2, BW3 for x36). 4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 6. After device power-up, 20s of stable input clocks (as specified by tKInit) must be supplied before reads and writes are issued. Rev: 1.03 7/2015 16/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 AC Electrical Characteristics (Continued) Data Input Hold Time -400 -375 -333 Min Max Min Max Min Max Min Max Notes Control Input Hold Time (R/W, LD) Control Input Hold Time (BWX) -450 Units Parameter tKHIX 0.275 — 0.4 — 0.4 — 0.4 — ns 2 tKHIX 0.22 — 0.28 — 0.28 — 0.28 — ns 3 tKHDX 0.22 — 0.28 — 0.28 — 0.28 — ns Symbol Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R/W, LD. 3. Control signals are BW0, BW1 and (BW2, BW3 for x36). 4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 6. After device power-up, 20s of stable input clocks (as specified by tKInit) must be supplied before reads and writes are issued. Rev: 1.03 7/2015 17/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Read-Write K-Based Timing Diagram NOOP Read NOOP NOOP Write Read Read NOOP NOOP Write Write K K tAVKH ADDR tKHAX A1 A2 tIVKH A3 A4 A5 A6 tKHIX LD tIVKH tKHIX R/ W QVLD tKHQX tKHQX tKLZ tDVKH tKHZ tKHDX D DQ tKHQV tKHDX tKHQX tKHQV D tDVKH D D CQ tQVLD tQVLD CQ Rev: 1.03 7/2015 18/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Read-Write CQ-Based Timing Diagram NOOP Read NOOP NOOP Write Read Read NOOP NOOP Write Write K K tAVKH ADDR tKHAX A1 A2 tIVKH A3 A4 A5 A6 tKHIX LD tIVKH tKHIX R/ W QVLD tDVKH tKHDX tKHDX DQ Q1 Q1+1 D2 D2+1 tDVKH Q3 Q3+1 Q4 Q4+1 tCQHQV tCQLQX D5 D5+1 D6 tCQHQX tCQLQV CQ tCQHQV tCQLQV tQVLD tCQHQX tCQLQX tQVLD CQ Rev: 1.03 7/2015 19/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. TDI Test Data In In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Rev: 1.03 7/2015 20/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram · · · · · · · · Boundary Scan Register · · 1 · 108 0 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · ·· 2 1 0 Control Signals TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. GSI Technology JEDEC Vendor ID Code See BSDL Model Bit # Presence Register ID Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X Rev: 1.03 7/2015 X X X X X X X X X X X X X X X X X X 0 21/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 0 1 1 0 1 1 0 0 1 © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.03 7/2015 22/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. Rev: 1.03 7/2015 23/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 GSI 011 GSI private instruction. 1 SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 GSI 110 GSI private instruction. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1 Test Port Input High Voltage VIHJ 0.7 * VDD VDD +0.3 V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ VDD – 0.2 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.2 V 5, 7 Test Port Output CMOS High VOHJC VDD – 0.1 — V 5, 8 Test Port Output CMOS Low VOLJC — 0.1 V 5, 9 Notes: 1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDD supply. 6. IOHJ = –2 mA 7. IOLJ = + 2 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA Rev: 1.03 7/2015 24/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDD/2 JTAG Port AC Test Load TDO 50 30pF* VDD/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Rev: 1.03 7/2015 25/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Package Dimensions—165-Bump FPBGA (Package GE) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 17±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 10.0 0.15 C B Rev: 1.03 7/2015 0.20(4x) 0.36~0.46 1.50 MAX. SEATING PLANE C 15±0.05 26/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology Preliminary GS82582T19/37GE-450/400/375/333 Ordering Information—GSI SigmaDDR-II+ SRAM Org Part Number1 Type Package Speed (MHz) TJ2 16M x 18 GS82582T19GE-450 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 C 16M x 18 GS82582T19GE-400 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 C 16M x 18 GS82582T19GE-375 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 375 C 16M x 18 GS82582T19GE-333 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 333 C 16M x 18 GS82582T19GE-450I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 I 16M x 18 GS82582T19GE-400I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 I 16M x 18 GS82582T19GE-375I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 375 I 16M x 18 GS82582T19GE-333I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 333 I 8M x 36 GS82582T37GE-450 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 C 8M x 36 GS82582T37GE-400 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 C 8M x 36 GS82582T37GE-375 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 375 C 8M x 36 GS82582T37GE-333 SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 333 C 8M x 36 GS82582T37GE-450I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 I 8M x 36 GS82582T37GE-400I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 I 8M x 36 GS82582T37GE-375I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 375 I 8M x 36 GS82582T37GE-333I SigmaDDR-II+ B2 SRAM RoHS-compliant 165-bump BGA 333 I Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS82582TxxGE-300T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Revision History File Name Types of Changes Format or Content GS82582T1937_r1 Format • Creation of new datasheet GS82582T1937_r1_01 Content • Updated speed bin offerings GS82582T1937_r1_02 Content • Removed x8 and x9 configurations GS82582T1937_r1_03 Content • Removed leaded part numbers • Added Power-Up Initialization section on page 10 • Added tKInit specification Rev: 1.03 7/2015 Revisions 27/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2012, GSI Technology