GS8342R08/09/18/36AE-250/200/167
36Mb SigmaDDR-II™
Burst of 4 SRAM
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36, x18, and x9) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb, 18Mb, 72Mb and 144Mb
devices
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The GS8342R08/09/18/36AE are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342R08/09/18/36AE SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
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The GS8342R08/09/18/36AE SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
Rev: 1.07 8/2012
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
De
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SigmaDDR-II™ Family Overview
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
ct
Features
250 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
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165-Bump BGA
Commercial Temp
Industrial Temp
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 4M x 8 has a 1M addressable index, and A0 and
A1 are not accessible address pins).
Parameter Synopsis
-250
-200
-167
tKHKH
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.5 ns
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
1M x 36 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
R/W
BW2
K
BW1
LD
SA
NC
CQ
B
NC
DQ27
DQ18
SA
BW3
C
NC
NC
DQ28
VSS
SA
D
NC
DQ29
DQ19
VSS
VSS
E
NC
NC
DQ20
VDDQ
VSS
F
NC
DQ30
DQ21
VDDQ
VDD
G
NC
DQ31
DQ22
VDDQ
VDD
H
Doff
VREF
VDDQ
VDDQ
VDD
J
NC
NC
DQ32
VDDQ
VDD
K
NC
NC
DQ23
VDDQ
VDD
L
NC
DQ33
DQ24
VDDQ
M
NC
NC
DQ34
VSS
N
NC
DQ35
DQ25
P
NC
NC
R
TDO
TCK
BW0
SA
NC
NC
DQ8
SA0
SA1
VSS
NC
DQ17
DQ7
VSS
VSS
VSS
NC
NC
DQ16
VSS
VSS
VDDQ
NC
DQ15
DQ6
VSS
VDD
VDDQ
NC
NC
DQ5
VSS
VDD
VDDQ
NC
NC
DQ14
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
VSS
VDD
VDDQ
NC
DQ13
DQ4
VSS
VDD
VDDQ
NC
DQ12
DQ3
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
VSS
SA
SA
SA
VSS
NC
NC
DQ10
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
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1
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. A2 and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Addresses
A10
72Mb
A2
144Mb
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
2M x 18 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
R/W
BW1
K
NC
LD
SA
SA
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA1
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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1
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Address
A2
72Mb
A7
144Mb
B5
288Mb
3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
4M x 9 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
R/W
NC
K
NC
LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
DQ4
C
NC
NC
NC
VSS
SA
NC
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ5
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ2
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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1
DQ8
SA
SA
C
SA
SA
NC
NC
DQ0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Address
A2
72Mb
A7
144Mb
B5
288Mb
4/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
4M x 8 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
NC
SA
R/W
NW1
K
NC
LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
NW0
SA
NC
NC
DQ3
C
NC
NC
NC
VSS
SA
NC
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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1
DQ7
SA
SA
C
SA
SA
NC
NC
NC
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
No
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Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7
3. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Rev: 1.07 8/2012
Expansion Address
A2
72Mb
A7
144Mb
B5
288Mb
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Pin Description Table
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
NC
No Connect
—
—
R/W
Synchronous Read/Write
Input
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Symbol
—
Input
Active Low
x18/x36 only
Input
Active Low
x8 only
Input
Active Low
Input
Active High
Input
Active Low
Input
Active High
Input
Active Low
Input
—
Input
—
Input
—
Output
—
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
Power Supply
Supply
1.8 V Nominal
Isolated Output Buffer Supply
Supply
1.5 V Nominal
Power Supply: Ground
Supply
—
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
LD
Synchronous Load Pin
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
VREF
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BW0–BW3
VDD
VDDQ
VSS
No
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Notes:
1. NC = Not Connected to die or any other pin.
2. C, C, K, or K cannot be set to VREF voltage.
Rev: 1.07 8/2012
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Background
ct
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
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Burst Operations
Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated
in the timing diagrams. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less
often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from
loading read or write command
inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.
SigmaDDR-II B4 SRAM Read Cycles
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for
SigmaDDR-II B4 SRAM Write Cycles
Ne
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The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in
response to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins
are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined
reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces
data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data
is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of
four transfers per address load.
No
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co
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The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/
W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is
checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the
rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst
of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the
next rising edge of K#, for a total of four transfers per address load.
Rev: 1.07 8/2012
7/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1a.
1b.
1c.
Apply VDD.
Apply VDDQ.
Apply VREF (may also be applied at the same time as VDDQ).
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2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
ct
1. Power-up and maintain Doff at low state.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of clean K clocks are always required to relock the DLL after reset.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar ).
• The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Special Functions
De
sig
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
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for
Ne
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Each write enable command and write address loaded into the RAM provides the base address for a beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,
“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
Beat 2
Beat 3
D0–D8
D9–D17
0
1
Data In
Don’t Care
1
0
Don’t Care
Data In
0
0
Data In
Data In
1
0
Don’t Care
Data In
No
t
Beat 4
BW1
Re
co
m
Beat 1
BW0
Rev: 1.07 8/2012
8/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Resulting Write Operation
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Unchanged
Written
Written
Written
Unchanged
Written
Beat 2
Beat 3
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Beat 1
ct
Byte 1
D0–D8
Beat 4
No
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for
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sig
Output Register Control
SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.07 8/2012
9/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Example Four Bank Depth Expansion Schematic
LD3
ct
R3/W3
R2/W2
LD1
R1/W1
LD0
R0/W0
A0–An
K
Bank 1
A
A
R/W
R/W
LD
LD
CQ
K
CQ
Ne
w
K
De
sig
Bank 0
DQ
Bank 2
Bank 3
A
A
R/W
R/W
LD
LD
K
CQ
DQ
K
CQ
DQ
me
nd
ed
for
DQ
n—
Di
sco
nt
inu
ed
Pr
od
u
LD2
DQ1-DQn
CQ0
Re
co
m
CQ1
CQ2
No
t
CQ3
Note:
For simplicity BWn not shown.
Rev: 1.07 8/2012
10/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Common I/O SigmaDDR-II B4 SRAM Truth Table
DQ
Kn
LD
↑
1
↑
↑
R/W
Operation
A+1
A+2
A+3
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Deselect
0
0
D@Kn+1
D@Kn+1
D@Kn+2
D@Kn+2
Write
0
1
Q@Kn+1
or
Cn+1
Q@Kn+2
or
Cn+2
Q@Kn+2
or
Cn+2
Q@Kn+3
or
Cn+3
Read
De
sig
A+0
No
t
Re
co
m
me
nd
ed
for
Ne
w
Note:
Q is controlled by K clocks if C clocks are not used.
Rev: 1.07 8/2012
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
B4 Byte Write Clock Truth Table
BW
BW
BW
Current Operation
D
D
D
D
K↑
(tn+1)
(tn+1½)
K↑
K↑
(tn+2)
K↑
(tn+2½)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
T
T
T
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
BW
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.07 8/2012
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
B4 Nybble Write Clock Truth Table
NW
NW
NW
Current Operation
D
D
D
D
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+1½)
K↑
(tn+2)
K↑
(tn+2½)
T
T
T
T
Write
Dx stored if NWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if NWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
NW
Ne
w
x36 Byte Write Enable (BWn) Truth Table
De
sig
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
BW1
BW2
BW3
D0–D8
D9–D17
D18–D26
D27–D35
1
1
1
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
1
1
1
Data In
Don’t Care
Don’t Care
Don’t Care
1
0
1
1
Don’t Care
Data In
Don’t Care
Don’t Care
0
0
1
1
Data In
Data In
Don’t Care
Don’t Care
1
1
0
1
Don’t Care
Don’t Care
Data In
Don’t Care
0
1
0
1
Data In
Don’t Care
Data In
Don’t Care
1
0
0
0
1
1
0
1
1
0
0
0
1
Re
co
m
me
nd
ed
for
BW0
1
Don’t Care
Data In
Data In
Don’t Care
0
1
Data In
Data In
Data In
Don’t Care
1
0
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
Data In
Don’t Care
Don’t Care
Data In
1
0
Don’t Care
Data In
Don’t Care
Data In
1
0
Data In
Data In
Don’t Care
Data In
1
0
0
Don’t Care
Don’t Care
Data In
Data In
0
1
0
0
Data In
Don’t Care
Data In
Data In
1
0
0
0
Don’t Care
Data In
Data In
Data In
0
0
0
0
Data In
Data In
Data In
Data In
No
t
0
Rev: 1.07 8/2012
13/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
x18 Byte Write Enable (BWn) Truth Table
BW1
D0–D8
D9–D17
1
1
Don’t Care
Don’t Care
0
1
Data In
1
0
Don’t Care
0
0
Data In
NW1
D0–D3
1
1
Don’t Care
0
1
Data In
1
0
Don’t Care
0
0
Data In
Data In
Data In
D4–D7
Don’t Care
Don’t Care
Data In
Data In
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
NW0
Don’t Care
n—
Di
sco
nt
inu
ed
Pr
od
u
x8 Nybble Write Enable (NWn) Truth Table
ct
BW0
Rev: 1.07 8/2012
14/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
VREF
Voltage in VREF Pins
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
TJ
Maximum Junction Temperature
TSTG
Storage Temperature
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
+/–100
mA dc
+/–100
mA dc
o
125
C
oC
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
De
sig
Recommended Operating Conditions
Power Supplies
Supply Voltage
Min.
Typ.
Max.
Unit
VDD
1.7
1.8
1.9
V
VDDQ
1.4
—
1.9
V
0.68
—
0.95
V
me
nd
ed
for
I/O Supply Voltage
Reference Voltage
Symbol
Ne
w
Parameter
VREF
Re
co
m
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O)
and 1.7 V ≤ VDDQ ≤ 1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The
power down sequence must be the reverse. VDDQ must not exceed VDD..
Operating Temperature
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
TA
0
25
70
°C
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
No
t
Parameter
Rev: 1.07 8/2012
15/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
HSTL I/O DC Input Characteristics
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.10
VDD + 0.3 V
V
1
DC Input Logic Low
VIL (dc)
–0.3 V
VREF – 0.10
V
1
ct
Parameter
HSTL I/O AC Input Characteristics
Parameter
Symbol
AC Input Logic High
VIH (ac)
AC Input Logic Low
VIL (ac)
VREF Peak-to-Peak AC Voltage
VREF (ac)
n—
Di
sco
nt
inu
ed
Pr
od
u
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
Min
Max
Units
Notes
VREF + 0.20
—
V
2,3
—
VREF – 0.20
V
2,3
—
5% VREF (DC)
V
1
VIH
VSS
50%
VSS – 1.0 V
Capacitance
Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Re
co
m
20% tKHKH
me
nd
ed
for
Undershoot Measurement and Timing
Ne
w
De
sig
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Output Capacitance
COUT
VOUT = 0 V
6
7
pF
Clock Capacitance
CCLK
—
5
6
pF
No
t
Parameter
Note:
This parameter is sample tested.
Rev: 1.07 8/2012
16/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
AC Test Conditions
Conditions
Input high level
VDDQ
Input low level
0V
Max. input slew rate
2 V/ns
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
VDDQ/2
Input reference level
VDDQ/2
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
50Ω
Input and Output Leakage Characteristics
Symbol
Input Leakage Current
(except mode pins)
Min.
Max
IIL
VIN = 0 to VDD
–2 uA
2 uA
IINDOFF
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–2 uA
2 uA
2 uA
Output Disable,
VOUT = 0 to VDDQ
–2 uA
2 uA
me
nd
ed
for
Doff
IOL
No
t
Re
co
m
Output Leakage Current
Test Conditions
Ne
w
Parameter
De
sig
VT = VDDQ/2
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
Rev: 1.07 8/2012
17/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Symbol
Min.
Max.
Units
Notes
Output High Voltage
VOH1
VDDQ/2
VDDQ
V
1, 3
Output Low Voltage
VOL1
Vss
VDDQ/2
V
2, 3
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
VOL2
Vss
0.2
V
4, 6
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
Output High Voltage
Output Low Voltage
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Parameter
Symbol
Test Conditions
Operating Current (x36):
DDR
IDD
Operating Current (x9):
DDR
Standby Current (NOP):
DDR
Notes:
-200
-167
Notes
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
450 mA
460 mA
400 mA
410 mA
350 mA
360 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
400 mA
410 mA
350 mA
360 mA
300 mA
310 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
350 mA
360 mA
300 mA
310 mA
250 mA
260 mA
2, 3
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
350 mA
360 mA
300 mA
310 mA
250 mA
260 mA
2, 3
220 mA
230 mA
210 mA
220 mA
200 mA
210 mA
2, 4
Ne
w
–40
to
85°C
Re
co
m
Operating Current (x8):
DDR
-250
0
to
70°C
me
nd
ed
for
Operating Current (x18):
DDR
ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
No
t
1.
2.
3.
4.
De
sig
Operating Currents
Rev: 1.07 8/2012
18/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
-250
Symbol
-200
-167
Min
Max
Min
Max
8.4
5.0
8.4
0.2
—
—
Clock
tKHKH
tCHCH
4.0
tTKC Variable
tKCVar
—
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.6
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.6
K to K High
C to C High
tKHKH
tCHCH
1.8
K to K High
C to C High
tKHKH
tCHCH
1.8
K, K Clock High to C, C Clock High
tKHCH
0
DLL Lock Time
tKCLock
K Static to DLL reset
Max
Units
8.4
ns
0.2
—
0.2
ns
2.0
—
2.4
—
ns
—
2.0
—
2.4
—
ns
—
2.2
—
2.7
—
ns
—
2.2
—
2.7
—
ns
1.8
0
2.3
0
2.8
ns
1024
—
1024
—
1024
—
cycle
tKCReset
30
—
30
—
30
—
ns
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.5
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.5
—
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.5
ns
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.5
—
ns
tCQHQV
—
0.30
—
0.35
—
0.40
ns
8
tCQHQX
–0.30
—
–0.35
—
–0.40
—
ns
8
tCQHCQH
tCQHCQH
1.55
—
1.95
—
2.45
—
ns
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.5
ns
4
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.5
—
ns
4
Address Input Setup Time
tAVKH
0.5
—
0.6
—
0.7
—
ns
Control Input Setup Time (RW, LD)
tIVKH
0.5
—
0.6
—
0.7
—
ns
2
Control Input Setup Time (BWX, NWX)
tIVKH
0.5
—
0.6
—
0.7
—
ns
3
Data Input Setup Time
tDVKH
0.35
—
0.4
—
0.5
—
ns
CQ, CQ High Output Valid
CQ, CQ High Output Hold
CQ Phase Distortion
Re
co
m
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
me
nd
ed
for
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
Ne
w
Output Times
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
No
t
Setup Times
Rev: 1.07 8/2012
n—
Di
sco
nt
inu
ed
Pr
od
u
6.0
De
sig
K, K Clock Cycle Time
C, C Clock Cycle Time
Min
ct
Parameter
Notes
AC Electrical Characteristics
19/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6
7
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Parameter
-250
Symbol
-200
-167
Min
Max
Min
Max
Min
Max
Units
Notes
AC Electrical Characteristics (Continued)
Hold Times
tKHAX
0.5
—
0.6
—
0.7
—
ns
Control Input Hold Time (RW, LD)
tKHIX
0.5
—
0.6
—
0.7
—
ns
2
Control Input Hold Time (BWX, NWX)
tKHIX
0.5
—
0.6
—
0.7
—
ns
3
Data Input Hold Time
tKHDX
0.35
—
0.4
—
0.5
—
ns
1.
2.
3.
4.
5.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control signals are RW.
Control signals BW0, BW1, and NW0, NW1 for x8 and BW2, BW3 for x36
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
6.
7.
8.
n—
Di
sco
nt
inu
ed
Pr
od
u
Notes:
ct
Address Input Hold Time
Rev: 1.07 8/2012
20/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
Rev: 1.07 8/2012
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
21/34
CQ
CQ
DQ
C
C
BWx
R/W
LD
Address
K
No
t
K
A
KHIX
KHIX
KHKH
CHCQV
CHCQX
IVKH
IVKH
AVKH
KHAX
KHKH
KHKL
Cont Read A
KHKL
me
nd
ed
for
Re
co
m
Read A
CHCQV
CQHQV
A+2
A
CHCQX
B
Write B
CHQV
B
B+1
KHIX
DVKH
IVKH
Cont Write B
B+2
C
Read C
A+3
CQHQX
B
CHQZ
B+1
B+2
B+3
ct
B+3
KHDX
n—
Di
sco
nt
inu
ed
Pr
od
u
CHQX
A+1
KHnKH
De
sig
KHnKH
CHQX1
KLKH
Ne
w
KLKH
NOP
C and C Controlled Read First Timing Diagram
GS8342R08/09/18/36AE-250/200/167
© 2006, GSI Technology
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
K and K Controlled Read First Timing Diagram
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
GS8342R08/09/18/36AE-250/200/167
Rev: 1.07 8/2012
22/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
Rev: 1.07 8/2012
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
23/34
CQ
CQ
DQ
C
C
BWx
R/W
LD
A
KHAX
KHIX
AVKH
KHKH
Cont Write A
IVKH
A
A
DVKH
B
KHKL
Read B
A+1
A+2
KHDX
A+2
KLKH
KLKH
KHKL
A+3
KHnKH
KHnKH
Cont Read B
CHQX1
B+1
NOP
CHQV
C
B+3
Write C
CHQX
C
B
CQHQV
CQHQX
B+2
C
CHQZ
ct
C+1
C+1
Cont Write C
n—
Di
sco
nt
inu
ed
Pr
od
u
CHCQV
CHCQX
De
sig
A+3
KHIX
IVKH
Ne
w
A+1
KHKH
IVKH
KHIX
me
nd
ed
for
Re
co
m
K
Address
No
t
K
Write A
C and C Controlled Write First Timing Diagram
C+2
GS8342R08/09/18/36AE-250/200/167
© 2006, GSI Technology
Rev: 1.07 8/2012
A
KHAX
CQ
CQ
A
DQ
CHCQX
A
CHCQV
IVKH
KHIX
AVKH
KHKH
Cont Write A
DVKH
IVKH
A+1
A+1
KHIX
me
nd
ed
for
Re
co
m
BWx
R/W
LD
Address
K
No
t
K
Write A1
KHIX
IVKH
A+2
KHDX
A+2
KHnKH
A+3
CHCQV
CHCQX
KHQX1
B+1
NOP
KHQV
C
B+3
Write C
C
C+1
Cont Write C
B
CQHQV
CQHQX
B+2
KHQX
C
KHQZ
C+1
n—
Di
sco
nt
inu
ed
Pr
od
u
Cont Read B
De
sig
KLKH
A+3
Ne
w
B
KHKL
Read B
K and K Controlled Write First Timing Diagram
ct
C+2
C+2
GS8342R08/09/18/36AE-250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
24/34
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
JTAG Port Operation
ct
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
n—
Di
sco
nt
inu
ed
Pr
od
u
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
Test Data In
In
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
De
sig
TDI
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
me
nd
ed
for
JTAG Port Registers
Ne
w
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Re
co
m
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
No
t
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Rev: 1.07 8/2012
25/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
·
·
·
·
·
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
JTAG TAP Block Diagram
·
·
·
Boundary Scan Register
·
·
1
·
2 1 0
0
108
0
Bypass Register
Instruction Register
TDO
De
sig
TDI
ID Code Register
·
· ··
2 1 0
Ne
w
31 30 29
Control Signals
me
nd
ed
for
TMS
Test Access Port (TAP) Controller
TCK
Re
co
m
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Bit #
GSI Technology
JEDEC Vendor
ID Code
Not Used
Presence Register
No
t
ID Register Contents
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
1
X
Rev: 1.07 8/2012
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
26/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
0 1 1 0 1 1 0 0 1
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Tap Controller Instruction Set
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
De
sig
Shift DR
Ne
w
1
me
nd
ed
for
1
0
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
Capture IR
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
No
t
Re
co
m
1
Capture DR
0
1
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Rev: 1.07 8/2012
27/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
De
sig
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
Ne
w
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
me
nd
ed
for
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Re
co
m
JTAG TAP Instruction Set Summary
Instruction
Code
EXTEST
SAMPLE-Z
RFU
Rev: 1.07 8/2012
Notes
000
Places the Boundary Scan Register between TDI and TDO.
1
001
Preloads ID Register and places it between TDI and TDO.
1, 2
No
t
IDCODE
Description
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z except CQ.
1
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
28/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
JTAG TAP Instruction Set Summary
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
SAMPLE/
PRELOAD
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Test Port Input Low Voltage
Test Port Input High Voltage
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output CMOS Low
Ne
w
Test Port Output Low Voltage
Test Port Output CMOS High
Min.
Max.
Unit
Notes
VILJ
–0.3
0.3 * VDD
V
1
VIHJ
0.6 * VDD
VDD +0.3
V
1
IINHJ
–300
1
uA
2
IINLJ
–1
100
uA
3
IOLJ
–1
1
uA
4
VOHJ
VDD – 200 mV
—
V
5, 6
VOLJ
—
0.4
V
5, 7
VOHJC
VDD – 100 mV
—
V
5, 8
VOLJC
—
100 mV
V
5, 9
De
sig
TMS, TCK and TDI Input Leakage Current
Symbol
No
t
Re
co
m
me
nd
ed
for
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Rev: 1.07 8/2012
29/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
JTAG Port AC Test Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDD/2
JTAG Port AC Test Load
TDO
ct
Conditions
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
50Ω
30pF*
VDD/2
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port Timing Diagram
tTKC
tTKH
TCK
TDI
De
sig
tTH
tTS
tTKL
tTH
TMS
tTKQ
me
nd
ed
for
TDO
Ne
w
tTS
tTH
tTS
Parallel SRAM input
Parameter
Re
co
m
JTAG Port AC Electrical Characteristics
Symbol
Min
Max
Unit
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
No
t
TCK Cycle Time
Rev: 1.07 8/2012
30/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
ct
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
14.0
1.0
10.0
15±0.05
0.20(4x)
No
t
Re
co
m
C
1.0
0.36~0.46
1.50 MAX.
SEATING PLANE
B
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
me
nd
ed
for
0.15 C
Ne
w
A
De
sig
17±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
11 10 9 8 7 6 5 4 3 2 1
Rev: 1.07 8/2012
31/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaDDR-II SRAM
Part Number1
Type
Package
Speed (MHz)
TA2
4M x 8
GS8342R08AE-250
SigmaDDR-II B4 SRAM
165-Pin BGA
250
C
4M x 8
GS8342R08AE-200
SigmaDDR-II B4 SRAM
165-Pin BGA
200
C
4M x 8
GS8342R08AE-167
SigmaDDR-II B4 SRAM
165-Pin BGA
167
C
4M x 8
GS8342R08AE-250I
SigmaDDR-II B4 SRAM
165-Pin BGA
250
I
4M x 8
GS8342R08AE-200I
SigmaDDR-II B4 SRAM
165-Pin BGA
200
I
4M x 8
GS8342R08AE-167I
SigmaDDR-II B4 SRAM
165-Pin BGA
167
I
4M x 9
GS8342R09AE-250
SigmaDDR-II B4 SRAM
165-Pin BGA
250
C
4M x 9
GS8342R09AE-200
SigmaDDR-II B4 SRAM
165-Pin BGA
200
C
4M x 9
GS8342R09AE-167
SigmaDDR-II B4 SRAM
165-Pin BGA
167
C
4M x 9
GS8342R09AE-250I
SigmaDDR-II B4 SRAM
165-Pin BGA
250
I
4M x 9
GS8342R09AE-200I
SigmaDDR-II B4 SRAM
165-Pin BGA
200
I
4M x 9
GS8342R09AE-167I
SigmaDDR-II B4 SRAM
165-Pin BGA
167
I
2M x 18
GS8342R18AE-250
SigmaDDR-II B4 SRAM
165-Pin BGA
250
C
2M x 18
GS8342R18AE-200
SigmaDDR-II B4 SRAM
165-Pin BGA
200
C
2M x 18
GS8342R18AE-167
SigmaDDR-II B4 SRAM
165-Pin BGA
167
C
2M x 18
GS8342R18AE-250I
SigmaDDR-II B4 SRAM
165-Pin BGA
250
I
2M x 18
GS8342R18AE-200I
SigmaDDR-II B4 SRAM
165-Pin BGA
200
I
2M x 18
GS8342R18AE-167I
SigmaDDR-II B4 SRAM
165-Pin BGA
167
I
1M x 36
GS8342R36AE-250
SigmaDDR-II B4 SRAM
165-Pin BGA
250
C
1M x 36
GS8342R36AE-200
SigmaDDR-II B4 SRAM
165-Pin BGA
200
C
1M x 36
GS8342R36AE-167
SigmaDDR-II B4 SRAM
165-Pin BGA
167
C
1M x 36
GS8342R36AE-250I
SigmaDDR-II B4 SRAM
165-Pin BGA
250
I
1M x 36
GS8342R36AE-200I
SigmaDDR-II B4 SRAM
165-Pin BGA
200
I
1M x 36
GS8342R36AE-167I
SigmaDDR-II B4 SRAM
165-Pin BGA
167
I
4M x 8
GS8342R08AGE-250
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
C
4M x 8
GS8342R08AGE-200
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
C
4M x 8
GS8342R08AGE-167
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
C
4M x 8
GS8342R08AGE-250I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
I
4M x 8
GS8342R08AGE-200I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
I
GS8342R08AGE-167I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
I
GS8342R09AGE-250
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
C
GS8342R09AGE-200
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
C
4M x 9
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Ne
w
me
nd
ed
for
Re
co
m
No
t
4M x 8
4M x 9
ct
Org
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8342R36AE-200T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.07 8/2012
32/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Ordering Information—GSI SigmaDDR-II SRAM
Part Number1
Type
Package
Speed (MHz)
TA2
4M x 9
GS8342R09AGE-167
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
C
4M x 9
GS8342R09AGE-250I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
I
4M x 9
GS8342R09AGE-200I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
I
4M x 9
GS8342R09AGE-167I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
I
2M x 18
GS8342R18AGE-250
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
C
2M x 18
GS8342R18AGE-200
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
C
2M x 18
GS8342R18AGE-167
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
C
2M x 18
GS8342R18AGE-250I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
I
2M x 18
GS8342R18AGE-200I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
I
2M x 18
GS8342R18AGE-167I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
I
1M x 36
GS8342R36AGE-250
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
C
1M x 36
GS8342R36AGE-200
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
C
1M x 36
GS8342R36AGE-167
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
C
1M x 36
GS8342R36AGE-250I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
250
I
1M x 36
GS8342R36AGE-200I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
200
I
1M x 36
GS8342R36AGE-167I
SigmaDDR-II B4 SRAM
RoHS-compliant 165-Pin BGA
167
I
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Org
No
t
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co
m
me
nd
ed
for
Ne
w
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8342R36AE-200T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.07 8/2012
33/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology
GS8342R08/09/18/36AE-250/200/167
Revision History
Types of Changes
Format or Content
Revisions
Content
GS8342RxxA_r1_01; GS8342RxxA_r1_02
Content
GS8342RxxA_r1_02; GS8342RxxA_r1_03
Content
GS8342RxxA_r1_03; GS8342RxxA_r1_04
Content
GS8342RxxA_r1_04;
GS8342RxxA_r1_05
Content
• Updated MAX tKHKH
• (Rev. 1.01a: Updated Note 4 in HSTL Output Driver DC Electrical Characteristics table)
• Updated tKHKH, tKHCH in AC Char table
• Added tKHKH and CQ Phase Distortion to AC Char table
• Added Power-up sequence section
• Added CZ operating current numbers
• Changed status to PQ
• Added VREF note to Pin Description table
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status
• Revised AC Characteristics Table
• Revised Four Bank Depth Expansion Schematic(pg. 10)
• Updated JTAG Port AC Test Conditions (pg. 31)
• Updated 165 BGA package drawing (pg. 33)
• (Rev1.06a: Editorial updates)
GS8342RxxA_r1_05;
GS8342RxxA_r1_06
Content
GS8342RxxA_r1_06;
GS8342RxxA_r1_07
Ne
w
De
sig
GS8342RxxA_r1; GS8342RxxA_r1_01
n—
Di
sco
nt
inu
ed
Pr
od
u
• Creation of new datasheet
GS8342RxxA_r1
ct
Rev. Code: Old; New
• Removed 333 & 300 MHz bins
No
t
Re
co
m
me
nd
ed
for
Content
Rev: 1.07 8/2012
34/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology