DM9161CI - Davicom Semiconductor Inc.

DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DAVICOM Semiconductor, Inc.
DM9161CI
Industrial-Temperature 10/100 Mbps Fast Ethernet
Physical Layer Single Chip Transceiver
DATA SHEET
Final
Version: DM9161CI-DS-F01
February 22, 2012
1
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Content
1. GENERAL DESCRIPTION.................................................................................................................................................................. 4
2. FEATURES ............................................................................................................................................................................................ 4
3. BLOCK DIAGRAM ............................................................................................................................................................................... 5
4. PIN CONFIGURATION: ....................................................................................................................................................................... 6
4.1 48-PIN LQFP...................................................................................................................................................................................... 6
5. PIN DESCRIPTION............................................................................................................................................................................... 7
5.1 NORMAL MII INTERFACE .................................................................................................................................................................... 7
5.2 MEDIA INTERFACE .............................................................................................................................................................................. 9
5.3 LED INTERFACE ................................................................................................................................................................................. 9
5.4 MODE.................................................................................................................................................................................................. 9
5.5 BIAS AND CLOCK ..............................................................................................................................................................................12
5.6 POWER .............................................................................................................................................................................................12
5.7 TABLE A (MEDIA TYPE SELECTION)..................................................................................................................................................12
5.8 PIN MAPS OF NORMAL MII, REDUCED MII, AND 10BASE-T GPSI (7-WIRED) MODE.....................................................................12
6. LED CONFIGURATION.....................................................................................................................................................................14
6.1 LED FUNCTION DESCRIPTION .........................................................................................................................................................15
7. FUNCTIONAL DESCRIPTION .........................................................................................................................................................16
7.1 MII INTERFACE..................................................................................................................................................................................16
7.2 100BASE-TX OPERATION................................................................................................................................................................18
8. MII REGISTER DESCRIPTION.........................................................................................................................................................25
8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00............................................................................................................................26
8.2 BASIC MODE STATUS REGISTER (BMSR) - 01...............................................................................................................................27
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02...........................................................................................................................28
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03...........................................................................................................................28
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04......................................................................................................29
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05.......................................................................................30
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) - 06 ..............................................................................................................31
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16..................................................................................................31
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17 .........................................................................33
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18..............................................................................................................34
8.12 (SPECIFIED CONFIG) REGISTER – 20 .............................................................................................................................................35
8.13 DAVICOM SPECIFIED INTERRUPT REGISTER – 21......................................................................................................................36
8.14 DAVICOM SPECIFIED RECEIVE ERROR COUNTER REGISTER (RECR) – 22.............................................................................36
8.15 DAVICOM SPECIFIED DISCONNECT COUNTER REGISTER (DISCR) – 23..................................................................................37
8.16 DAVICOM HARDWARE RESET LATCH STATE REGISTER (RLSR) – 24......................................................................................38
8.17 POWER SAVING CONTROL REGISTER (PSCR) – 29 ....................................................................................................................38
9. DC AND AC ELECTRICAL CHARACTERISTICS .......................................................................................................................39
9.1 ABSOLUTE MAXIMUM RATINGS (25°C)............................................................................................................................................39
9.2 OPERATING CONDITIONS .................................................................................................................................................................39
9.3 DC ELECTRICAL CHARACTERISTICS (DVDD = 3.3V) .....................................................................................................................40
2
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4 AC ELECTRICAL CHARACTERISTICS & TIMING WAVEFORMS ..........................................................................................................40
10. PACKAGE INFORMATION............................................................................................................................................................48
11. ORDER INFORMATION..................................................................................................................................................................49
3
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1. General Description
DAVICOM’s DM9161CI is a industrial-temperature
physical layer, low power, and single-chip 10BASET/100BASE-TX transceiver specifically designed for
consumer electronics, industrial, and enterprise applications.
Through using a CMOS process, the DM9161CI has
the advantage of ensuring both high performance
and savings in power consumption.
Through utilization of automatic media speed and
protocol selection, the auto-negotiation function is
strongly supported in the DM9161CI. Then due to the
built-in wave shaping filter, the DM9161CI has a
significant convenience of not requiring an external
filter to transport signals to the media in 10BASE-T or
100BASE-TX during Ethernet operation.
Through its Media Independent Interface (MII), the
DM9161CI not only connects the Medium Access
Control (MAC) layer but also ensure a high interoperability and flexibility for our different vendors. In
media usage applications, the DM9161CI provides a
direct interface either to an Unshielded Twisted Pair
Category 5 Cable (UTP5) for 100BASE-TX Fast
Ethernet, or an UTP5/UTP3 Cable for 10BASE-T
Ethernet. The DM9161CI contains the entire physical
layer functions of 100BASE-TX. Those physical layer
functions are defined by IEEE802.3u include the
Physical Coding Sub layer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium
Dependent Sub layer (TP-PMD), 10BASE-TX
Encoder/Decoder (ENC/DEC), and Twisted Pair
Media Access Unit (TPMAU).
2. Features

Fully complies with IEEE 802.3 / IEEE 802.3u 10Base-

T/ 100Base-TX, ANSI X3T12 TP-PMD 1995
and Full-duplex/Collision. Support Dual-
standards
LED optional control
Support HP MDI/MDI-X auto crossover function

Single low power Supply of 3.3V with an advanced
(HP Auto-MDIX)
CMOS technology, Built in 3.3V to 1.8V
Support Auto-Negotiation function, compliant with
regulator
IEEE 802.3u

Lower Power consumption modes:
Fully integrated Physical layer transceiver On-chip

Power Reduced mode (cable detection)
filtering with direct interface to magnetic transformer

Power Down mode
Selectable repeater or node mode

Supports industrial-temperature (-40℃ ~ +85℃)
Selectable MII or RMII (Reduced MII) mode for

Selectable TX drivers for 1:1 or 1.25:1 transformers for
100Base-TX and 10Base-TX. Selectable MII or
additional power reduction . 1.25: 1 transformers only
GPSI (7-Wired) mode for 10Base-T
when HP Auto-MDIX Disable.
Selectable full-duplex or half-duplex

operation

LED status outputs indicate Link/ Activity, Speed10/100
DM9161CIE pin to pin Compatible with DM9161AE /

MII management interface with mask-able interrupt
output capability

Provide Loopback mode for
Compatible with 3.3V and 5.0V tolerant I/Os
DM9161BE

DSP architecture PHY Transceiver.

48-pin LQFP - 0.18um process
easy system diagnostics
4
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
3. Block Diagram
4B/5B
Encoder
Scrambler
25M OSCI
LED1-4#
TX CGM
LED
Driver
NRZ
to
NRZI
Parallel
to Serial
NRZI to
MLT-3
MLT-3
Driver
Rise/Fall
Time
CTL
100TXD+/-
AutoMDIX
25M CLK
125M CLK
MII
Signals
MII
Interface/
Control
4B/5B
Decoder
Codegroup
Alignment
Descrambler
Serial to
Parallel
NRZI
to
NRZ
MLT-3 to
NRZI
Adaptive
EQ
RXI+/-
RX
RXI+/-
TX
10TXD+/-
RX
CRM
Digital
Logic
10BASE-T
Module
Register
5
Collision
Detection
Carrier
Sense
AutoNegotiation
Final
Version: DM9161CIIII-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
4. Pin Configuration:
6
RXD[1]/PHYAD[1]
RXD[2]/PHYAD[2]
RXD[3]/PHYAD[3]
MDIO
28
26
25
27
RXD[0]/PHYAD[0]
29
MDINTR#
32
LEDMODE
DGND
33
DVDD33
RXCLK/10BTSER
34
30
CRS/PHYAD[4]
35
31
COL/RMII
36
4.1 48-pin LQFP
RXDV/TESTMODE
37
24
RXER/RXD[4]/RPTR
38
23
DVDD33
DISMDIX
39
22
TXCLK/ISOLATE
RESET#
40
21
TXEN
VDD33
XT2
41
20
TXD[0]
19
TXD[1]
XT1
43
18
TXD[2]
DGND
44
17
TXD[3]
42
DM9161CIEP
MDC
5
6
7
8
9
10
11
12
AGND
TX+
TX-
AVDD18
PWRDWN
LED0/OP0
LED1/OP1
LED2/OP2
AGND
CABLESTS/LINKSTS
13
4
14
48
3
47
BGRES
RX-
BGRESG
RX+
DGND
AVDD18
TXER/TXD[4]
15
2
16
46
1
45
AVDD18
NC
AGND
Final
Version: DM9161CIIII-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5. Pin Description
I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled high D: Pulled low
5.1 Normal MII Interface
Pin No.
Pin Name
16
TXER/TXD [4]
I/O
Description
I Transmit Error/The Fifth TXD Data Bit
In 100Mbps mode, when the signal indicates active high and TXEN is
active, the HALT symbol substitutes the actual data nibble.
In 10Mbps, the input is ignored
In bypass mode (bypass BP4B5B), TXER becomes the TXD [4] pin, the
fifth TXD data bit of the 5B symbol
I Transmit Data
4-bit nibble data inputs (synchronous to the TXCLK) when in
10/100Mbps nibble mode.
In 10Mbps GPSI (7-Wired) mode, the TXD [0] pin is used as the serial
data input pin, and TXD [1:3] are ignored.
20,19,18,17
TXD [0:3]
21
TXEN
I
22
TXCLK/
ISOLATE
O,
Z,
LI
(D)
24
MDC
I
25
MDIO
I/O
29,28,27,26
RXD[0:3]
/PHYAD[0:3]
O,
Z,
LI
(D)
32
MDINTR
IO,
LI
(D)
7
Transmit Enable
Active high indicates the presence of valid nibble data on the TXD [0:3]
for both 100Mbps and 10Mbps nibble modes.
In 10Mbps GPSI (7-Wired) mode, active high indicates the presence of
valid 10Mbps data on TXD [0].
Transmit Clock
The transmitting clock provides the timing reference for the transfer of
the TXEN, TXD, and TXER. TXCLK is provided by the PHY
25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode,
10MHz in 10Mbps GPSI (7-Wired) mode
ISOLATE Setting: (When power up reset, latch input)
0: Reg 0.10 will be initialized to “0”. (Ref.to 8.1 Basic Control Register)
1: Reg 0.10 will be initialized to “1”.
Management Data Clock
Synchronous clock for the MDIO management data. This clock is
provided by management entity, and it is up to 12.5MHz
Management Data I/O
Bi-directional management data which may be provided by the station
management entity or the PHY
Receive Data Output
4-bit nibble data outputs (synchronous to RXCLK) when in 10/100Mbps
MII mode
In 10Mbps GPSI (7-Wired) mode, the RXD [0] pin is used as the serial
data output pin, and the RXD [1:3] are ignored
PHY address [0:3] (power up reset latch input)
PHY address sensing input pins
Status Interrupt Output:
Whenever there is a status change (link, speed, duplex depend on
interrupt register [21] )
The interrupt output assert low when pull up.
Asserted high when pull down.
Final
Version: DM9161CIIII-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8
34
RXCLK
/10BTSER
O,
Z,
LI
(U)
35
CRS
/PHYAD[4]
O,
Z,
LI
(D)
36
COL
/RMII
O,
Z,
LI
(D)
37
RXDV
/TESTMODE
O,
Z,
LI
(D)
38
RXER/RXD[4]
/RPTR
O,
Z,
LI
(D)
31
LEDMODE
I
40
RESET#
I
Receive Clock
The received clock provides the timing reference for the transfer of the
RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may
recover the RXCLK reference from the received data or it may derive the
RXCLK reference from a nominal clock
25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in
10Mbps GPSI (7-Wired) mode
10BTSER only support for 10M mode; (power up reset latch input)
0 = GPSI (7-Wired) mode in 10M mode
1 = MII mode in 100M mode
Carrier Sense Detect/ PHYAD[4]
Asserted high to indicate the presence of carrier due to receive or
transmit activities in half-duplex mode of 10BASE-T or 100BASE-TX. In
repeater mode or full-duplex mode, this signal is asserted high to indicate
the presence of carrier due to receive activity only
This pin is also used as PHYAD [4] (power up reset latch input)
PHY address sensing input pin
Collision Detection
Asserted high to indicate the detection of the collision conditions in halfduplex mode of 10Mbps and 100Mbps. In full-duplex mode, this signal is
always logical 0
Reduced MII enable:
This pin is also used to select Normal MII or Reduced MII. (power up
reset latch input)
0= Normal MII (default)
1= Reduced MII
This pin is always pulled low except used as reduced MII
Receive Data Valid
Asserted high to indicate that the valid data is presented on the RXD [0:3]
Test mode control pin (power up reset latch input)
0 = normal operation (default)
1 = enable test mode
Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol
Asserted high to indicate that an invalid symbol has been detected
In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the
fifth RXD data bit of the 5B symbol
This pin is also used to select Repeater or Node mode. (power up reset
latch input)
0 = Node Mode (default)
1 = Repeater Mode
LED MODE Select
Reference LED function description
0: support Dual-LED
1: Normal LED
Reset
Active low input that initializes the DM9161CI.
Final
Version: DM9161CIIII-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.2 Media Interface
Pin No.
Pin Name
3,4
RX+
RX7,8
TX+
TX5.3 LED Interface
Pin No.
11
12
LED1
/OP1
13
LED2
/OP2
5.4 Mode
Pin No.
10
9
Pin Name
LED0
/OP0
Pin Name
PWRDWN
14
CABLESTS
/LINKSTS
39
DISMDIX
45
NC
I/O
Description
I/O Differential Receive Pair
Differential data is received from the media
I/O Differential Transmit Pair/PECL Transmit Pair
Differential data is transmitted to the media in TP mode
PECL data is transmitted to the media in Fiber mode
I/O
Description
O, LED Driver output 0
LI OP0: (power up reset latch input)
(U) This pin is used to control the forced or advertised operating mode of the
DM9161CI according to the Table A. The value is latched into the
DM9161CI registers at power-up/reset
O,
LI LED Driver output 1
(U) OP1: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of
the DM9161CI according to the Table A. The value is latched into the
DM9161CI registers at power-up/reset
O, LED Driver output 2
LI OP2: (power up reset latch input)
(U) This pin is used to control the forced or advertised operating mode of the
DM9161CI according to the Table A. The value is latched into the
DM9161CI registers at power-up/reset
I/O
Description
I Power Down Control
Asserted high to force the DM9161CI into power down mode. When in
power down mode, most of the DM9161CI circuit block’s power is
turned off, only the MII management interface (MDC, MDIO) logic is
available (the PHY should respond to management transactions and
should not generate spurious signals on the MII)). To leave power down
mode, the DM9161CI needs the hardware or software reset with the
PWRDWN pin low
O, Cable Status or Link Status
LI This pin is used to indicate the status of the cable connection when
(D) power up reset latch low (Default)
0 = Without cable connection
1 = With cable connection
This pin is used to indicate the status of the Link connection when
power up reset latch high
0 = With link
1 = Without link
I HP Auto-MDIX Control
(D) 1: Disable auto mode
0: Enable HP Auto-MDIX mode
- Not connect
Final
Version: DM9161CIIII-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.5 Bias and Clock
Pin No.
Pin Name
47
BGRESG
48
BGRES
42
XT2
43
XT1
I/O
P
O
I/O
I
Description
Band gap Ground
Band gap Voltage Reference Resistor 6.8K ohm +/- 1%
Crystal Output; REF_CLK input for RMII mode
Crystal Input
5.6 Power
Pin No.
1,2,9
5
6
46
23,30
41
15,33,44
I/O
P
P
P
P
P
P
P
Description
Analog 1.8V Regulator Power output
Analog Receive Ground
Analog Transmit Ground
Analog Substrate Ground
Digital Power
Digital Power for Crystal
Digital Ground
Pin Name
AVDD18
AGND
AGND
AGND
DVDD33
VDD33
DGND
5.7 Table a (Media Type Selection)
OP2
OP1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
OP0
Function
0
1
0
1
0
1
0
1
Dual Speed 100/10 HDX
Reserved
Reserved
Manually Select 10TX HDX
Manually Select 10TX FDX
Manually Select 100TX HDX
Manually Select 100TX FDX
Auto-negotiation Enables All Capabilities
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode
Normal MII Mode
Reduced MII Mode
10Base-T GPSI (7-Wired) Mode
TXD [0:1]
TXD [0:1]
TXD [0] ; TXD [1] = NC
TXD [2:3]
NC
NC
TXEN
TXEN
TXEN
TXER/TXD [4]
NC
NC
TXCLK
NC
TXCLK
RXD [0:1]
RXD [0:1]
RXD [0] ; RXD [1] = NC
RXD[2:3]
NC
NC
RXER/RXD[4]/RPTR/NODE
RPTR/NODE
RPTR/NODE
RXDV
CRS DV
NC
RXCLK
NC
RXCLK
12
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
COL
NC
COL
CRS
(PHYADR [4])
(BP4B5B)
NC
CRS
MDC
MDC
MDC
MDIO
MDIO
MDIO
RESET#
RESET#
RESET#
XT1 (25 MHz)
XT1 or XT2 (REF_CLK 50MHz)
XT1 (25 MHz)
13
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
6. LED Configuration
LEDs flash once per 500ms after power-on reset or
software reset by writing PHY register. All LED pins
are dual function pins, which can be configured as
either active high or low by pulling them low or high
accordingly. If the pin is pulled high, the LED is
active low after reset. Likewise, if the pin is pulled
low, the
14
LED is active high. LEDs flash once per 500ms after
power-on reset or software reset by writing PHY
register. All LED pins are dual function pins, which
can be configured as either active high or low by
pulling them low or high accordingly. If the pin is
pulled high, the LED is active low after reset.
Likewise, if the pin is pulled low, the
LED is active high.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
6.1 LED Function Description
Normal LED mode
Name
Pin
LED0
11
LED1
12
CABLESTS / LINKSTS
Name
Pin
LED2
13
CABLESTS
14
/ LINKSTS
* Pin 31 = LEDMODE
LED_MODE = 1
Lo
Hi
FDX
HDX
SPEED: 100M
SPEED: 10M
Pull Down
Lo
Hi
Link
Link Fail
Flashing (HiLo) Active
Without Cable
With Cable connection
connection
Lo
FDX
SPEED: 100M
Hi
HDX
SPEED: 10M
Pull Up
Lo
Hi
N/A
Flashing (HiLo) Active
With Link
Without Link
For Dual-LED.
Name
Pin
LED0
11
LED1
12
CABLESTS / LINKSTS
Name
Pin
LED2
13
CABLESTS
14
/ LINKSTS
* Pin 31 = LEDMODE
Link Fail
Lo
Lo
Lo
LED_MODE = 0
LINK Mode
SPEED: 100M
Link OK
Active
Lo
Flashing (LoHi)
Hi
Pull Down
Hi
FDX
HDX
Without Cable
connection
With Cable connection
SPEED: 10M
Link OK
Active
HI
Flashing (HiLo)
Lo
Pull Up
Lo
Hi
HDX
FDX
Flashing (LoHi)
Collision
With Link
Without Link
6.1.1 Dual-LED application circuit
PAD
PAD
15
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7. Functional Description
The DM9161CI Fast Ethernet single chip transceiver,
providing the functionality as specified in IEEE 802.3u,
integrates a complete 100Base-TX module and a complete
10Base-T module. The DM9161CI provides a Media
Independent Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
The DM9161CI performs all PCS (Physical Coding Sub
layer), PMA (Physical Media Access), TP-PMD (Twisted
Pair Physical Medium Dependent) sub layer, 10Base-T
Encoder/Decoder, and Twisted Pair Media Access Unit
(TPMAU) functions. Figure 7-1 shows the major functional
blocks implemented in the DM9161CI.
100Base-TX
100Base-TX
Transmitter
Transmitter
100Base-TX
100Base-TX
Receiver
Receiver
10Base-T
10Base-T
Tranceiver
Tranceiver
MII Interface
MII Interface
Carrier
Carrier
Sense
Sense
Collision
Collision
Detection
Detection
MII Serial
MII Serial
Management
Management
Interface
Interface
Auto
Auto
Negotiation
Negotiation
Auto MDIX
Auto MDIX
Figure 7-1
7.1 MII Interface
The DM9161C provides a Media Independent Interface (MII)
as defined in the IEEE 802.3u standard (Clause 22).
The purpose of the MII interface is to provide a simple, easy
to implement connection between the MAC Reconciliation
layer and the PHY. The MII is designed to make the
differences between various media transparent to the MAC
sub layer.
The MII consists of a nibble wide receive data bus, a nibble
wide transmit data bus, and control signals to facilitate data
transfers between the PHY and the Reconciliation layer.
•
16
TXD (transmit data) is a nibble (4 bits) of data that are
driven by the reconciliation sub layer synchronously
with respect to TXCLK. For each TXCLK period, which
TXEN is asserted, TXD (3:0) are accepted for
transmission by the PHY.
•
TXCLK (transmit clock) output to the MAC reconciliation
sub layer is a continuous clock that provides the timing
reference for the transfer of the TXEN, TXD, and TXER
signals.
•
TXEN (transmit enable) input from the MAC
reconciliation sub layer indicates that nibbles are being
presented on the MII for transmission on the physical
medium.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
•
RXDV (receive data valid) input from the PHY indicates
that the PHY is presenting recovered and decoded
nibbles to the MAC reconciliation sub layer. To interpret
a receive frame correctly by the reconciliation sub layer,
RXDV must encompass the frame, starting no later
than the Start-of-Frame delimiter and excluding any
End-Stream delimiter.
•
RXER (receive error) transitions are synchronously with
respect to RXCLK. RXER will be asserted for 1 or more
clock periods to indicate to the reconciliation sub layer
that an error was detected somewhere in the frame
being transmitted from the PHY to the reconciliation sub
layer.
•
CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle, and
de-asserted by the PHY when the transmit and receive
medium are idle. Figure 7-2 depicts the behavior of
CRS during 10Base-T and 100Base-TX transmission.
MII Interface (continued)
•
TXER (transmit coding error) transitions are
synchronously with respect to TXCLK. If TXER is
asserted for one or more clock periods, and TXEN is
asserted, the PHY will emit one or more symbols that
are not part of the valid data delimiter set somewhere in
the frame being transmitted.
•
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sub layer synchronously
with respect to RXCLK. For each RXCLK period which
RXDV is asserted, RXD (3:0) are transferred from the
PHY to the MAC reconciliation sub layer.
•
RXCLK (receive clock) output to the MAC reconciliation
sub layer is a continuous clock that provides the timing
reference for the transfer of the RXDV, RXD, and
RXER signals.
TXD
IDLE
SSD
J/K
Preamble
CRS
ESD
T/R
IDLE
100Base-TX
CRS
TXD
Data
SFD
Preamble
Data
SFD
EFD
10Base-T
Figure 7-2
17
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
These two busses include various controls and signal
indications that facilitate data transfers between the
DM9161CI and the Reconciliation layer.
7.2 100Base-TX Operation
The 100Base-TX transmitter receives 4-bit nibble data
clocked in at 25MHz at the MII, and outputs a scrambled
5-bit encoded MLT-3 signal to the media at 100Mbps. The
on-chip clock circuit converts the 25MHz clock into a
125MHz clock for internal use.
7.2.1 100Base-TX Transmit
The 100Base-TX transmitter consists of the functional
blocks shown in figure 7-3. The 100Base-TX transmit
section converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125, a million symbols per
second serial data stream.
The IEEE 802.3u specification defines the Media
Independent Interface. The interface specification defines
a dedicated receive data bus and a dedicated transmit
data bus.
25M OSCI
LED1-4#
LED
Driver
TX CGM
4B/5B
Encoder
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
100TXD+/-
Rise/Fall
Time
CTL
AutoMDIX
25M CLK
125M CLK
MII
Signals
MII
Interface/
Control
4B/5B
Decoder
Codegroup
Alignment
Descrambler
Serial to
Parallel
NRZI
to
NRZ
MLT-3 to
NRZI
Adaptive
EQ
RXI+/-
RX
RXI+/-
TX
10TXD+/-
RX
CRM
Digital
Logic
10BASE-T
Module
Register
Collision
Detection
Carrier
Sense
AutoNegotiation
Figure 7-3
18
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
The block diagram in figure 7-3 provides an overview of the
functional blocks contained in the transmit section.
The transmitter section contains the following functional
blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Encoder
- NRZI to MLT-3
- MLT-3 Driver
7.2.1.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a 5-bit (5B)
code group for transmission, see reference Table 7-1. This
conversion is required for control and packet data to be
combined in code groups. The 4B5B encoder substitutes
the first 8 bits of the MAC preamble with a J/K code group
pair (11000 10001) upon transmit. The 4B5B encoder
continues to replace subsequent 4B preamble and data
nibbles with corresponding 5B code-groups. At the end of
the transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the 4B5B
encoder injects the T/R code group pair (01101 00111)
indicating end of frame. After the T/R code group pair, the
4B5B encoder continuously injects IDLEs into the transmit
data stream until Transmit Enable is asserted and the next
transmit packet is detected.
The DM9161CI includes a Bypass 4B5B conversion option
within the 100Base-TX Transmitter for support of
applications like 100 Mbps repeaters, which do not require
4B5B conversion.
7.2.1.2 Scrambler
The scrambler is required to control the radiated emissions
(EMI) by spreading the transmit energy across the
frequency spectrum at the media connector and on the
twisted pair cable in 100Base-TX operation.
19
By scrambling the data, the total energy presented to the
cable is randomly distributed over a wide frequency range.
Without the scrambler, energy levels on the cable could
peak beyond FCC limitations at frequencies related to
repeated 5B sequences like continuous transmission of
IDLE symbols. The scrambler output is combined with the
NRZ 5B data from the code group encoder via an XOR
logic function. The result is a scrambled data stream with
sufficient randomization to decrease radiated emissions at
critical frequencies.
7.2.1.3 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI encoder block
7.2.1.4 NRZ to NRZI Encoder
Since the transmit data stream has been scrambled and
serialized, the data must be NRZI encoded for compatibility
with the TP-PMD standard for 100Base-TX transmission
over Category-5 unshielded twisted pair cable.
7.2.1.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting the
data stream output from the NRZI encoder into two binary
data streams with alternately phased logic one events.
7.2.1.6 MLT-3 Driver
The two binary data streams, created at the MLT-3
converter, are fed to the twisted pair output driver, which
converts these streams to current sources and alternately
drives either side of the transmit transformer’s primary
winding, resulting in a minimal current MLT-3 signal. Refer to
figure 7-4 for the block diagram of the MLT-3 converter.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2.1.7 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 7-1
20
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
D
Q
CK
Binary
In
Q
.
.
Binary plus
Common
driver
MLT-3
Binary minus
Binary
In
MLT-3
Figure 7-4
7.2.2 100Base-TX Receiver
7.2.2.2 Adaptive Equalizer
The 100Base-TX receiver contains several function blocks
that convert the scrambled 125Mb/s serial data to
synchronous 4-bit nibble data, which is then provided to the
MII.
The receive section contains the following functional blocks:
When transmitting data at high speeds over copper twisted
pair cable, attenuation based on frequency becomes a
concern. In high speed twisted pair signaling, the frequency
content of the transmitted signal can vary greatly during
normal operation based on the randomness of the
scrambled data stream. This variation in signal attenuation
caused by frequency variations must be compensated for to
ensure the integrity of the received data. In order to ensure
quality transmission when employing MLT-3 encoding, the
compensation must be able to adapt to various cable
lengths and cable types depending on the installed
environment. The selection of long cable lengths for a given
implementation requires significant compensation, which will
be over-kill in a situation that includes shorter, less
attenuating cable lengths. Conversely, the selection of short
or intermediate cable lengths requiring less compensation
will cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to ensure proper conditioning of the received
signal independent of the cable length.
- Signal Detect
- Adaptive Equalizer
- MLT-3 to NRZI Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
7.2.2.1 Signal Detect
The signal detects function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
Standards for both voltage thresholds and timing
parameters.
7.2.2.3 MLT-3 to NRZI Decoder
The DM9161CI decodes the MLT-3 information from the
Digital Adaptive Equalizer into NRZI data. The relation
between NRZI and MLT-3 data is shown in figure 7-4.
7.2.2.4 Clock Recovery Module
21
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
end-of-frame delimiter (T/R symbols).
The Clock Recovery Module accepts NRZI data from the
MLT-3 to NRZI decoder. The Clock Recovery Module locks
onto the data stream and extracts the 125MHz reference
clock. The extracted and synchronized clock and data are
presented to the NRZI to NRZ Decoder.
7.2.2.5 NRZI to NRZ
The transmit data stream is required to be NRZI encoded in
for compatibility with the TP-PMD standard for 100Base-TX
transmission over Category-5 unshielded twisted pair cable.
This conversion process must be reversed on the receive
end. The NRZI to NRZ decoder receives the NRZI
data stream from the Clock Recovery Module and
converts it to a NRZ data stream to be presented to
the Serial to Parallel conversion block.
7.2.2.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.
7.2.2.7 Descrambler
Because the scrambling process requires to control the
radiated emissions of transmit data streams, the receiver
must descramble the receive data streams. The
descrambler receives scrambled parallel data streams from
the Serial to Parallel converter, descrambles the data
streams, and presents the data streams to the Code Group
alignment block.
7.2.2.8 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected and subsequent data is aligned on
a fixed boundary.
7.2.2.9 4B5B Decoder
The T/R symbol pair is also stripped from the nibble
presented to the Reconciliation layer.
7.2.3 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When
the DM9161CI is operating in 10Base-T mode, the coding
scheme is Manchester. Data processed for transmit is
presented to the MII interface in nibble format, converted to
a serial bit stream, then Manchester encoded. When
receiving, the Manchester encoded bit stream is decoded
and converted into nibble format for presentation to the MII
interface.
7.2.4 Collision Detection
For half-duplex operation, a collision is detected when the
transmit and receive channels are active simultaneously.
When a collision has been detected, it will be reported by the
COL signal on the MII interface. Collision detection is
disabled in Full Duplex operation.
7.2.5 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex operation
during transmission or reception of data. During full-duplex
mode, CRS is asserted only during receive operations.
7.2.6 Auto-Negotiation
The objective of Auto-negotiation is to provide a means to
exchange information between segment linked devices and
to automatically configure both devices to take maximum
advantage of their abilities. It is important to note that Autonegotiation does not test the link segment characteristics.
The Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to a
remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to reject
un-shared modes of operation. This allows devices on both
ends of a segment to establish a link at the best common
mode of operation. If more than one common mode exists
between the two devices, a mechanism is provided to allow
the devices to resolve to a single mode of operation using a
predetermined
priority
resolution
function.
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first 2 5-bit code groups
received are the start-of-frame delimiter (J/K symbols). The
J/K symbol pair is stripped and two nibbles of preamble
pattern are substituted. The last two code groups are the
22
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Auto-Negotiation (continued)
Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation
feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is
examined. If it is discovered that the signal matches a technology, supported by the receiving device, a
connection will be automatically established using that technology. This allows devices, which do not support
Auto-negotiation but support a common mode of operation, to establish a link.
7.2.7 MII Serial Management
The MII serial management interface consists of a data interface, basic register set, and a serial management
interface to the register set. Through this interface it is possible to control and configure multiple PHY devices,
get status and error information, and determine the type and capabilities of the attached PHY device(s).
The DM9161CI management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for
registers 0 through 6 with vendor-specific registers 16, 17, 18, 21, 22, 23 and 24.
In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits
(preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP) :< 10> indicates Read operation and <01> indicates Write operation.
For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for
MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management
registers.
7.2.8 Serial Management Interface
The serial control interface uses a simple two-wired serial interface to obtain and control the status of the
physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock),
and MDI/O (Management Data Input/Output) signals.
The MDIO pin is bi-directional and may be shared by up to 32 devices.
7.2.9 Management Interface - Read Frame Structure
MDC
MDIO Read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
A4
Op Code
A3
A0
PHY Address
R4
R3
R0
Register Address
0
Z
D15
//
D14
Turn Around
//
D1
D0
Data
Read
Write
Idle
7.2.10 Management Interface - Write Frame Structure
MDC
MDIO Write
32 "1"s
Idle
Preamble
0
1
SFD
0
1
Op Code
A4
A3
PHY Address
A0
R4
R3
R0
Register Address
Write
1
0
Turn Around
D15
D14
Data
D1
D0
Idle
Figure 7-5
23
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2.11 Power Reduced Mode
The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable
disconnection, DM9161CI will automatically turn off the power and enter the Power Reduced mode, regardless of its
operation mode being N-way auto-negotiation or forced mode. While in the Power Reduced mode, the transmit circuit will
continue sending out fast link pulse with minimum power consumption. If a valid signal is detected from the media, which
might be N-way fast link pulse, 10Base-T normal link pulse, or 100Base-TX MLT3 signals, the device wakes up and resumes
normal operation mode.
Automatic reduced power down mode can be disabled by writing Zero to Reg.16.4.
7.2.12 Power down Mode
Power Down mode is entered by setting Reg.0.11 to ONE or pulling PWRDWN pin high, which disables all transmit and
receive functions, and MII interface functions except the MDC/MDIO management interface.
7.2.13 Reduced Transmit Power Mode
Additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a
8.5KΩ resistor on BGRES and BGRESG pins, and the TX+/TX- pulled high resistors being changed from 50Ω to 78Ω. This
configuration could reduce about 20% of transmit power.
7.3 HP Auto-MDIX Functional Descriptions
The DM9161CI supports the automatic detect cable connection type, MDI/MDIX (straight through/cross over). A
manual configuration by register bit for MDI or MDIX is still accepted.
When set to automatic, the polarity of MDI/MDIX controlled timing is generated by 16-bits LFSR. The switching cycle time is
located from 200ms to 420ms. The polarity control is always switch until detect received signal. After selected MDI or MDIX,
the polarity status can be read by register bit (20.7). (See page33, 8.12 specified config register-20 bit 7)7.3.1 Function Setting.
Pin 39 is used to enable HP Auto-MDIX function.
Pull pin 39 low will enable it, and pull pin 39 high will disable it.
Specified config Register 20 bit 4 (20, 4) is used by programmer to disable HP Auto-MDIX function. Write register
20 bit 4 to “1 “will disable HP Auto-MDIX function. Its default value is “0 “. When the register 20 bit 4 (20, 4) is set to “1 “, the
register 20 bit 5(20, 5) is used to select straight through or cross over mode, “0 “is for straight through, and “1 “is for cross over.
RX + /- from DM9161CI
TX + /- from DM9161CI
RX+/- to RJ45
TX+/- to RJ45
* MDI: __________
* MDIX: - - - - - - - - This feature is able to detect the required cable connection type. (Straight through or crossed over) and make correction
automatically
24
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8. MII Register Description
AD
Name
15
D
00 CONTROL Reset
01
STATUS
02
03
PHYID1
PHYID2
04 Auto-Neg.
Advertise
05 Link Part.
Ability
0
T4
Cap.
0
0
1
Next
Page
LP
Next
Page
06 Auto-Neg.
Expansion
16 Specified
BP
Config.
4B5B
17 Specified 100
Conf/Stat FDX
18
10T
Rsvd
Conf/Stat
19
PWDOR
20
Specified
config
21
MDINTR
22
RCVER
14
13
12
11
Loop
back
0
TX FDX
Cap.
1
0
0
Speed Auto-N Power
select
Enable Down
1
1
0
TX HDX 10 FDX 10 HDX
Cap.
Cap.
Cap.
1
1
1
0
0
0
1
1
1
FLP Rcv
Ack
LP
Ack
Remote
Fault
LP
RF
Reserved
Reserved
10
9
Isolate
0
8
7
Restart
Full
Auto-N Duplex
0
1
Reserved
0
FC
Adv
LP
FC
T4
Adv
LP
T4
5
4
Coll.
Test
0
1
3
2
1
0
Reserved
Pream.
Supr.
1
0
0000
0
0
6
Auto-N
Compl.
0
0
1
Model No.
001011
TX FDX TX HDX 10 FDX 10 HDX
Adv
Adv
Adv
Adv
LP
LP
LP
LP
TX FDX TX HDX 10 FDX 10 HDX
Remote
Fault
0
0
000_0000
Auto-N
Link
Jabber
Cap.
Status
Detect
1
0
0
0
0
0
Version No.
0001
Advertised Protocol Selector Field
Extd
Cap.
1
0
Link Partner Protocol Selector Field
Reserved
BP
SCR
100
HDX
LP
Enable
Pardet LP Next Next Pg New Pg LP AutoN
Fault
Pg Able
Able
Rcv
Cap.
BP
BP_ADP Repeater
TX
FEF_EN RMII_E Force TST_SE LEDCO RPDCTR Reset
Pream.
Sleep
Remote
ALIGN
OK
N
100LNK
L0
L_SEL
-EN
St. Mch
Supr.
mode
LoopOut
10
10 HDX Reserve Reverse Reverse
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
FDX
d
d
d
HBE
SQUE
JAB
10T
Reserved
Polarity
Enable Enable Enable
Serial
Reverse
Reserved
PD10DR PD100l
V
PDchip
PDcrm
PDaeq
PDdrv
PDecli
PDeclo
PD10
TSTSE1 TSTSE2 FORCE_ FORCE_ PREAM TX10M_ NWAY_ Reserved MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Rmii_acc PD_valu
TXSD
FEF
BLEX
PWR
PWR
NTL
_dlpbk
Value
wn
u
e
Int_sts
Reserve Reserve Reverse Fdx_ms Spd_msk Lnk_msk Int_msk
d
d
d
k
Reserve Reserve Reverse Fdx_chg Spd_chg Lnk_chg Reserve
d
d
d
d
Int_sts
Receiver Error Counter
23 DIS_connec
t
Reversed
Disconnect_counter
24
RSTLH
Lh_led_ Lh_mdint Lh_cabst Lh_isolat Lh_rmii Lh_seril1 Lh_repea Lh_testm Lh_op2
mode
r
s
e
0
ter
ode
25
RADVR
Reserved
26
RLPAR
Reserved
29
PSCR
30 MONITOR
Reserved
Lh_op1
Lh_op0 Lh_phya Lh_phya Lh_phya Lh_phya Lh_phya
d4
d3
d2
d1
d0
preamble amplitud TX_PW
x
e
R
Reserved
Reserved
Moni_en
Moni_index
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
<Access Type>:
RO = Read only
RW = Read/Write
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#) Value latched in from pin # at reset
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
25
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.1 Basic Mode Control Register (BMCR) - 00
26
Bit
0.15
Bit Name
Reset
0.14
Loopback
0.13
Speed selection
0.12
Auto-negotiation
enable
0.11
Power down
0.10
Isolate
0.9
Restart
Auto-negotiation
Default
Description
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep returning a
value of one until the reset process is completed
0, RW
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
1, RW
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will
return auto-negotiation selected medium type
1, RW
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in autonegotiation status
0, RW
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down
state and while in the power-down state, the PHY should not
generate spurious signals on the MII
1=Power down
0=Normal operation
0,RW
Isolate
1 = Isolates the DM9161CI from the MII with the exception of the
serial management. (When this bit is asserted, the DM9161CI does
not respond to the TXD [0:3], TX_EN, and TX_ER inputs, and it
shall present a high impedance on its TX_CLK, RX_CLK, RX_DV,
RX_ER, RXD [0:3], COL and CRS outputs. When PHY is isolated
from the MII it shall respond to the management transactions)
0 = Normal operation
0,RW/SC Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until autonegotiation is initiated by the DM9161CI. The operation of the autonegotiation process will not be affected by the management entity
that clears this bit
0 = Normal operation
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
0.8
Duplex mode
1,RW
0.7
Collision test
0,RW
0.6-0.0
Reserved
0,RO
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With autonegotiation enabled, this bit reflects the duplex capability selected
by auto-negotiation
0 = Normal operation
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0 = Normal operation
Reserved
Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) - 01
Bit
1.15
Bit Name
100BASE-T4
Default
0,RO/P
1.14
100BASE-TX
full-duplex
1,RO/P
1.13
100BASE-TX
half-duplex
1,RO/P
1.12
10BASE-T
full-duplex
1,RO/P
1.11
10BASE-T
half-duplex
1,RO/P
1.10-1.7
Reserved
0,RO
1.6
MF preamble
suppression
1,RO
1.5
Auto-negotiation
Complete
0,RO
1.4
Remote fault
0, RO/LH
1.3
Auto-negotiation
1,RO/P
27
Description
100BASE-T4 Capable
1 = DM9161CI is able to perform in 100BASE-T4 mode
0 = DM9161CI is not able to perform in 100BASE-T4 mode
100BASE-TX Full Duplex Capable
1 = DM9161CI is able to perform 100BASE-TX in full duplex mode
0 = DM9161CI is not able to perform 100BASE-TX in full duplex
mode
100BASE-TX Half Duplex Capable
1 = DM9161CI is able to perform 100BASE-TX in half duplex mode
0 = DM9161CI is not able to perform 100BASE-TX in half duplex
mode
10BASE-T Full Duplex Capable
1 = DM9161CI is able to perform 10BASE-T in full duplex mode
0 = DM9161CI is not able to perform 10BASE-TX in full duplex
mode
10BASE-T Half Duplex Capable
1 = DM9161CI is able to perform 10BASE-T in half duplex mode
0 = DM9161CI is not able to perform 10BASE-T in half duplex mode
Reserved
Read as 0, ignore on write
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9161CI
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
Auto Configuration Ability
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
ability
1.2
Link status
0,RO/LL
1.1
Jabber detect
0, RO/LH
1.0
Extended
capability
1,RO/P
1 = DM9161CI is able to perform auto-negotiation
0 = DM9161CI is not able to perform auto-negotiation
Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through
a management interface or a DM9161CI reset. This bit works only
in 10Mbps mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161CI. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
2.15-2.0
Bit Name
OUI_MSB
Default
<0181h>
Description
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
3.15-3.10
Bit Name
OUI_LSB
Default
<101110>,
RO/P
3.9-3.4
VNDR_MDL
<001011>,
RO/P
3.3-3.0
MDL_REV
<0001>,
RO/P
28
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9161CI device as they will be transmitted to its link
partner during Auto-negotiation.
Bit
4.15
Bit Name
NP
4.14
ACK
4.13
RF
4.12-4.11
Reserved
4.10
FCS
4.9
T4
4.8
TX_FDX
4.7
TX_HDX
4.6
10_FDX
4.5
10_HDX
4.4-4.0
Selector
29
Default
0,RO/P
Description
Next page Indication
1 = Next page available
0 = No next page available
The DM9161CI has no next page, so this bit is permanently set to
0
0,RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9161CI's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
0, RW
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
X, RW
Reserved
Write as 0, ignore on read
0, RW
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
0, RO/P
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9161CI does not support 100BASE-T4 so this bit is
permanently set to 0
1, RW
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
1, RW
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local device
0 = 100BASE-TX half duplex is not supported
1, RW
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
1, RW
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
0 = 10BASE-T half duplex is not supported
<00001>, RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
5.15
Bit Name
NP
5.14
ACK
5.13
RF
5.12-5.11
Reserved
5.10
FCS
5.9
T4
5.8
TX_FDX
5.7
TX_HDX
5.6
10_FDX
5.5
10_HDX
5.4-5.0
Selector
30
Default
0, RO
Description
Next Page Indication
1 = Link partner, next page available
0 = Link partner, no next page available
0, RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9161CI's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
0, RO
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
0, RO
Reserved
Read as 0, ignore on write
0, RO
Flow Control Support
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
0, RO
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
0, RO
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
0, RO
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
0, RO
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
0, RO
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.7 Auto-negotiation Expansion Register (ANER) - 06
Bit
6.15-6.5
Bit Name
Reserved
Default
0, RO
6.4
PDF
0, RO/LH
6.3
LP_NP_ABLE
0, RO
6.2
NP_ABLE
0,RO/P
6.1
PAGE_RX
0, RO/LH
6.0
LP_AN_ABLE
0, RO
Description
Reserved
Read as 0, ignore on write
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
NP_ABLE = 1: DM9161CI, next page available
NP_ABLE = 0: DM9161CI, no next page
DM9161C does not support this function, so this bit is always 0
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports Autonegotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
31
Bit
16.15
Bit Name
BP_4B5B
16.14
BP_SCR
16.13
BP_ALIGN
16.12
BP_ADPOK
16.11
REPEATER
16.10
TX
16.9
16.8
Reserved
RMII_Enable
Default
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
0, RW
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
0, RW
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol
encoder and scrambler) bypassed
0 = Normal operation
1, RW
Bypass ADPOK
1=Reserved
0=Normal operation
(Pin#38),RW Repeater/Node Mode
The value of the Repeater/Node pin (38) is latched into this bit at
power-up/reset
1 = Repeater mode
0 = Node mode
1, RW
100BASE-TX Mode Control
1 = 100BASE-TX operation
1, RO
Reserved
(Pin#36), RW Reduced MII Enable
Select normal MII or reduced MII. The value of the RMII pin(36) is
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
32
16.7
F_LINK_100
0, RW
16.6
SPLED_CTL
0, RW
16.5
COLLED_CTL
0, RW
16.4
RPDCTR-EN
1, RW
16.3
SMRST
0, RW
16.2
MFPSC
1, RW
16.1
SLEEP
0, RW
16.0
RLOUT
0, RW
latched into this bit at power-up/reset
1 = Enable Reduced MII
0 = Normal MII
Force Good Link in 100Mbps
1 = Force 100Mbps good link status
0 = Normal 100Mbps operation
This bit is useful for diagnostic purposes
Speed LED Disable
1 = Disable SPEED LED output.
0 = Normal SPEED LED output to indicate speed status
Collision LED Enable
1 = FDX/COL LED output is configured to indicate Fullduplex/Collision status
0 = FDX/COL LED output is configured to indicate Full/half duplex
status
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
1 = Enable automatic reduced power down
0 = Disable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
17.15
Bit Name
100FDX
17.14
100HDX
17.13
10FDX
17.12
10HDX
17.11Reserved
17.9
17.8-17.4 PHYADR[4
:0]
17.3-17.0 ANMB[3:0]
33
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after autonegotiation. This bit is invalid when it is not in the auto-negotiation mode
1, RO
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after autonegotiation. This bit is invalid when it is not in the auto-negotiation mode
1, RO
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after autonegotiation. This bit is invalid when it is not in the auto-negotiation mode
1, RO
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after autonegotiation. This bit is invalid when it is not in the auto-negotiation mode
0, RO
Reserved
Read as 0, ignore on write
(PHYADR), PHY Address Bit 4:0
RW
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
0, RO
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written
to these bits.
b3 b2 b1 B0
0 0 0 0 In IDLE state
0 0 0 1 Ability match
0 0 1 0 Acknowledge match
0 0 1 1 Acknowledge match fail
0 1 0 0 Consistency match
0 1 0 1 Consistency match fail
0 1 1 0 Parallel detects signal_link_ready
0 1 1 1 Parallel detects signal_link_ready fail
1 0 0 0 Auto-negotiation completed successfully
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
18.15
Bit Name
Reserved
Default
0, RO
18.14
LP_EN
1, RW
18.13
HBE
1,RW
18.12
SQUELCH
1, RW
18.11
JABEN
1, RW
18.10
10BT_SER
(#PIN
34),RW
18.9-18.1
Reserved
0, RO
18.0
POLR
0, RO
Description
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9161CI is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9161CI is in
10BASE-T full duplex or 10BASE-T transceiver Loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
10BASE-T GPSI Mode ( Default value depend on #pin34 strap
condition)
1 = 10BASE-T GPSI mode selected (#pin34 pull down)
0 = 10BASE-T MII mode selected (#pin34 pull up, default)
GPSI mode is not supported for 100Mbps operation
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
8.11 Power down Control Register (PWDOR) - 19
Bit
Bit Name
Default
Description
19.15-19.9 Reserved
0, RO
Reserved
Read as 0, ignore on write
19.8
PD10DRV
0, RW
Vendor power down control test
19.7
PD100DL
0, RW
Vendor power down control test
19.6
PDchip
0, RW
Vendor power down control test
19.5
PDcom
0, RW
Vendor power down control test
19.4
PDaeq
0, RW
Vendor power down control test
19.3
PDdrv
0, RW
Vendor power down control test
19.2
PDedi
0, RW
Vendor power down control test
19.1
PDedo
0, RW
Vendor power down control test
19.0
PD10
0, RW
Vendor power down control test
* When selected, the power down value is control by Register 20.0
34
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.12 (Specified config) Register – 20
Bit
20.15
20.14
20.13
20.12
20.11
20.10
20.9
20.8
20.7
20.6
20.5
20.4
20.3
20.2
20.1
20.0
35
Bit Name
TSTSE1
TSTSE2
Reserved
Default
0,RW
0,RW
0, RO
Description
Vendor test select control
Vendor test select control
Reserved
Read as 0, ignore on write
TSTSEL3
0,RW
Vendor test select control
PREAMBLEX
0,RW
Preamble Saving Control
1: 10M TX preamble bit count is normal.
0:when bit 10 is set, the 10M TX preamble count is reduced
When bit 11 of register 29 is set, 12-bit preamble bit is reduced.
Otherwise 22-bit preamble bit is reduced.
TX10M_PWR
0,RW
10M TX Power Saving Control
1: enable 10M TX power saving
0: disable 10M TX power saving
NWAY_PWR
0,RW
N-Way Power Saving Control
1: disable N-Way power saving
0: enable N-Way power saving
Reserved
0, RO
Reserved
Read as 0, ignore on write
MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value
1: MDIX mode
0: MDI mode
AutoNeg_dpbk
0,RW
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
Mdix_fix Value
0, RW
MDIX_CNTL force value:
When MDIX_DOWN = 1, MDIX_CNTL value depend on the
register value.
Mdix_do wn
0,RW
MDIX Down
Manual force MDI/MDIX.
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5
0: Enable HP Auto-MDIX
MonSel1
0,RW
Vendor monitor select
MonSel0
0,RW
Vendor monitor select
RMII_Ver
0,RW
RMII version
1: support RMII 1.0
0: support RMII 1.2
PD_value
0,RW
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.13 DAVICOM Specified Interrupt Register – 21
Bit
21.15
Bit Name
INTR PEND
Default
0, RO
21.1421.12
21.11
Reserved
0, RO
FDX mask
1, RW
21.10
SPD mask
1, RW
21.12
LINK mask
1, RW
21.8
INTR mask
1, RW
21.7-21.5
21.4
Reserved
FDX change
0, RO
0,RO/LH
21.3
SPD change
0, RO/LH
21.2
LINK change
0, RO/LH
21.1
21.0
Reserved
INTR status
0, RO
0, RO/LH
Description
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
Reserved
Full-duplex Interrupt Mask
When this bit is set, the Duplex status change will not generate the
interrupt
Speed Interrupt Mask
When this bit is set, the Speed status change will not generate the
interrupt
Link Interrupt Mask
When this bit is set, the link status change will not generate the
interrupt
Master Interrupt Mask
When this bit is set, no interrupts will be generated under any
condition
Reserved
Duplex Status Change Interrupt
“1” indicates a change of duplex since last register read. A read of
this register will clear this bit
Speed Status Change Interrupt
“1” indicates a change of speed since last register read. A read of
this register will clear this bit
Link Status Change Interrupt
“1” indicates a change of link since last register read. A read of this
register will clear this bit
Reserved
Interrupt Status
The status of MDINTR#. “1” indicates that the interrupt mask is off
that one or more of the change bits are set. A read of this register
will clear this bit
8.14 DAVICOM Specified Receive Error Counter Register (RECR) – 22
Bit
22.15-0
36
Bit Name
Rcv_ Err_ Cnt
Default
0, RO
Description
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by read this register.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.15 DAVICOM Specified Disconnect Counter Register (DISCR) – 23
Bit
23.1523.8
23.7-23.0
37
Bit Name
Reserved
Default
0, RO
Disconnect
Counter
0, RO
Description
Reserved
Disconnect Counter those increments upon detection of
disconnection. Clean by read this register.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.16 DAVICOM Hardware Reset Latch State Register (RLSR) – 24
Bit
24.15
24.14
24.13
24.12
24.11
24.10
24.9
24.8
24.7
24.6
24.5
24.4
24.3
24.2
24.1
24.0
Bit Name
LH_LEDMODE
LH_MDINTR
LH_CSTS
LH_ISO
LH_RMII
LH_TP10SER
LH_REPTR
LH_TSTMOD
LH_OP2
LH_OP1
LH_OP0
LH_PH4
LH_PH3
LH_PH2
LH_PH1
LH_PH0
Default
1,RO
1,RO
0,RO
0,RO
0,RO
1,RO
0,RO
0,RO
1,RO
1,RO
1,RO
0,RO
0,RO
0,RO
0,RO
0,RO
Description
LEDMODE pin reset latch value
MDINTR pin reset latch value
CABLESTS pin reset latch value
TXCLK pin reset latch value
COL pin reset latch value
RXCLK pin reset latch value
RXER pin reset latch value
RXDV pin reset latch value
LED2 pin reset latch value
LED1 pin reset latch value
LED0 pin reset latch value
CRS pin reset latch value
RXD3 pin reset latch value
RXD2 pin reset latch value
RXD1 pin reset latch value
RXD0 pin reset latch value
8.17 Power Saving Control Register (PSCR) – 29
Bit
29.15-12
29.11
Bit Name
RESERVED
PREAMBLEX
Default
0,RO
0,RW
29.10
29.9
RESERVED
TX_PWR
0,RO
0.RW
29.8-0
RESERVED
0,RO
38
Description
reserved
Preamble Saving Control
When bit 10 of register 20 is set and bit 11 of
register 20 is cleared, the 10M TX preamble count is reduced.
1: 10-bit preamble bit is reduced.
0: 20-bit preamble bits is reduced.
reserved
TX Power Saving Control Disabled
1: disable TX driving power saving function
0: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
reserved
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings (-40°C~+85°C)
Symbol
DVDD
VIN
VOUT
TSTG
TA
LT
Parameter
Supply Voltage
DC Input Voltage (VIN)
DC Output Voltage(VOUT)
Storage Temperature range
Ambient Temperature
Lead Temperature
(LT, soldering, 10 sec.).
Min.
-0.3
-0.5
-0.3
-65
-40
-
Max.
3.6
5.5
3.6
+150
+85
+260
Unit
V
V
V
°C
°C
°C
Conditions
*1
*2
*2
-
*1: Power pin
*2: IO pin
9.2 Operating Conditions
Parameter
Symbol
DVDD
Supply Voltage
TA
Ambient Temperature
PD
100BASE-TX
(Power Dissipation) 10BASE-T TX.
*
Auto-negotiation
Power Down Mode
Min.
3.135
0
-
Typ.
3.300
130
120
50
8.2
Max.
3.465
+70
-
Unit
V
°C
mA
mA
mA
mA
Conditions
3.3V
3.3V
3.3V
3.3V
Comments
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated that in the
39
operational sections of this specification is not
implied.
Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.3 DC Electrical Characteristics (DVDD = 3.3V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
TTL Inputs
(TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR,
RESET# )
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
2.0
V
IIL
Input Low Leakage Current
-1
uA
VIN = 0V
IIH
Input High Leakage Current
1
uA
VIN = 3.3V
VOL
Output Low Voltage
0.4
V
IOL = 4mA
VOH
Output High Voltage
2.4
V
IOH = -4mA
Receiver
VICM
RX+/RX- Common mode Input Voltage
1.8
V
100 Ω Termination Across
Transmitter
VTD100 100TX+/- Differential Output Voltage
1.9
2.0
2.1
V
Peak to Peak
VTD10
10TX+/- Differential Output Voltage
4.4
5
5.6
V
Peak to Peak
ITD100 100TX+/- Differential Output Current
│19│
│20│
│21│
mA
ITD10
10TX+/- Differential Output Current
│44│
│50│
│56│
mA
9.4 AC Electrical Characteristics & Timing Waveforms
9.4.1 TP Interface
Symbol
Parameter
tTR/F
100TX+/- Differential Rise/Fall Time
tTM
100TX+/- Differential Rise/Fall Time Mismatch
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
tT/T
100TX+/- Differential Output Peak-to-Peak Jitter
XOST
100TX+/- Differential Voltage Overshoot
Min.
3.0
0
0
Typ.
-
0
0
-
Max.
5.0
0.5
0.5
Unit
ns
ns
ns
1.4
5
ns
%
Conditions
9.4.2 Oscillator/Crystal Timing
Symbol
tCKC
tPWH
tPWL
40
Parameter
OSC Frequency
OSC Cycle Time
OSC Pulse Width High
OSC Pulse Width Low
Min.
24.99925
39.9988
16
16
Typ.
25
40
20
20
Max.
25.00075
40.0012
24
24
Unit
MHz
ns
ns
ns
Conditions
30ppm
30ppm
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.3 Power On Reset Timing
t1
RESET#
Strap pins
t2
pwrst#.vsd
Symbol
t1
t2
Parameter
RESET# Low Period
Strap pin hold time with RESET#
Min.
1
40
Typ.
-
Max.
-
Unit
ms
ns
Conditions
-
9.4.4 MDC/MDIO Timing
Symbol
t0
t1
t2
t3
Parameter
MDC Cycle Time
MDIO Setup Before MDC
MDIO Hold After MDC
MDC To MDIO Output Delay
Min.
80
10
10
0
Typ.
-
Max.
300
Unit
ns
ns
ns
ns
Conditions
When OUTPUT By STA
When OUTPUT By STA
When OUTPUT By DM9161CI
9.4.5 MDIO Timing When OUTPUT by STA
9.4.6 MDIO Timing When OUTPUT by DM9161CI
41
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.7 MII 100BASE-TX Transmit Timing Parameters
Symbol
tTXc
tTXh, tTXl
tTXs
tTXh
tTXOD
t1
t2
tTXpd
tTXr/f
Parameter
TXCLK Cycle Time
TXCLK High/Low Time
TXD [0:3], TXEN, TXER Setup To TXCLK High
TXD [0:3], TXEN, TXER Hold From TXCLK
High
TXCLK to Output Delay
TXEN Sampled To CRS Asserted
TXEN Sampled To CRS De-asserted
TXEN Sampled To TX+/- Out (Tx Latency)
100TX Driver Rise/Fall Time
Min.
39.9988
16
12
0
Typ.
40
20
-
Max.
40.0012
24
-
Unit
ns
ns
ns
ns
3
4
4
8
4
25
5
ns
BT
BT
BT
ns
Conditions
30ppm
90% To 10%, Into
100ohm
Differential
Note 1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing.
9.4.8 MII 100BASE-TX Transmit Timing Diagram
TXCLK
tTXc
tTXS
TXD [0:3],
TXEN, TXER
tTXOD
tTXh
t2
t1
CRS
100TX+/-
tTXh
tTXpd
tTXr/f
9.4.9 MII 100BASE-TX Receive Timing Parameters
Symbol
Parameter
Min.
Typ. Max.
Unit Conditions
tRXc
RXCLK Cycle Time
39.9988
40
40.0012
30ppm
TRXh, tRXl RXCLK High/Low Time
16
20
24
tRXs
RXD [0:3], RXDV, RXER Setup To RXCLK High
10
ns
tRXh
RXD [0:3], RXDV, RXER Hold From RXCLK High
10
ns
tRXpd
RX+/- In To RXD [0:3] Out (Rx Latency)
15
BT
t1
CRS Asserted To RXD [0:3], RXDV, RXER
4
BT
t2
CRS De-asserted To RXD [0:3], RXDV, RXER
0
BT
t3
RX+/- In To CRS Asserted
10
14
BT
t4
RX+/- Quiet To CRS De-asserted
14
18
BT
t5
RX+/- In To COL De-Asserted
14
18
BT
1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing.
42
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.10 MII 100BASE-TX Receive Timing Diagram
RXCLK
tTXpd
tRXS tRXh
tRXh
tRXc
RXD [0:3],
RXDV, RXER
t1
t2
t4
CRS
t3
RX+/-
t5
t5
COL
9.4.11 MII 10BASE-T Nibble Transmit Timing Parameters
Symbol
tTXs
tTXh
t1
t2
tTXpd
Parameter
TXD[0:3), TXEN, TXER Setup To TXCLK High
TXD[0:3], TXEN, TXER Hold From TXCLK High
TXEN Sampled To CRS Asserted
TXEN Sampled To CRS De-asserted
TXEN Sampled To 10TXO Out (Tx Latency)
Min.
5
5
-
Typ.
2
15
2
Max.
4
20
4
Unit
ns
ns
BT
BT
BT
Conditions
9.4.12 MII 10BASE-T Nibble Transmit Timing Diagram
TXCLK
tTXh
tTXS
TXD [0:3],
TXEN, TXER
t2
t1
CRS
10TX+/-
43
tTXpd
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.13 MII 10BASE-T Receive Nibble Timing Parameters
Symbol
tRXs
tRXh
tRXpd
t1
t2
t3
t4
Parameter
RXD [0:3], RXDV, RXER Setup To RXCLK High
RXD [0:3], RXDV, RXER Hold From RXCLK High
RX+/- To RXD [0:3] Out (Rx Latency)
CRS Asserted To RXD [0:3], RXDV, RXER,Asserted
CRS De-asserted To RXD [0:3], RXDV, RXER,Deasserted
RXI In To CRS Asserted
RXI Quiet To CRS De-asserted
Min.
5
5
1
-
Typ.
7
14
-
Max.
20
3
Unit
ns
ns
BT
BT
BT
1
1
2
10
4
15
BT
BT
Conditions
9.4.14 MII 10BASE-T Receive Nibble Timing Diagram
RXCLK
tTXpd
tRXS tRXh
RXD [0:3],
RXDV, RXER
t1
t2
CRS
t4
t3
RX+/-
9.4.15 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol
t1
t2
t3
t4
t5
-
44
Parameter
Clock/Data Pulse Width
Clock Pulse To Data Pulse Period
Clock Pulse To Clock Pulse Period
FLP Burst Width
FLP Burst To FLP Burst Period
Clock/Data Pulses in a Burst
Min.
55.5
111
8
17
Typ.
100
62.5
125
2
-
Max.
69.5
139
24
33
Unit
ns
us
us
ms
ms
pulse
Conditions
DATA = 1
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.16 Auto-negotiation and Fast Link Pulse Timing Diagram
Clock Pulse
FAST LINK
PULSES
Data Pulse
Clock Pulse
t1
t1
t2
t3
FLP Burst
FLP Bursts
FLP Burst
t4
t5
9.4.17 RMII Receive Timing Diagram
100 Mb/s Reception with no errors
9.4.18 RMII Transmit Timing Diagram
100 Mb/s Transmission
45
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.19 RMII Timing Diagram
REF_CLK
TREF
Tsu Thold
TXD[1:0], TX_EN,
RXD[1:0], CRS_DV,
RX_ER
9.4.20 RMII Timing Parameter
Symbol
Fref
Tref%
Tref
Tsu
Thold
46
Parameter
REF_CLK Frequency
REF_CLK Duty Cycle
REF_CLK Clock Cycle
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER
Data Setup to REF_CLK rising edge
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER
Data hold from REF_CLK rising edge
Min.
49.9985
Typ.
50
Max.
50.0015
Unit
MHz
35
4
20
-
65
-
%
ns
ns
2
-
-
ns
Conditions
30ppm
(1.5KHZ)
30ppm
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.21 Magnetic Selection Guide
Refer to Table 2 for transformer requirements.
Transformers, meeting these requirements, are
available from a variety of magnetic manufacturers.
Designers should test and qualify all magnetic before
•
using them in an application. The transformers listed
in Table 2 are electrical equivalents, but may not be
pin-to-pin equivalents.
Refer to the following tables 5-1 and 5-2 for 10/100M magnetic sources and specification requirements. The
magnetics which meet these requirements are available from a variety of magnetic manufacturers. Designers
should test and qualify all magnetic specifications before using them in an application. The magnetics listed in
the following table are electrical equivalents, but may not be pin-to-pin equivalents.
Manufacturer
Part Number
MAGCOM`
HS9016, HS9024
Delta
LFE8563-DC, LFE8563T-DC
Table 5-1: 10/100M Magnetics Sources
Parameter
Tx / RX turns ratio
Inductance
Insertion loss
Return loss
Differential to
mode rejection
common
Transformer isolation
Values
Units
Test Condition
1:1 CT / 1:1
350
μH (Min)
-
1.1
dB ( Max )
1 – 100 MHz
-18
dB ( Min )
1 –30 MHz
-14
dB ( Min )
30 – 60 MHz
-12
dB ( Min )
60 – 80 MHz
-40
dB ( Min )
1 – 60 MHz
-30
dB ( Min )
60 – 100 MHz
1500
V
-
Table 5-2: Magnetic Specification Requirements
47
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
10. Package Information
48 Pins LQFP Package Outline Information:
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
Dimension in mm
Min
Nom
Max
1.60
0.05
0.15
1.35
1.40
1.45
0.17
0.22
0.27
0.17
0.20
0.23
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
0.45
0.60
0.75
1.00 REF
0.08
0.08
0.20
0.20
o
o
o
0
3.5
7
o
0
o
12 TYP
o
12 TYP
Dimension in inch
Min
Nom
Max
0.063
0.002
0.006
0.053
0.055 0.057
0.007
0.009 0.011
0.007
0.008 0.009
0.004
0.008
0.004
0.006
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
0.020 BSC
0.018
0.024 0.030
0.039 REF
0.003
0.003
0.008
0.008
o
o
o
0
3.5
7
o
0
o
12 TYP
o
12 TYP
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
48
Final
Version: DM9161CI-DS-F01
February 22, 2012
DM9161CI
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
11. Order Information
Part Number
DM9161CIEP
Pin Count
48
Package
LQFP(Pb-Free)
DAVICOM‘s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM. DAVICOM
will not be bound by any terms inconsistent with these
unless DAVICOM agrees otherwise in writing. Acceptance
of the buyer’s orders shall be based on these terms.
Disclaimer
The information appearing in this publication is believed to
be accurate. Integrated circuits sold by DAVICOM
Semiconductor are covered by the warranty and patent
indemnification, and the provisions stipulated in the terms of
sale only. DAVICOM makes no warranty, express, statutory,
implied or by description, regarding the information in this
publication or regarding the freedom of the described chip(s)
from patent infringement. FURTHER, DAVICOM MAKES
NO WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any time
without notice. Accordingly, the reader is cautioned to verify
that the data sheets and other information in this publication
are current before placing orders. Products described herein
are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without
additional processing by DAVICOM for such applications.
Please note that application circuits illustrated in this
document are for reference purposes only.
Company Overview
DAVICOM Semiconductor, Inc. develops and manufactures
integrated circuits for integration into data communication
products. Our mission is to design and produce IC products
that are the industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we have
built an organization that is able to develop chipsets in
response to the evolving technology requirements of our
customers while still delivering products that meet their cost
requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently available
and soon to be released products are based on our
proprietary designs and deliver high quality, high
performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Industrial Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: +886-3-5798797
FAX: +886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the
limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
49
Final
Version: DM9161CI-DS-F01
February 22, 2012

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