DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip General Description The DM9331 is a physical-layer, single-chip, low power transceiver for media converter application. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, and it also provides PECL interface to connect the external fiber optical transceiver. Through the Media Converter Interface (MCI), the DM9331 connects to another DM9331 for the twisted pair to the fiber media converter, or fiber to fiber repeater. including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD) and a PECL compliant interface for a fiber optical module, compliant with ANSI X3.166. The DM9331 provides a strong support for the auto-negotiation function utilizing automatic selection of full- or half-duplex mode. Furthermore, due to the built-in wave-shaping filter, the DM9331 needs no external filter to transport signals to the media on the 100base-TX Ethernet operation. The DM9331 uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, Block Diagram 100Base-FX PECL Interface 100Base-TX Transceiver 100BaseTX PCS Media Converter Interface Auto-Negotiation TX/RX Module Clock Circuit Block Preliminary Version: DM9331-DS-P02 September 21, 2001 Biasing/ Power Block MII Register LED Driver MII Management Control 1 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Table of Contents General Description ..................................................1 Block Diagram ..........................................................1 MII Register Description ......................................... 18 - Key to Default ....................................................... 18 Features....................................................................4 Basic Mode Control Register (BMCR) - 00............. 19 Pin Configuration: DM9331 LQFP ............................5 Basic Mode Status Register (BMSR) - 01 .............. 20 Pin Description..........................................................6 Media Converter Interface, 19 pins .......................6 Media Interface, 5 pins ..........................................7 LED Interface, 3 pins .............................................7 Mode, 1 pin ............................................................8 Bias and Clock, 3 pins ...........................................8 Power, 15 pins .......................................................8 Table A ..................................................................8 Auto-negotiation Advertisement Register (ANAR) - 04.......................................................................... 21 LED Configuration.....................................................9 DAVICOM Specified Configuration Register (DSCR) - 16.......................................................................... 23 Functional Description ............................................10 MCI interface .......................................................10 100Base-TX Operation........................................11 100Base-TX Transmit .........................................11 100Base-TX Operation........................................12 4B5B Encoder......................................................12 Scrambler ............................................................12 Parallel to Serial Converter..................................12 NRZ to NRZI Encoder .........................................12 NRZI to MLT-3.....................................................12 MLT-3 Driver........................................................12 4B5B Code Group ...............................................13 100Base-TX Receiver .........................................14 Signal Detect .......................................................14 Adaptive Equalizer ...............................................14 MLT-3 to NRZI Decoder ......................................14 Clock Recovery Module.......................................14 NRZI to NRZ........................................................14 Serial to Parallel...................................................14 Descrambler ........................................................14 Code Group Alignment ........................................14 4B5B Decoder .....................................................15 Auto-Negotiation ..................................................15 MII Serial Management .......................................16 Serial Management Interface ..............................16 Management Interface – Read Frame Structure.16 Management Interface – Write Frame Structure 16 Power Reduced Mode.........................................17 Power Down Mode ..............................................17 Reduced Transmit Power Mode..........................17 Link Fault Propagation ........................................17 2 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05........................................................ 21 Auto-negotiation Expansion Register (ANER) - 06.......................................................................... 22 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 ........................................... 24 DAVICOM Specified Interrupt Register - 21 ........... 25 Absolute Maximum Ratings.................................... 26 Operating Conditions........................................... 26 Comments ........................................................... 26 DC Electrical Characteristics .................................. 27 AC Electrical Characteristics & Timing Waveforms ................................................................................ 28 TP Interface......................................................... 28 Oscillator Timing .................................................. 28 MDC/MDIO Timing .............................................. 28 MDIO Timing when OUTPUT by STA................. 29 MDIO Timing when OUTPUT by DM9331........... 29 Auto-negotiation and Fast Link Pulse Timing Parameters.......................................................... 29 Auto-negotiation and Fast Link Pulse Timing Diagram............................................................... 29 TXD to TP or FX Transmit Latency Timing Diagram ............................................................................ 30 TXD to TP or FX Transmit Latency Parameters. 30 TP or FX to RXD Receive Latency Timing Diagram ............................................................................ 30 TP or FX to RXD Receive Latency Parameters.. 30 Application Notes.................................................... 31 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Network Interface Signal Routing ........................31 1. 100Base-TX Side Application..........................31 2. 100Base-TX Side (Power Reduction Application) .............................................................................32 3. 100Base-FX Side Application..........................33 4. Power Decoupling Capacitors .........................34 5. Ground Plane Layout.......................................35 6. Power Plane Partitioning .................................36 7. Media Converter Interface ...............................37 8. Link Fault Propagation Application ..................38 9. Media Converter or Repeater Application .......39 10. Link Fault Propagation LED Display................40 Magnetics Selection Guide .....................................41 Preliminary Version: DM9331-DS-P02 September 21, 2001 Package Information...............................................42 Ordering Information...............................................43 Disclaimer ...............................................................43 Company Overview.................................................43 Products..................................................................43 Contact Windows....................................................43 Warning ..................................................................43 3 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Features 4 100Base-TX to 100Base-FX media converter application chip set. 100Base-FX to 100Base-FX repeater application chip set under full duplex mode. 100Base-TX to 100Base-TX repeater application chip set under full duplex mode. Optional Fault propagation on no link condition. Fully compliant with IEEE 802.3u 100Base-TX/FX Compliant with ANSI X3T12 TP-PMD 1995 standard Supports Auto-Negotiation function to 100 Mbps full/half duplex, compliant with IEEE 802.3u. Remote fault detection capability Far end fault signaling option in FX mode Selectable twisted-pair or fiber mode output Selectable full-duplex or half-duplex operation Provides Loopback mode for easy system diagnostics LED status outputs indicate Link/Activity, Full/Halfduplex and Fault LED. Single Low-Power Supply of 3.3V with 0.35µm CMOS technology Very Low Power consumption modes: ● Power Reduced mode (cable detection) ● Power Down mode ● Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. Compatible with 3.3V and 5.0V tolerant I/Os 48-pin LQFP small package (1x1 cm) Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Preliminary Version: DM9331-DS-P02 September 21, 2001 CHIPEN NC FAULTLED# DGND MDINTR# DVDD DVDD RXD[0] RXD[1] TPSET0 FXFAULT/TPSET1 MDIO 36 35 34 33 32 31 30 29 28 27 26 25 Pin Configuration RXDV 37 24 MDC NC 38 23 DVDD DVDD 39 22 TXCLK RESET# 40 21 TXEN DVDD 41 20 TXD[0] NC 42 19 TXD[1] OSCIN 43 18 LNKFAULTEN DGND 44 17 LNKFAULT# SD 45 16 DVDD AGND 46 15 DGND BGRESG 47 14 TPFAULT BGRES 48 13 LINK/ACTLED#/OP2 7 8 9 AGND TX+/FXTD+ TX-/FXTD- AVDD LINKLED#/OP1 6 AGND 12 5 11 4 RX-/FXRD- FULL/HALFLED#/OP0 3 10 2 AVDD RX+/FXRD+ PWRDWN 1 AVDD DM9331 5 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Pin Description I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output, U : Pull-up D : Pull-down Media converter interface, 18 pins 6 Pin No. 14 Pin Name TPFAULT I/O Description O Twisted Pair Fault 0 = Twisted pair link fault. 1 = Twisted pair normal work. 17 LNKFAULT# I Link Fault Propagation 0 = Link fault propagation is active. 1 = normal operation. 18 LNKFAULTEN I Link Fault Propagation Enable 0 = Link fault propagation disable. 1 = Link fault propagation enable 20,19 TXD[0:1] I Transmit Data 2-bit data inputs (synchronous to the 50MHz OSCIN). 21 TXEN I 22 TXCLK O 24 MDC I 25 MDIO I/O 26 FXFAULT/ TPSET1 O,Z ,LI (D) 27 TPSET0 Z,LI (D) 29,28 RXD[0:1] Transmit Enable Active high indicates the presence of valid data on the TXD[0:1] for 100Mbps mode Transmit Clock 25MHz transmit clock. Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 2.5MHz Management Data I/O Bi-directional management data that may be provided by the station management entity or the PHY. Fiber Fault 0 = Fiber link fault; Fiber receive far end fault package or fiber disconnect. 1 = Fiber normal work. TPSET1 (reset latch input) 0 = Fiber mode; default pull low. 1 = Twisted pair mode; need 4.7kΩ resistor to pull high. Twisted Pair set (reset latch input) 0 = Fiber mode; default pull low. 1 = Twisted pair mode; need 4.7kΩ resistor to pull high. Receive Data Output 2-bit data outputs (synchronous to the 50MHz OSCIN ) 32 MDINTR# O,Z ,LI (D) O, Z Status Interrupt Output: Asserted low whenever there is a status change (link, speed, duplex). The MDINTR# pin has a high impedance output, a 2.2KΩ pull-high resistor is needed. Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 34 FAULTLED# 36 CHIPEN 37 RXDV 40 RESET# O,Z Link Fault LED Active Low. In TP mode, Indicates TP Fault LED. In FX mode, Indicates FX Fault LED. Z,LI Chip Set Enable (D) Need a 4.7kΩ resistor pull high for enabling a chip set. O,Z Receive Data Valid Asserted high to indicate that the valid data is present on the RXD[0:1]. I Reset Active low input initializes the DM9331. Media interface, 5 pins Pin No. 3,4 Pin Name RX+/FXRD+ RX-/FXRD- 7,8 TX+/FXTD+ TX-/FXTD- 45 SD I/O Description I Differential receive pair/PECL receive pair Differential data is received from the media. Differential Pseudo ECL signal is received from the media in fiber mode. O Differential transmit pair/PECL transmit pair Differential data is transmitted to the media in TP mode. Differential Pseudo ECL signal transmits to the media in fiber mode. I Fiber-optic signal detect PECL signal which indicates whether or not the fiber-optic receive pair is receiving valid signal levels. LED interface, 3 pins Pin No. 11 12 13 I/O Description O Full-Duplex/ Half-Duplex LED ,LI Active states indicate Full-duplex mode. Active states see LED (U) configuration. OP0 : (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9331 according to the Table A. The value is latched into the DM9331 registers at power-up/reset. LINK LED# O Link LED /OP1 ,LI Active states indicate good link. Active states see LED configuration. (U) OP1 : (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9331 according to the Table A. The value is latched into the DM9331 registers at power-up/reset. LINK/ACT LED# O Link LED & Activity LED : /OP2 ,LI Active states indicate good link. It is also an activity LED function when (U) transmitting or receiving data. Active states see LED configuration. OP2 : (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9331 according to the Table A. The value is latched into the DM9331 registers at power-up/reset. Pin Name FULL /HALF LED# /OP0 Preliminary Version: DM9331-DS-P02 September 21, 2001 7 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Mode, 1 pin Pin No. 10 Pin Name PWRDWN I/O Description I Power down control Asserted high to force DM9331 into power down mode. When in power down mode, most of the DM9331 circuit block’s power is turned off, only the MII management interface (MDC, MDIO) logic is available. To leave power down mode, DM9331 need the hardware or software reset with the PWRDWN pin low. Bias and clock, 3 pins Pin No. 47 48 43 Pin Name BGRESG BGRES OSCIN I/O Description P Bandgap Ground I/O Bandgap Voltage Reference Resistor 6.8K ohm I 3.3V 50MHz clock input.must be using 3.3v output oscillators. Pin Name AVDD AGND DVDD I/O P Analog Power P Analog Ground P Digital Power Power, 15 pins Pin No. 1,2,9 5,6,46 16,23,30,31, 39,41 15,33,44 DGND P Description Digital Ground Table A OP2 8 OP1 OP0 Function 0 0 0 0 0 1 Auto negotiation enables 100TX Full/Half capabilities Manually select 100FX HDX 0 1 0 Manually select 100FX FDX 1 0 1 Manually select 100TX HDX Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip LED Configuration LEDs flash once for about 200ms after power-on reset or software reset by writing PHY register. All LED pins are dual function pins, which can be configured as either active high or low by pulling them low or high accordingly. If the pin is pulled high, the LED is active low after reset. Likewise, if the pin is pulled low, the LED is active high. DM9331 VCC 300 Ohm 10K Ohm Pull High for Reset Pull Low for Reset 300 Ohm 10K Ohm Preliminary Version: DM9331-DS-P02 September 21, 2001 9 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Functional Description The DM9331 Fast Ethernet single-chip transceiver, providing the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 100Base-FX module. The DM9331 provides a Media Converter Interface (MCI) as connection interface. The DM9331 performs all PCS (Physical Coding Sublayer), PMA (Physical Media Access), TP-PMD (Twisted Pair Physical Medium Dependent) sublayer and a PECL compliant interface for a fiber optic module. Figure 1 shows the major functional blocks implemented in the DM9331. 100Base-TX/FX Transmitter Media Converter Interface (MCI) 100Base-TX/FX Receiver MII Serial Management Interface Auto Negotiation Figure 1 MCI Interface The DM 9331 provides a Media Converter Interface (MCI) . The purpose of the MCI interface is to provide a simple, easy to implement connection to another DM9331. The MCI consists of a 2 bits receive data bus, a two bits transmit data bus, and control signals to facilitate data transfers between the two DM9331 chips. • • 10 TXD (transmit data) is a two bits of data that are driven by the reconciliation sublayer synchronously with respect to OSCIN clock For each OSCIN clock period which TXEN is asserted, TXD (1:0) are accepted for transmission by the PHY. RXDV signal reconciliation sublayer indicates that data are being presented on the MCI for transmission on the physical medium. • RXD (receive data) is a two bits of data that are sampled by the reconciliation sublayer synchronously with respect to OSCIN clock. For each OSCIN clock period which RXDV is asserted, RXD (1:0) are transferred from the PHY to another DM9331. • RXDV (receive data valid) output to another DM9331 TXEN signal indicates that the DM9331 is data ready. TXEN (transmit enable) input from another DM9331 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip chip set. 100Base-TX Operation The 100Base-TX transmitter receives 2-bits data clocked in at 50MHz from the MCI, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The onchip clock circuit converts the 25MHz clock into a 125MHz clock for internal use. These two busses include various controls and signal indications that facilitate data transfers between the DM9331 100Base-TX Transmit The 100Base-TX transmitter consists of the functional blocks shown in figure 2. The 100Base-TX transmit section converts 2-bits synchronous data provided by the MCI to a scrambled MLT-3 125 million symbols per second serial data stream. 50M OSCI LED1-3# LED Driver TX CGM 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver TX± Rise/Fall Time CTL 25M CLK 125M CLK MCI Signals MCI Interface/ Control 4B/5B Decoder Codegroup Alignment Descrambler Serial to Parallel NRZI to NRZ MLT-3 to NRZI Adaptive EQ RX± RX CRM Digital Logic RX± Auto-Negotiation TX/RX Module TX± Register Figure 2 Preliminary Version: DM9331-DS-P02 September 21, 2001 11 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 100Base-TX Operation The block diagram in figure 2 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Encoder - NRZI to MLT-3 - MLT-3 Driver cable in 100Base-TX operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, reference Table 1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair (01101 00111) indicating end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9331 includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair 12 Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI Encoder block NRZ to NRZI Encoder After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. NRZI to MLT-3 The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3 signal. Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 4B5B Code Group Symbol Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F 4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5B code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H Idle SFD (1) SFD (2) ESD (1) ESD (2) Error undefined 0101 0101 undefined undefined undefined 11111 11000 10001 01101 00111 00100 V V V V V V V V V V Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Table 1 Preliminary Version: DM9331-DS-P02 September 21, 2001 13 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 100Base-TX Receiver MLT-3 to NRZI Decoder The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 2-bit nibble data that is then provided to the MCI. The DM9331 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The receive section contains the following functional blocks: The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder. - Signal Detect - Digital Adaptive Equalizer - MLT-3 to NRZI Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX Standards for both voltage thresholds and timing parameters. Adaptive Equalizer When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 14 Clock Recovery Module NRZI to NRZ The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. Serial to Parallel The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the descrambler. Descrambler Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R symbols). The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. Auto-Negotiation The objective of Auto-negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Autonegotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device Preliminary Version: DM9331-DS-P02 September 21, 2001 to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined. If it is discovered that the signal matches a technology that the receiving device supports, a connection will be automatically established using that technology. This allows devices that do not support Auto-negotiation but support a common mode of operation to establish a link. 15 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers. MII Serial Management The MII serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, get status and error information, and determine the type and capabilities of the attached PHY device(s). Serial Management Interface The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock), and MDI/O (Management Data Input/Output) signals. The DM9331 management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, and 18. In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code The MDIO pin is bi-directional and may be shared by up to 32 devices. Management Interface - Read Frame Structure MDC MDIO Read 32 "1"s Idle 0 Preamble 1 SFD 1 0 A4 Op Code A3 A0 PHY Address R4 R3 R0 Register Address 0 Z D15 Turn Around // // D14 D1 D0 Data Read Write Idle Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle Preamble 0 1 SFD 0 1 Op Code A4 A3 PHY Address A0 R4 R3 R0 Register Address Write 1 0 Turn Around D15 D14 Data D1 D0 Idle Figure 5 16 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Power Reduced Mode The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable disconnection, DM9331 will automatically turn off the power and enter the Power Reduced mode, regardless of its operation mode being N-way auto-negotiation or forced mode. While in the Power Reduced mode, the transmit circuit will continue sending out fast link pules with minimum power consumption. If a valid signal is detected from the media, which might be N-way fast link pules, 10Base-T normal link pules, or 100Base-TX MLT3 signals, the device wakes up and resumes normal operation mode. Automatic reduced power down mode can be disabled by writing Zero to Reg.16.4. Power Down Mode Power Down mode is entered by setting Reg.0.11 to ONE or pulling PWRDWN pin high, which disables all transmit, receive functions and MCI interface functions except the MDC/MDIO management interface. Reduced Transmit Power Mode Preliminary Version: DM9331-DS-P02 September 21, 2001 Additional Transmit power reduction can be gained by designing with 1.25:1 turns ration magnetics on its TX side and using a 8.5KΩ resistor on BGRES and BGRESG pins, and the TX+/TX- pull-high resistors being changed from 50 Ω to 78Ω. This configuration could reduce about 20% of transmit power. Link Fault Propagation The DM9331 will propagate link fault signals from media to another DM9331. If link fault happens, the DM9331 will send out fault signals to another DM9331. In FX mode, their are two types of link failure, receive link failure or remote fault (receive far end fault).In the event of a fiber receive link failure, the DM9331 will send out an FX fault signal. The DM9331 will send out a far end fault signal to the fiber optic media, if the DM9331 receive the fault signal from the other device. In TP mode, In the event of a TP receive link failure, the DM9331 will send out a TP fault signal. The DM9331 will stop to transmit idle signal to the CAT5 media, if the DM9331 receive the fault signal from the other device. 17 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip MII Register Description ADD Name 00 CONTROL 01 04 05 06 16 17 21 15 Reset 14 13 12 11 10 9 Loop Speed Auto-N Power Isolate Restart back select Enable Down Auto-N STATUS T4 TX FDX TX HDX Reserved Cap. Cap. Cap. Auto-Neg. Next FLP Rcv Remote Reserved FC T4 Advertise Page Ack Fault Adv Adv Link Part. LP Next LP LP Reserved LP LP Ability Page Ack RF FC T4 Auto-Neg. Reserved Expansion Aux. BP BP BP BP_A Rsvd TX/FX FEF Config. 4B5B SCR ALIGN DPOK Select Enable Aux. 100 100 Reserved Conf/Stat FDX HDX MDINTR INTR Reserved FDX Rsvd Link PEND Mask Mask 8 Full Duplex 7 Coll. Test 6 5 4 3 2 Reserved 1 Pream. Auto-N Remote Auto-N Link Rsvd Extd Supr. Compl. Fault Cap. Status Cap. TX FDX TX HDX Rsvd Rsvd Advertised Protocol Selector Field Adv Adv LP LP LP LP Link Partner Protocol Selector Field TX FDX TX HDX 10 FDX 10 HDX Pardet LP Next Next Pg New Pg LP AutoN Fault Pg Able Able Rcv Cap. RMCI Force SPDLE Rsvd RPDCT Reset Pream. Sleep Remote Enable 100LNK D_CTL R-EN St. Mch Supr. mode LoopOut Reserved Auto-N. Monitor Bit [3:0] INTR Mask Reserved FDX Rsvd Link Rsvd Change Change Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> <Access Type>: RO = Read only RW = Read/Write Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high 18 0 Preliminary Version: DM9331-DS-P02 September 21, 2001 INTR Status DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Basic Mode Control Register (BMCR) - 00 Bit 0.15 Bit Name Reset Default 0, RW/SC 0.14 Loopback 0, RW 0.13 Speed selection 1, RW 0.12 Auto-negotiation enable 1, RW 0.11 Power down 0, RW 0.10 Isolate 0,RW 0.9 Restart autonegotiation 0,RW/SC 0.8 Duplex mode 1,RW Preliminary Version: DM9331-DS-P02 September 21, 2001 Description Reset: 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed Loopback: Loop-back control register 1 = Loop-back enabled 0 = Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the MCI receive outputs Speed select: 1 = 100Mbps 0 = invalid Auto-negotiation enable: 1 = Auto-negotiation is enabled, bit 8 and 13 will be in autonegotiation status. Power Down: While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MCI. 1=Power down 0=Normal operation Isolate: 1 = Isolates the DM9331 from the MCI with the exception of the serial management. (When this bit is asserted, the DM9331 does not respond to the TXD[0:1] and TXEN inputs, and it shall present a high impedance on its TXCLK, RXDV, and RXD[0:1] outputs. When the PHY is isolated from the MCI, it shall respond to the management transactions) 0 = Normal operation Restart auto-negotiation: 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning a value of 1 until autonegotiation is initiated by the DM9331. The operation of the autonegotiation process will not be affected by the management entity that clears this bit 0 = Normal operation Duplex mode: 1 = Full duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With autonegotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation 19 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 0.7 Collision test 0,RW 0.6-0.0 Reserved 0,RO Collision test: 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TXEN 0 = Normal operation Reserved: Write as 0, ignore on read Basic Mode Status Register (BMSR) - 01 Bit 1.15 Bit Name 100BASE-T4 Default 0,RO/P 1.14 100BASE-TX full duplex 1,RO/P 1.13 100BASE-TX half duplex 1,RO/P 1.12 1.11 1.10-1.7 Reserved Reserved Reserved 0,RO/P 0,RO/P 0,RO 1.6 MF preamble suppression 0,RO 1.5 Autonegotiation Complete Remote fault 0,RO 1.4 1.3 1.2 1.1 1.0 20 Autonegotiation ability Link status Reserved Extended capability 0, RO/LH 1,RO/P 0,RO/LL 0,RO/LH 1,RO/P Description 100BASE-T4 capable: 1 = DM9331 is able to perform in 100BASE-T4 mode 0 = DM9331 is not able to perform in 100BASE-T4 mode 100BASE-TX full duplex capable: 1 = DM9331 is able to perform 100BASE-TX in full duplex mode 0 = DM9331 is not able to perform 100BASE-TX in full duplex mode 100BASE-TX half duplex capable: 1 = DM9331 is able to perform 100BASE-TX in half duplex mode 0 = DM9331 is not able to perform 100BASE-TX in half duplex mode Reserved Reserved Reserved: Write as 0, ignore on read MII frame preamble suppression: 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed Auto-negotiation complete: 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed Remote fault: 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9331 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected Auto configuration ability: 1 = DM9331 is able to perform auto-negotiation 0 = DM9331 is not able to perform auto-negotiation Link status: 1 = Valid link is established (for 100Mbps operation) 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface Reserved Extended capability: 1 = Extended register capable. 0 = Basic register capable only Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9331 device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Bit Name NP 4.14 ACK 4.13 RF 4.12-4.11 Reserved 4.10 FCS 4.9 T4 4.8 TX_FDX 4.7 TX_HDX 4.6 4.5 4.4-4.0 Reserved Reserved Selector Default 0,RO/P Description Next page indication: 0 = No next page available 1 = Next page available The DM9331 has no next page, so this bit is permanently set to 0 0,RO Acknowledge: 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9331's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. 0, RW Remote fault: 1 = Local device senses a fault condition 0 = No fault detected 0, RW Reserved: Write as 0, ignore on read 0, RW Flow control support: 1 = Controller chip supports flow control ability 0 = Controller chip doesn’t support flow control ability 0, RO/P 100BASE-T4 support: 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The DM9331 does not support 100BASE-T4 so this bit is permanently set to 0 1, RW 100BASE-TX full duplex support: 1 = 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX full duplex is not supported 1, RW 100BASE-TX support: 1 = 100BASE-TX is supported by the local device 0 = 100BASE-TX is not supported 0, RW Reserved 0, RW Reserved <00001>, RW Protocol selection bits: These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit 5.15 Bit Name NP Default 0, RO 5.14 ACK 0, RO Preliminary Version: DM9331-DS-P02 September 21, 2001 Description Next page indication: 0 = Link partner, no next page available 1 = Link partner, next page available Acknowledge: 1 = Link partner ability data reception acknowledged 21 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 5.13 RF 5.12-5.11 Reserved 5.10 FCS 5.9 T4 5.8 TX_FDX 5.7 TX_HDX 5.6 10_FDX 5.5 10_HDX 5.4-5.0 Selector 0 = Not acknowledged The DM9331's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. 0, RO Remote Fault: 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner X, RO Reserved: Write as 0, ignore on read 0, RW Flow control support: 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesn’t support flow control ability by link partner 0, RO 100BASE-T4 support: 1 = 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 is not supported by the link partner 0, RO 100BASE-TX full duplex support: 1 = 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX full duplex is not supported by the link partner 0, RO 100BASE-TX support: 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 0, RO 10BASE-T full duplex support: 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 0, RO 10BASE-T support: 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link partner <00000>, RO Protocol selection bits: Link partner’s binary encoded protocol selector Auto-negotiation Expansion Register (ANER)- 06 6.15-6.5 Reserved X, RO 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 0, RO 6.2 NP_ABLE 0,RO/P 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE 0, RO 22 Reserved: Write as 0, ignore on read Local device parallel detection fault: PDF = 1 : A fault detected via parallel detection function. PDF = 0 : No fault detected via parallel detection function Link partner next page able: LP_NP_ABLE = 1 : Link partner, next page available LP_NP_ABLE = 0 : Link partner, no next page Local device next page able: NP_ABLE = 1 : DM9331, next page available NP_ABLE = 0 : DM9331, no next page DM9331 does not support this function, so this bit is always 0. New page received: A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management. Link partner auto-negotiation able: A “1” in this bit indicates that the link partner supports Autonegotiation. Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip DAVICOM Specified Configuration Register (DSCR) - 16 Bit 16.15 Bit Name BP_4B5B Default 0, RW 16.14 BP_SCR 0, RW 16.13 BP_ALIGN 0, RW 16.12 BP_ADPOK 0, RW 16.11 16.10 Reserved TX 0,RW 1, RW 16.9 FEF 0, RW 16.8 Reserved 1, RW 16.7 F_LINK_100 0, RW 16.6 Reserved 0, RW 16.5 Reserved 0, RO 16.4 RPDCTR-EN 1, RW 16.3 SMRST 0, RW 16.2 MFPSC 0, RW 16.1 SLEEP 0, RW Preliminary Version: DM9331-DS-P02 September 21, 2001 Description Bypass 4B5B encoding and 5B4B decoding : 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation Bypass scrambler/descrambler function : 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation Bypass symbol alignment function: 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions ( symbol encoder and scrambler) bypassed 0 = Normal operation BYPASS ADPOK : Force signal detector (SD) active. This register is for debug only, not release to customer. 1=Force SD is OK, 0=Normal operation Reserved 100BASE-TX or FX mode control: 1 = 100BASE-TX operation 0 = 100BASE-FX operation Far End Fault enable : Control the Far End Fault mechanism associated with 100Base-FX operation. 1 = Enable 0 = Disable Reserved: Write as 1. Force good link in 100Mbps: 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes. Reserved: Write as 0. Reserved: Write as 0, ignore on read. Reduced power down control enable: This bit is used to enable automatic reduced power down. 0: Disable automatic reduced power down. 1: Enable automatic reduced power down. Reset state machine: When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed. MF preamble suppression control: MCI frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Sleep mode: 23 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 16.0 RLOUT 0, RW Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote loopout control: When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit 17.15 Bit Name 100FDX Default 1, RO 17.14 100HDX 1, RO 17.13 17.12 17.1117.9 17.8-17.4 17.3-17.0 Reserved Reserved Reserved 0, RO 0, RO 0, RO Reserved ANMB[3:0] 0, RW 0, RO Description 100M full duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. 100M half duplex operation mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half-duplex mode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. Reserved Reserved Reserved: Read as 0, ignore on write Reserved. Auto-negotiation monitor bits: These bits are for debug only. The auto-negotiation status will be written to these bits. B3 b2 b1 b0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 24 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail Auto-negotiation completed successfully Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip DAVICOM Specified Interrupt Register – 21 Bit 21.15 Bit Name INTR PEND Default 0, RO 21.1421.12 21.11 Reserved 0, RO FDX mask 1, RW 21.10 21.9 Reserved LINK mask 1, RW 1, RW 21.8 INTR mask 1, RW 21.7-21.5 21.4 Reserved FDX change 0, RO 0,RO/LH 21.3 21.2 Reserved LINK change 0, RO/LH 0, RO/LH 21.1 Reserved 0, RO 21.0 INTR status 0, RO/LH Preliminary Version: DM9331-DS-P02 September 21, 2001 Description Interrupt pending : Indicates that the interrupt is pending and is cleared by the current read. This bit shows the same result as bit 0. (INTR Status) Reserved Full-duplex interrupt mask : When this bit is set, the Duplex status change will not generate the interrupt Reserved Link interrupt mask : When this bit is set, the link status change will not generate the interrupt Master interrupt mask : When this bit is set, no interrupts will be generated under any condition. Reserved Duplex status change interrupt : “1” indicates a change of duplex since last register read. A read of this register will clear this bit. Reserved Link status change interrupt : “1” indicates a change of link since last register read. A read of this register will clear this bit. Reserved Interrupt status : The status of MDINTR#. “1” indicates that the interrupt mask is off that one or more of the change bits are set. A read of this register will clear this bit. 25 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Absolute Maximum Ratings Absolute Maximum Ratings ( 25°°C ) Symbol DVCC, AVCC VIN VOUT Tstg Tc LT Parameter Supply Voltage DC Input Voltage (VIN) DC Output Voltage(VOUT) Storage Temperature Rang (Tstg) Case Temperature Lead Temp. (TL, Soldering, 10 sec.) Min. -0.3 -0.5 -0.3 -65 0 --- Max. 3.6 5.5 3.6 +125 85 235 Unit V V V °C °C °C Min. 3.135 ０ 0 ----------- Max. 3.465 70 85 88 25 45 18 3 Unit V °C °C mA mA mA mA mA Conditions EIAJ-4701B JEDEC J-STD-020A Operating Conditions Symbol DVCC,AVCC TA Tc PD (Power Dissipation) Parameter Supply Voltage Operating Ambient Temperature Case Temperature 100BASE-TX 100BASE-FX Auto-negotiation Power Reduced Mode (without cable ) Power Down Mode Conditions As TA = 70°C 3.3V 3.3V 3.3V 3.3V 3.3V Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any 26 other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip DC Electrical Characteristics (VCC = 3.3V, TA = 0 ~ 70°C) Symbol Parameter Min. Typ. Max. Unit Conditions TTL Inputs (TXD0, TXD1, TXEN, LNKFAULTPROG, LNKFAULTEN, MDC, MDIO,CHIPEN, OPMODE0-2, TPSET0, TPSET1, DISFEF,SCRAMEN, RESET# ) VIL Input Low Voltage ----0.8 V VIH Input High Voltage 2.0 ----V IIL Input Low Leakage Current ----10 uA VIN = 0.4V IIH Input High Leakage Current -----10 uA VIN = 2.7V MCI TTL Outputs ( RXD0, RXD1, RXDV, RXER,TPFAULT, FXFAULT MDIO) VOL Output Low Voltage ----0.4 V IOL = 4mA VOH Output High Voltage 2.4 ----V IOH = -4mA Non-MCI TTL Outputs (LINKLED#, ACTIVELED#, FULL/HALFLED#, FAULTLED#, MDINTR#) VOL Output Low Voltage ----0.4 V IOL = 2mA VOH Output High Voltage 2.4 ----V IOH = -2mA Receiver VICM RX+/RX- Common mode Input Voltage --1.2 --V 100 Ω Termination Across Transmitter VTD100 100TX+/- Differential Output Voltage 1.9 2.0 2.1 V Peak to Peak ITD100 100TX+/- Differential Output Current │19│ │20│ │21│ mA VOH PECL Output Voltage – High VCCV VCC0.88 1.05 VOL PECL Output Voltage – Low VCCVCCV 1.81 1.62 VIH PECL Input Voltage – High VCCV VCC0.88 1.16 VIL PECL Input Voltage – Low VCCV VCC1.48 1.81 IFD100 100FX+/- Differential Output Current │17│ │18│ │19│ mA Preliminary Version: DM9331-DS-P02 September 21, 2001 27 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip AC Electrical Characteristics & Timing Waveforms TP Interface Symbol tTR/F tTM tTDC tT/T XOST Parameter 100TX+/- Differential Rise/Fall Time 100TX+/- Differential Rise/Fall Time Mismatch 100TX+/- Differential Output Duty Cycle Distortion 100TX+/- Differential Output Peak-to-Peak Jitter 100TX+/- Differential Voltage Overshoot Min. 3.0 0 0 Typ. ------- Max. 5.0 0.5 0.5 Unit ns ns ns 0 0 ----- 1.4 5 ns % Min. 19.998 8 8 Typ. 20 10 10 Max. 20.002 12 12 Unit ns ns ns Conditions Oscillator Timing Symbol tCKC tPWH tPWL Parameter OSC Cycle Time OSC Pulse Width High OSC Pulse Width Low Conditions 50ppm MDC/MDIO Timing Symbol t0 t1 t2 t3 Parameter MDC Cycle Time MDIO Setup Before MDC MDIO Hold After MDC MDC To MDIO Output Delay Min. 80 10 10 0 Typ. --------- Max. ------300 Unit ns ns ns ns Conditions When OUTPUT By STA When OUTPUT By STA When OUTPUT By DM9331 MDIO timing when OUTPUT by STA MDC t0 10ns (Min) t1 10ns (Min) t2 MDIO 28 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip MDIO timing when OUTPUT by DM9331 t0 MDC 0 - 300 ns t3 MDIO Auto-negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 - Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses in a Burst Min. --55.5 111 8 17 Typ. 100 62.5 125 2 Max. --69.5 139 24 33 Unit ns us us ms ms pulse Conditions DATA = 1 Auto-negotiation and Fast Link Pulse Timing Diagram Clock Pulse FAST LINK PULSES Data Pulse Clock Pulse t1 t1 t2 t3 FLP Burst FLP Bursts FLP Burst t4 t5 Preliminary Version: DM9331-DS-P02 September 21, 2001 29 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip TXD to TP or FX Transmit Latency Timing Diagram TXD [1:0] td TX± TXD to TP or FX Transmit Latency Parameters Symbol td Parameter TXD[1:0] to TX± or FXTD± ( TX Latency ) Min. - Typ. - Max. 165 Unit ns Conditions Min. - Typ. - Max. 205 Unit ns Conditions TP or FX to RXD Receive Latency Timing Diagram RX± td RXD [1:0] TP or FX to RXD Receive Latency Parameters Symbol td 30 Parameter RX± or FXRD± to RXD[1:0] ( RX Latency ) Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Application Notes Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9331 RX± and TX± pins. Traces routed from RX± and TX± to the transformer should run in close pairs directly to the transformer. The designer should be careful not to place the transmit pair across the receive pair. As always, vias should be avoided as much as possible. The network interface should be void of any signals other than the TX± and RX± pairs between the RJ-45 to the transformer and the transformer to the DM9331. There should be no power or ground planes in the area under the network side of the transformer to include the area under the RJ-45 connector. (Refer to Figure 5 and 6.) Keep chassis ground away from all active signals. The RJ-45 connector and any unused pin should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor. The Band Gap resistor should be placed as physically close to pins 47 and 48 as possible. (Refer to Figure 1, 2, 3-1, and 3-2). The designer should not run any high-speed signal near the Band Gap resistor placement. 1. 100Base-TX Side Application RX+ RX- Transformer 3 50Ω 1% RJ45 1:1 4 1 0.1µF 50Ω 1% 2 AGND 3 3.3V AVCC 0.1µF DM9331 0.1µF 50Ω 1% TX+ TX- 4 AGND AGND 1:1 7 50Ω 1% 5 6 3.3V AVCC 7 8 8 0.1µF BGRES 47 BGRESG 48 75Ω 1% AGND 6.8KΩ, 1% 75Ω 1% 75Ω 1% 75Ω 1% 0.1µF/2KV or 0.01µF/2KV Chasis GND Figure 1 Preliminary Version: DM9331-DS-P02 September 21, 2001 31 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 2. 100Base-TX Side (Power Reduction Application) RX+ RX- Transformer 3 50Ω 1% RJ45 1:1 1 4 0.1µF 2 50Ω 1% AGND 3.3V AVCC 3 0.1µF DM9331 TX+ TX- 4 0.1µF 78Ω 1% 5 AGND AGND 7 78Ω 1% 1.25:1 6 3.3V AVCC 7 8 8 0.1µF BGRES BGRESG 47 48 75Ω 1% AGND 8.5KΩ, 1% 75Ω 1% 75Ω 1% 75Ω 1% 0.1µF/2KV or 0.01µF/2KV Chasis GND Figure 2 32 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 3. 100Base-FX Side Application FXVCC (3.3V) 127Ω FXRD+ 83Ω 127Ω FXRD- 3.3V Fiber Transceiver 1 GND_RX FXVCC (3.3V) AGND 83Ω 127Ω 3 RDAGND SD 83Ω FXVCC (3.3V) DM9331 2 RD+ 4SD FXVCC (3.3V) FXVCC (3.3V) AGND 69Ω 5VCC_RX 6VCC_TX 7TD- FXTD- 182Ω 8TD+ 69Ω AGND FXTD+ 9GND_TX 182Ω BGRES BGRESG AGND AGND 6.8KΩ, 1% Figure 3-1 FXVCC (5V) 83Ω FXRD+ 83Ω FXRD- FXVCC (5V) 59Ω 68Ω 59Ω 83Ω 59Ω FXVCC (5V) DM9331 68Ω 62Ω 1 GND_RX 2 RD+ AGND 68Ω AGND SD 5V Fiber Transceiver FXVCC (5V) FXVCC (5V) 3 RD4SD 5VCC_RX 6VCC_TX AGND 7TDFXTD- 268Ω 8TD+ 62Ω AGND FXTD+ 9GND_TX 268Ω BGRES BGRESG AGND AGND 6.8KΩ, 1% Figure 3-2 Preliminary Version: DM9331-DS-P02 September 21, 2001 33 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 4. Power Decoupling Capacitors Davicom Semiconductor recommends all the decoupling capacitors for all power supply pins are placed as close as possible to the power pads of the DM9331 (The best placed distance is < 3mm from the above mentioned pins). The recommended decoupling capacitance is 0.1µF or 0.01µF, as required by the design layout. 41 39 1 2 31 DM9331 30 23 16 9 Figure 4 34 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 5. Ground Plane Layout A single ground plane approach is recommended to minimize EMI. Bad ground plane partitioning can cause more EMI emissions that could make the network interface card not compliant with specific FCC regulations (part 15). Figure 5 shows a recommended ground layout scheme. Figure 5 Preliminary Version: DM9331-DS-P02 September 21, 2001 35 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 6. Power Plane Partitioning The power planes are approximately illustrated in Figure 6. The ferrite bead used should have an impedance at least 75 Ω at 100MHz. A suitable bead is the Panasonic surface mound bead, part number EXCCL4532U or an equivalent. A 10µF electrolytic bypass capacitors should be connected between VCC and Ground at each side of the ferrite bead. Figure 6 36 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 7. Media Converter Interface Through the Media Converter Interface (MCI), the DM9331 connects to another DM9331 for the FX to TP media converter or FX to FX, TP to TP repeater application. 50MHz VCC VCC 4.7K OSCIN TPSET0 RXDV FXRD± TPSET1 TXEN TXD[0:1] RXD[0:1] DM9331 TX± DM9331 TXD[0:1] FXTD± 4.7K OSCIN RX± RXD[0:1] TXEN RXDV FX mode TP mode 50MHz OSCIN OSCIN RXDV FXRD± TXEN TXD[0:1] RXD[0:1] DM9331 TXD[0:1] FXTD± RXDV FX mode FX mode 50MHz VCC 4.7K RX± VCC 4.7K 4.7K OSCIN TPSET0 TPSET1 RXDV TPSET1 TXEN TXD[0:1] RXD[0:1] DM9331 TX± DM9331 TXD[0:1] TX± VCC 4.7K OSCIN TPSET0 FXRD± RXD[0:1] TXEN VCC FXTD± DM9331 RXD[0:1] TXEN RX± RXDV TP mode TP mode Figure 7 Preliminary Version: DM9331-DS-P02 September 21, 2001 37 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 8. Link Fault propagation Application The DM9331 will propagate link fault signals from media to another DM9331. If link fault happens, the DM9331 will send out fault signal to another DM9331. In FX mode, there are two types of link failures, receive link failure or remote fault (receive far end fault). In the event of a fiber receive link failure, the DM9331 will send out an FX fault signal. The DM9331 will send out a far end fault signal to the fiber optic media, if the DM9331 receive the fault signal from the other device. In TP mode, in the event of a TP receive link failure, the DM9331 will send out a TP fault signal. The DM9331 will stop to transmit idle signal to the CAT5 media, if the DM9331 receive the fault signal from the other device. VCC VCC VCC VCC 4.7K TPSET0 LNKFAULTEN FXRD± TPFAULT DM9331 (MCI) FX mode TP mode VCC VCC LNKFAULTEN LNKFAULTEN FXFAULT LNKFAULT# DM9331 (MCI) FX mode FX mode VCC VCC VCC TPSET0 RX± VCC VCC 4.7K 4.7K 4.7K TPSET1 TPSET0 LNKFAULTEN TPSET1 LNKFAULTEN TPFAULT LNKFAULT# DM9331 TX± FXRD± LNKFAULT# (MCI) 4.7K FXTD± DM9331 FXFAULT VCC RX± LNKFAULT# (MCI) FXTD± TX± DM9331 FXFAULT FXRD± TPSET1 LNKFAULTEN LNKFAULT# FXTD± 4.7K TX± DM9331 TPFAULT LNKFAULT# (MCI) RX± (MCI) TP mode TP mode Figure 8 38 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 9. Media Converter or Repeater Application The DM9331 chip set can easily use media converters or repeaters for long distance device connection. You can use two media converters to connect two devices whose distance is 2.2km. See Figure 9-1. If the distance is more Converter Cat5 SW than 2.2km, you can add an FX repeater to extend distance. See Figure 9-2. In the last miles, if the distance of the user device is more than 100m, you can add TP repeaters to extend the distance to 400m. See figure 9-3. Converter Fiber Optic DM9331 DM9331 TP Converter Cat5 SW FX DM9331 DM9331 TP FX Repeater FX TP extend the distance Fiber Optic ∫ ∫ DM9331 DM9331 FX SW DM9331 DM9331 Figure 9-1 Fiber Optic Cat5 ∫ ∫ FX Converter Cat5 sw DM9331 DM9331 FX TP under full-duplex mode Figure 9-2 Repeater Cat5 SW DM9331 DM9331 TP TP Cat5 Repeater extend the distance DM9331 DM9331 TP TP Cat5 ∫ ∫ ∫ ∫ Repeater User Cat5 DM9331 DM9331 TP DM9102A NIC TP under full-duplex mode Figure 9-3 Preliminary Version: DM9331-DS-P02 September 21, 2001 39 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip 10. Link Fault Propagation LED Display converter (LC), remote converter (RC) and remote device (RD), and three segments of transmit and receive connection. Table 10 lists the LED status of all devices. It shows the current link status of all the devices when they are at auto-negotiation modes. Since the media converter is a “dummy” device, the link fault propagation becomes very important. The devices at the both ends need to know whether the link is OK or Non-OK on the whole path. Figure 10 shows the DM9331 to the DM9331 connection. The whole path is separated into local device (LD), local Local Device LT Local Converter FT DM9331 DM9331 LD Remote Converter TP RC FX Remote Device DM9331 DM9331 LC LR RT FR FX TP RR RD Figure 10 Local Local Converter Remote Converter Remote Condition device device (autoTP side FX side FX side TP side Link Link negotiation ) LED Link LED Fault LED Link LED Fault LED Link LED Fault LED Link LED Fault LED LED LT disconnect off off on on off on on off off off LR disconnect off off off on off on off on off on LT & LR off off on on off on on off off off disconnect FT disconnect off off off on on off on off off off FR disconnect off off off off on on on off off off FT & FR off off off off on off on off off off disconnect RT disconnect on on off on off on off off off off RR disconnect off off off on on on off off on off RT & RR off off off on on on off off on off disconnect Table 10 40 Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Magnetics Selection Guide Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should test and qualify Manufacturer Pulse Engineering Delta YCL Halo Nano Pulse Inc. Fil-Mag Bel Fuse Valor Macronics all magnetics before using them in an application. The transformers listed in Table 2 are electrical equivalents, but may not be pin-to-pin equivalents. Part Number PE-68515, H1078, H1012 H1102 LF8200, LF8221x 20PMT04, 20PMT05 TG22-3506ND, TD22-3506G1, TG22-S010ND TG22-S012ND NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PT41715 S558-5999-01 ST6114, ST6118 HS2123, HS2213 Table 2 Preliminary Version: DM9331-DS-P02 September 21, 2001 41 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Package Information unit: inches/mm LQFP 48L (F.P. 2mm) Outline Dimensions y Symbol Dimensions in inches Min. Max. Dimensions in mm Min. Nom. Max. A - - 0.063 - - 1.6 A1 0.002 - 0.006 0.05 - 0.15 A2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 b1 0.007 0.008 0.009 0.17 0.20 0.23 C 0.004 - 0.008 0.09 - 0.20 C1 0.004 - 0.006 0.09 - 0.16 D 0.354BSC 9.00BSC D1 0.276BSC 7.00BSC E 0.354BSC 9.00BSC E1 0.276BSC 7.00BSC e L 0.020BSC 0.018 L1 0.024 0.50BSC 0.030 0.45 0.039REF y Θ 42 Nom. 0.004MAX 0º - 0.60 0.75 1.00REF Notes: 1. To be determined at seating plane. 2. Dimensions D1 and E 1do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimensions b do not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 4. Exact shape of each corner is optional. 5. These dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. Controlling dimension: millimeter. 8. Reference documents: JEDEC MS-026 , BBC. 0.1MAX 12º 0º - 12º Preliminary Version: DM9331-DS-P02 September 21, 2001 DM9331 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip Ordering Information Part Number DM9331E Pin Count 48 Package LQFP DAVICOM’s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM deserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858 Taipei Sales & Marketing Office: 8F, No. 3, Lane 235, Bao-chiao Rd., Hsin-tien, Taipei, Taiwan, R.O.C. TEL: 02-29153030 FAX: 02-29157575 Email: [email protected] Web Site: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Preliminary Version: DM9331-DS-P02 September 21, 2001 43