DM5866 960H and 720H 4 channels NTSC/PAL Decoder DAVICOM Semiconductor, Inc. DM5866 960H and 720H 4 channels NTSC/PAL Decoder DATA SHEET Final Version: DM5866-DS-F01 August 19, 2015 Final Doc No: DM5866-DS-F01 August 19, 2015 1 DM5866 960H and 720H 4 channels NTSC/PAL Decoder REVISION HISTORY: Date Revision Description 2012/02/02 1.1 Initial release 2012/02/04 1.2 Application schematics modified Final Doc No: DM5866-DS-F01 August 19, 2015 2 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Table of Contents INTRODUCTION .....................................................................................................................6 FEATURES ....................................................................................................................................... 7 APPLICATIONS ................................................................................................................................. 8 TERMINAL ASSIGNMENT ........................................................................................................9 TERMINAL FUNCTIONS.................................................................................................................... 10 BLOCK DIAGRAM ................................................................................................................. 15 VIDEO DECODER .................................................................................................................. 16 VIDEO INTERFACE .......................................................................................................................... 16 Multi-channel Time Division Multiplexing ............................................................................ 17 4-CH VIDEO DECODER ................................................................................................................... 19 VIDEO DECODER UNIT .................................................................................................................... 20 Video Synchronization .......................................................................................................... 20 Automatic Gain Control ........................................................................................................ 20 Y/C Separation ...................................................................................................................... 21 UV demodulation .................................................................................................................. 21 Luma/Chroma Processor ...................................................................................................... 21 Video Interface ..................................................................................................................... 21 Fast Switch Parameter RAM ................................................................................................. 21 FILTER RESPONSE ........................................................................................................................... 22 Anti-alias LPF (960H) ............................................................................................................. 22 Decimation filter (960H) ....................................................................................................... 22 Luma notch filter (960H)....................................................................................................... 23 Chroma band pass filter (960H) ............................................................................................ 23 Y sharpness filter (960H)....................................................................................................... 24 UV demodulation low pass filter (960H) .............................................................................. 25 Final Doc No: DM5866-DS-F01 August 19, 2015 3 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Anti-alias LPF (720H) ............................................................................................................. 25 Decimation filter (720H) ....................................................................................................... 26 Luma notch filter (720H)....................................................................................................... 26 Chroma band pass filter (720H) ............................................................................................ 27 Y sharpness filter (720H)....................................................................................................... 27 UV demodulation low pass filter (720H) .............................................................................. 28 AUDIO CODEC ...................................................................................................................... 29 DIGITAL AUDIO FORMAT ................................................................................................................. 31 EXTENDED DIGITAL AUDIO FORMAT ................................................................................................. 32 CASCADE MODE FOR MULTI-CHIP OPERATION ................................................................................... 33 PLL ...................................................................................................................................... 35 HOST INTERFACE.................................................................................................................. 36 CHIP-LEVEL OUTPUT UNIT .................................................................................................... 37 GENERAL PURPOSE INPUT /OUTPUT (GPIO) .......................................................................... 39 GPO ........................................................................................................................................... 39 GPI ............................................................................................................................................. 40 INTERNAL CONTROL REGISTERS............................................................................................ 42 SYSTEM CONTROL.......................................................................................................................... 42 VIDEO ADC .................................................................................................................................. 56 PLL ............................................................................................................................................. 63 AUDIO ADC/DAC ......................................................................................................................... 69 VIDEO DECODER ............................................................................................................................ 79 AGC ....................................................................................................................................... 80 Video Detection Misc............................................................................................................ 81 Color Killer ............................................................................................................................ 82 2D Comb Filter ...................................................................................................................... 82 Final Doc No: DM5866-DS-F01 August 19, 2015 4 DM5866 960H and 720H 4 channels NTSC/PAL Decoder ELECTRICAL SPECIFICATIONS .............................................................................................. 106 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE .............................. 106 Recommended Operating Conditions ................................................................................ 107 Crystal Specifications .......................................................................................................... 108 ELECTRICAL CHARACTERISTICS........................................................................................................ 108 DC ELECTRICAL CHARACTERISTICS .................................................................................................. 108 Analog Processing and A/D Converters .............................................................................. 109 Timing ................................................................................................................................. 110 PACKAGING ....................................................................................................................... 113 ORDERING INFORMATION.................................................................................................. 114 DISCLAIMER.............................................................................................................................. 114 PRODUCTS ............................................................................................................................... 114 CONTACT WINDOWS................................................................................................................. 114 Final Doc No: DM5866-DS-F01 August 19, 2015 5 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Introduction The DM5866 is a high-end 4-channel video decoder designed for cameras with Sony’s new 960H CCD sensor. The DM5866 converts 4 channels of 9/6.5 MHz analog CVBS signals to 4 channels of digital 36/27 MHz CCIR656 signals. The DM5866 integrates two internal PLLs, and decodes both 960H and 720H videos using the same (27MHz) external clock source. The DM5866 also features a patented fast switch function. With the fast switch function, the DM5866 can decode up to 8 analog CVBS with little frame rate loss. The DM5866 also includes five audio ADCs and one audio DAC. Audio cascade up to 16 channels is also supported. Final Doc No: DM5866-DS-F01 August 19, 2015 6 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Features Video Decoder Accepts NTSC (M,J), PAL (B, D, G, H, I, M, Nc) and SONY 960H CCD Camera Each 2 of the 4 video decoders could be programmed to operate at 27 or 36MHz. Hardware Fast Switch function Fast Switch also controllable by software or external pin Software channel ID in active region Four 10-bits video ADCs with built in 9/6.5 MHz analog low pass filter Automatic gain control for Luminance and Chrominance Programmable brightness, contrast, saturation, hue, and sharpness 5-H comb filter for YC separation Chrominance line filter for PAL phase error DLL for video synchronization, supports 27MHz crystal within +/-1000 ppm variance Advanced video synchronization for weak and noisy CVBS. Supports video signal transmitted by 500-meter long cable Up to 5 CCIR656 output interfaces which could be configured as 5 sets of CCIR656 (36/27MHz) or 3 sets of TDM2 (72/54MHz) or 3 set of TDM4 (144/108MHz) Support line lock camera Audio Codecs Five audio ADCs and one audio DAC are integrated Master I2S/DSP playback, record and audio-mixing Supports extended I2S/DSP format transmitting up to 16 audio channels using one data pin Audio cascade up to 16 channels 16-bit or 8-bit 48/24/16/8 KHz PCM format Final Doc No: DM5866-DS-F01 August 19, 2015 7 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Miscellaneous Use a single external 27MHz crystal to support both 960H and 720H video Two programmable PLLs integrated Slave I2C bus Ultra low power consumption. Under 500mW for normal operation. Under 50mW for suspend mode. 128-pin LQFP package (14mmx14mm) 1.8V core power, 3.3V analog power and 1.8V analog power Applications Suggested applications include DVR Car DVR Video capture card Final Doc No: DM5866-DS-F01 August 19, 2015 8 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Terminal Assignment 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSS CLKNO2 CLKPO2 VDDI oCCIRD_1[0] oCCIRD_1[1] oCCIRD_1[2] VDDA AOUT VSSA VSSA AINN AIN1 AIN2 AIN3 AIN4 AIN5 VDDA VDDV oCCIRD_1[3] VSS oCCIRD_1[4] oCCIRD_1[5] oCCIRD_1[6] DM5866 INA0 INB0 VSSV VSSV INA1 INB1 VDDV VDDV INA2 INB2 AGND VSSV 128 Pin LQFP_14x14 oCCIRD_1[7] VDDO XO XI VSS CLKNO3 CLKPO3 VDDI oCCIRD_2[0] oCCIRD_2[1] oCCIRD_2[2] oCCIRD_2[3] VSS oCCIRD_2[4] oCCIRD_2[5] oCCIRD_2[6] NC VDDO NC NC NC NC NC NC NC NC oCCIRD_3[0] oCCIRD_3[1] oCCIRD_3[2] oCCIRD_3[3] VDDI oCCIRD_3[4] oCCIRD_3[5] oCCIRD_3[6] oCCIRD_3[7] VSS oCCIRD_2[7] VDDO CLKNO4 CLKPO4 VSS VSS SI2CLK SI2CD VDDI ALINKI SADD[0] SADD[1] TEST_EN VSS AVSS_2 AVDD_2 NC INA3 INB3 VDDV AVDD_1 NC AVSS_1 NC NC oCCIRD_0[7] oCCIRD_0[6] oCCIRD_0[5] oCCIRD_0[4] VDDO oCCIRD_0[3] oCCIRD_0[2] oCCIRD_0[1] oCCIRD_0[0] VSS CLKPO1 CLKNO1 VDDI ACLKR ASYNR ADATR ADATM VSS ACLKP ASYNP ADATP IRQ VDDO HRSTZ ALINKO VSS MPP4 MPP3 MPP2 MPP1 VDDI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Final Doc No: DM5866-DS-F01 August 19, 2015 9 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Terminal Functions Analog Video/Audio Interface Pins Pin Name Pin number Type INA0 13 A INB0 14 A INA1 17 A INB1 18 A INA2 21 A INB2 22 A INA3 25 A INB3 26 A AIN1 AIN2 AIN3 AIN4 AIN5 AINN AOUT 6 7 8 9 10 5 2 A A A A A A A Final Doc No: DM5866-DS-F01 August 19, 2015 Description CVBS input A of channel 0 or S-VIDEO Y of channel 0 CVBS input B of channel 0 or S-VIDEO Y of channel 0 CVBS input A of channel 1 or S-VIDEO C of channel 0 CVBS input B of channel 1 or S-VIDEO C of channel 0 CVBS input A of channel 2 or S-VIDEO Y of channel 1 CVBS input B of channel 2 or S-VIDEO Y of channel 1 CVBS input A of channel 3 or S-VIDEO C of channel 1 CVBS input B of channel 3 or S-VIDEO C of channel 1 Audio input of channel 1 Audio input of channel 2 Audio input of channel 3 Audio input of channel 4 Audio input of channel 5 Audio input negative control Audio output 10 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Digital Video/Audio Interface Pins Pin Name Pin number Type ACLKR ASYNR ADATR ADATM ACLKP ASYNP ADATP ALINKI ALINKO 98,99,100, 101,103,104 105,106 85,86,87, 88,90,91, 92,93 69,70,71, 72,74,75, 76,77 56,57,58, 59,61,62, 63,64 111 112 113 114 116 117 118 40 122 MPP4 124 IO MPP3 125 IO MPP2 126 IO MPP1 127 IO oCCIRD_0[7:0] oCCIRD_1[7:0] oCCIRD_2[7:0] oCCIRD_3[7:0] Final Doc No: DM5866-DS-F01 August 19, 2015 Description O Video data output of channel 0 or TDM72/144 output Data Bus O Video data output of channel 1, or TDM72/144 output Data Bus O Video data output of channel 2 O Video data output of channel 3 O O O O O O I I O Audio serial clock output of record Audio serial sync output of record. Audio serial data output of record Audio serial data output of mixing Audio serial clock output of playback Audio serial sync output of playback Audio serial data input of playback Audio Multi-chip serial input Audio Multi-chip serial output FLD/ACTIVE/NOVID/FASTSW_SEL of channel 4 FLD/ACTIVE/NOVID/FASTSW_SEL of channel 3 FLD/ACTIVE/NOVID/FASTSW_SEL of channel 2 FLD/ACTIVE/NOVID/FASTSW_SEL of channel 1 11 DM5866 960H and 720H 4 channels NTSC/PAL Decoder System Control Pins Pin Name Pin number Type HRSTZ 121 I XI 82 I XO SADD[1:0] CLKPO1 83 38,39 108 O I O CLKNO1 109 O CLKPO2 95 O CLKNO2 96 O CLKPO3 CLKNO3 CLKPO4 79 80 66 O O O CLKNO4 67 O TEST_EN SI2CD SI2CLK IRQ 37 42 43 119 I IO I O Final Doc No: DM5866-DS-F01 August 19, 2015 Description System reset Crystal 27MHz connection or Oscillator clock input. Crystal 27MHz connection I2C Device ID strapping 36/72/144MHz clock output for oCCIRD_0 Inverse of 36/72/144MHz clock output for oCCIRD_0 36/72/144MHz clock output for oCCIRD_1 Inverse of 36/72/144MHz clock output for oCCIRD_1 36MHz clock output for oCCIRD_2 Inverse of 36MHz clock output oCCIRD_2 36MHz clock output for oCCIRD_3 Inverse of 36MHz clock output for oCCIRD_3 Test enable, please connect it to ground Slave I2C data Slave I2C clock Interrupt request output 12 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Power, Ground and NC Pins Pin Name Pin number Type VDDA VSSA VDDV VSSV 1,11 3,4 12,19,20,27 15,16,24 P G P G AGND 23 G AVDD_1 AVSS_1 AVDD_2 AVSS_2 28 30 34 35 41,60,78,94, 110,128 53,68,84, 102,120 36,44,55,65, 73,81,89,97, 107,115,123 29,31,32,33, 45,46,47,48, 49,50,51,52, 54 P G P G 1.8V Power for analog audio DAC Ground for analog audio DAC 1.8V Power for video ADC Ground for video ADC Analog ground (used as signal input reference, CH_AGND) 1.8V Power for analog clock PLL1 Ground for analog clock PLL1 1.8V Power for analog clock PLL2 Ground for analog clock PLL2 P 1.8V Power for internal logic P 3.3V Power for output driver G Ground for internal logic and output driver VDDI VDDO VSS NC Final Doc No: DM5866-DS-F01 August 19, 2015 Description Not Connected 13 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Pin Usage of Video Output Video Out 1 oCCIRD_0[7:0] SD: CCIR656/TDM2/TDM4 2 oCCIRD_1[7:0] SD: CCIR656/TDM2/TDM4 3 oCCIRD_2[7:0] (Only for VD2) (Only SD CCIR656, No TDM out) 4 oCCIRD_3[7:0] (Only for VD3) (Only SD CCIR656, No TDM out) 5 (a) set CCIROPINOPT=1 (b) supporting SD: CCIR656/TDM2/TDM4 Data Bus[7:0]: Pin no. {116, 117, 118, 119, 122, 124, 125, 127} Final Doc No: DM5866-DS-F01 August 19, 2015 14 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Block Diagram VIN1A VIN1B M U X Video Decoder 960/720H ADC VIN2A VIN2B VIN3A VIN3B M U X VD0[7:0] Video Decoder 960/720H VD1[7:0] OTDM IF M U X Video Decoder 960/720H VD3[7:0] ADC VIN4A VIN4B AIN1 AIN2 AIN3 AIN4 AIN5 AOUT Final Doc No: DM5866-DS-F01 August 19, 2015 M U X VD2[7:0] TDMO Video Decoder 960/720H 5x Audio ADC Audio DAC I2S IF Audio Mix Audio cas IF ACLKR/ASYNR/ ADATR ADATM ACLKP/ASYNP ADATP ALINKO ALINKI 15 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Video Decoder Video Interface The DM5866 outputs 27MHz CCIR656 with 720x480/720x576 resolution (conventional 720H), or outputs 36MHz CCIR656-like format (BT.1302) with 960x480/960x576 resolution (Sony 960H). For these video outputs, SAV (Start of Active Video) and EAV (End of Active Video) are inserted to indicate active video interval. Each channel uses one output port to transmit video data, that is, luminance and chrominance data are transmitted through the same port. The output timing diagram is shown below. CLK CCIR_n[7:0] FFh 00h 00h XY 80h EAV code 4 data cycles 10h 80h 10h Horizontal Blanking FFh 00h 00h XZ Cb0 Y0 Cr0 Y1 SAV code 4 data cycles Cb2 Y2 Cr2 Y3 Cbn Yn Crn Yn+1 FFh 00h Active Horizontal Line HACITVE The number of data cycles in active horizontal line will vary according to the output format. For 720H video outputs, the active horizontal line contains 1440 cycles. For 960 H video outputs, the active horizontal line contains 1920 cycles. SAV and EAV indicate the active video interval. The values of the first three bytes in SAV and EAV are invariant preamble: 0xFF, 0x00, and 0x00. Different values are designated to the last byte according to different conditions: Field, V time, and H time. The MSB of this byte is always set to 1 and it’s followed by three bits to represent the condition of F, V, and H respectively. The last four bits are used as protection bits. The detailed code sequences of SAV and EAV are illustrated in the following table. FVH Value Condition SAV/EAV Code Sequence Field V time H time F V H Byte 0 Byte 1 Byte 2 Byte 3 Odd Odd Odd Odd Even Even Even Even Active Active Blank Blank Active Active Blank Blank SAV EAV SAV EAV SAV EAV SAV EAV 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x9D 0xAB 0xB6 0xC7 0xDA 0xEC 0xF1 Final Doc No: DM5866-DS-F01 August 19, 2015 16 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Multi-channel Time Division Multiplexing The DM5866 supports 2/4-channel time division multiplexed output format. Thus two or four video channels can be transmitted through one output port. The clock rate should be two or four times of the original sampling rate according to the number of channels to be multiplexed. The basic case is the non-multiplexed output. The clock rate follows the original data rate (27 MHz for 720H video, 36 MHz for 960H video). The timing diagram is illustrated below. CLK1X tlw thw CCIR 00 00 FF tsu th XY Y0 Cb0 Cr0 When two-channel multiplexing is selected, two times of the original clock rate is used (54 MHz for 720H video, 72 MHz for 960H video). The timing diagram is illustrated below. CLK2X CH0 FF CH1 00 00 Cb20 Y20 tlw thw TDM2X FF Cb20 CH0 Final Doc No: DM5866-DS-F01 August 19, 2015 XY 00 Cr20 tsu Y20 00 Cb0 Y21 th Cr20 XY Y21 Cb0 CH1 17 DM5866 960H and 720H 4 channels NTSC/PAL Decoder When four-channel multiplexing is selected, four times of the original clock rate is used (108 MHz for 720H video, 144 MHz for 960H video). The timing diagram is illustrated below. CLK4X CH0 FF 00 CH1 Cb0 CH2 Cr0 Y0 Y17 Cr16 Y16 CH3 Cr32 FF Cb0 CH0 Y16 00 Cr32 CH2 CH1 Cb34 Y33 tlw thw TDM4X XY 00 Y0 tsu th Cr16 Y33 00 Cr0 Y17 XY Cb34 CH3 In the Multi-channel Time Division Multiplexing mode, channel IDs are used to indicate the corresponding channels. Channel IDs are defined as the last four bits in SAV/EAV code sequence (i.e. the originally-defined protection bits). The relationship between SAV/EAV code sequence and channel ID is illustrated in the following table. Condition Field V time FVH Value H time F V H EAV/SAV Code Sequence Byte 0 Byte 1 Byte 3 Byte 2 Ch0 Odd Odd Odd Odd Even Even Even Even Active Active Blank Blank Active Active Blank Blank SAV EAV SAV EAV SAV EAV SAV EAV Final Doc No: DM5866-DS-F01 August 19, 2015 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Ch1 Ch2 Ch3 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0x93 0xA0 0xA1 0xA2 0xA3 0xB0 0xB1 0xB2 0xB3 0xC0 0xC1 0xC2 0xC3 0xD0 0xD1 0xD2 0xD3 0xE0 0xE1 0xE2 0xE3 0xF0 0xF1 0xF2 0xF3 18 DM5866 960H and 720H 4 channels NTSC/PAL Decoder 4-CH Video Decoder gain1A VIN1A VADC 0 A VIN1B A CCIR sel_1 Video decoder 0 oCCIRD_0 B gain1B gain2A A CCIR VIN2A VADC 1 B Video decoder 1 oCCIRD_1 B sel_2 VIN2B gain2B gain3A VIN3A VADC 2 A VIN3B A CCIR sel_3 Video decoder 2 oCCIRD_2 B gain3B gain4A A CCIR VIN4A VADC 3 B Video decoder 3 oCCIRD_3 B sel_4 VIN4B gain4B The DM5866 contains four 960H/720H video decoders supporting up to 8 CVBS inputs. Each CVBS has its own gain amplifier. For each pair of VINA and VINB, a 2-to-1 MUX selects one CVBS source and passes this source to one video analog-to-digital converter (VADC). The DM5866 has 4 VADCs and 4 video decoders (VD). The VADCs and VDs are organized as 2 banks as shown in the above figure. Each bank can be independently configured to operate at 27MHz (for 720H) or 36MHz (for 960H). Final Doc No: DM5866-DS-F01 August 19, 2015 19 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Video Decoder Unit V Video Interface BT.656 or BT.1302 U C UV Demod AGC+CAGC C_sv Y_cvbs Video Synchronization CVBS B Y Y/C Separation 2D Comb Filter A Luma/Chroma Processor Gain Adjust CCIR SV Fast Switch Parameter RAM Video Decoder Fast Switch Select The DM5866 video decoder contains a Video Synchronization block, an AGC block, an YC separation block, a UV Demodulation block, a Luma/Chroma Processor block and a BT 656 output block. A patented Fast Switch is also included. In addition to CVBS, the DM5866 video decoder supports S-Video as well. Video Synchronization Video Synchronization performs video detection function. It automatically detects NTSC(M), NTSC(443), PAL(B,D,G,H,I), PAL(M), PAL(N), PAL(60). A smart video detection algorithm has been adopted. Therefore the DM5866 can perform fast and stable video synchronization even if the input signal is weak or the external crystal is with error as large as +/- 1000 ppm. Automatic Gain Control Automatic Gain Control (AGC) block performs both Luma AGC and Chroma AGC (CGAC). After video synchronization, Luma AGC adjusts input Luma level to the standard level (1Vpp). A further CAGC is performed after Luma AGC for signal with different Luma and Chroma attenuation. Final Doc No: DM5866-DS-F01 August 19, 2015 20 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Y/C Separation Y/C Separation is for CVBS input only. After this block CVBS signal is separated into Luma and Chroma components. A 5-H 2D comb filter is adapted in the Y/C separation block. UV demodulation After Y/C separation, the UV demodulation block performs UV demodulation to the Chroma component. The phase and frequency of the UV demodulation is from a color burst subcarrier tracking block for both NTSC and PAL mode. A UV demodulation LPF is also adopted to filter out chroma noise. Luma/Chroma Processor This block contains a programmable Luma sharpness filter. Hue, Saturation, Brightness and Contrast adjustment are also supported. The adjusted video is then transformed from YUV to YCbCr domain for CCIR656 output interface. Video Interface The DM5866 video decoder supports 27MHz BT.656 (for 720H) and 36MHz BT.656-like (for 960H) video output format. A horizontal cropping function also included in this block. Fast Switch Parameter RAM The DM5866 features a patented hardware video source fast switch function. The Fast Switch block has a table which stores video characteristic. Each time HW switches to a previously tracked video source it could complete video synchronization within several lines. With this feature, the DM5866 can decode up to 8 CVBS with little frame rate loss. Final Doc No: DM5866-DS-F01 August 19, 2015 21 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Filter response Anti-alias LPF (960H) Decimation filter (960H) Final Doc No: DM5866-DS-F01 August 19, 2015 22 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Luma notch filter (960H) Chroma band pass filter (960H) Final Doc No: DM5866-DS-F01 August 19, 2015 23 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Y sharpness filter (960H) NSTC PAL Final Doc No: DM5866-DS-F01 August 19, 2015 24 DM5866 960H and 720H 4 channels NTSC/PAL Decoder UV demodulation low pass filter (960H) Anti-alias LPF (720H) Final Doc No: DM5866-DS-F01 August 19, 2015 25 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Decimation filter (720H) Luma notch filter (720H) Final Doc No: DM5866-DS-F01 August 19, 2015 26 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Chroma band pass filter (720H) Y sharpness filter (720H) NTSC Final Doc No: DM5866-DS-F01 August 19, 2015 27 DM5866 960H and 720H 4 channels NTSC/PAL Decoder PAL UV demodulation low pass filter (720H) Final Doc No: DM5866-DS-F01 August 19, 2015 28 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Audio CODEC The audio codec in the DM5866 consists of five audio ADCs, one audio DAC, one audio mixer, one I2S/DSP decoder and two I2S/DSP encoders as shown below. The I2S/DSP decoder and encoders always operate in the master mode. Audio Codec ACLKR I2S/DSP Encoder (master) ADATR I2S/DSP Encoder (master) ASYNR ADATM ASYNR ACLKR AIN1 AIN2 AIN3 AIN4 AIN5 X X DAGC_GAIN1 MIXGAIN_1 X X DAGC_GAIN2 MIXGAIN_2 X X DAGC_GAIN3 MIXGAIN_3 X X DAGC_GAIN4 MIXGAIN_4 X X AADC AADC AADC AADC AADC ADAC_SRC MIXER MUX DAGC_GAIN5 MIXGAIN_5 X ADAC AOUT DAGC_GAIN_P X MIXGAIN_P ACLKP ASYNP ADATP Final Doc No: DM5866-DS-F01 August 19, 2015 I2S/DSP Decoder (master) 29 DM5866 960H and 720H 4 channels NTSC/PAL Decoder The I2S/DSP decoder is used for playback of digital input. It generates ACLKP and ASYNP signals and accepts serial data via ADATP from a slave device. The levels of the five analog audio inputs (AIN1 ~ AIN5) are programmable via the registers DAGC_GAIN1, DAGC_GAIN2, DAGC_GAIN3, DAGC_GAIN4 and DAGC_GAIN5. The six input audio sources can be mixed by the used-defined ratio specified by registers MIXGAIN_1, MIXGAIN_2, MIXGAIN_3, MIXGAIN_4, MIXGAIN_5, MIXGAIN_P. The mixed audio can be output through I2S/DSP encoder or DAC. The codec provides three interfaces for audio output. The audio DAC can output analog audio for any one of the six input audio sources or the mixed audio. The analog output level is adjustable via register DAGC_GAIN_P. Two I2S/DSP encoders are present to output digital audio signal. The first one generates ACLKR, ASYNR and ADATR to output the 4 recorded audio inputs. The second encoder uses ADATM and shares the other two signals (ACLKR and ASYNR) to output the mixed audio. The codec also supports audio cascade mode for multi-chip operation which will be described in a dedicated section. Final Doc No: DM5866-DS-F01 August 19, 2015 30 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Digital Audio Format The 3 digital audio interfaces (decoder for playback and encoder for record or mixing) follow the standard I2S or DSP protocol as shown below. Only master mode (codec being the master) is supported. I2S Format 1/fs ASYN ACLK ADAT Data 1 Data 2 MSB LSB 8 or 16 bits DSP Format 1/fs ASYN ACLK Data 1 ADAT Data 2 MSB LSB 8 or 16 bits Final Doc No: DM5866-DS-F01 August 19, 2015 31 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Extended Digital Audio Format The digital audio encoders also support an extended I2S/DSP format to carry multiple audio channels through a single ADAT pin as shown below. Extended I2S Format (Illustrate the case when the number of channels is 8) 1/fs ASYNR ACLKR ADATR / ADATM Data 0 Data 1 Data 2 Data 3 Data 4 MSB Data 5 Data 6 Data 7 LSB 8 or 16 bits Extended DSP Format (Illustrate the case when the number of channels is 8) 1/fs ASYNR ACLKR ADATR / ADATM Data 0 Data 1 Data 2 Data 3 MSB Data 4 Data 5 Data 6 Data 7 LSB 8 or 16 bits Final Doc No: DM5866-DS-F01 August 19, 2015 32 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Cascade Mode for Multi-Chip Operation By using audio cascade mode, up to 16 analog audio sources can be cascaded and output through a single ACLKR/ASYNR/ADATR interface using the extended I2S/DSP format. Hence up to 4 chips can be cascaded in multi-chip application. A typical audio cascade system is shown below. The table shown below summarizes the operation of audio cascade mode for various system configurations. Please note that 16-bit I2S/DSP data is not supported when using 16-channel cascade. The analog audio input AIN5 can be optionally cascaded and output using the ADATM pin by setting the registers MIXCASEN and ADATMOPT as ‘1’. 2-chip cascade 3-chip cascade 4-chip cascade (8 channels) (12 channels) (16 channels) 8-bit data 16-bit data 8-bit data 16-bit data 8-bit data 16-bit data fs=48KHz supported supported supported supported supported prohibited fs=24KHz supported supported supported supported supported prohibited fs=16KHz supported supported supported supported supported prohibited fs=8KHz supported supported supported prohibited supported supported The Operation of Audio Cascade Mode for Various System Configurations Final Doc No: DM5866-DS-F01 August 19, 2015 33 DM5866 960H and 720H 4 channels NTSC/PAL Decoder 1/fs ASYNR a5_3 AIN5 ALINKO aC aD aE aF AIN4 AIN3 AIN2 AIN1 casID=3 XI ALINKI a5_2 AIN5 ALINKO a8 a9 aA aB AIN4 AIN3 AIN2 AIN1 casID=2 XI ALINKI a5_1 AIN5 ALINKO a4 a5 a6 a7 AIN4 AIN3 AIN2 AIN1 casID=1 ACLKR ASYNR ADATR aF aE ADATM a5 _3 a5 _2 ADATR aB aA ADATM a5 _2 aD aC aB aA a9 a8 a7 a6 a5 _1 a5 _0 a5 a4 a5 _1 a5 _0 a3 a2 a5 a4 a3 a2 a3 a2 a1 a0 a1 a0 a1 a0 ACLKR ASYNR a9 a8 a7 a6 OSC 27MHz XI ALINKI a5_0 AIN5 ALINKO a0 a1 a2 a3 AIN4 AIN3 AIN2 AIN1 casID=0 XI ACLKR ASYNR ADATR a7 ADATM a5 _1 a6 a5 a4 a5 _0 ACLKR ASYNR ADATR a3 a2 ADATM a1 a0 a5 _0 ALINKI A Typical Audio Cascade System <Note> 1. Here we use I2S mode as an example. The DSP mode works accordingly. 2. The waveform is a simplified version. In real system the “ASYNR”signals in different cascade stages are not synchronous. Final Doc No: DM5866-DS-F01 August 19, 2015 34 DM5866 960H and 720H 4 channels NTSC/PAL Decoder PLL The DM5866 has two internal PLLs to generate the system and pixel clocks. A 27MHz or 36 MHz is required for the PLLs. The default PLL setting is shown in the following table. Crystal In clock (MHz) PLL out (MHz) Function PLL1 27 144 System/pixel clock PLL2 27 74.25 SMPTE 274M pixel clock PLL default operated clock The PLL parameters for various system configurations are shown in the following table. Crystal(MHz) PLL out(MHz) M N OD 27 27 36 36 27 27 27 36 36 36 144 108 144 108 144 108 74.25 144 108 74.25 64(62+2) 16(14+2) 16(14+2) 12(10+2) 64(62+2) 16(14+2) 22(20+2) 16(14+2) 12(10+2) 66(64+2) 6(4+2) 2(0+2) 2(0+2) 2(0+2) 6(4+2) 2(0+2) 2(0+2) 2(0+2) 2(0+2) 8(6+2) 1 1 1 1 1 1 2 1 1 2 PLL1 PLL2 Final Doc No: DM5866-DS-F01 August 19, 2015 35 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Host Interface In the DM5866, I2C is used for setting configuration and parameters, for example, brightness, contrast, saturation, hue, and sharpness control. The typical timing diagram of I2C write and read access is illustrated in the following figure. SI2CLK 1 2 8 9 1 2 8 1 9 8 2 9 SI2CD START ACK WRITE ADDRESS REG ADDRESS ACK WRITE DATA ACK STOP Write operation of I2C bus SI2CLK 1 2 8 9 1 2 8 1 9 2 8 1 9 2 8 9 SI2CD START WRITE ADDRESS ACK REG ADDRESS ACK STOP START READ ADDRESS ACK READ DATA ACK STOP Read operation of I2C bus 1 1 0 Write/Read Address Slave Address 0 0 SADD[1] SADD[0] R/W 0: Write; 1: Read The external Pull-up/Pull-down resisters connected to the pins “DQ0” and “DQ1” indicate the device address SADD[1] and SADD[0]. When pull-up resistor is connected to DQ0 or DQ1, it indicates SADD[1] or SADD[0] with a high value. Otherwise when pull-down resistor is connected to DQ0 or DQ1, it indicates SADD[1] or SADD[0] with a low value. SADD[1:0]=2’h0 SADD[1:0]=2’h1 SADD[1:0]=2’h2 SADD[1:0]=2’h3 Final Doc No: DM5866-DS-F01 August 19, 2015 Write Address Read Address C0 C2 C4 C6 C1 C3 C5 C7 36 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Chip-Level Output Unit Three video output ports are available at chip level. The following figure depicts the data path of output ports. The output ports are flexible in use. It can be programmed to output various output combinations. As shown in the figure, the register CCIROMXm_n is used to select up to 4 output videos from 6 possible sources. By programming register CCIROTMD_X, user can specify whether single channel (CCIR656/BT.1302), 2-channel TDM (@54/72 MHz), 4-channel TDM (@108/144 MHz) is to be output. CCIROTMD_0 (0x68[5:4], Video-Out Format Select 0) 0: CCIR656 1: 54 / 72 MHz TDM Out (2 channels) 2: 108 /144 MHz TDM Out (4 channels) 3: Prohibited CCIROTMD_0 CCIROMX0_0 0 VDOUT_0 CCIROMX0_1 VDOUT_1 TDM Out 54 / 72 MHz VDOUT_1 1 CCIROUT_0 CCIROMX0_2 VDOUT_3 0 VDOUT_0 CCIROMX1_1 VDOUT_2 oCCIRD_0[7:0] (chip I/Os) 2 CCIROMX0_3 1 VDOUT_3 TDM Out 108 / 144 MHz 2 oCCIRD_1[7:0] (chip I/Os) CCIROMX1_3 0 VDOUT_0 TDM Out 54 / 72 MHz CCIR_OUT1 CCIROTMD_4 (0x9D[1:0], Video-Out Format Select 4) 0: CCIR656 1: 54 / 72 MHz TDM Out (2 channels) 2: 108 /144 MHz TDM Out (4 channels) 3: Prohibited CCIROTMD_4 CCIROMX4_0 VDOUT_1 CCIROTMD_1 (0x68[7:6], Video-Out Format Select 1) 0: CCIR656 1: 54 / 72 MHz TDM Out (2 channels) 2: 108 /144 MHz TDM Out (4 channels) 3: Prohibited CCIROUT_1 CCIR_OUT0 CCIROMX4_1 TDM Out 54 / 72 MHz VDOUT_2 CCIROMX1_2 TDM Out 108 / 144 MHz CCIROTMD_1 CCIROMX1_0 CCIROMXm_n [2:0] MUX Output 0 VDOUT_0 1 VDOUT_1 2 VDOUT_2 3 VDOUT_3 1 CCIROUT_4 VDOUT_2 CCIROMX4_2 VDOUT_3 TDM Out 108 / 144 MHz (shares with other chip I/Os) 2 Video-Out Source Select (0x71 ~ 0x74, 0x9E ~ 0x9F) CCIROMX4_3 CCIR_OUT4 <Note> (1) VDOUT_0 ~ VDOUT_3 are from Video Decoder 0 ~ Video Decoder 3 respectively. Data Path of Chip-Level Video Output Unit Final Doc No: DM5866-DS-F01 August 19, 2015 37 DM5866 960H and 720H 4 channels NTSC/PAL Decoder CCIROUT_0 and CCIROUT_1 have dedicated chip I/O pins (oCCIRD_0 and oCCIRD_1 respectively), while CCIROUT_4 has to share I/O pins with others. To use CCIROUT_4, please set CCIROPINOPT as ‘1’ and refer to the following table. Final Doc No: DM5866-DS-F01 August 19, 2015 I/O Pin number I/O Pin Name CCIROUT_4 Bus 116 ACLKP CCIROUT_4[7] 117 ASYNP CCIROUT_4[6] 118 ADATP CCIROUT_4[5] 119 IRQ CCIROUT_4[4] 122 ALINKO CCIROUT_4[3] 124 MPP4 CCIROUT_4[2] 125 MPP3 CCIROUT_4[1] 127 MPP1 CCIROUT_4[0] 38 DM5866 960H and 720H 4 channels NTSC/PAL Decoder General Purpose Input /Output (GPIO) The DM5866 supports GPIO function. The function only valid when REG70 [4]=0 and REG7A[6]=0. REG7A~REG7F are corresponding GPIO registers and MPP1~MPP4 (pin No.127~24) are corresponding pins. We separate GPIO function into GPI and GPO for description. GPO function is used to set the programmable pin high or low by register. GPI function is used to detect the input signal high, low, raising edge or falling edge and then output high level signal to interrupt pin(IRQ). GPI and GPO are described below. GPO DM5866 0 GPO_0 1 VDMPP0 0 GPO_1 1 VDMPP1 0 GPO_2 1 VDMPP2 0 GPO_3 MPP1 GPOE_0 MPP2 GPOE_1 MPP3 GPOE_2 MPP4 1 VDMPP3 GPOE_3 GPOSEL There are four GPO pin (MPP1~MPP4) in DM5866.The GPO function only valid when REG70[4]=0, REG7A[6]=0, GPOSEL=0 (REG7A[7]) and GPOE_X=1 (REG7C[7:4]). Fig.x shows the GPO function. Pin MPP1~MPP4 can be programmed by GPO_0~GPO_3 (REG7C[3:0]) through GPO function. Final Doc No: DM5866-DS-F01 August 19, 2015 39 DM5866 960H and 720H 4 channels NTSC/PAL Decoder GPI GPIINT_0 GPIINT_0 GPIINT_0 GPIINT_0 GPI_3 GPI_2 GPI_1 GPI_0 DM5866 GPOSEL_1 GPI logic MPP1 IRQ 0 GPI logic MPP2 DQ14 GPI logic MPP3 osclki GPI logic 1 GPIMSK_3 GPIMSK_2 GPIMSK_1 GPIMSK_0 GPINTOPT GPOE_0 MPP4 The DM5866 supports four GPI input pin and one IRQ output pin. Fig.x1 shows the GPI block diagram. The GPI function only valid when REG70[4]=0, REG7A[6]=0, GPOE_X=0 (REG7C[7:4]) and GPOSEL_1=0 (REG7A[4]). The MPP1~MPP4 are the GPI input pin and DQ14 is the IRQ output pin. The GPI_0~GPI_3 are the read only status register. They show the GPI input from MPP1~MPP4 high or low. The GPIINT_0~GPIINT_3 are also read only status register. They show that GPI input MPP1~MPP4 high or low or raising edge or falling edge happened. The GPIINTOPT is the option to select GPI format from MPP1~MPP4 high or low or raising edge or falling edge. The GPIINTOPT table shows below. The GPIMSK_0~GPIMSK_3 are the mask signal for the corresponding GPI input. Final Doc No: DM5866-DS-F01 August 19, 2015 40 DM5866 960H and 720H 4 channels NTSC/PAL Decoder GPINTOPT table GPINTOPT=2h0 GPINTOPT=2h0 Raising edge trigger falling edge trigger high high MPPX MPPX low low 1 1 GPIINT_X GPIINT_X 0 0 GPINTOPT=2h0 GPINTOPT=2h0 High level trigger Low level trigger high MPPX high MPPX low low 1 GPIINT_X 1 GPIINT_X 0 Final Doc No: DM5866-DS-F01 August 19, 2015 0 41 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Internal Control Registers System Control Address= 8’h64 System Control Page 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 PAGE_3 PAGE_2 PAGE_1 PAGE_0 PAGE_0: VD space 0, to access VD_0 register please program this bit to 1. PAGE_1: VD space 1, to access VD_1 register please program this bit to 1. PAGE_2: VD space 2, to access VD_2 register please program this bit to 1. PAGE_3: VD space 3, to access VD_3 register please program this bit to 1. In case of register read, only one of the four bits can be set to 1. Address= 8’h65 System Reset 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 RSTZ TRSTZ TRSTZ: When 1, reset whole chip except SW PLL, GPIO and Device ID setting. (WO) RSTZ: When 1, reset all video decoders, TDM and audio interface. It also resets video decoder configurations. Final Doc No: DM5866-DS-F01 August 19, 2015 42 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h66 Global INT Mask 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 VDMAS K_3 VDMAS K_2 VDMAS K_1 VDMAS K_0 VDMASK_0: Enable INT from VD_0. VDMASK_1: Enable INT from VD_1. VDMASK_2: Enable INT from VD_2. VDMASK_3: Enable INT from VD_3. Address= 8’h67 Global INT Status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 VDINT_3 VDINT_2 VDINT_1 VDINT_0 VDINT_0: VD_0 INT status. (RO) VDINT_1: VD_1 INT status. (RO) VDINT_2: VD_2 INT status. (RO) VDINT_3: VD_3 INT status. (RO) Final Doc No: DM5866-DS-F01 August 19, 2015 43 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h68 CCIR656 IO Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2’h0 2’h0 0 0 0 0 CCIROTMD_1 CCIROTMD_0 CCIROE _3 CCIROE _2 CCIROE _1 CCIROE _0 CCIROE_0: Chip CCIR656_0 related 9 pins output enable. When 1, output mode. When 0, input mode. CCIROE_1: Chip CCIR656_1 related 9 pins output enable. When 1, output mode. When 0, input mode. CCIROE_2: Chip CCIR656_2 related 9 pins output enable. When 1, output mode. When 0, input mode. CCIROE_3: Chip CCIR656_3 related 9 pins output enable. When 1, output mode. When 0, input mode. CCIROTMD_0: Chip CCUROUT_0 output Mode type. 2’h0: CCIR656 output mode. 2’h1: 54/72Mhz TDM mode with D1 resolution for each channel. 2’h2: 108/144Mhz TDM mode with D1 resolution for each channel. CCIROTMD_1: Chip CCUROUT_1 output Mode type. 2’h0: CCIR656 output mode. 2’h1: 54/72Mhz TDM mode with D1 resolution for each channel. 2’h2: 108/144Mhz TDM mode with D1 resolution for each channel. Final Doc No: DM5866-DS-F01 August 19, 2015 44 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h69 PIXCLK Polarity 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 OPIXCL K3_INV OPIXCL K2_INV OPIXCL K1_INV OPIXCL K0_INV OPIXCL K4_INV 1-bit 0-bit OPIXCLK4_INV: When 1, inverse output pixclk of CCIROUT_4. OPIXCLK0_INV: When 1, inverse output pixclk of CCIROUT_0. OPIXCLK1_INV: When 1, inverse output pixclk of CCIROUT_1. OPIXCLK2_INV: When 1, inverse output pixclk of CCIROUT_2. OPIXCLK3_INV: When 1, inverse output pixclk of CCIROUT_3. Address= 8’h6A IC Mode Control 7-bit 6-bit 5-bit 4-bit 0 0 0 0 3-bit 2-bit 2’h2 2’h0 PINCFG CLKADCOPT CLKADCOPT: The VADC_1 input clock selection. (144Mhz for 960H, 108MHz for 720H) 2’h0: The default value, sources from PLL1. 2’h1: Clock sources from PLL2. 2’h2: Clock source from chip pin NO.126. PINCFG: IC pin mode option. Set 2’h0 for 720 Video decoder x4. Set 2’h2 for 960 Video decoder x4. Final Doc No: DM5866-DS-F01 August 19, 2015 45 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h6B Output Pixclk Delay Configuration 7-bit 6-bit 0 5-bit 4-bit 3’h0 3-bit 2-bit 1-bit 0 0-bit 3’h0 DLYMUX_PIXCLK1 DLYMUX_PIXCLK0 DYLMUX_PIXCLK0: Programmable pixclk delay of CCIROUT_0. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) DYLMUX_PIXCLK1: Programmable pixclk delay of CCIROUT_1. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) Address= 8’h6C VD Power Down 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 VDPWD N_3 VDPWD N_2 VDPWD N_1 VDPWD N_0 VDPWDN_0: When 1, VD 0 into power down mode. VDPWDN_1: When 1, VD 1 into power down mode. VDPWDN_2: When 1, VD 2 into power down mode. VDPWDN_3: When 1, VD 3 into power down mode. Final Doc No: DM5866-DS-F01 August 19, 2015 46 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h6D VD Power On Rstz 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 VDPRST 3 VDPRST 2 VDPRST 1 VDPRST 0 VDPRST0: Write 1, reset VD 0. VDPRST1: Write 1, reset VD 1. VDPRST2: Write 1, reset VD 2. VDPRST3: Write 1, reset VD 3. Address= 8’h6E IP Test Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_VA DCBYP EN SW_VA DCTSTE N SW_PLL BYPEN SW_PLL TSTEN SW_MBI SPATEN VADCSEL SW_MBISTPATEN: When 1, drive MBIST detail signal to chip IO pins. SW_PLLTSTEN: When 1, drive PLL out clocks to chip IO pins. SW_PLLBYPEN: When 1, bypass internal pll out source. SW_VADCTSTEN: When 1, drive VADCSEL indicated ADC outputs to chip IO pins. SW_VADCBYPEN: When 1, bypass VADCBYPOPT indicated ADC with chip input ADC signals. Final Doc No: DM5866-DS-F01 August 19, 2015 47 DM5866 960H and 720H 4 channels NTSC/PAL Decoder VADC_SEL: valid for SW_VADCTSTEN 3’h0: VADC_doutA=VADC_dout1, VADC_doutB=VADC_dout2 3’h1: VADC_doutA=VADC_dout3, VADC_doutB=VADC_dout4 3’h2: VADC_doutA= VADCMX0_0 =>[VADC_dout1/VADC_dout2] mux VADC_doutA= VADCMX0_1 =>[VADC_dout3/VADC_dout4] mux 3’h3: will drive VADC_0 analog IP Do [15:1], selected signal to [VADC_doutA, VADC_doutB] 3’h4: will drive VADC_1 analog IP Do [15:1], selected signal to [VADC_doutA, VADC_doutB] Address= 8’h6F MBIST Status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 BISTGO MBDON E MBERR _4 MBERR _3 MBERR _2 MBERR _1 MBERR _0 MBERR_0: When 1, memory of group 0 has error, Set by HW, write 1 to clear. MBERR_1: When 1, memory of group 1 has error, Set by HW, write 1 to clear. MBERR_2: When 1, memory of group 2 has error, Set by HW, write 1 to clear. MBERR_3: When 1, memory of group 3 has error, Set by HW, write 1 to clear. MBERR_4: When 1, memory of group 4 has error, Set by HW, write 1 to clear. MBDONE: MBIST has finished self test, Set by HW, write 1 to clear. BISTGO: Write 1to start MBIST logic. HW auto clear this bit after MBIST done. Final Doc No: DM5866-DS-F01 August 19, 2015 48 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h70 CCIROUT_4 Output Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 1-bit 0-bit CCIROP INOPT CCIROPINOPT: CCIROUT_4 output When set 1, enable CCIR656_4 bus as output. Address= 8’h71 CCIROUT_0 Otdm Configuration 1 7-bit 6-bit 0 5-bit 4-bit 3’h1 3-bit 2-bit 0 3’h0 CCIROMX0_1 CCIROMX0_0 CCIROMX0_0: The mux of CCIROUT_0’s channel 0 at OTDM mode. CCIROMX0_1: The mux of CCIROUT_0’s channel 1 at OTDM mode. Address= 8’h72 CCIROUT_0 Otdm Configuration 2 7-bit 6-bit 0 5-bit 3’h3 CCIROMX0_3 4-bit 3-bit 0 2-bit 1-bit 0-bit 3’h2 CCIROMX0_2 CCIROMX0_2: The mux of CCIROUT_0’s channel 2 at OTDM mode. CCIROMX0_3: The mux of CCIROUT_0’s channel 3 at OTDM mode. Final Doc No: DM5866-DS-F01 August 19, 2015 49 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h73 CCIROUT_1 Otdm Configuration 1 7-bit 6-bit 0 5-bit 4-bit 3’h1 3-bit 2-bit 0 1-bit 0-bit 3’h0 CCIROMX1_1 CCIROMX1_0 CCIROMX1_0: The mux of CCIROUT_1’s channel 0 at OTDM mode. CCIROMX1_1: The mux of CCIROUT_1’s channel 1 at OTDM mode. Address= 8’h74 CCIROUT_1 Otdm Configuration 2 7-bit 6-bit 0 5-bit 4-bit 3’h3 3-bit 2-bit 0 1-bit 0-bit 3’h2 CCIROMX1_3 CCIROMX1_2 CCIROMX1_2: The mux of CCIROUT_1’s channel 2 at OTDM mode. CCIROMX1_3: The mux of CCIROUT_1’s channel 3 at OTDM mode. Address= 8’h75 IO/Clock Configuration 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ACLKP OE ALINKO E IRQOE IRQOE: If using DQ14 as IRQ, set this bit as ‘1’. Otherwise, this bit is “don’t care” ALINKOE: If audio data is to be sent to next stage using audio cascade mode, set as ‘1’. Otherwise, set as ‘0’ ACLKPOE: Set as ‘1’ when I2S playback is to be enabled. Final Doc No: DM5866-DS-F01 August 19, 2015 50 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h77 CHIP Status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PWRON PWRON: Power On status. (RO) Address= 8’h78 I2C Master Configuration 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’hB8 CH device address CH0~CH3: i2c slave device address. (R/W) -DM5866 device address will be {4’hC,4’h0} -I2CMaster_0: device address will be {4’hC,4’h2} -I2CMaster_1: device address will be {4’hC,4’h4} -I2CMaster_2: device address will be {4’hC,4’h6} -I2CMaster_3: device address will be {4’hC,4’h8} -For broadcast I2CMaster_CH0~I2CMaster_CH3, device address {4’HC,4’HE} Final Doc No: DM5866-DS-F01 August 19, 2015 51 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h79 I2CM status 7-bit 6-bit 0 0 MI2CRD CMD 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2’h0 0 0 0 0 MI2CSEL CHNAC K3 CHNAC K2 CHNAC K1 CHNAC K0 CHNACK0: CH0 I2C fail (RO, WC) . CHNACK1: CH1 I2C fail (RO, WC) . CHNACK2: CH2 I2C fail (RO, WC) . CHNACK3: CH3 I2C fail (RO, WC) . MI2CSEL: The device address is 0xCA and select which channel will be set. -I2CMaster_CH0: device address will be {4’hC 4’ha} & {MI2CSEL=2’b00}. -I2CMaster_CH1: device address will be {4’hC 4’ha} & {MI2CSEL=2’b01}. -I2CMaster_CH2: device address will be {4’hC 4’ha} & {MI2CSEL=2’b10}. -I2CMaster_CH3: device address will be {4’hC 4’ha} & {MI2CSEL=2’b11}. MI2CRDCMD: When 1, the MI2C restart command enable. Address= 8’h7A GPO Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 GPOSE L MI2CEN MCLKO PT GPOSE L_1 GPOSEL_1: Set 1, pin No.63 output osclki signal Final Doc No: DM5866-DS-F01 August 19, 2015 52 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Set 0, pin No.63 output IRQ function MCLKOPT: When 1, fast master I2C clock speed. MI2CEN: When 1, enable master I2C interface. (R/W) GPOSEL: Set 1, pin MPP1 (pin No.127), MPP2 (pin No.126), MPP3(pin No.125), MPP4 (pin No.124) select VDMPP signal Set 0, pin MPP1 (pin No.127), MPP2 (pin No.126), MPP3(pin No.125), MPP4 (pin No.124) select GPO signal Address= 8’h7C GPIO 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 GPOE_3 GPOE_2 GPOE_1 GPOE_0 GPO_3 GPO_2 GPO_1 GPO_0 GPOE_0: GPO_0 output enable GPOE_1: GPO_1 output enable GPOE_2: GPO_2 output enable GPOE_3: GPO_3 output enable GPO_0: GPOSEL = 0 and GPOE_0=1 Set 0 MPP1 output low, set 1 output high. GPO_1: GPOSEL = 0 and GPOE_1=1 Set 0 MPP2 output low, set 1 output high. GPO_2: GPOSEL = 0 and GPOE_2=1 Set 0 MPP3 output low, set 1 output high. GPO_3: GPOSEL = 0 and GPOE_3=1 Set 0 MPP4 output low, set 1 output high. Final Doc No: DM5866-DS-F01 August 19, 2015 53 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h7D GPIO 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 GPIMSK _3 GPIMSK _2 GPIMSK _1 GPIMSK _0 GPINTOPT GPIMSK_0: GPI mask. GPIMSK_1: GPI mask. GPIMSK_2: GPI mask. GPIMSK_3: GPI mask. GPINTOPT: GPI interrupt option Address= 8’h7E GPIO 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 GPIINT_ 3 GPIINT_ 2 GPIINT_ 1 GPIINT_ 0 GPI_3 GPI_2 GPI_1 GPI_0 GPIINT_0: RO. GPI interrupt status register GPI_0: RO. GPI status register Final Doc No: DM5866-DS-F01 August 19, 2015 54 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h7F SW FAST SWITCH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 OFASTS W_OPT OFASTS W_SEL3 OFASTS W_SEL2 OFASTS W_SEL1 OFASTS W_SEL0 OFASTW_SEL0:valid when VD0 REG04[4]=1 and OFASTSW_OPT=1 set 0, select VIN1A as VD0 CVBS source set 1, select VIN1B as VD0 CVBS source OFASTW_SEL1:valid when VD1 REG04[4]=1 and OFASTSW_OPT=1 set 0, select VIN2A as VD1 CVBS source set 1, select VIN2B as VD1 CVBS source OFASTW_SEL2:valid when VD2 REG04[4]=1 and OFASTSW_OPT=1 set 0, select VIN3A as VD2 CVBS source set 1, select VIN3B as VD2 CVBS source OFASTW_SEL3:valid when VD3 REG04[4]=1 and OFASTSW_OPT=1 set 0, select VIN4A as VD3 CVBS source set 1, select VIN4B as VD3 CVBS source OFASTSW_OPT: valid when REG04[4]=1 Set 0, VD0-VD3 SW FASTSW control signal from OFASTSW_SEL0OFASTSW_SEL3 Set 1, VD0-VD3 SW FASTSW control signal from input pin MPP0~MPP3 Final Doc No: DM5866-DS-F01 August 19, 2015 55 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Video ADC Address= 8’h80 Video ADC 0 Configuration 1 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWGAIN _0 pd_v2 pd_v1 SW_sel_ 2 SW_sel_ 1 pd_v1: Power down VIN1A & VIN1B, active high. pd_v2: Power down VIN2A & VIN2B, active high. SWGAIN_0: Software programs VADC 0’s gain setting, active high. When low, the VADC 0’ gain setting programmed by Hardware auto. SW_sel_1: Software select active CVBS input. (0: VIN1A, 1: VIN1B) SW_sel_2: Software select active CVBS input. (0: VIN2A, 1: VIN2B) Address= 8’h81 Video ADC 0 Configuration 2 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 4’hA 0 0 0 0 bias_vadc12 SvideoC _2B SvideoC _2A SvideoC _1B SvideoC _1A bias_vadc12: VADC 0’s bias setting. SvideoC_1A: Channel VIN1A chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_1B: Channel VIN1B chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_2A: Channel VIN2A chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_2B: Channel VIN2B chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. Final Doc No: DM5866-DS-F01 August 19, 2015 56 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h82 Video ADC 0 Configuration 3 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_gain1B SW_gain1A SW_gain1A: VIN1A’s gain value, valid when REG80[2]=1. SW_gain1B: VIN1B’s gain value, valid when REG80[2]=1. Ps. Minimum gain is set by 4’h0. Maximum gain is set by 4’hf. The characteristic is the same as REG83 Address= 8’h83 Video ADC 0 Configuration 4 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_gain2B SW_gain2A SW_gain2A: VIN2A’s gain value, valid when REG80[2]=1. SW_gain2B: VIN2B’s gain value, valid when REG80[2]=1. Final Doc No: DM5866-DS-F01 August 19, 2015 57 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h84 Video ADC 0 Configuration 5 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 clmp1B clmp1A Clmp1A: VIN1A’s clamp value. Clmp1B: VIN1B’s clamp value. The clamp can be used to adjust the sync tip value to the nominal value of 20. Address= 8’h85 Video ADC 0 Configuration 6 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Clmp2B clmp2A Clmp2A: VIN2A’s clamp value. Clmp2B: VIN2B’s clamp value. Address= 8’h86 Video ADC 1 Configuration 1 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWGAIN _1 pd_v4 pd_v3 SW_sel_ 4 SW_sel_ 3 pd_v3: Power down VIN3A & VIN3B, active high. pd_v4: Power down VIN3A & VIN3B, active high. Final Doc No: DM5866-DS-F01 August 19, 2015 58 DM5866 960H and 720H 4 channels NTSC/PAL Decoder SWGAIN_1: Software programs VADC 1’s gain setting, active high. When low, the VADC 1’ gain setting programmed by Hardware auto. SW_sel_3: Software select active CVBS input. (0: VIN3A, 1: VIN3B) SW_sel_4: Software select active CVBS input. (0: VIN4A, 1: VIN4B) Address= 8’h87 Video ADC 1 Configuration 2 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 4’hA 0 0 0 0 bias_vadc34 SvideoC _4B SvideoC _4A SvideoC _3B SvideoC _3A bias_vadc34: VADC 1’s bias setting. SvideoC_3A: Channel VIN3A chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_3B: Channel VIN3B chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_4A: Channel VIN4A chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. SvideoC_4B: Channel VIN4B chroma clamping. When 1, the analog clamping level is set to 50% for chroma signal processing. Address= 8’h88 Video ADC 1 Configuration 3 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_gain3B SW_gain3A SW_gain3A: VIN3A’s gain value, valid when REG86[2]=1. Final Doc No: DM5866-DS-F01 August 19, 2015 59 DM5866 960H and 720H 4 channels NTSC/PAL Decoder SW_gain3B: VIN3B’s gain value, valid when REG86[2]=1. Address= 8’h89 Video ADC 1 Configuration 4 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_gain4B SW_gain4A SW_gain4A: VIN4A’s gain value, valid when REG86[2]=1. SW_gain4B: VIN4B’s gain value, valid when REG86[2]=1. Address= 8’h8A Video ADC 1 Configuration 5 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Clmp3B Clmp3A Clmp3A: VIN3A’s clamp value. Clmp3B: VIN3B’s clamp value. Address= 8’h8B Video ADC 1 Configuration 6 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Clmp4B Clmp4A Clmp4A: VIN4A’s clamp value. Clmp4B: VIN4B’s clamp value. Final Doc No: DM5866-DS-F01 August 19, 2015 60 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h8C Video ADC LPF Option 7-bit 6-bit 5-bit 4-bit 0 0 0 0 3-bit 2-bit 1-bit 0-bit 2’h0 2’h0 lpf_34 lpf_12 lpf_12: VADC 0 LPF selected. lpf_34: VADC 1 LPF selected. lpf_xx: 2’h0: 6MHz 2’h1: 9MHz Others: bypass Address= 8’h8D VADC Clk Delay Configuration 1 7-bit 6-bit 0 5-bit 3’h0 DLYMUX_ANA34 4-bit 3-bit 0 2-bit 1-bit 0-bit 3’h0 DLYMUX_ANA12 DLYMUX_ANA12: Programmable delay of digcore aclk_out0 from aclk_0. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) DLYMUX_ANA34: Programmable delay of digcore aclk_out1 from aclk_1. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) Final Doc No: DM5866-DS-F01 August 19, 2015 61 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h8E VADC Clk Delay Configuration 2 7-bit 6-bit 0 5-bit 4-bit 3-bit 3’h0 2-bit 0 1-bit 0-bit 3’h0 DLYMUX_ANA72 DLYMUX_ANA36 DLYMUX_ANA36: Programmable delay of digcore aclk36_out from aclk36. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) DLYMUX_ANA72: Programmable delay of digcore aclk72_out from aclk72. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) Address= 8’h8F VADC Digcore Config 7-bit 6-bit 5-bit 4-bit 3-bit 0 0 0 0 0 2-bit 1-bit 0-bit 3’h0 DLYMUX_VD DLYMUX_VD: Programmable delay of VD clk. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) Final Doc No: DM5866-DS-F01 August 19, 2015 62 DM5866 960H and 720H 4 channels NTSC/PAL Decoder PLL Formula: CLK_OUT = XIN * (M+2)/[(N+2)*OD*2] Where CLK_OUT: PLL output frequency XIN: PLL input frequency. M: The numerator of PLL formula. [N, OD]: The denominator of PLL formula. Attention: 1. 100MHz <= CLK_OUT * OD <= 250MHz 2. 1MHz <= XIN/(N+2)<=25MHz 3. OD >=1 Truth Table: PD 0 0 Don’t Care Don’t Care Other BP 0 0 1 Don’t Care OE 0 0 0 1 CLK_OUT CLK_OUT XIN XIN 0 Undefined PD: Power down control; Active high. BP: Bypass XIN to CLK_OUT; Active high. OE: CLK_OUT enable pin, Active low. Final Doc No: DM5866-DS-F01 August 19, 2015 63 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h90 SW PLL Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWPLL2 SWPLL1 SWPLL RST SWPLL1: set PLL1 input configuration from SWPLL1_XX set, otherwise hard wired with chip default vale. (144MHz) SWPLL2: set PLL2 input configuration from SWPLL2_XX set, otherwise hard wired with chip default vale. (74.25MHz) SWPLLRST: set 1, chip will enter a reset mode waiting for PLL stable in 1ms. After that, SW needs to re-program all register setting except PLL configuration. Address= 8’h91 SW PLL Config 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWPLL2 _OE SWPLL1 _OE SWPLL2 _PD SWPLL2 _BP SWPLL1 _PD SWPLL1 _BP SWPLL1_BP: PLL1_BP SW program source. SWPLL1_PD: PLL1_PD SW program source. SWPLL2_BP: PLL2_BP SW program source. SWPLL2_PD: PLL2_PD SW program source. SWPLL1_OE: PLL1_OE SW program source. SWPLL2_OE: PLL2_OE SW program source. Final Doc No: DM5866-DS-F01 August 19, 2015 64 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h92 SWPLL1 M 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 1-bit 0-bit 8’h0 SWPLL1_M[7:0] SWPLL1_M: PLL1_M SW program source. Address= 8’h93 SWPLL1_N 7-bit 6-bit 5-bit 0 0 0 4-bit 3-bit 5’h0 SWPLL1 _M[8] SWPLL1_N SWPLL1_N: PLL1_N SW program source Address= 8’h94 SWPLL2_M 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 8’h0 SWPLL2_M[7:0] SWPLL2_M: PLL2_M SW program source Final Doc No: DM5866-DS-F01 August 19, 2015 65 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h95 SWPLL2_N 7-bit 6-bit 5-bit 0 0 0 4-bit 3-bit 2-bit 1-bit 0-bit 1-bit 0-bit 5’h0 SWPLL2 _M[8] SWPLL2_N SWPLL2_N: PLL2_N SW program source Address= 8’h96 SWPLL_OD 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 4’h0 4’h0 SWPLL2_OD SWPLL1_OD SWPLL1_OD: PLL1_OD SW program source SWPLL2_OD: PLL2_OD SW program source DM5866 PLL SETTINGS Ref: 27MHz Ref: 27MHz 144 MHz 108 MHz 74.25 MHz M 62 14 20 N 4 0 0 OD 1 1 2 PD 0 0 0 OE 0 0 0 BP 0 0 0 OE 0 0 0 BP 0 0 0 DM5866 PLL SETTINGS Ref: 36MHz Ref: 36MHz 144 MHz 108 MHz 74.25 MHz Final Doc No: DM5866-DS-F01 August 19, 2015 M 14 10 64 N 0 0 6 OD 1 1 2 PD 0 0 0 66 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h9D CCIROUT_4 Output Control 7-bit 6-bit 0 5-bit 4-bit 3’h0 3-bit 2-bit 0 0 DLYNUX_PIXCLK4 1-bit 0-bit 2’h0 CCIROTMD_4 DYLMUX_PIXCLK4: Programmable pixclk delay of CCIR656_4. (3’h0: zero delay 3’h7: max delay, add 0.6ns at every step) CCIROTMD_4: Chip CCIROUT_4 output Mode type. 2’h0: CCIR656 output mode. 2’h1: 54/72Mhz TDM mode with D1 resolution for each channel. 2’h2: 108/144Mhz TDM mode with D1 resolution for each channel. Address= 8’h9E CCIROUT_4 Otdm Configuration 1 7-bit 6-bit 0 5-bit 3’h0 CCIROMX4_1 4-bit 3-bit 0 2-bit 1-bit 0-bit 3’h0 CCIROMX4_0 CCIROMX4_0: The mux of CCIR656_4’s channel 0 at OTDM mode. CCIROMX4_1: The mux of CCIR656_4’s channel 1 at OTDM mode. Final Doc No: DM5866-DS-F01 August 19, 2015 67 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h9F CCIROUT_4 Otdm Configuration 2 7-bit 6-bit 0 5-bit 3’h0 CCIROMX4_3 4-bit 3-bit 0 2-bit 1-bit 0-bit 3’h0 CCIROMX4_2 CCIROMX4_2: The mux of CCIR656_4’s channel 0 at OTDM mode. CCIROMX4_3: The mux of CCIR656_4’s channel 2 at OTDM mode. Final Doc No: DM5866-DS-F01 August 19, 2015 68 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Audio ADC/DAC Address= 8’hF0 Audio ADC/DAC Test Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ADAC_ mute ADAC_r eset ADAC_p d AADC_t est AADC_r eset AADC_reset: Audio ADC reset. (R/W: Active high) AADC_test: Audio ADC test pin. ADAC_pd: Audio DAC power down. (R/W: Active high) ADAC_reset: Audio DAC reset. (R/W: Active high) ADAC_mute: Audio DAC mute. (R/W: Active high) Address= 8’hF1 Audio DAGC Config 1 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 AADC_DAGC_2 AADC_DAGC_1 0-bit AADC_DAGC_1: Audio ADC 1 digital gain control. AADC_DAGC_2: Audio ADC 2 digital gain control. Final Doc No: DM5866-DS-F01 August 19, 2015 69 DM5866 960H and 720H 4 channels NTSC/PAL Decoder ADAC_DAGC_X[3:0], MIXGAIN_X[3:0] Set Real Gain dB Set Real Gain dB 4’h0 0 - 4’h8 1.00 0 4’h1 0.125 -18.06 4’h9 1.25 1.94 4’h2 0.25 -12.04 4’hA 1.5 3.52 4’h3 0.375 -8.52 4’hB 1.75 4.86 4’h4 0.5 -6.02 4’hC 2.00 6.02 4’h5 0.625 -4.08 4’hD 2.25 7.04 4’h6 0.75 -2.50 4’hE 2.50 7.96 4’h7 0.875 -1.16 4’hF 2.75 8.79 Address= 8’hF2 Audio DAGC Configuration 2 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 AADC_DAGC_4 AADC_DAGC_3 0-bit AADC_DAGC_3: Audio ADC 3 digital gain control. AADC_DAGC_4: Audio ADC 4 digital gain control. Address= 8’hF3 Audio DAGC Configuration 3 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 AADC_DAGC_P AADC_DAGC_5 0-bit AADC_DAGC_5: Audio ADC 5 digital gain control. Final Doc No: DM5866-DS-F01 August 19, 2015 70 DM5866 960H and 720H 4 channels NTSC/PAL Decoder AADC_DAGC_P: Audio ADC digital gain control, source is selected from REGF8: ADAC_SRC . Address= 8’hF4 Audio ADC Format 7-bit 6-bit 5-bit 4-bit 0 0 0 0 AADC_ MULCH 3-bit 2-bit 1-bit 0-bit 2’h0 0 0 AADC_FSRATE AADC_I 2SMOD E AADC_I2SMODE: (Digital I2S/DSP record interface): (master only) 1’b0: I2S mode 1’b1: DSP mode AADC_FSRATE: (Digital I2S/DSP record interface) 2’b00: 48KHz 2’b01: 24KHz 2’b10: 16KHz 2’b11: 8KHz AADC_MULCH: When 1, out 5 channels in record path. When 0, out 2 channels in record path. Final Doc No: DM5866-DS-F01 August 19, 2015 71 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’hF5 MIX Gain Configuration 1 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 MIXGAIN_2 MIXGAIN_1 0-bit MIXOUT = AIN1 * ADC_DAGC_1 * MIXGAIN_1 + AIN2 * ADC_DAGC_2 * MIXGAIN_2 + AIN3 * ADC_DAGC_3 * MIXGAIN_3 + AIN4 * ADC_DAGC_4 * MIXGAIN_4 + AIN5 * ADC_DAGC_5 * MIXGAIN_5 + ADATP * MIXGAIN_P Address= 8’hF6 MIX Gain Configuration 2 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 MIXGAIN_4 MIXGAIN_3 0-bit Refer to REG F5 Address= 8’hF7 MIX Gain Configuration 3 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h0 4’h0 MIXGAIN_P MIXGAIN_5 0-bit Refer to REG F5 Final Doc No: DM5866-DS-F01 August 19, 2015 72 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’hF8 Audio DAC Format 7-bit 6-bit 5-bit 0 3’h0 ADAC_T IME ADAC_SRC 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 ADAC_I 2SMOD E ADAC_P RCH ADAC_FSRATE ADAC_PRCH: When ADAC selecting the playback input source and PLAY_PRCH=0, ADAC chooses the playback left channel. Otherwise use playback right channel. ADAC_I2SMODE: (Digital I2S/DSP playback interface): (mater only). 1’b0: I2S mode 1’b1: DSP mode. ADAC_FSRATE: (Digital I2S/DSP playback interface): 2’b00: 48KHz 2’b01: 24KHz 2’b10: 16KHz 2’b11: 8KHz DAC_SRC: 3’h0: ADATP (playback) 3’h1: MIXOUT 3’h2: AIN_1 3’h3: AIN_2 3’h4: AIN_3 3’h5: AIN_4 3’h6: AIN_5 Final Doc No: DM5866-DS-F01 August 19, 2015 73 DM5866 960H and 720H 4 channels NTSC/PAL Decoder ADAC_TIME: When 1, use ADAC_FSRATE, ADAC mode to generate ACLKP/ASYNP. Otherwise share the same timing signals with ACLKR/ASYNR. Address= 8’hF9 Audio ADC/DAC Test Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 AADC_p d5 AADC_p d4 AADC_p d3 AADC_p d2 AADC_p d1 1-bit 0-bit AADC_pdX: Power down of Audio ADC X, active high. Address= 8’hFA Audio ADC/DAC Bias 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 4’h0 4’h0 ADAC_bias AADC_bias ADAC_bias: Audio DAC’s bias setting. AADC_bias: Audio ADC’s bias setting. Final Doc No: DM5866-DS-F01 August 19, 2015 74 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’hFB Audio ADC/DAC Test Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 3’h0 0 0 0 AADCSEL SW_AU DIOTST EN 1-bit 0-bit 2’h0 VADCBYPOPT VADCBYPOPT:Video ADC bypass source option 2’b00: external A/B channel mode. 2’b01: external only A channel mode. 2’b10: external ADI mode. SW_AUDIOTSTEN:When 1, chip enter to Audio Test mode, and drives Audio ADC/DAC test signal to I/O pins. AADCSEL: Under Audio ADC test mode. 3’h0: AADC_1[15:0] selected to output pins. 3’h1: AADC_2[15:0] selected to output pins. 3’h2: AADC_3[15:0] selected to output pins. 3’h3: AADC_4[15:0] selected to output pins. 3’h4: AADC_5[15:0] selected to output pins. Address= 8’hFC Audio Cascade Mode Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2’h0 0 0 0 0 0 0 casID SWCAS LVL0 SWCASI D MIXCAS EN I2SRCA SEN ACASIE N ACASO EN Final Doc No: DM5866-DS-F01 August 19, 2015 75 DM5866 960H and 720H 4 channels NTSC/PAL Decoder casID and SWCASLVL0 are effective only if (SWCASID=1). In this case SW should program these two registers to indicate the cascade ID of current stage. Please refer to the table below. If (SWCASID=0), these two registers are “don’t care”. ID of Current Stage SWCASLVL0 casID[1:0] 0 1’b1 2’b00 1 1’b0 2’b00 2 1’b0 2’b01 3 1’b0 2’b10 SWCASID: 0: The cascade ID is determined by HW logic. 1: The cascade ID is determined by SW through registers casID & SWCASLVL0. MIXCASEN: When set as 1 the analog audio input AIN5 will be included in the cascade operation (using ADATM). I2SRCASEN: 0: Audio cascade operation is disabled. 1: Audio cascade operation is enabled. ACASIEN: 0: Cascade input pin (ALINKI) is disabled. 1: Cascade input pin (ALINKI) is enabled. ACASOEN: Output enable control of cascade output pin (ALINKO). Active High. Final Doc No: DM5866-DS-F01 August 19, 2015 76 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’hFD Audio Cascade Mode Control and Status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 1 0 0 0 0 0 2’h0 FCLK14 4 I2SDAT AWIDTH ACASID CHG ACASA CT ACASID VLD ACASID FCLK144: Set as 0 when PLL is configured to output 108 MHz clock. Set as 1 when PLL is configured to output 144 MHz clock. I2SDATAWIDTH: 0: The I2S/DSP interface uses 16-bit data. 1: The I2S/DSP interface uses 8-bit data. ACASIDCHG: (RO, Write One to Clear) This flag is asserted when a change in ACASID is detected. ACASACT: (RO) This flag is asserted when audio cascade is in operation. ACASIDVLD: (RO) 0: The value of the register ACASID is not valid. 1: The value of the register ACASID is valid. ACASID: (RO) Indicate the cascade ID recognized by HW. 0: The ID of current stage is 1 or 0. 1: The ID of current stage is 2. 2: The ID of current stage is 3. Final Doc No: DM5866-DS-F01 August 19, 2015 77 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’hFE Mixed Audio Cascade & Audio Record 2 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ADATM OPT ADATR_ 2EN ADATMOPT: Set this bit the same value as MIXCASEN. ADATR_2EN: Set as 1 to enable audio record channel 2 (using MI2CD1) Address= 8’hFF REVNUM 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h65 REVNUM Final Doc No: DM5866-DS-F01 August 19, 2015 78 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Video Decoder HSYNC signal: BLANK TIP HSYNC_LEVEL HSYNCTH SYNC TIP HSYNC signal HSYNC_LEVEL=SYNC TIP + HSYNCTH Address= 8’h00 VD Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 0 1 0 BBRSTZ IFLDFA STSW FASTS WEN S_Video ADC_A ADI_AD C EN SRSTZ SRSTZ: SW reset video decoder, WO EN: Enable Video decoding function S_Video: input signal is S-Video FASTSWEN: Enable fast switch function IFLDFASTSW: Set 1 : Fast switch boundary at every field end. Only Valid when REG04[3] : 1’b0. Set 0: Fast switch boundary at frame end. BBRSTZ: BB reset only, WO Final Doc No: DM5866-DS-F01 August 19, 2015 79 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h01 WATCHSEL 7-bit 6-bit 5-bit 4-bit 4’hf 3-bit 2-bit 0 0 3-bit 2-bit 1-bit 0-bit 2’b01 AGC_LMT AGC_LMT: Analog AGC range AGC Address= 8’h02 AGC 7-bit 6-bit 5-bit 4-bit 4’h0 1 AGC_gain 1-bit 0-bit 0 1 1 AGC_DT RACKE N HWAGC EN SYNCC AGCEN 2-bit 1-bit 0-bit SYNCCAGCEN: Set 1, enable CAGC gain update. HWAGCEN: Hardware AGC enable AGC_DTRACKEN: Dynamic sync tip tracking enable AGC_gain: SW set AGC gain, RW Address= 8’h03 AGCDOWN_TH 7-bit 6-bit 5-bit 4-bit 3-bit 8’h63 AGCDOWNTH[7:0] AGCDOWNTH: ADC couldn’t larger than 867, if it is, will decrease the agc_gain. Final Doc No: DM5866-DS-F01 August 19, 2015 80 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h04 AGCDOWN_TH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 0 0 0 1 0 0 FASTSWOPT OFASTS W 1-bit 0-bit 2’h3 AGCDOWNTH[9:8] OFASTSW: Set 1: FASTSW control from input PIN(MPOUT). Set 0: FASTSW source from internal logic related to FASTSWOPT, RW FASTSWOPT: Set fast switch frame length ((FASTSWOPT+1)x8), RW Video Detection Misc Address= 8’h05 HSYNCTH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h30 HSYNCTH HSYNCTH: Set horizontal sync threshold level Address= 8’h06 Vdet_misc 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 0 1 1 BLACK OUT SETUP_ 7.5IRE OCCIRE N ColorPO UT MONOU T MUKSEL ColorPOUT: Set 1, VD will drive Color panel when no video signal detected, otherwise drive black panel. Color panel setting see 0x2A[6:4] Final Doc No: DM5866-DS-F01 August 19, 2015 81 DM5866 960H and 720H 4 channels NTSC/PAL Decoder OCCIREN: Set 1, VD will out CCIR656 SETUP_7.5IRE: Set 1, add 7.5 IRE to the BLANK_TIP BLACKOUT: Set 1, VD will drive black panel or blue panel when no video signal detected. MONOUT:force CCIR656 Cb=128, Cr=128 Color Killer Address= 8’h08 ColorKill TH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h20 CBDIFFTH[7:0] CBDIFFTH: Set the color burst difference threshold 2D Comb Filter Address= 8’h09 Com2D_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 FORCE_ VCOMB NOTCH FLTSEL DIS_VC OMB FORCE_ MONO DIS_VCOMB: Set 1 to disable vertical comb filter NOTCHFLTSEL: Set 0, use the wide band notchfilter Set 1, use the narrow band notchfilter FORCE_MONO: Set 1 to force the MONO signal mode. Final Doc No: DM5866-DS-F01 August 19, 2015 82 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h0C PAL SW CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2’h0 2-bit 1-bit 0 0-bit 0 Y_SHARP_GAIN PALSW OPT PALSWOPT: Set 1 to use standard pal switch define to demodulation. For line lock camera, set this bit to 1. Y_SHARP_GAIN: 2’h0 : no sharpness function 2’h1: sharpness gain 0.5 2’h2: sharpness gain 1 2’h3: sharpness gain 2 Address= 8’h10 VD Decoder status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PAL_Nc PALI,B,B1,G ,H,D/ PAL_N PAL_M PAL_60 NTSC443 NTSCJ/NTSCM COLOR KILL_52 5 COLOR KILL_62 5 The register show the video decoded status RO. Set 1 to enable SW force mode. Final Doc No: DM5866-DS-F01 August 19, 2015 83 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h11 VD_STS 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKLO CK_STS T DET_NO NILT DET_NONILT: RO. Detect the non-interlaced signal format. CLKLOCK_STST: RO. Clock offset lock status Address= 8’h12 DAGC_LMT 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h3 4’hf CLKOFF_LOCK DAGC_LMT 0-bit DAGC_LMT: Digital AGC range CLKOFF_LOCK: Clock offset locking function. 4’h0: always tracking Others: clock offset lock within CLKOFF_LOCK * 8 ppm. Address= 8’h13 VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 1 1 0 1 0 0 1 SWFAR 54MD HWFAR 54OPT GAINLO CK_OPT CLKOFF DIS CBADJ BLANK_ SHIFTE N ALINEL OCK CLKOFF _TRACK EN CLKOFF_TRACKEN: CLKOFFSET tracking enable Final Doc No: DM5866-DS-F01 August 19, 2015 84 DM5866 960H and 720H 4 channels NTSC/PAL Decoder ALINELOCK: active line lock option, fixed line start position. BLANK_SHIFTEN: set 1, blank level will be modified according to color burst mean value per line. CBADJ: Color burst adjust CLKOFFDIS: Disable clock offset tracking function GAINLOCK_OPT: Enable gain locking function after 16 frame decoded. HWFAR54OPT: Set 1, FAR4FS will operate in 54Mhz when detecting 4.43 subcarrier SWFAR54MD: Software force FAR4FS operate in 54Mhz. Address= 8’h14 VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 1 0 1 VDETOP T LTRACK OPT CLKLO CKOPT LLCFASTMD CLKLOCKOPT: Set 0 : Always tracking clock offset when abs(clkoffset)> CLKOFF_LOCK (REG12[7:4]) Set 1 : keep tracking until first time abs(clkoffset)< CLKOFF_LOCK(REG12[7:4]) LTRACKOPT: Set 1: Hardware continues active line (video) decoding when miss valid HSYNC signal until video loss. Set 0: Hardware performs active line (video) decoding until valid HSYNC signal detected. VDETOPT: Set 1: using rising edge of HSYNC signal as line detection timing. Set0: using falling edge of HSYNC signal as line detection timing. For long cable application, set this bit to 1. LLCFASTMD[1:0]: Line lock Auto Detection stable period. Valid when REG3B[5]=1. Final Doc No: DM5866-DS-F01 August 19, 2015 85 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Set 0: check line lock mode right after decode started Set 1: check line lock mode after 8 frames decoded. Set 2, 3: check line lock mode after 16 frames decoded. Address= 8’h15 CLKOFF_CTL 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 1 0 0 CLKFRA CEN FIXHSY NC_MD L SWFIXC LOCKO FF SWFIXCLOCKOFF: Set 1, SW fixed clock offset. Force clock offset value= {REG25[4:0],REG24[7:0],REG23[7:0]}. FIXHSYNC_MDL: Set 1, fixed the HSYNC_LEVEL to be REG05 HSYNCTH. CLKFRACEN: Set 1, enable fraction clock offset tracking. Address= 8’h17 CTI gain 7-bit 6-bit 0 0 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 6’d10 HMIDTR ACK HMIDTRACK: Set 1: tracking BLANK TIP each line at Front Porch Blanking position (REG4B[7:0]). Set 0: tracking BLANK TIP at CVBS serration period. Final Doc No: DM5866-DS-F01 August 19, 2015 86 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h18 LOWTRACK 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 FSHYBC OPT DISCOL KILL NONINT EN CAGCO PT TRHSYN COPT LOWTR ACK TRHSYN CTH TRHSYNCTH: Set 1: enable HW auto update HSYNCTH during video detection. Set 0: use fix HSYNCTH (REG05[7:0]) during video detection. LOWTRACK: Set 1: tracking SYNC TIP per line(s) from LOWLEVEL TRACKER. Set 0: tracking SYNC TIP at CVBS serration period. TRHSYNCOPT: Set 1: use fix HSYNCTH (REG05) during video detection Set 0: enable HW auto update HSYNCTH during video detection. CAGCOPT: Set 1 to enable color AGC. NONINTEN: Set 1 to enable auto detect non-interlaced singal. DISCOLKILL: Set 1 to disable auto detect color kill mode FSHYBCOPT: ONLY valid under FASTSWEN. Set 1: Keep previous tracked HSYNCTH Set 0: use REG05 as HSYNCTH Final Doc No: DM5866-DS-F01 August 19, 2015 87 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h20 AGC gain 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 DAGC Gain AAGC Gain AAGC Gain: Analog AGC gain setting, RO DAGC Gain: Digital AGC gain setting, RO Address= 8’h21 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SYNC_TIP[7:0] SYNC_TIP: RO Address= 8’h22 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 BLANK_TIP[7:0] BLANK_TIP: RO Final Doc No: DM5866-DS-F01 August 19, 2015 88 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h23 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKOFF[7:0] CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm) Address= 8’h24 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKOFF[15:8] CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm) Address= 8’h25 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SYNC_TIP[20:16] SYNC_TIP: RO Final Doc No: DM5866-DS-F01 August 19, 2015 89 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h26 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 BLANK_TIP[9:8] SYNC_TIP[9:8] BLANK_TIP: RO SYNC_TIP: RO Address= 8’h29 Blue Panel Select 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PALBLP ANL NTSCBL PANL PALBLPANL: Valid when REG06[3]=1. When no signal, SW sets PAL blue panel out. NTSCBLPANL: Valid when REG06[3]=1. When no signal, SW sets NTSC blue panel out. When PALBPANL=0, NTSCBLPANL=0. HW takes PAL as default mode. Address= 8’h2A VD_MISC 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 0 0 0 0 0 0 ColorOut Final Doc No: DM5866-DS-F01 August 19, 2015 1-bit 0-bit 2’h2 MPP_OPT 90 DM5866 960H and 720H 4 channels NTSC/PAL Decoder MPP_OPT: (Enable when GPOSEL (REG7A[7]) = 1’b1) 2’h0: drive field info to pin. 2’h1: drive Active info to pin. 2’h2: drive NOVID info to pin. 2’h3: drive FASTSW_SEL info to pin. VD_MPP signal pin out: (VD0,VD1,VD2,VD3)( MI2CD0, MI2CD1, MI2CD2, MI2CD3) ColorOut: valid when REG06[3]=1 and REG06[0]=1. 3’h0: blue panel 3’h1: red panel 3’h2: white panel 3’h3: green panel 3’h4: magenta panel 3’h7: color rotation mode, blue red white green magenta black blue… Color Process Address= 8’h2B COLOR_EXT 7-bit 6-bit 0 0 5-bit 4-bit 2’h1 3-bit 2-bit 1-bit 0-bit 0 0 0 1 NTSC_C CIREXT EXT_CO LOR CCIRBL ANKOP T EXT_COLOR: Set 1, Y/Cb/Cr value from 8’h1~8’hfe Final Doc No: DM5866-DS-F01 August 19, 2015 91 DM5866 960H and 720H 4 channels NTSC/PAL Decoder NTSC_CCIREXT: Set 1 in NTSC mode, CCIR656 output 487 active line. CCIRBLANKOPT: Set 1: output blanking period close to standard CCIR656. Set 0: with short V blank lines before active field start. Address= 8’h2C Hue 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’h0 Hue[7:0] Hue: Hue[9:0] = {REG33[1:0],REG2C[7:0]} 10’h0~10’h3ff 0~360 degree Address= 8’h2D Saturation 7-bit 6-bit 5-bit 4-bit 3-bit 8’h10 Saturation Saturation: unsigned, Range : 0 ~ 15.9375 8’hff : maximum, about x16 color intensity. 8’h00: (no color) Final Doc No: DM5866-DS-F01 August 19, 2015 92 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h2E Contrast 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’h80 Contrast Contrast: unsigned, Range : 0~2 8’hff: maximum (x2) contrast 8’h80: original signal (x1) 8’h00: minimum contrast Address= 8’h2F Brightness 7-bit 6-bit 5-bit 4-bit 3-bit 8’h00 Brightness Brightness: singed 8’h7f: brightest 8’h80: darkest Final Doc No: DM5866-DS-F01 August 19, 2015 93 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h30 INT Mask 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 MDCHG _1_MAS K VLOST_ 1_MASK VDET_1 _MASK MDCHG _0_MAS K VLOST_ 0_MASK VDET_0 _MASK VDET_0_MASK: Set 1, enable register 0x31 VDET_0 interrupt function, RW VLOST_0_MASK: Set 1, enable register 0x31 VLOST_0 interrupt function, RW MDCHG_0_MASK: Set 1 enable register 0x31 MDCHG_0 interrupt function, RW VDET_1_MASK: Set 1 to enable register 0x31 VDET_1 interrupt function, RW VLOST_1_MASK: Set 1 enable register 0x31 VLOST_1 interrupt function, RW MDCHG_1_MASK:Set 1 enable register 0x31 MDCHG_1 interrupt function, RW Address= 8’h31 INT status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 MDCHG _1 VLOST_ 1 VDET_1 MDCHG _0 VLOST_ 0 VDET_0 VDET_0: when detect video signal, the interrupt set, set by HW, set 1 to clear VLOST_0: when lose video signal, the interrupt set, set by HW, set 1 to clear MDCHG_0: when detect video signal change, the interrupt set, set by HW, set 1 to clear VDET_1: valid for fast switch mode channel B, when detect video signal, the interrupt set, set by HW, set 1 to clear VLOST_1: valid for fast switch mode channel B, when lose video signal, the interrupt set, set by HW, set 1 to clear Final Doc No: DM5866-DS-F01 August 19, 2015 94 DM5866 960H and 720H 4 channels NTSC/PAL Decoder MDCHG_1: valid for fast switch mode channel B, when detect video signal change format, the interrupt set, set by HW, set 1 to clear Address= 8’h32 650 Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 S960H STVL65 0 S960H :Sony Effio mode NTSC mode : 948x480 PAL mode: 936x576 STVL650: 960 Mode When set 1 : NTSC mode 960x480, PAL mode 960x576 When set 0 : NTSC mode 720x480, PAL mode 720x576 Address= 8’h33 HUE 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Hue[9:8] Hue: Hue[9:0] = {REG33[1:0],REG2C[7:0]} 10’h0~10’h3ff Final Doc No: DM5866-DS-F01 August 19, 2015 0~360 degree 95 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h34 FIELD OPTION 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 FIELD_I NV FIELD_ ONLY FIELD_ONLY: CCIR656 signal output field 0 only FILED_INV: Inverse output CCIR656 signal field Address= 8’h35 Chroma Average 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 CAVNTS CMD CAVPAL MD CAVNTSCMD: Set 1, enable NTSC mode Cb/Cr line average. Set 0, disable. CAVPALMD: Set 1, enable PAL mode Cb/Cr line average. Set 0, disable. Address= 8’h36 MASK CCIR656 LINE 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 MASKA LL Final Doc No: DM5866-DS-F01 August 19, 2015 PAL_M SK3 96 DM5866 960H and 720H 4 channels NTSC/PAL Decoder PAL_MSK3: Set 1, it will mask field 0 and 1 last lines according to REG37 MASKALL: mask all active Address= 8’h37 MASK LINE 7-bit 6-bit 5-bit 4-bit 3’h3 0 3-bit 2-bit 1-bit 0-bit 3’h3 0 MSK_LINE_F1 MSK_LINE_F0 MSK_LINE_F0: When REG36[0] = 1, Mask Field 0 last number of active lines (0-7) MSK_LINE_F1: When REG36[0] = 1, Mask Field 1 last number of active lines (0-7) Address= 8’h38 MONO TH 7-bit 6-bit 5-bit 1 0 0 4-bit 3-bit MONO_ EN 2-bit 1-bit 0-bit 5’d31 MONO_TH MONO_TH: MONO mode AGC threshold. AGC max value 30. when set MONO_TH 31. AGC will always less than MONO_TH. MONO_EN: Set 0, when no valid color burst detected. Output CCIR656 Y through Notch filter. Set 1, when no valid color burst detected. Output CCIR656 Y through Notch filer if AGC_GAIN>=MONO_TH, otherwise output CCIR656 Y with ADC data. When No valid color burst detected (color kill mode). Output CCIR656 Cb/Cr with 128 (no color). Final Doc No: DM5866-DS-F01 August 19, 2015 97 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h39 COLOR BURST DETECT 7-bit 6-bit 0 5-bit 4-bit 3-bit 2-bit 1-bit 3’h4 4’h5 COLBSTCYC COLBSTHSEL 0-bit COLBSTHSEL:Color Burst detection threshold. 4’h0:COLBSTH = 0.125*(BLANK TIP – SYNC TIP) 4’h1:COLBSTH = 0.25*(BLANK TIP – SYNC TIP) 4’h2:COLBSTH = 0.375*(BLANK TIP – SYNC TIP) 4’h3:COLBSTH = 0.5*(BLANK TIP – SYNC TIP) 4’h4:COLBSTH = 0.09375*(BLANK TIP – SYNC TIP) 4’h5:COLBSTH = 0.078125*(BLANK TIP – SYNC TIP) 4’h6:COLBSTH = 0.0625*(BLANK TIP – SYNC TIP) 4’h7:COLBSTH = 0.03125*(BLANK TIP – SYNC TIP) 4’h8:COLBSTH = 0 When color burst peak to peak value larger than COLBSTHSEL, it’s been considered a good color burst signal cycle. COLBSTCYC: Final Doc No: DM5866-DS-F01 August 19, 2015 When COLBSTCYC numbers of valid color bust cycle detected, VD will decode video with color and Color AGC will optionally started. Otherwise will enter color kill mode. 98 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h3A CAGC 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 1 0 0 0 0 0 0 0 CAGCE N CAGCL OCKOP cagc_gain cagc_gain: RO. Chroma gain value. [5:2] integer, [1:0] fractional. (max 15.75, min 1) CAGCLOCKOPT: Set 1, enable color AGC tracking until CAGC gain stable. Set 0, color AGC tracking for first 15 video decoded frames. CAGCEN : Set 1, enable color AGC. Address= 8’h3B Line Lock Camera 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CAMLO CKOPT LOCKC AM_DET HLOCK DET1 ACTSHIFT ACTSHIFT: Active region shift, 2’s compliment (-16~15) HLOCKDET1: Set 1, to enable auto-detect Line Lock camera. LOCKCAM_DET: RO, Line lock camera detected. (RO) CAMLOCKOPT: Set 1, when line lock camera used. Final Doc No: DM5866-DS-F01 August 19, 2015 99 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h3C LLOCKTH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’d20 LLOCKTH LLOCKTH: Line Lock auto detection threshold, valid only when 0x3B[5]=1. When REG13[1]=1, line boundary difference within a field larger than LLOCKTH, Line Lock Camera detected. Note: when clock offset tracking unstable and REG13[1]=1, line boundary difference might be large wthin a field. Address= 8’h3D VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ORSTO PT OBFOV F OBFUD F LLFAR4 FSOPT1 LLFAR4 FSOPT LLFAR4FSOPT: Set 1, decode video chroma without clock offset compensation. Set 0, decode video choma after clock offset compensation. Set this bit to one for Line Lock Camera. LLFAR4FSOPT1: Set 1, Auto adjust the active region related to clock offset. When force line lock mode, set this bit to 1; OBFUDF: RO. CCIR output buffer under flow. OBFOVF: RO. CCIR output buffer over flow. ORSTOPT: Set 1, Reset CCIR output buffer when output buffer overflow or underflow. Final Doc No: DM5866-DS-F01 August 19, 2015 100 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h3D OUT BUFFER 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h1a OBFTH OBFTH: CCIR656 output buffer ready threshold. Once CCIR656 output buffer count is larger than OBFTH, starts output CCIR656 active region. PS. CCIR656 output buffer max length is 48, set OBFTH around middle level of buffer length. Address= 8’h40 CCIROUT TYP EN 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 H_SAV_ ACT CROPE N FLDCHI DEN EAVCHI DEN SWCHID EN SWCHIDEN: Valid when REG00[5]=1(FASTSWEN). Add SW channel ID in first 4 data of active line, valid at fast switch mode.(field/frame) EAVCHIDEN: Valid when REG00[5]=1(FASTSWEN) Add channel ID in EAV[3:0] and SAV[3:0], valid at fasts witch mode. (field/frame) FLDCHIDEN: Valid when REG00[6:5]=2’h3 (IFLDFASTSW, FASTSWEN), output CVBS source A to field 0, output CVBS source B to field 1. CROPEN: Video cropping function enable. H_SAV_ACT: Set 1, HSYNC signal will include SAV data, otherwise HSYNC signal only at active region. Final Doc No: DM5866-DS-F01 August 19, 2015 101 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h41 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2’h0 2’h3 2’h0 2’h0 H_STR[9:8] H_ACT[9:8] V_STR[9:8] V_ACT[9:8] H_STR[9:8]: It defined the number of pixels start after SAV. H_ACT[9:8]: It defined the number of active region. V_STR[9:8]: It defined VSYNC start after active region line. V_ACT[9:8]: It defined the number of VSYNC during active region. H_STR + H_ACT < total number of pixels per line. V_STR + V_ACT < total number of lines per field. Address= 8’h42 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’h0 H_STR[7:0] Address= 8’h43 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 8’hC0 H_ACT[7:0] Final Doc No: DM5866-DS-F01 August 19, 2015 102 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h44 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’h0 V_STR[7:0] Address= 8’h45 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 8’d240 V_ACT[7:0] Address= 8’h46 Cb/Cr Slicer 7-bit 6-bit 5-bit 4-bit 3-bit 1 3’h2 SLICER _EN SLICER_RANGE SLICER_EN: CB/CR coring function enable. SLICER_RANGE: Coring range (0 ~7). When 128 – SLICER_RANGE < (CB/CR) < 128+SLICER_RANGE, force the Chroma value to 128. Final Doc No: DM5866-DS-F01 August 19, 2015 103 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h4B BLANK1TIP 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’hdc BLANK1TIP BLANK1TIP: valid when REG17[7]. Line Blanking sample position. Address= 8’h4C HSYNCLOWCYC 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 7’d20 0 HSYNCLOWCYC HSYNCLOWCYC: When low level (signal smaller than HSYNC LEVEL) signal exists over HSYNCLOWCYC, it’s considered as a HSYNC signal Candidate. Address= 8’h4D LMARG27 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h30 LMARG27 LMARG27: Sync singal detect margin after video detect. Final Doc No: DM5866-DS-F01 August 19, 2015 104 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Address= 8’h4E MARG27 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h30 MARG27 MARG27: Sync singal detect margin before video detect. Final Doc No: DM5866-DS-F01 August 19, 2015 105 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range Supply voltage range IOVDD to DGND -0.5V to 4.6V DVDD to DGND -0.5V to 2.5V PLL_AVDD to PLL_AGND -0.5V to 2.5V CH1_AVDD to CH1_AGND -0.5V to 2.5V Digital input voltage range, Vl to DGND Input voltage range, XTAL1 to PLL_GND Analog input voltage range Al to CH1_AGND Digital Output voltage range, VO to DGND Operating free-air temperature, TA Final Doc No: DM5866-DS-F01 August 19, 2015 -0.5V to 4.6V -0.5V to 2.5V -0.2V to 2.0V -0.5V to 4.6V -65C to 150C 106 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Recommended Operating Conditions IODVDD DVDD PLL_AVDD Audio VI(P-P) VIH VIL VIH_XTAL Digital I/O supply voltage Digital supply voltage Analog PLL supply voltage Analog core supply voltage Analog input voltage (accoupling necessary) Analog input voltage (accoupling necessary) Digital input voltage high Digital input voltage low XTAL input voltage high VIL_XTAL XTAL input voltage low IOH IOL IOH_SCLK High-level output current Low-level output current SCLK high-level output current SCLK low-level output current Operating free-air temperature CH1_AVDD VI(P-P) IOL_SCLK TA Final Doc No: DM5866-DS-F01 August 19, 2015 MIN 2.97 1.62 TYP 3.3 1.8 MAX 3.63 1.98 UNIT V V 1.62 1.8 1.98 V 1.7 1.8 1.9 V 1.0 V 5 0.8 V V 0.25 1.5 2 -0.3 0.7 PLL_AVDD -40 V 0.3 PLL_AVDD 2 -2 mA mA 4 mA -4 mA 85 V o C 107 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Crystal Specifications CRYSTAL SPECIFICATIONS Frequency Frequency tolerance MIN NOM MAX UNIT 27.0/36.0 100 MHz ppm Electrical Characteristics DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH1_AVDD = 1.8 V, IOVDD = 3.3 V For minimum/maximum values: TA = -40C to 85C, and for typical values: TA = 25C unless otherwise noted DC Electrical Characteristics PARAMETER TEST CONDITIONS (see NOTE 1) IDD(IO_D) Digital I/O supply current IDD(D) Digital core supply current IDD(PLL_A) Analog PLL supply current IDD(CH1-A) IDD(A) Analog ADC/DAC supply current PTOT Total power dissipation, normal mode PDOWN Total power dissipation, power-down mode Ci Input capacitance VOH Output voltage high Color bar input Color bar input VOL IOL = -2 mA Output voltage low TYP MAX UNIT 77.3 mA 442.4 mA 12 Color bar input 101.1 Color bar input 1254.4 Color bar input By design IOH = 2 mA VOH_SCLK SCLK output voltage IOH = 4 mA high VOL_SCLK SCLK output voltage low IOL = -2 mA IIH High-level input current VI = VIH IIL Low-level input current VI = VIL NOTE 1: Measured with a load of 15 pf. Final Doc No: DM5866-DS-F01 August 19, 2015 MIN mA 205 mW 15.3 mW 8 pF 0.8 IOVDD V 0.22 IOVDD 2.3 V V 0.6 50 50 V A A 108 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Analog Processing and A/D Converters PARAMETER TEST CONDITIONS MIN TYP MAX Zi Input impedance, analog By design 500 video inputs Ci Input capacitance, analog By design 10 video inputs Vi(pp) Input voltage range * 0.25 1 Ccoupling = 0.1 F 12 G Gain control range DNL DC differential non-linearity A/D only 2 INL DC integral non-linearity A/D only 3 Fr Frequency response 6 MHz -0.9 -3 SNR Signal-to-noise ratio 6 MHz, 1.0 Vp-p 50 NS Noise spectrum 50% flat field 50 DP Differential phase 1.5 DG Differential gain 0.5% * The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 . Final Doc No: DM5866-DS-F01 August 19, 2015 UNIT k pF V dB LSB LSB dB dB dB 109 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Timing Clocks, Video Data, Sync timing Data Format : CCIR656 output PARAMETER PIXCLK High pulse duration PIXCLK Low pulse duration CCIR656 data out setup time CCIR656 data out hold time SYMBOL thw tlw tsu th MIN 18.5 18.5 18.5 18.5 TYP MAX UNIT ns ns ns ns Output:CCIR656 PIXCLK (27MHz) CCIR656 (27MHz) thw tlw FF 00 tsu th 00 XY Cb0 Y0 Cr0 Figure 3-2 . Clocks, CCIR656 Output Data Timing Data Format : CCIR656 input PARAMETER PIXCLK High pulse duration PIXCLK Low pulse duration CCIR656 data out setup time CCIR656 data out hold time Final Doc No: DM5866-DS-F01 August 19, 2015 SYMBOL thw tlw tsu th MIN 18.5 18.5 18.5 18.5 TYP MAX UNIT ns ns ns ns 110 DM5866 960H and 720H 4 channels NTSC/PAL Decoder I2C Host Port Timing PARAMETER TEST CONDITIONS MIN t1 Bus free time between STOP and START t2 Setup time for a (repeated) START condition t3 Hold time (repeated) START condition t4 Setup time for STOP condition t5 Data setup time t6 Data hold time t7 Rise time I2CD and I2CLK signal t8 Fall time I2CD and I2CLK signal Cb Capacitive load for each bus line fI2C I2C clock frequency STOP TYP MAX UNIT 1.3 s 0.6 s 0.6 s 0.6 200 0 s ns ns 50 250 ns 250 START START ns 120 pF 400 kHz STOP SI2CD t1 t5 t6 t7 t8 t2 t3 t4 SI2CLK Write Address SADD[0] Pull low SADD[1] Pull low SADD[0] Pull high SADD[1] Pull low SADD[0] Pull low SADD[1] Pull high SADD[0] Pull high SADD[1] Pull high SI2CLK 1 2 8 9 1 2 Read Address C0 C1 C2 C3 C4 C5 C6 C7 8 9 1 2 8 9 SI2CD START SI2CLK 1 WRITE ADDRESS 2 8 9 ACK 1 2 REG ADDRESS 8 9 ACK 1 2 DATA 8 9 1 ACK 2 STOP 8 9 SI2CD START WRITE ADDRESS Final Doc No: DM5866-DS-F01 August 19, 2015 ACK REG ADDRESS ACK STOP START READ ADDRESS ACK DATA NOACK STOP 111 DM5866 960H and 720H 4 channels NTSC/PAL Decoder AC Characteristic of Digital Audio Interface ADATP Input Valid tod ACLK tlw tsu th thw Output Valid ADATR/ADATM ASYNR Min tlw thw tod tsu th clock low time clock high time output delay time input setup time input hold time Final Doc No: DM5866-DS-F01 August 19, 2015 Typ Max Unit ns ns ns ns ns 112 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Packaging Final Doc No: DM5866-DS-F01 August 19, 2015 113 DM5866 960H and 720H 4 channels NTSC/PAL Decoder Ordering Information Part Number Pin Count DM5866EP 128 Package LQFP (Pb-Free and Halogen-Free) Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. 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To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the Sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5646929 MAIL: [email protected] HTTP: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function. Final Doc No: DM5866-DS-F01 August 19, 2015 114