DM5160 960H and 720H 1 channel NTSC/PAL Decoder DAVICOM Semiconductor, Inc. DM5160 960H and 720H 1 channel NTSC/PAL Decoder DATA SHEET Preliminary Version: DM5160-DS-P01 February 27, 2013 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 1 DM5160 960H and 720H 1 channel NTSC/PAL Decoder REVISION HISTORY: Date Revision Description 2012/03/19 1.1 Initial release Preliminary Doc No: DM5160-DS-P01 February 27, 2013 2 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Table of Contents INTRODUCTION .....................................................................................................................6 FEATURES .................................................................................................................................. 6 APPLICATIONS ............................................................................................................................ 7 TERMINAL ASSIGNMENT ........................................................................................................8 TERMINAL FUNCTIONS ................................................................................................................. 9 BLOCK DIAGRAM ................................................................................................................. 11 INTRODUCTION ......................................................................................................................... 12 Video Synchronization ...................................................................................................... 12 Automatic Gain Control .................................................................................................... 12 Y/C Separation .................................................................................................................. 12 UV demodulation.............................................................................................................. 12 Luma/Chroma Processor ................................................................................................... 13 Mirror Function ................................................................................................................ 13 Video Interface ................................................................................................................. 13 VIDEO INTERFACE ...................................................................................................................... 14 BT601 SYNCHRONIZATION SIGNALS...................................................................................... 16 FILTER RESPONSE ...................................................................................................................... 18 Anti-alias LPF (960H) ......................................................................................................... 18 Decimation filter (960H) ................................................................................................... 18 Luma notch filter (960H) ................................................................................................... 19 Chroma band pass filter (960H)......................................................................................... 19 Y sharpness filter (960H) ................................................................................................... 20 UV demodulation low pass filter (960H) ............................................................................ 21 Anti-alias LPF (720H) ......................................................................................................... 22 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 3 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Decimation filter (720H) ................................................................................................... 22 Luma notch filter (720H) ................................................................................................... 23 Chroma band pass filter (720H)......................................................................................... 23 Y sharpness filter (720H) ................................................................................................... 24 UV demodulation low pass filter (720H) ............................................................................ 25 PLL ...................................................................................................................................... 26 HOST INTERFACE.................................................................................................................. 28 INTERNAL CONTROL REGISTERS............................................................................................ 29 VIDEO DECODER ....................................................................................................................... 29 AGC .................................................................................................................................. 30 Video Detection Misc ........................................................................................................ 31 Color Killer ........................................................................................................................ 32 2D Comb Filter .................................................................................................................. 32 PLL ........................................................................................................................................ 63 ELECTRICAL SPECIFICATIONS ................................................................................................ 66 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE ................................ 66 Recommended Operating Conditions ............................................................................... 67 Crystal Specifications ........................................................................................................ 68 ELECTRICAL CHARACTERISTICS ...................................................................................................... 68 DC ELECTRICAL CHARACTERISTICS ................................................................................................. 68 Analog Processing and A/D Converters ............................................................................. 69 Timing .............................................................................................................................. 70 PACKAGING ......................................................................................................................... 72 ORDERING INFORMATION.................................................................................................... 73 DISCLAIMER ........................................................................................................................... 73 PRODUCTS ............................................................................................................................ 73 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 4 DM5160 960H and 720H 1 channel NTSC/PAL Decoder CONTACT WINDOWS............................................................................................................... 73 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 5 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Introduction The DM5160 is a 1-channel video decoder designed for cameras with Sony’s new 960H CCD sensor. The DM5160 converts 9/6.5 MHz analog CVBS signals to digital 36/27 MHz CCIR656 signals. The DM5160 integrates an internal PLL, and decodes both 960H and 720H videos using the same (27MHz) external clock source. Features Video Decoder Accepts NTSC (M), PAL (B, D, G, H, I, M, Nc) and SONY 960H CCD Camera Video decoder could be programmed to operate at 27 or 36MHz. 10-bits video ADCs with built in 9/6.5 MHz analog low pass filter Automatic gain control for Luminance and Chrominance Programmable brightness, contrast, saturation, hue, and sharpness Support video interface YCbCr 4:2:2, 4:1:1, 4:2:0 format Support mirror function 5-H comb filter for YC separation Chrominance line filter for PAL phase error DLL for video synchronization, supports 27MHz crystal within +/-1000 ppm variance Advanced video synchronization for weak and noisy CVBS. Supports video signal transmitted by 500-meter long cable Support line lock camera Preliminary Doc No: DM5160-DS-P01 February 27, 2013 6 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Miscellaneous Use a single external 27MHz crystal to support both 960H and 720H video One programmable PLL integrated Slave I2C bus Ultra low power consumption. Under 150mW for normal operation. Under 50mW for suspend mode. 32-pin LQFP (5mmx5mm) or 32-pin QFN (4mmx4mm) package 1.8V core power, 3.3V analog power and 1.8V analog power Applications Suggested applications include DVR Car DVR Video capture card Preliminary Doc No: DM5160-DS-P01 February 27, 2013 7 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Terminal Assignment 32 31 30 29 28 27 26 25 AIP1A 1 24 VSYNC AIP1B 2 23 FID PLL_AGND 3 22 SDA PLL_AVDD 4 DM5160 21 SCL XTAL1 5 32 PIN LQFP 20 DVDD XTAL2 6 19 DGND AGND 7 18 Y0 RESETB 8 17 Y1 9 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 10 11 12 13 14 15 16 8 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Terminal Functions Pin Name Pin number Type Description Analog Video Signals AIP1A 1 AIP1B 2 A A AGND 7 G Analog input A. Analog input B. (analog chroma input) Analog ground. (used as signal input reference) Pin Name Pin number Type XTAL1 5 I XTAL2 6 O Clock input. A 27 MHz fundamental crystal or a single-ended oscillator can be connected Clock output. For connecting a crystal Pin Name Pin number Type Description Host Interface SCL SDA 21 22 I I/O The I2C serial interface Clock line. The I2C serial interface Data line. Pin Name Pin number Type Description 8 28 27 I I O Reset input. Low active Power down control pin. # is high active Interrupt output signal Pin number Type Description O Vertical Sync and multi-purpose output. See register for control information. Description Clock Signals General Signals RESETB PDN INTREQ Pin Name Video Output Signals VSYNC Preliminary Doc No: DM5160-DS-P01 February 27, 2013 24 9 DM5160 960H and 720H 1 channel NTSC/PAL Decoder HSYNC 25 O FID(MPOUT) 23 O AVID PCLK 26 9 O O Y7/I2CSEL 11 O Y6,Y5,Y4,Y3, Y2,Y1,Y0 12,13,14,15, O 16,17,18 Horizontal Sync and multi-purpose output. See register for control information. Multi-purpose output pin See register for control information. Active video indicator. Data output clk. Digital Video data output of 4:2:2 YCbCr[7]. I2CSEL: The i2c interface address select pin 0 Digital Video data output of 4:2:2 YCbCr[6:0]. Pin Name Pin number Type Description G P P G P G P NC NC Analog ground. 1.8V analog supply ADC. 1.8V analog supply PLL Analog ground PLL 3.3V digital I/O power Digital ground 1.8V digital core power Non Connected Non Connected Power and Ground Pins CH_AGND 31 CH_AVDD 32 PLL_AVDD 4 PLL_AGND 3 IO_DVDD 10 DGND 19 DVDD 20 REFP 29 REFM 30 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 10 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Block Diagram Video Synchronization AGC+CAGC Y/C Separation 2D Comb Filter UV Demod Luma/Chroma Processor Mirror Function Video Interface BT.656 or BT.1302 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 11 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Introduction The DM5160 video decoder contains two Video ADCs, a Video Synchronization block, an AGC block, an YC separation block, a UV Demodulation block, a Luma/Chroma , Processor block a Mirror Function block, and a BT 656 output block. In addition to CVBS, the DM5160 video decoder supports S-Video as well. Video Synchronization Video Synchronization performs video detection function. It automatically detects NTSC(M), NTSC(443), PAL(B,D,G,H,I), PAL(M), PAL(N), PAL(60). A smart video detection algorithm has been adopted. Therefore the DM5160 can perform fast and stable video synchronization even if the input signal is weak or the external crystal is with error as large as +/- 1000 ppm. Automatic Gain Control Automatic Gain Control (AGC) block performs both Luma AGC and Chroma AGC (CGAC). After video synchronization, Luma AGC adjusts input Luma level to the standard level (1Vpp). A further CAGC is performed after Luma AGC for signal with different Luma and Chroma attenuation. Y/C Separation Y/C Separation is for CVBS input only. After this block CVBS signal is separated into Luma and Chroma components. A 5-H 2D comb filter is adapted in the Y/C separation block. UV demodulation After Y/C separation, the UV demodulation block performs UV demodulation to the Chroma component. The phase and frequency of the UV demodulation is from a color burst subcarrier tracking block for both NTSC and PAL mode. A UV demodulation LPF is also adopted to filter out chroma noise. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 12 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Luma/Chroma Processor This block contains a programmable Luma sharpness filter. Hue, Saturation, Brightness and Contrast adjustment are also supported. The adjusted video is then transformed from YUV to YCbCr domain for CCIR656 output interface. Mirror Function The DM5160 also supports mirroring function. When mirroring function is performed, the samples at each line are horizontally left-right flipped. The following figure illustrates the result of horizontal mirroring. Video Interface The DM5160 video decoder supports 27MHz BT.656 (for 720H) and 36MHz BT.656-like (for 960H) video output format with BT.601 synchronization signals. A horizontal cropping function also included in this block. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 13 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Video Interface The DM5160 outputs 27MHz CCIR656 with 720x480/720x576 resolution (conventional 720H), or outputs 36MHz CCIR656-like format (BT.1302) with 960x480/960x576 resolution (Sony 960H). For these video outputs, SAV (Start of Active Video) and EAV (End of Active Video) are inserted to indicate active video interval. Each channel uses one output port to transmit video data, that is, luminance and chrominance data are transmitted through the same port. The output timing diagram is shown below. YCbCr 4:2:2 The number of data cycles in active horizontal line will vary according to the output YCbCr 4:2:2 format. For 720H video outputs, the active horizontal line contains 1440 cycles. For 960 H video outputs, the active horizontal line contains 1920 cycles. The DM5160 also supports the 4:2:0 and 4:1:1 format. The output timing diagram is shown below. YCbCr 4:2:0 Odd Line: Even Line: The number of data cycles in active horizontal line will vary according to the output YCbCr 4:2:0 format. For 720H video outputs, the active horizontal line contains 1080 cycles. For 960 H video outputs, the active horizontal line contains 1440 cycles. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 14 DM5160 960H and 720H 1 channel NTSC/PAL Decoder YCbCr 4:1:1 The number of data cycles in active horizontal line will vary according to the output YCbCr 4:1:1 format. For 720H video outputs, the active horizontal line contains 1080 cycles. For 960 H video outputs, the active horizontal line contains 1440 cycles. SAV and EAV indicate the active video interval. The values of the first three bytes in SAV and EAV are invariant preamble: 0xFF, 0x00, and 0x00. Different values are designated to the last byte according to different conditions: Field, V time, and H time. The MSB of this byte is always set to 1 and it’s followed by three bits to represent the condition of F, V, and H respectively. The last four bits are used as protection bits. The detailed code sequences of SAV and EAV are illustrated in the following table. FVH Value Condition SAV/EAV Code Sequence Field V time H time F V H Byte 0 Byte 1 Byte 2 Byte 3 Odd Odd Odd Odd Even Even Even Even Active Active Blank Blank Active Active Blank Blank SAV EAV SAV EAV SAV EAV SAV EAV 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x9D 0xAB 0xB6 0xC7 0xDA 0xEC 0xF1 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 15 DM5160 960H and 720H 1 channel NTSC/PAL Decoder BT601 Synchronization Signals External syncs are provided via the following signals ˙VSYNC (vertical sync signal) ˙HSYNC (horizontal sync signal) ˙FID (field indicator) ˙AVID (active video indicator) VSYNC, HSYNC and FID are programmed to be the external syncs for BT.601. And the AVID indicates the valid region of video active region. The default settings for a 525/625 line video output are given as an example below. Fig: BT 601 Timing diagram Preliminary Doc No: DM5160-DS-P01 February 27, 2013 16 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Fig: Horizontal Synchronization Signals Preliminary Doc No: DM5160-DS-P01 February 27, 2013 17 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Filter response Anti-alias LPF (960H) Decimation filter (960H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 18 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Luma notch filter (960H) Chroma band pass filter (960H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 19 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Y sharpness filter (960H) NSTC PAL Preliminary Doc No: DM5160-DS-P01 February 27, 2013 20 DM5160 960H and 720H 1 channel NTSC/PAL Decoder UV demodulation low pass filter (960H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 21 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Anti-alias LPF (720H) Decimation filter (720H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 22 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Luma notch filter (720H) Chroma band pass filter (720H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 23 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Y sharpness filter (720H) NTSC PAL Preliminary Doc No: DM5160-DS-P01 February 27, 2013 24 DM5160 960H and 720H 1 channel NTSC/PAL Decoder UV demodulation low pass filter (720H) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 25 DM5160 960H and 720H 1 channel NTSC/PAL Decoder PLL The DM5160 has an internal PLL to generate the system and pixel clocks. A 27MHz or 36 MHz is required for the PLL. The default PLL setting is shown in the following table. Crystal In clock (MHz) PLL out (MHz) Function 27 54 System/pixel clock PLL1 PLL default operated clock The PLL parameters for various system configurations are shown in the following table. Crystal(MHz) PLL out(MHz) M N OD 27 27 36 36 72 54 72 54 62 14 14 10 4 0 0 0 2 2 2 2 PLL1 Formula: CLK_OUT = XIN * (M+2)/[(N+2)*OD*2] Where CLK_OUT: PLL output frequency XIN: PLL input frequency. M: The numerator of PLL formula. [N, OD]: The denominator of PLL formula. Attention: 1. 100MHz <= CLK_OUT * OD <= 250MHz 2. 1MHz <= XIN/(N+2)<=25MHz 3. OD >=1 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 26 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Truth Table: PD BP 0 0 0 CLK_OUT 0 0 0 XIN Don’t Care 1 0 XIN 1 0 Don’t Care Don’t Care OE CLK_OUT Other Undefined PD: Power down control; Active high. BP: Bypass XIN to CLK_OUT; Active high. OE: CLK_OUT enable pin, Active low. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 27 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Host Interface In the DM5160, I2C is used for setting configuration and parameters, for example, brightness, contrast, saturation, hue, and sharpness control. The typical timing diagram of I2C write and read access is illustrated in the following figure. Write operation of I2C bus START WRITE ADDRESS ACK REG ADDRESS ACK STOP START READ ADDRESS ACK READ DATA ACK STOP Read operation of I2C bus 1 0 1 Write/Read Address Slave Address 1 1 0 I2CSEL R/W 0: Write; 1: Read The external Pull-up/Pull-down resister connected to the pin “Y7/I2CSEL” indicates the device address I2CSEL. When pull-up resistor is connected to the pin, it indicates I2CSEL with a high value. Otherwise when pull-down resistor is connected to the pin, it indicates I2CSEL with a low value. I2CSEL = 0 I2CSEL = 1 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 Write Address Read Address B8 BA B9 BB 28 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Internal Control Registers Video Decoder HSYNC signal: HSYNC_LEVEL=SYNC TIP + HSYNCTH Address= 8’h00 VD Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 0 1 0 S_Video ADC_A ADI_AD C EN SRSTZ BBRSTZ SRSTZ: SW reset video decoder, WO EN: Enable Video decoding function S_Video: When input signal is S-Video, set this bit to be 1 BBRSTZ: Base Band reset only, WO Preliminary Doc No: DM5160-DS-P01 February 27, 2013 29 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h01 WATCHSEL 7-bit 6-bit 5-bit 4-bit 4’hf 3-bit 2-bit 0 0 3-bit 2-bit 1 0 1-bit 0-bit 2’b01 AGC_LMT AGC_LMT: Analog AGC range AGC Address= 8’h02 AGC 7-bit 6-bit 5-bit 4-bit 4’h0 AGC_gain 1-bit 0-bit 1 1 AGC_DT RACKE N HWAGC EN SYNCC AGCEN 2-bit 1-bit 0-bit SYNCCAGCEN: Set 1, enable CAGC gain update. HWAGCEN: Hardware AGC enable AGC_DTRACKEN: Dynamic sync tip tracking enable AGC_gain: SW set AGC gain, RW Address= 8’h03 AGCDOWN_TH 7-bit 6-bit 5-bit 4-bit 3-bit 8’h63 AGCDOWNTH[7:0] AGCDOWNTH: ADC couldn’t larger than 867, if it is, will decrease the agc_gain. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 30 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h04 AGCDOWN_TH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 0 0 0 0 0 0 1-bit 0-bit 2’h3 AGCDOWNTH[9:8] Video Detection Misc Address= 8’h05 HSYNCTH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h30 HSYNCTH HSYNCTH: Set horizontal sync threshold level Address= 8’h06 Vdet_misc 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 0 1 1 BLACK OUT SETUP_ 7.5IRE OCCIRE N ColorPO UT MONOU T MUKSEL ColorPOUT: Set 1, VD will drive Color panel when no video signal detected, otherwise drive black panel. Color panel setting see 0x2A[6:4] OCCIREN: Set 1, VD will out CCIR656 SETUP_7.5IRE: Set 1, add 7.5 IRE to the BLANK_TIP BLACKOUT: Set 1, VD will drive black panel or blue panel when no video signal detected. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 31 DM5160 960H and 720H 1 channel NTSC/PAL Decoder MONOUT: Force CCIR656 Cb=128, Cr=128 Color Killer Address= 8’h08 ColorKill TH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h30 CBDIFFTH[7:0] CBDIFFTH: Set the color burst difference threshold 2D Comb Filter Address= 8’h09 Com2D_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 NOTCH FLTSEL DIS_VC OMB 1-bit 0-bit FORCE_ MONO DIS_VCOMB: Set 1 to disable vertical comb filter NOTCHFLTSEL: Set 0, use the wide band notchfilter Set 1, use the narrow band notchfilter FORCE_MONO: Set 1 to force the MONO signal mode. Address= 8’h0C PAL SW CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 2’h0 0 0 Y_SHARP_GAIN PALSWI NV PALSW OPT Preliminary Doc No: DM5160-DS-P01 February 27, 2013 32 DM5160 960H and 720H 1 channel NTSC/PAL Decoder PALSWOPT: Set 1 to use standard pal switch define to demodulation. For line lock camera, set this bit to 1. PALSWINV: Only valid when PALSWOPT=1. Set 1, PAL switch will be inversed. Y_SHARP_GAIN: 2’h0: no sharpness function 2’h1: sharpness gain 0.5 2’h2: sharpness gain 1 2’h3: sharpness gain 2 Address= 8’h10 VD Decoder status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PAL_Nc PALI,B,B1,G ,H,D/ PAL_N PAL_M PAL_60 NTSC443 NTSCJ/NTSCM COLOR KILL_52 5 COLOR KILL_62 5 The register show the video decoded status RO. Set 1 to enable SW force mode. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 33 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h11 VD_STS 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKLO CK_STS T DET_NO NILT DET_NONILT: RO. Detect the non-interlaced signal format. CLKLOCK_STST: RO. Clock offset lock status Address= 8’h12 DAGC_LMT 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 4’h3 4’hf CLKOFF_LOCK DAGC_LMT 0-bit DAGC_LMT: Digital AGC range CLKOFF_LOCK: Clock offset locking function. 4’h0: always tracking Others: clock offset lock within CLKOFF_LOCK * 8 ppm. Address= 8’h13 VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 1 1 0 1 0 1 1 SWFAR 54MD HWFAR 54OPT GAINLO CK_OPT CLKOFF DIS CBADJ BLANK_ SHIFTE N ALINEL OCK CLKOFF _TRACK EN Preliminary Doc No: DM5160-DS-P01 February 27, 2013 34 DM5160 960H and 720H 1 channel NTSC/PAL Decoder CLKOFF_TRACKEN: CLKOFFSET tracking enable ALINELOCK: Active line lock option, fixed line start position. BLANK_SHIFTEN: Set 1, blank level will be modified according to color burst mean value per line. CBADJ: Color burst adjust CLKOFFDIS: Disable clock offset tracking function GAINLOCK_OPT: Enable gain locking function after 16 frame decoded. HWFAR54OPT: Set 1, FAR4FS will operate in 54 MHz when detecting 4.43 subcarrier SWFAR54MD: Software force FAR4FS operate in 54MHz. Address= 8’h14 VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 1 0 1 1 1 VDETOP T LTRACK OPT CLKLO CKOPT LLCFASTMD CLKLOCKOPT: Set 0 : Always tracking clock offset when abs(clkoffset)> CLKOFF_LOCK (REG12[7:4]) Set 1 : keep tracking until first time abs(clkoffset)< CLKOFF_LOCK(REG12[7:4]) LTRACKOPT: Set 1: Hardware continues active line (video) decoding when miss valid HSYNC signal until video loss. Set 0: Hardware performs active line (video) decoding until valid HSYNC signal detected. VDETOPT: Set 1: using rising edge of HSYNC signal as line detection timing. Set0: using falling edge of HSYNC signal as line detection timing. For long cable application, set this bit to 1. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 35 DM5160 960H and 720H 1 channel NTSC/PAL Decoder LLCFASTMD[1:0]: Line lock Auto Detection stable period. Valid when REG3B[5]=1. Set 0: check line lock mode right after decode started Set 1: check line lock mode after 8 frames decoded. Set 2, 3: check line lock mode after 16 frames decoded. Address= 8’h15 CLKOFF_CTL 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 1 1 0 0 CLKFRA CEN FIXHSY NC_MD L SWFIXC LOCKO FF SWFIXCLOCKOFF: Set 1, SW fixed clock offset. Force clock offset value= {REG25[4:0],REG24[7:0],REG23[7:0]}. FIXHSYNC_MDL: Set 1, fixed the HSYNC_LEVEL to be REG05 HSYNCTH. CLKFRACEN: Set 1, enable fraction clock offset tracking. Address= 8’h17 HSYNC TRACK 7-bit 6-bit 1 0 HMIDTR ACK SWBLA NKTIP 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 6’d10 HMIDTRACK: Set 1: tracking BLANK TIP each line at Front Porch Blanking position (REG4B[7:0]). Set 0: tracking BLANK TIP at CVBS serration period. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 36 DM5160 960H and 720H 1 channel NTSC/PAL Decoder SWBLANK1TIP: Only valid when REG17[8] = 1. Set 1: the estimation position of blanking level is REG4B[7:0]. Address= 8’h18 LOWTRACK 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 1 0 0 0 1 0 NONINT EN CAGCO PT TRHSYN COPT LOWTR ACK TRHSYN CTH DISCOL KILL TRHSYNCTH: Set 1: enable HW auto update HSYNCTH during video detection. Set 0: use fix HSYNCTH (REG05[7:0]) during video detection. LOWTRACK: Set 1: tracking SYNC TIP per line(s) from LOWLEVEL TRACKER. Set 0: tracking SYNC TIP at CVBS serration period. TRHSYNCOPT: Set 1: use fix HSYNCTH (REG05) during video detection Set 0: enable HW auto update HSYNCTH during video detection. CAGCOPT: Set 1 to enable color AGC. NONINTEN: Set 1 to enable auto detect non-interlaced signal. DISCOLKILL: Set 1 to disable auto detect color kill mode Preliminary Doc No: DM5160-DS-P01 February 27, 2013 37 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h1A BURST DETECT OPTION 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 FCOLR DETEN COLR2C YC BRST_DLY BRST_DLY: The number of color burst cycle delay. COLR2CYC: Set 1, using two color burst cycle average to demodulation. Set 0, using four color burst cycle average to demodulation. FCOLRDETEN: Set 1, fixed the color burst detect position. Set 0, using auto detect color burst. Address= 8’h1B Reserved 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Reserved Reserved: RO. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 38 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h20 AGC gain 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 DAGC Gain AAGC Gain AAGC Gain: Analog AGC gain setting, RO DAGC Gain: Digital AGC gain setting, RO Address= 8’h21 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SYNC_TIP[7:0] SYNC_TIP: RO Address= 8’h22 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 BLANK_TIP[7:0] BLANK_TIP: RO Preliminary Doc No: DM5160-DS-P01 February 27, 2013 39 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h23 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKOFF[7:0] CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm) Address= 8’h24 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 CLKOFF[15:8] CLKOFF: RO, internal 2’s compliment clock offset tracking status. Unit (ppm) Address= 8’h25 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SYNC_TIP[20:16] SYNC_TIP: RO Preliminary Doc No: DM5160-DS-P01 February 27, 2013 40 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h26 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 BLANK_TIP[9:8] SYNC_TIP[9:8] BLANK_TIP: RO SYNC_TIP: RO Address= 8’h29 Blue Panel Select 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PALBLP ANL NTSCBL PANL PALBLPANL: Valid when REG06[3]=1. When no signal, SW sets PAL blue panel out. NTSCBLPANL: Valid when REG06[3]=1. When no signal, SW sets NTSC blue panel out. When PALBPANL=0, NTSCBLPANL=0. HW takes PAL as default mode. Address= 8’h2A VD_MISC 7-bit 6-bit 5-bit 4-bit 0 0 0 0 ColorOut 3-bit 2-bit 1-bit 0-bit 2’h0 2’h2 MPOUTMD MPP_OPT MPP_OPT: 2’h0: drive field info to pin. 2’h1: drive Active info to pin. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 41 DM5160 960H and 720H 1 channel NTSC/PAL Decoder 2’h2: drive NOVID info to pin. MPOUTMD: 2’h0: drive the XTI clock to FID(MPOUT) pin. 2’h1: drive the MPP to FID(MPOUT) pin. 2’h2 or 2’h3: drive FID_601 to FID(MPOUT) pin. ColorOut: valid when REG06[3]=1 and REG06[0]=1. 3’h0: blue panel 3’h1: red panel 3’h2: white panel 3’h3: green panel 3’h4: magenta panel 3’h7: color rotation mode, blue white green magenta red black blue… Color Process Address= 8’h2B COLOR_EXT 7-bit 6-bit 0 1 5-bit 4-bit 2’h0 3-bit 2-bit 1-bit 0-bit 0 0 0 1 NTSC_C CIREXT EXT_CO LOR CCIRBL ANKOP T EXT_COLOR: Set 1, Y/Cb/Cr value from 8’h1~8’hfe NTSC_CCIREXT: Set 1 in NTSC mode, CCIR656 output 487 active line. CCIRBLANKOPT: Set 1: output blanking period close to standard CCIR656. Set 0: with short V blank lines before active field start. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 42 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h2C Hue 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’h0 Hue[7:0] Hue: Hue[9:0] = {REG33[1:0],REG2C[7:0]} 10’h0~10’h3ff 0~360 degree Address= 8’h2D Saturation 7-bit 6-bit 5-bit 4-bit 3-bit 8’h10 Saturation Saturation: unsigned, Range: 0 ~ 15.9375 8’hff: maximum, about x16 color intensity. 8’h00: (no color) Address= 8’h2E Contrast 7-bit 6-bit 5-bit 4-bit 3-bit 8’h80 Contrast Contrast: unsigned, Range: 0~2 8’hff: maximum (x2) contrast 8’h80: original signal (x1) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 43 DM5160 960H and 720H 1 channel NTSC/PAL Decoder 8’h00: minimum contrast Address= 8’h2F Brightness 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h00 Brightness Brightness: singed 8’h7f: brightest 8’h80: darkest Address= 8’h30 INT Mask 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 MDCHG _0_MAS K VLOST_ 0_MASK VDET_0 _MASK VDET_0_MASK: Set 1, enable register 0x31 VDET_0 interrupt function, RW VLOST_0_MASK: Set 1, enable register 0x31 VLOST_0 interrupt function, RW MDCHG_0_MASK: Set 1 enable register 0x31 MDCHG_0 interrupt function, RW Preliminary Doc No: DM5160-DS-P01 February 27, 2013 44 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h31 INT status 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 MDCHG _0 VLOST_ 0 VDET_0 VDET_0: when detect video signal, the interrupt set, set by HW, set 1 to clear VLOST_0: when lose video signal, the interrupt set, set by HW, set 1 to clear MDCHG_0: when detect video signal change, the interrupt set, set by HW, set 1 to clear Address= 8’h32 650 Mode 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0 0 0 0 0 0 0 STVL65 0 0-bit S960H S960H : Sony Effio mode NTSC mode : 948x480 PAL mode: 936x576 STVL650: (9960 mode)960 Mode When set 1 : NTSC mode 960x480, PAL mode 960x576 When set 0 : NTSC mode 720x480, PAL mode 720x576 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 45 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h33 HUE 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 Hue[9:8] Hue: Hue[9:0] = {REG33[1:0],REG2C[7:0]} 10’h0~10’h3ff 0~360 degree Address= 8’h34 FIELD OPTION 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 FIELD_I NV FIELD_ ONLY FIELD_ONLY: CCIR656 signal output field 0 only FILED_INV: Inverse output CCIR656 signal field Address= 8’h35 Chroma Average 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 CAVNTS CMD CAVPAL MD INVEN INVEN: Mirror function enable. Set 1, enable mirror function. See pag.12 CAVNTSCMD: Set 1, enable NTSC mode Cb/Cr line average. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 46 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Set 0, disable. CAVPALMD: Set 1, enable PAL mode Cb/Cr line average. Set 0, disable. Address= 8’h36 MASK CCIR656 LINE 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 1 MASKA LL PAL_M SK3 PAL_MSK3: Set 1, it will mask field 0 and 1 last lines according to REG37 MASKALL: mask all active Address= 8’h37 MASK LINE 7-bit 6-bit 0 5-bit 3’h0 MSK_LINE_F1 4-bit 3-bit 0 2-bit 1-bit 0-bit 3’h0 MSK_LINE_F0 MSK_LINE_F0: When REG36[0] = 1, Mask Field 0 last number of active lines (0-7) MSK_LINE_F1: When REG36[0] = 1, Mask Field 1 last number of active lines (0-7) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 47 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h38 MONO TH 7-bit 6-bit 5-bit 1 0 0 4-bit 3-bit 2-bit 1-bit 0-bit 5’h1f MONO_ EN MONO_TH MONO_TH: MONO mode AGC threshold. AGC max value 30. when set MONO_TH 31. AGC will always less than MONO_TH. MONO_EN: Set 0, when no valid color burst detected. Output CCIR656 Y through Notch filter. Set 1, when no valid color burst detected. Output CCIR656 Y through Notch filer if AGC_GAIN>=MONO_TH, otherwise output CCIR656 Y with ADC data. When No valid color burst detected (color kill mode). Output CCIR656 Cb/Cr with 128 (no color). Address= 8’h39 COLOR BURST DETECT 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 1 3’h4 4’h5 CAGCT RACKE N COLBSTCYC COLBSTHSEL 0-bit COLBSTHSEL: Color Burst detection threshold. 4’h0 :COLBSTH = 0.125*(BLANK TIP – SYNC TIP) 4’h1 :COLBSTH = 0.25*(BLANK TIP – SYNC TIP) 4’h2 :COLBSTH = 0.375*(BLANK TIP – SYNC TIP) 4’h3 :COLBSTH = 0.5*(BLANK TIP – SYNC TIP) Preliminary Doc No: DM5160-DS-P01 February 27, 2013 48 DM5160 960H and 720H 1 channel NTSC/PAL Decoder 4’h4:COLBSTH = 0.09375*(BLANK TIP – SYNC TIP) 4’h5 :COLBSTH = 0.078125*(BLANK TIP – SYNC TIP) 4’h6 :COLBSTH = 0.0625*(BLANK TIP – SYNC TIP) 4’h7 :COLBSTH = 0.03125*(BLANK TIP – SYNC TIP) 4’h8 :COLBSTH = 0 When color burst peak to peak value larger than COLBSTHSEL, it’s been considered a good color burst signal cycle COLBSTCYC: When COLBSTCYC numbers of valid color bust cycle detected, VD will decode video with color and Color AGC will optionally started. Otherwise will enter color kill mode CAGCTRACKEN: CAGC Track enable. Set 0 to disable CAGC track Address= 8’h3A CAGC 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 1 0 0 0 0 0 0 0 CAGCE N CAGCL OCKOP cagc_gain cagc_gain: RO. Chroma gain value. [5:2] integer, [1:0] fractional. (max 15.75, min 1) CAGCLOCKOPT: Set 1, enable color AGC tracking until CAGC gain stable. Set 0, color AGC tracking for first 15 video decoded frames. CAGCEN : Set 1, enable color AGC. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 49 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h3B Line Lock Camera 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 1 0 0 0 0 0 0 0 CAMLO CKOPT LOCKC AM_DET HLOCK DET1 1-bit 0-bit ACTSHIFT ACTSHIFT: Active region shift, 2’s compliment (-16~15) HLOCKDET1: Set 1, to enable auto-detect Line Lock camera. LOCKCAM_DET: RO, Line lock camera detected. (RO) CAMLOCKOPT: Set 1, when line lock camera used. Address= 8’h3C LLOCKTH 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 8’h20 LLOCKTH LLOCKTH: Line Lock auto detection threshold, valid only when 0x3B[5]=1. When REG13[1]=1, line boundary difference within a field larger than LLOCKTH, Line Lock Camera detected. Note: when clock offset tracking unstable and REG13[1]=1, line boundary difference might be large within a field. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 50 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h3D VD_CFG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 1 0 0 0 0 0 0 ORSTO PT OBFOV F OBFUD F LLFAR4 FSOPT1 LLFAR4 FSOPT LLFAR4FSOPT: Set 1, decode video chroma without clock offset compensation. Set 0, decode video choma after clock offset compensation. Set this bit to one for Line Lock Camera. LLFAR4FSOPT1: Set 1, Auto adjust the active region related to clock offset. When force line lock mode, set this bit to 1; OBFUDF: RO. CCIR output buffer under flow. OBFOVF: RO. CCIR output buffer over flow. ORSTOPT: Set 1, Reset CCIR output buffer when output buffer overflow or underflow. Address= 8’h3D DROP FRAME 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 FRDROP FRDRO PEN FRDROPEN: Frame drop enable. Set 1 to enable drop frame function. FRDROP: Drop frame number: Output Frame Rate = (1-1/FRDROP)*Frame_Rate when FRDROP>0. NTSC mode Frame_Rate = 30 frame/sec PAL mode Frame_Rate = 25 frame/sec Preliminary Doc No: DM5160-DS-P01 February 27, 2013 51 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Ex. FREROPEN=1, FRDROP=2, NTSC mode; Output Frame Rate = (1-1/2)*30 frame/sec = 15 frame/sec Address= 8’h3F OUT BUFFER 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h1a OBFTH OBFTH: CCIR656 output buffer ready threshold. Once CCIR656 output buffer count is larger than OBFTH, starts output CCIR656 active region. PS. CCIR656 output buffer max length is 48, set OBFTH around middle level of buffer length. Address= 8’h40 CCIROUT TYP EN 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 PIX420E N PIX411E N CROPE N CROPEN: Video cropping function enable. PIX411EN: PIXOUT 411 mode enable. Set 1, the PIXOUT set to be YCbCr 4:1:1 The output format as below: CbYCrYYYCbYCrYYY… PIX420EN: PIXOUT 420 mode enable. Set 1, the PIXOUT set to be YCbCr 4:2:0 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 52 DM5160 960H and 720H 1 channel NTSC/PAL Decoder The output format as below: Odd line: CbYYCbYY… Even line: YCrYYCrY… Address= 8’h41 Cropping Register 7-bit 6-bit 5-bit 4-bit 2’h0 2’h3 H_STR[9:8] H_ACT[9:8] 3-bit 2-bit 1-bit 2’h0 0-bit 2’h0 H_STR[9:8]: It defined the number of pixels start after SAV. H_ACT[9:8]: It defined the number of active region. H_STR + H_ACT < total number of pixels per line. Address= 8’h42 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h0 H_STR[7:0] Preliminary Doc No: DM5160-DS-P01 February 27, 2013 53 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h43 Cropping Register 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit 8’hC0 H_ACT[7:0] Address= 8’h46 Cb/Cr Slicer 7-bit 6-bit 5-bit 4-bit 3-bit 1 3’h2 SLICER _EN SLICER_RANGE SLICER_EN: CB/CR coring function enable. SLICER_RANGE: Coring range (0 ~7). When 128 – SLICER_RANGE < (CB/CR) < 128+SLICER_RANGE, force the Chroma value to 128. Address= 8’h4A BT.601 Configuration 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 HSYNC_ INV VSYNC_ INV FID_INV AVID_ INV HSYNC_ EAV_ STR VSYNC_ ODD_ STR HSYNCWIDTH HSYNC_INV: Inverses output of BT.601 HSYNC signal. VSYNC_INV: Inverses output of BT.601 VSYNC signal. FID_INV: Inverses output of FID signal. (output pin is FID(MPOUT), see REG2A[3:2]) AVID_INV: Inverses output of AVID signal. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 54 DM5160 960H and 720H 1 channel NTSC/PAL Decoder HSYNC_EAV_STR: BT. 601 HSYNC option, please refer capture of Synchronization Signals. VSYNC_ODD_STR: BT. 601 VSYCN option, please refer capture of Synchronization Signals. HSYNCWIDTH: Software programmed the value of HSYNC valid length, this register only works when HSYNC_EAV_STR set 0. Address= 8’h4B BLANK1TIP 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h93 BLANK1TIP BLANK1TIP: valid when REG17[7]. Line Blanking sample position. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 55 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h4C HSYNCLOWCYC 7-bit 6-bit 5-bit 4-bit 0 3-bit 2-bit 1-bit 0-bit 7’d20 HSYNCLOWCYC HSYNCLOWCYC: When low level (signal smaller than HSYNC LEVEL) signal exists over HSYNCLOWCYC, it’s considered as a HSYNC signal Candidate. Address= 8’h4D LMARG27 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 1-bit 0-bit 8’h50 LMARG27 LMARG27: Sync signal detect margin after video detect. Address= 8’h4E MARG27 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 8’h50 MARG27 MARG27: Sync signal detect margin before video detect. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 56 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h50 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 HSYNC_ INV VSYNC_ INV INTREQ _INV MPOUT _INV HSYNC_ CSR_OE VSYNC_ CSR_OE INTREQ _CSR_O E MPOUT _CSR_O E MPOUT_CSR_OE: FID(MPOUT) output enable. INTREQ_CSR_OE: INTREQ output enable VSYNC_CSR_OE: VSYNC output enable HSYNC_CSR_OE: HSYNC output enable MPOUT_INV: FID(MPOUT) output inverse INTREQ_INV: INTREQ output inverse VSYNC_INV: VSYNC output inverse HSYNC_INV: HSYNC output inverse Address= 8’h51 RSTZ 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SHRSTZ TRSTZ TRSTZ: system reset SHRSTZ: SW hardware reset Preliminary Doc No: DM5160-DS-P01 February 27, 2013 57 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h52 VD POWER DOWN 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 HWPDN POR HWPDE N PLLPW RDNOP T SW_VD PWRDN IODIS SW_VDPWRDN: SW Power down video decoder. (When 1, power down) PLLPWRDNOPT: PLL Power down option. HWPDEN: HW Power down video decoder. HWPDNPOR: Only valid when HWPDEN=1. When 1, PIN PDN=1 is power down. When 0, PIN PDN=0 is power down IODIS: when 1 in normal function, all pin set to be input pin Address= 8’h54 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 4’ha 0 0 1 0 Bias B_Svide oC SWGAIN _EN pd_B pd_A pd_A: power down VADC channel A pd_B: power down VADC channel B B_SvideoC: when channel B input signal is S-video C, B_SvideoC set 1 SWGAIN_EN: software gain enable. Bias: video ADC bias config Preliminary Doc No: DM5160-DS-P01 February 27, 2013 58 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h55 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_GAINA SW_GAINA: Set SWGAIN_EN=1, software set VADC channel A0 gain. Address= 8’h56 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SW_GAINB SW_GAINB: Set SWGAIN_EN=1, software set VADC channel B gain. Address= 8’h57 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ClmpA ClmpA: VADC A0 channel clamp. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 59 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h58 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 ClmpB ClmpB: VADC B channel clamp. Address= 8’h59 VADC CONFIG 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 LPF_BY P lpf_sel LPF_BYP: Bypass Video ADC LPF when 1. lpf_sel: The bandwidth of the low pass filter is 10MHz when 1, 6.5MHz when 0 Address= 8’h5A TEST MODE 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 2’h0 SW_PLL BYPASS EN SW_VA DCBYP ASSEN SW_PLL _MBIST TST SW_VA DCTST VADCTST_SEL SW_PLL_MBISTTST: Set 1, drive PLL&MBIST detail signal to chip IO pins. SW_PLLBAPSSEN: Set 1, bypass internal pll out source. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 60 DM5160 960H and 720H 1 channel NTSC/PAL Decoder VADCTST_SEL: valid for VADCTSTEN and VADCBYPEN. in VADCTSTEN case: 2’b0: Dout = DoutA, 2’b1: Dout = DoutB 2’b2: Dout = when clk27 high DoutA, clk27 low DoutB SW_VADCTST: Set 1, drive VADCSEL indicated ADC outputs to chip IO pins. SW_VADCBYPASSEN: Set 1, bypass ADC data in from I/O pins. Address= 8’h5B MBIST CONTROL 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 MBDON E MBERR _1 MBERR _0 BISTGO BISTGO: Set 1 to start MBIST logic. HW auto clear this bit after MBIST done. MBDONE: Set by HW, set 1 to clear. MBEER_0: when read back 1, sram broken, Set by HW, set 1 to clear. MBEER_1: when read back 1, sram broken, Set by HW, set 1 to clear. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 61 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h5D CONFIG 7-bit 6-bit 0 5-bit 4-bit 3-bit 2-bit 1-bit 3’h0 0 3’h0 DYMUX_VCLK OPCLK_ INV DLYMUX_PCLK 0-bit DLYMUX_PCLK: Selected PCLK delay time. (3’h0 is smallest, 3’h7 is longest ) OPCLK_INV: Set 1 to inverse PCLK output. DLYMUX_VCLK: Selected pll_54 delay time to vadc. (3’h0 is smallest, 3’h7 is longest ) Address= 8’h5F REVISION_ID 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 8’h3B REVISION_ID REVISION_ID: RO, The DM5160 CHIP version ID. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 62 DM5160 960H and 720H 1 channel NTSC/PAL Decoder PLL Formula: CLK_OUT = XIN * (M+2)/[(N+2)*OD*2] Where CLK_OUT: PLL output frequency XIN: PLL input frequency. M: The numerator of PLL formula. [N, OD]: The denominator of PLL formula. Attention: 1. 100MHz <= CLK_OUT * OD <= 250MHz 2. 1MHz <= XIN/(N+2)<=25MHz 3. OD >=1 Truth Table: PD BP 0 0 0 CLK_OUT 0 0 0 XIN Don’t Care 1 0 XIN 1 0 Don’t Care Don’t Care OE CLK_OUT Other Undefined PD: Power down control; Active high. BP: Bypass XIN to CLK_OUT; Active high. OE: CLK_OUT enable pin, Active low. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 63 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h60 SW PLL Control 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWPLL RST SWPLL1 SWPLL1: set PLL1 input configuration from SWPLL1_XX set, otherwise hard wired with chip default vale. SWPLLRST: set 1, chip will enter a reset mode waiting for PLL stable in 1ms. After that, SW needs to re-program all register setting except PLL configuration. Address= 8’h61 SW PLL Config 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 0 0 0 0 0 0 0 0 SWPLL1 _OE SWPLL1 _PD SWPLL1 _BP SWPLL1_OD SWPLL1_BP: PLL1_BP SW program source. SWPLL1_PD: PLL1_PD SW program source. SWPLL1_OE: PLL1_OE SW program source. SWPLL1_OD: PLL1_OD SW program source Preliminary Doc No: DM5160-DS-P01 February 27, 2013 64 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Address= 8’h62 SWPLL1 M 7-bit 6-bit 5-bit 4-bit 3-bit 2-bit 1-bit 0-bit 2-bit 1-bit 0-bit OE 0 0 BP 0 0 OE 0 0 BP 0 0 8’h0 SWPLL1_M[7:0] SWPLL1_M: PLL1_M SW program source. Address= 8’h63 SWPLL1_N 7-bit 6-bit 5-bit 0 0 0 4-bit 3-bit 5’h0 SWPLL1 _M[8] SWPLL1_N SWPLL1_N: PLL1_N SW program source DM5160 PLL SETTINGS Ref: 27MHz Ref: 27MHz 72 MHz 54 MHz M 62 14 N 4 0 OD 2 2 PD 0 0 DM5160 PLL SETTINGS Ref: 36MHz Ref: 36MHz 72 MHz 54 MHz Preliminary Doc No: DM5160-DS-P01 February 27, 2013 M 14 10 N 0 0 OD 2 2 PD 0 0 65 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range Supply voltage range: IOVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... PLL_AVDD to PLL_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. CH1_AVDD to CH1_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... Digital input voltage range, Vl to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, XTAL1 to PLL_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog input voltage range Al to CH1_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Output voltage range, VO to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Doc No: DM5160-DS-P01 February 27, 2013 66 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Recommended Operating Conditions IODVDD DVDD PLL_AVDD CH1_AVDD VI(P-P) VIH VIL VIH_XTAL VIL_XTAL IOH IOL IOH_SCLK IOL_SCLK TA Digital I/O supply voltage Digital supply voltage Analog PLL supply voltage Analog core supply voltage Analog input voltage (ac-coupling necessary) Digital input voltage high Digital input voltage low XTAL input voltage high XTAL input voltage low High-level output current Low-level output current SCLK high-level output current SCLK low-level output current Operating free-air temperature Preliminary Doc No: DM5160-DS-P01 February 27, 2013 MIN TYP MAX UNIT 2.97 3.3 3.63 V 1.62 1.8 1.98 V 1.62 1.8 1.98 V 1.7 1.8 1.9 V 1.0 V 5 V 0.8 V 0.25 2 -0.3 0.7 PLL_AVDD V 0.3 PLL_AVDD -40 V 2 mA -2 mA 4 mA -4 mA 125 o C 67 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Crystal Specifications CRYSTAL SPECIFICATIONS MIN NOM MAX UNIT 27.0/36.0 MHz ±100 ppm Frequency Frequency tolerance Electrical Characteristics DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH1_AVDD = 1.8 V, IOVDD = 3.3 V For minimum/maximum values: TA = 0°C to 70°C, and for typical values: TA = 25°C unless otherwise noted DC Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (see NOTE 1) Color bar input 4.8 mA IDD(D) Digital core supply current Color bar input 50.7 mA IDD(PLL_A) Analog PLL supply current Color bar input 5.9 mA IDD(CH1-A) Analog PLL supply current Color bar input 26.1 mA PTOT Total power dissipation, normal mode Color bar input 165 205 mW PDOWN Total power dissipation, power-down mode Color bar input Ci By design IDD(IO_D) Digital I/O supply current Input capacitance Preliminary Doc No: DM5160-DS-P01 February 27, 2013 5 mW 8 pF 68 DM5160 960H and 720H 1 channel NTSC/PAL Decoder VOH Output voltage high IOH = 2 mA VOL Output voltage low IOL = -2 mA 0.8 IOVDD V 0.2 V 2 IOV DD VOH_SCLK SCLK output voltage high IOH = 4 mA 2 . 3 V VOL_SCLK SCLK output voltage low IOL = -2 mA 0 . 6 V IIH High-level input current VI = VIH ±50 µA IIL Low-level input current VI = VIL ±50 µA NOTE 1: Measured with a load of 15 pf. Analog Processing and A/D Converters PARAMETER TEST CONDITIONS By design Zi inputs Input impedance, analog video Ci inputs Input capacitance, analog video By design Vi(pp) Input voltage range * Ccoupling = 0.1 µF ∆G Gain control range DNL DC differential non-linearity INL Fr MIN TYP 500 MAX UNIT kΩ 10 0.25 pF 1 V 12 dB A/D only ±2 LSB DC integral non-linearity A/D only ±3 LSB Frequency response 6 MHz Preliminary Doc No: DM5160-DS-P01 February 27, 2013 -0.9 -3 dB 69 DM5160 960H and 720H 1 channel NTSC/PAL Decoder SNR Signal-to-noise ratio 6 MHz, 1.0 Vpp 50 dB NS Noise spectrum 50% flat field 50 dB DP Differential phase 1.5 ° DG Differential gain 0.5% * The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 Ω. Timing Clocks, Video Data, Sync timing (27/36MHz) Data Format : CCIR656 output PARAMETER PIXCLK High pulse duration PIXCLK Low pulse duration CCIR656 data out setup time CCIR656 data out hold time Preliminary Doc No: DM5160-DS-P01 February 27, 2013 SYMBOL thw tlw tsu th MIN 18.5/13.5 18.5/13.5 18.5/13.5 18.5/13.5 TYP MAX UNIT ns ns ns ns 70 DM5160 960H and 720H 1 channel NTSC/PAL Decoder I2C Host Port Timing PARAMETER TEST CONDITIONS t1 Bus free time between STOP and START t2 Setup time for a (repeated) START condition t3 Hold time (repeated) START condition t4 Setup time for STOP condition t5 Data setup time t6 Data hold time t7 Rise time I2CD and I2CLK signal t8 Fall time I2CD and I2CLK signal Cb Capacitive load for each bus line fI2C I2C clock frequency I2CSEL = 0 I2CSEL = 1 Preliminary Doc No: DM5160-DS-P01 February 27, 2013 MIN TYP MAX UNIT 1.3 µs 0.6 µs 0.6 µs 0.6 200 0 250 µs ns 50 ns ns 250 ns 120 pF 400 kHz Write Address B8 BA Read Address B9 BB 71 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Packaging 32 PIN LQFP Preliminary Doc No: DM5160-DS-P01 February 27, 2013 72 DM5160 960H and 720H 1 channel NTSC/PAL Decoder Ordering Information Part Number Pin Count DM5160EP 32 Package LQFP (Pb-Free and Halogen-Free) Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. 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To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the Sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5646929 MAIL: [email protected] HTTP: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function. Preliminary Doc No: DM5160-DS-P01 February 27, 2013 73