IT8783E/F (For A Version)

TI
AL
IT8783E/F
EN
Environment Control – Low Pin Count Input / Output
(EC - LPC I/O)
FI
D
Preliminary Specification V0.5
ITE TECH. INC.
C
O
N
(For A Version)
This specification is subject to Change without notice. It is provided “AS IS” and for reference only.
For purchasing information, please contact the nearest sales representatives.
Please note that the IT8783E/F V0.5 is applicabe to the A version.
N
O
C
TI
AL
EN
FI
D
Copyright © 2010 ITE Tech. Inc.
TI
AL
This is a Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous material issued for the products herein
referenced. Please contact ITE Tech. Inc. for the latest document(s).
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT8783E/F is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
Tel:
Fax:
886-2-29126889
886-2-2910-2551, 886-2-2910-2552
EN
ITE Tech. Inc.
Marketing Department
7F, No.233-1, Baociao Rd., Sindian City,
Taipei County 23145, Taiwan, ROC
If you have any marketing or sales questions, please contact:
P.Y. Chang, at ITE Taiwan:
E-mail: [email protected], Tel: 886-2-29126889 X6052, Fax: 886-2-29102551
You may also find the local sales representative nearest you on the ITE web site.
FI
D
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
C
O
N
Or e-mail [email protected] for more product information/services
N
O
C
TI
AL
EN
FI
D
Revision History
Revision History
Section
Revision
Page No.
Pin Description of Serial Port 6 Signals
„
The power information of the followings was added:
− Pin 85
z
RTS6#
z
GP34
z
CIRRX1
− Pin 77
z
SOUT6
z
GP35
17
Table 5-12
Pin Description of Keyboard Controller Signals
„
The power information of the followings was added:
z
GP10-13
21
Table 5-16
Pin Description of Miscellaneous Signals
„
The second function for pin 77 was corrected to #SOUT6.
23
GPIO Set 4 Multi-Function Pin Selection
Default=00h)
„
The default was modified to 00h.
Location Mapping Table
„
GP 60-62 were removed.
Register
(Index=28h,
80
C
O
N
FI
D
Table 8-18
EN
8.3.11
TI
AL
Table 5-9
www.ite.com.tw
A
IT8783F/E V0.5
N
O
C
TI
AL
EN
FI
D
Contents
CONTENTS
1. Features
................................................................................................................................................ 1
TI
AL
2. General Description ....................................................................................................................................... 3
3. Block Diagram................................................................................................................................................ 5
4. Pin Configuration ........................................................................................................................................... 7
5. Pin Description............................................................................................................................................. 11
6. List of GPIO Pins ......................................................................................................................................... 27
7. Power On Strapping Options ....................................................................................................................... 31
C
O
N
FI
D
EN
8. Configuration .............................................................................................................................................. 33
8.1 Description of Configuring Sequence ............................................................................................... 33
8.2 Description of Configuration Registers ............................................................................................. 35
8.2.1 Logical Device Base Address .............................................................................................. 43
8.3 Global Configuration Registers (LDN: All) ........................................................................................ 44
8.3.1 Configure Control (Index=02h)............................................................................................. 44
8.3.2 Logical Device Number (LDN, Index=07h) .......................................................................... 44
8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) ............................................................................ 44
8.3.4 Chip ID Byte 2 (Index=21h, Default=83h) ............................................................................ 44
8.3.5 Configuration Select and Chip Version (Index=22h, Default=00h) ...................................... 44
8.3.6 Clock Selection Register (Index=23h, Default=00h) ............................................................ 44
8.3.7 Software Suspend and Flash I/F Control Register (Index=24h, Default=0ss0s0s0b, MB
PnP)..........................................................................................................................................
8.3.8 GPIO Set 1 Multi-function Pin Selection Register (Index=25h, Default=00h)...................... 46
8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) .................... 46
8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) .................... 47
8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=00h) .................... 48
8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h) .................... 48
8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h) .................... 49
8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h) ...................................................... 50
8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=03h) .................... 51
8.3.16 GPIO Set 6 Enable Register (Index=2Dh, Default=00h) ..................................................... 51
8.3.17 Test 1 Register (Index=2Eh, Default=00h) .......................................................................... 52
8.3.18 Test 2 Register (Index=2Fh, Default=00h)........................................................................... 52
8.4 FDC Configuration Registers (LDN=00h) ......................................................................................... 53
8.4.1 FDC Activate (Index=30h, Default=00h) .............................................................................. 53
8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h) ............................................. 53
8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h).............................................. 53
8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)......................................................... 53
8.4.5 FDC DMA Channel Select (Index=74h, Default=02h) ......................................................... 53
8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)....................................... 53
8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)....................................... 54
8.5 Serial Port 1 Configuration Registers (LDN=01h) ............................................................................ 55
8.5.1 Serial Port 1 Activate (Index=30h, Default=00h).................................................................. 55
8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) .................................. 55
8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)................................... 55
8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) ............................................ 55
8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 56
8.6 Serial Port 2 Configuration Registers (LDN=02h) ............................................................................ 57
8.6.1 Serial Port 2 Activate (Index=30h, Default=00h).................................................................. 57
www.ite.com.tw
i
IT8783F/E V0.5
45
IT8783E/F (For A Version)
C
O
N
FI
D
EN
TI
AL
8.6.2 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) .................................. 57
8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)................................... 57
8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) ............................................ 57
8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 58
8.7 Parallel Port Configuration Registers (LDN=03h)............................................................................. 59
8.7.1 Parallel Port Activate (Index=30h, Default=00h).................................................................. 59
8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)..................... 59
8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h) .................... 59
8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)................ 59
8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) ............... 59
8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h) ........................................... 60
8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h) ............................................. 60
8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h) ............................. 60
8.8 Environment Controller Configuration Registers (LDN=04h) ........................................................... 61
8.8.1 Environment Controller Activate Register (Index=30h, Default=00h) .................................. 61
8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h) ................. 61
8.8.3 Environment Controller Base Address LSB Register (Index=61h, Default=90h) .................. 61
8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h) ....................... 61
8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h) ........................ 61
8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h) ........................... 61
8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h) ................................... 62
8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h) .............................................. 62
8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)....................................... 62
8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h) ............ 63
8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)....................................... 63
8.8.12 APC/PME Special Code Index Register (Index=F5h).......................................................... 65
8.8.13 APC/PME Special Code Data Register (Index=F6h)........................................................... 65
8.8.14 APC/PME Control (PCR 7) Data Register (Index=F7h)....................................................... 65
8.9 KBC(Keyboard) Configuration Registers (LDN=05h) ....................................................................... 66
8.9.1 KBC(Keyboard) Activate (Index=30h, Default=01h) ............................................................ 66
8.9.2 KBC (Keyboard) Data Base Address MSB Register (Index=60h, Default=00h) ................. 66
8.9.3 KBC (Keyboard) Data Base Address LSB Register (Index=61h, Default=60h) .................. 66
8.9.4 KBC (Keyboard) Command Base Address MSB Register (Index=62h, Default=00h) ........ 66
8.9.5 KBC (Keyboard) Command Base Address LSB Register (Index=63h, Default=64h) ......... 66
8.9.6 KBC (Keyboard) Interrupt Level Select (Index=70h, Default=01h)...................................... 66
8.9.7 KBC(Keyboard) Interrupt Type (Index=71h, Default=02h) .................................................. 67
8.9.8 KBC(Keyboard) Special Configuration Register (Index=F0h, Default=08h)........................ 67
8.10 KBC(Mouse) Configuration Registers (LDN=06h)............................................................................ 68
8.10.1 KBC(Mouse) Activate (Index=30h, Default=00h)................................................................. 68
8.10.2 KBC(Mouse) Interrupt Level Select (Index=70h, Default=0Ch)........................................... 68
8.10.3 KBC(Mouse) Interrupt Type (Index=71h, Default=02h) ....................................................... 68
8.10.4 KBC (Mouse) Special Configuration Register (Index=F0h, Default=00h) ........................... 68
8.11 GPIO Configuration Registers (LDN=07h) ....................................................................................... 69
8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)........... 69
8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)............ 69
8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h).................................... 69
8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h)..................................... 69
8.11.5 Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h) ............................ 69
8.11.6 Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h) ............................. 69
8.11.7 Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h) .......... 70
8.11.8 Watch Dog Timer 1, 2, 3 Control Register (Index=71h, 81h, 91h Default=00h).................. 70
8.11.9 Watch Dog Timer 1, 2, 3 Configuration Register (Index=72h, 82h, 92h Default=001s0000b)
www.ite.com.tw
ii
IT8783F/E V0.5
Contents
C
O
N
FI
D
EN
TI
AL
70
8.11.10 Watch Dog Timer 1, 2, 3 Time-Out Value (LSB) Register (Index=73h, 83h, 93h,
Default=38h)......................................................................................................................... 70
8.11.11 Watch Dog Timer 1, 2, 3 Time-Out Value (MSB) Register (Index=74h, 84h, 94h
Default=00h)......................................................................................................................... 71
8.11.12 GPIO Pin Set 1, 2, 3, 4, and 5 Polarity Registers (Index=B0h, B1h, B2h, B3h, and B4h ,
Default=00h)......................................................................................................................... 71
8.11.13 GPIO Pin Set 1, 2, 3, 4, and 5 Pin Internal Pull-up Enable Registers (Index=B8h, B9h,
BAh, BBh, and BCh, Default=00h) ....................................................................................... 71
8.11.14 Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h, and C4h,
Default=01h, 00h, 00h, 40h, and 00h) ................................................................................. 71
8.11.15 Simple I/O Set 1, 2, 3, 4, 5, and 6 Output Enable Registers (Index=C8h, C9h, CAh, CBh,
CCh, and CDh Default=01h, 00h, 00h, 40h, 00h, and 00h)................................................. 71
8.11.16 Panel Button De-bounce 0 Input Pin Mapping Register (Index=E0h, Default=00h)............ 72
8.11.17 Panel Button De-bounce 1 Input Pin Mapping Register (Index=E1h, Default=00h)............ 72
8.11.18 IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h) .... 72
8.11.19 IRQ External Routing 1-0 Interrupt Level Selection Registers (Index=E4h, Default=00h) .. 72
8.11.20 SPI Function Pin Selection Register (Index=EFh, Default=00001s0).................................. 72
8.11.21 SMI# Control Register 1 (Index=F0h, Default=00h)............................................................. 73
8.11.22 SMI# Control Register 2 (Index=F1h, Default=00h)............................................................. 73
8.11.23 SMI# Status Register 1 (Index=F2h, Default=00h) .............................................................. 74
8.11.24 SMI# Status Register 2 (Index=F3h, Default=00h) .............................................................. 74
8.11.25 SMI# Pin Mapping Register (Index=F4h, Default=00h) ....................................................... 75
8.11.26 Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h) ........ 75
8.11.27 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)................. 75
8.11.28 Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h) ....................................... 75
8.11.29 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h).................................. 75
8.11.30 GP LED Blinking 1 Control Register (Index=F9h, Default=00h) .......................................... 76
8.11.31 GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h) .................................. 76
8.11.32 GP LED Blinking 2 Control Register (Index=FBh, Default=00h).......................................... 76
8.12 Serial Port 3, 4, 5, 6 Configuration Registers (LDN=08h, 09h, 0Ah, 0Bh) ....................................... 77
8.12.1 Serial Port 3, 4, 5, 6 Activate (Index=30h, Default=00h)...................................................... 77
8.12.2 Serial Port 3, 4, 5, 6 Base Address MSB Register (Index=60h, Default= 03h, 02h, 03h, 02h)77
8.12.3 Serial Port 3, 4, 5, 6 Base Address LSB Register (Index=61h, Default= F8h) .................... 77
8.12.4 Serial Port 3, 4, 5, 6 Interrupt Level Select Register (Index=70h, Default= 04h, 03h, 04h,
03h)....................................................................................................................................... 77
8.12.5 Serial Port 3, 4, 5, 6 Special Configuration Register 1 (Index=F0h, Default=00h) .............. 77
8.13 Consumer IR Configuration Registers (LDN=0Ch) .......................................................................... 79
8.13.1 Consumer IR Activate (Index=30h, Default=00h) ................................................................ 79
8.13.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h)................................. 79
8.13.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h).................................. 79
8.13.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh) .......................................... 79
8.13.5 Consumer IR Special Configuration Register (Index=F0h, Default=06h)............................ 79
9. Functional Description ................................................................................................................................. 83
9.1 LPC Interface .................................................................................................................................... 83
9.1.1 LPC Transactions................................................................................................................. 83
9.1.2 LDRQ# Encoding ................................................................................................................. 83
9.2 Serialized IRQ ................................................................................................................................... 83
9.2.1 Continuous Mode ................................................................................................................. 83
9.2.2 Quiet Mode ........................................................................................................................... 84
9.2.3 Waveform Samples of SERIRQ Sequence.......................................................................... 84
9.2.4 SERIRQ Sampling Slot ........................................................................................................ 85
www.ite.com.tw
iii
IT8783F/E V0.5
IT8783E/F (For A Version)
General Purpose I/O ......................................................................................................................... 86
Advanced Power Supply Control and Power Management Event (PME#) ...................................... 88
SPI Serial Flash Controller................................................................................................................ 89
9.5.1 Overview............................................................................................................................... 89
9.5.2 Features ............................................................................................................................... 89
9.5.3 Register Description ............................................................................................................. 89
9.5.4 Function Descriptions........................................................................................................... 91
9.6 Environment Controller ..................................................................................................................... 93
9.6.1 Interfaces.............................................................................................................................. 93
9.6.2 Registers .............................................................................................................................. 93
9.6.3 Operation............................................................................................................................ 110
9.7 Floppy Disk Controller (FDC).......................................................................................................... 115
9.7.1 Introduction......................................................................................................................... 115
9.7.2 Reset .................................................................................................................................. 115
9.7.3 Hardware Reset (LRESET# Pin)........................................................................................ 115
9.7.4 Software Reset (DOR Reset and DSR Reset)................................................................... 115
9.7.5 Digital Data Separator ........................................................................................................ 115
9.7.6 Write Precompensation ...................................................................................................... 115
9.7.7 Data Rate Selection ........................................................................................................... 116
9.7.8 Status, Data and Control Registers.................................................................................... 116
9.7.9 Controller Phases............................................................................................................... 119
9.7.10 Command Set .................................................................................................................... 122
9.7.11 Data Transfer Command.................................................................................................... 132
9.7.12 Control Command .............................................................................................................. 135
9.7.13 DMA Transfer ..................................................................................................................... 139
9.7.14 Low-Power Mode ............................................................................................................... 139
9.8 Serial Port (UART) .......................................................................................................................... 140
9.8.1 Data Registers.................................................................................................................... 140
9.8.2 Control Register ................................................................................................................. 140
9.8.3 Status Register................................................................................................................... 146
9.8.4 Reset .................................................................................................................................. 148
9.8.5 Programming...................................................................................................................... 148
9.8.6 Software Reset................................................................................................................... 148
9.8.7 Clock Input Operation......................................................................................................... 148
9.8.8 FIFO Interrupt Mode Operation.......................................................................................... 149
9.9 Consumer Remote Control (TV Remote) IR (CIR) ......................................................................... 150
9.9.1 Overview............................................................................................................................. 150
9.9.2 Features ............................................................................................................................. 150
9.9.3 Block Diagram .................................................................................................................... 150
9.9.4 Transmit Operation............................................................................................................. 152
9.9.5 Receive Operation.............................................................................................................. 152
9.9.6 Register Description and Address...................................................................................... 152
9.10 Parallel Port..................................................................................................................................... 161
9.10.1 SPP and EPP Modes ......................................................................................................... 161
9.10.2 EPP Mode Operation ......................................................................................................... 162
9.10.3 ECP Mode Operation ......................................................................................................... 163
9.11 Keyboard Controller (KBC) ............................................................................................................. 170
9.11.1 Host Interface ..................................................................................................................... 170
9.11.2 Data Registers and Status Register................................................................................... 171
9.11.3 Keyboard and Mouse Interface .......................................................................................... 171
9.11.4 KIRQ and MIRQ ................................................................................................................. 171
10. DC Electrical Characteristics ..................................................................................................................... 173
C
O
N
FI
D
EN
TI
AL
9.3
9.4
9.5
www.ite.com.tw
iv
IT8783F/E V0.5
Contents
TI
AL
11. AC Characteristics (VCC = 5V ± 5%, Ta = -40°C to + 100°C) .................................................................. 175
11.1 Clock Input Timings ........................................................................................................................ 175
11.2 LCLK (PCICLK) and LRESET Timings........................................................................................... 175
11.3 LPC and SERIRQ Timings.............................................................................................................. 176
11.4 Modem Control Timings.................................................................................................................. 176
11.5 Floppy Disk Drive Timings .............................................................................................................. 177
11.6 EPP Address or Data Write Cycle Timings..................................................................................... 178
11.7 EPP Address or Data Read Cycle Timings .................................................................................... 179
11.8 ECP Parallel Port Forward Timings ................................................................................................ 180
11.9 ECP Parallel Port Backward Timings ............................................................................................. 181
11.10
RSMRST#, PWROK1/2, and ACPI Power Control Signal Timings ................................... 182
12. Package Information .................................................................................................................................. 183
13. Ordering Information .................................................................................................................................. 185
C
O
N
FI
D
EN
14. Top Marking Information............................................................................................................................ 187
www.ite.com.tw
v
IT8783F/E V0.5
IT8783E/F (For A Version)
FIGURES
Figure 9-1. Start Frame Timing ......................................................................................................................... 84
Figure 9-2. Stop Frame Timing ......................................................................................................................... 84
TI
AL
Figure 9-3. General Logic of GPIO Function .................................................................................................... 87
Figure 9-4. Application Example ..................................................................................................................... 110
Figure 9-5. Temperature Interrupt Response Diagram................................................................................... 114
Figure 9-6. CIR Block Diagram ....................................................................................................................... 150
Figure 9-7. Keyboard and Mouse Interface .................................................................................................... 170
Figure 11-1. Clock Input Timings .................................................................................................................... 175
Figure 11-2. LCLK (PCICLK) and LRESET Timings....................................................................................... 175
Figure 11-3. LPC and SERIRQ Timings ......................................................................................................... 176
Figure 11-4. Modem Control Timings ............................................................................................................. 176
Figure 11-5. Floppy Disk Drive Timings.......................................................................................................... 177
EN
Figure 11-6. EPP Address or Data Write Cycle Timings ................................................................................ 178
Figure 11-7. EPP Address or Data Read Cycle Timings ................................................................................ 179
Figure 11-8. ECP Parallel Port Forward Timings............................................................................................ 180
C
O
N
FI
D
Figure 11-9. ECP Parallel Port Backward Timings ......................................................................................... 181
www.ite.com.tw
vi
IT8783F/E V0.5
Contents
TABLES
Table 4-1. Pins Listed in Numeric Order............................................................................................................. 9
TI
AL
Table 5-1. Pin Description of Supplies Signals ................................................................................................. 11
Table 5-2. Pin Description of LPC Bus Interface Signals ................................................................................. 11
Table 5-3. Pin Description of Infrared Port Signals........................................................................................... 11
Table 5-4. Pin Description of Serial Port 1 Signals ........................................................................................... 12
Table 5-5. Pin Description of Serial Port 2 Signals ........................................................................................... 13
Table 5-6. Pin Description of Serial Port 3 Signals ........................................................................................... 14
Table 5-7. Pin Description of Serial Port 4 Signals ........................................................................................... 15
Table 5-8. Pin Description of Serial Port 5 Signals ........................................................................................... 16
Table 5-9. Pin Description of Serial Port 6 Signals ........................................................................................... 17
Table 5-10. Pin Description of Parallel Port Signals ......................................................................................... 18
Table 5-11. Pin Description of Floppy Disk Controller Signals ......................................................................... 19
EN
Table 5-12. Pin Description of Keyboard Controller Signals............................................................................. 21
Table 5-13. Pin Description of Hardware Monitor Signals ................................................................................ 21
Table 5-14. Pin Description of Fan Controller Signals...................................................................................... 22
Table 5-15. Pin Description of SFI Signals ....................................................................................................... 23
Table 5-16. Pin Description of Miscellaneous Signals...................................................................................... 23
Table 6-1. General Purpose I/O Group 1 (Set 1) .............................................................................................. 27
Table 6-2. General Purpose I/O Group 2 (Set 2) .............................................................................................. 27
FI
D
Table 6-3. General Purpose I/O Group 3 (Set 3) .............................................................................................. 28
Table 6-4. General Purpose I/O Group 4 (Set 4) .............................................................................................. 28
Table 6-5. General Purpose I/O Group 5 (Set 5) .............................................................................................. 29
Table 6-6. General Purpose I/O Group 6 (Set 6) .............................................................................................. 29
Table 7-1. Power On Strapping Options ........................................................................................................... 31
Table 8-1. Global Configuration Registers........................................................................................................ 35
Table 8-2. FDC Configuration Registers........................................................................................................... 36
Table 8-3. Serial Port 1 Configuration Registers .............................................................................................. 36
N
Table 8-4. Serial Port 2 Configuration Registers .............................................................................................. 36
Table 8-5. Parallel Port Configuration Registers............................................................................................... 37
Table 8-6. Environment Controller Configuration Registers ............................................................................. 37
O
Table 8-7. KBC(Keyboard) Configuration Registers......................................................................................... 38
Table 8-8. KBC(Mouse) Configuration Registers ............................................................................................. 38
Table 8-9. GPIO Configuration Registers ......................................................................................................... 38
Table 8-10. Serial Port 3 Configuration Registers ............................................................................................ 40
C
Table 8-11. Serial Port 4 Configuration Registers ............................................................................................ 42
Table 8-12. Serial Port 5 Configuration Registers ............................................................................................ 42
Table 8-13. Serial Port 6 Configuration Registers ............................................................................................ 42
www.ite.com.tw
vii
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 8-14. Consumer IR Configuration Registers........................................................................................... 43
Table 8-15. Base Address of Logical Devices .................................................................................................. 43
Table 8-16 Interrupt Level Mapping Table ........................................................................................................ 79
TI
AL
Table 8-17 DMA Channel Mapping Table......................................................................................................... 79
Table 8-18 Location Mapping Table ................................................................................................................. 80
Table 9-1. Memory Stick Register List .............................................................................................................. 89
Table 9-2. Address Map on LPC Bus ............................................................................................................... 93
Table 9-3. Environment Controller Registers.................................................................................................... 94
Table 9-4. Status Register 0 (ST0) ................................................................................................................. 120
Table 9-5. Status Register 1 (ST1) ................................................................................................................. 121
Table 9-6. Status Register 2 (ST2) ................................................................................................................. 121
Table 9-7. Status Register 3 (ST3) ................................................................................................................. 122
Table 9-8. Command Set Symbol ................................................................................................................... 122
EN
Table 9-9. Command Set Summary................................................................................................................ 125
Table 9-10. Effects of MT and N Bit ................................................................................................................ 133
Table 9-11. SCAN Command Result .............................................................................................................. 134
Table 9-12. VERIFY Command Result ........................................................................................................... 135
Table 9-13. Interrupt Identification .................................................................................................................. 137
Table 9-14. HUT Value ................................................................................................................................... 138
Table 9-15. SRT Value.................................................................................................................................... 138
FI
D
Table 9-16. HLT Value .................................................................................................................................... 138
Table 9-17. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands ....................... 139
Table 9-18. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands .. 139
Table 9-19. Serial Channel Registers ............................................................................................................. 140
Table 9-20. Interrupt Identification Register.................................................................................................... 142
Table 9-21. Receiver FIFO Trigger Level Encoding ....................................................................................... 143
Table 9-22. Baud Rate Using (24 MHz ÷ 13) Clock........................................................................................ 144
Table 9-23. Stop Bit Number Encoding .......................................................................................................... 145
N
Table 9-24. Reset Control of Register and Pinout Signal ............................................................................... 148
Table 9-25. List of CIR Registers .................................................................................................................... 152
Table 9-26. Modulation Carrier Frequency ..................................................................................................... 157
Table 9-27. Receiver Demodulation Low Frequency (HCFS = 0) .................................................................. 158
O
Table 9-28. Receiver Demodulation High Frequency (HCFS = 1) ................................................................. 159
Table 9-29. Parallel Port Connector in Different Modes ................................................................................. 161
Table 9-30. Address Map and Bit Map for SPP and EPP Modes................................................................... 161
Table 9-31. Bit Map of ECP Register .............................................................................................................. 164
C
Table 9-32. ECP Register Definitions ............................................................................................................. 164
Table 9-33. ECP Mode Description................................................................................................................. 165
Table 9-34. ECP Pin Description .................................................................................................................... 165
www.ite.com.tw
viii
IT8783F/E V0.5
Contents
Table 9-35. Mode and Description of Extended Control Register (ECR) ....................................................... 167
Table 9-36. Data Register READ/WRITE Controls......................................................................................... 170
C
O
N
FI
D
EN
TI
AL
Table 9-37. Status Register ............................................................................................................................ 171
www.ite.com.tw
ix
IT8783F/E V0.5
N
O
C
TI
AL
EN
FI
D
Features
Features
„ Low Pin Count Interface
− Complies with Intel Low Pin Count Interface
Specification Rev. 1.1
− Supports LDRQ#, SERIRQ protocols
− Supports PCI PME# Interfaces
−
−
−
„
Keyboard Controller
8042 compatible for PS/2 keyboard and mouse
− Hardware KBC
− GateA20 and Keyboard reset output
− Supports multiple keyboard power-on events
(Any keys, 2-5 sequential keys, 1-3
simultaneous keys)
− Supports mouse double-click and/or mouse
move power on events
−
„ ACPI & LANDesk Compliant
− ACPI V. 2.0 compliant
− Register sets compatible with “Plug and Play
ISA Specification V. 1.0a”
− LANDesk 3.X compliant
− Supports 12 logical devices
„ Enhanced Hardware Monitor
− Built-in 8-bit Analog to Digital Converter
− 3 thermal inputs from either remote thermal
resistor or thermal diode or diode-connected
transistor, the temperature sensor of the
current mode
− 8 voltage monitor inputs (VBAT measured
internally)
− 1 chassis open detection input with low power
Flip-Flop dual-powered by battery or VCCH
− Watch Dog comparison of all monitored values
− SST/PECI I/F support
− H/W Smart fan control
„
Enhanced digital data separator
3-Mode drives supported
Supports automatic write protection via
software
TI
AL
1.
40 General Purpose I/O Pins
Input mode supports either switch de-bounce
or programmable external IRQ input routing
− Output mode supports 2 sets of programmable
LED blinking periods
− 8 GPIO Pins in the same group
EN
−
„
FI
D
„
„ Fan Speed Controller
− Provides fan on-off and PWM control
− Supports 3 programmable Pulse Width
Modulation (PWM) outputs
− 128 steps of PWM modes
− Monitors 3 fan tachometer inputs
N
„ Six 16C550 UARTs
− Supports six standard Serial Ports
− Supports IrDA 1.0/ASKIR protocols
− Supports CIR
C
O
„ IEEE 1284 Parallel Port
− Standard mode: Bi-directional SPP compliant
− Enhanced mode: EPP V. 1.7 and V. 1.9
compliant
− High-speed mode: ECP, IEEE 1284 compliant
− Back-drive current reduction
− Printer power-on damage reduction
− Supports POST (Power-On Self Test) Data
Port
„
Serial Flash I/F for BIOS
Supports 8 M-bit of SPI I/F
− Supports H/W lock
−
Watch Dog Timer
Time resolution 1 minute or 1 second,
maximum 65535 minutes or 65535 seconds
− Output to KRST# and PWROK when expired
−
„
ITE’s Innovative Automatic Power-failure
Resume and Power Button De-bounce
„
VCCH and Vbat Supported
„
Single 24/48 MHz Clock Input
„
Built-in 32.768 kHz Oscillator
„
+5V/3.3V Power Supply
„
Supports RS485 Automatic Direction
Control
„
Supports Wide Operation Temperature
Range: -40 ℃-100℃
„
128-pin QFP / 128-pin LQFP
Floppy Disk Controller
− Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M
floppy disk drives
www.ite.com.tw
Specfications subject to Change without Notice
1
IT8783F/E V0.5
ITPM-PN-2010083
6/25/2010
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
2
IT8783F/E V0.5
General Description
2.
General Description
TI
AL
The IT8783E/F is a highly integrated Super I/O using the Low Pin Count Interface. It provides the most
commonly used legacy Super I/O functionality plus the latest Environment Control initiatives, including H/W
Monitor and Fan Speed Controller. The device’s LPC interface complies with Intel “LPC Interface
Specification Rev. 1.1”. The IT8783E/F is ACPI & LANDesk compliant.
The IT8783E/F features an enhanced hardware monitor providing three thermal inputs from remote thermal
resistors, or thermal diode or diode-connected transistor (2N3904).
The IT8783E/F contains one Fan Speed Controller, which can control up to three fan speeds through three
separate 128 steps of Pulse Width Modulation (PWM) output pins and monitor up to three FANs’
Tachometer inputs. It also features six 16C550 UARTs, one IEEE 1284 Parallel Port, one Floppy Disk
Controller and one Keyboard Controller.
EN
Integrated in the IT8783E/F are 12 logical devices, which can be individually enabled or disabled via
software configuration registers, one high-performance 2.88MB floppy disk controller, with digital data
separator, supporting two drives in 360K/ 720K/ 1.2M/ 1.44M/ 2.88M format, one multi-mode highperformance parallel port supporting the bi-directional Standard Parallel Port (SPP), Enhanced Parallel Port
(EPP V. 1.7 and EPP V. 1.9), and IEEE 1284 compliant Extended Capabilities Port (ECP), six 16C550
standard compatible enhanced UARTs performing asynchronous communication, and supporting an IR
interface. The device also features one fan speed controller controlling and monitoring three fans, six GPIO
ports controlling up to 40 GPIO pins, and one integrated Keyboard Controller.
C
O
N
FI
D
The IT8783E/F utilizes power-saving circuitry to reduce power consumption, and once a logical device is
disabled, the inputs are inhibited with the clock disabled and the outputs are tri-stated. The device requires a
single 24/48 MHz clock input and operates with +5V/3.3V power supply. The IT8783E/F is available in 128pin LQFP / 128-pin QFP.
www.ite.com.tw
3
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
4
IT8783F/E V0.5
Block Diagram
24 / 48 MHz
OSC.
Serial Port I/F
IR I/F
Clock
Gen.
PME#
Keyboard
Controlle
r
16C550
UART 1
16C550
UART 3/5
IrDA 1.0
/ASKIR
CIR
CIR I/F
Serial Port I/F
TI
AL
Block Diagram
EN
3.
16C550
UART 2
Floppy
Drive I/F
Floppy
Disk
Controlle
r
General
Purpose
I/O
Serial
Flash I/F
Fan
Speed
Controller
FI
D
Parallel Port
SMBG I/F
N
8-bit
ADC
Serial Port I/F
Serial Port I/F
Fan
Tachometers
I/O Ports
Serial
Flash I/F
Fan I/F
Thermal
Sensor
Thermal
Resistor
Thermal
Diode
C
O
Monitored
Voltages
Keyboard I/F
WDT1,2,3
16C550
UART 4/6
IEEE1284
Paralle
l
Port
Mouse I/F
www.ite.com.tw
5
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
6
IT8783F/E V0.5
Pin Description
4.
Pin Configuration
C
O
N
FI
D
EN
TI
AL
IT8783E Top View
www.ite.com.tw
IT8783F Top View
7
IT8783F/E V0.5
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
CTS2#
RI2#
DCD2#
SIN1
SOUT1/JP3
DSR1#
RTS1#/JP2
DTR1#/JP1
CTS1#
RI1#
DCD1#
GNDD
PD7/GP67
PD6/GP66
PD5/GP65
PD4/GP64
PD3/GP63
PD2/GP62
PD1/GP61
PD0/GP60
STB#/SMBC_M
AFD#/SMBC_R/DCD6#
ERR#/RTS6#
INIT#/SMBD_M/SOUT6
SLIN#/SMBD_R/SIN6
ACK#/DTR6#
TI
AL
IT8783E/F (For A Version)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
BUSY/DSR6#
PE/CTS6#
SLCT/RI6#
AVCC
VIN0
VIN1
VIN2
VIN3/ATXPG/DSR6#
VIN4/DCD6#
VIN5/FAN_TAC3/SIN6/GP30
VIN6/CTS6#/GP31
VIN7/SO/GP32
VREF
TMPIN1
TMPIN2
TMPIN3/RI6#
GNDA
RSMRST#/RTS6#/GP34/CIRRX1
DCD5#/GP20
MCLK/GP10
MDAT/GP11
KCLK/GP12
KDAT/GP13
3VSBSW#/GP40
PWROK1/GP41
SUSC#/SOUT6/GP35
PSON#/GP42
PANSWH#/GP43
GNDD
PME#/GP45
PWRON#/GP46
SUSB#/GP47
RI5#/GP21
VBAT
COPEN#
VCCH
SOUT5/GP22
DSKCHG#/IRRX
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
KRST#/GP36
GA20
PCICLK
SIN5/GP23
CLKIN
GNDD
DENSEL#/PWROK2
MTRA#/GP50
SST/MTRB#/PCIRST1#/PECIRQT
DRVA#/GP51
PECI/DRVB#
WDATA#/GP52
DIR#/GP53
STEP#/GP54
HDSEL#/GP55
WGATE#/GP56
RDATA#/GP57
TRK0#/CIRTX
INDEX#/CIRRX
WPT#/IRTX
N
O
C
www.ite.com.tw
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
EN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
FI
D
DTR2#/JP4
RTS2/JP5
DSR2#
VCC
SOUT2/JP6
SIN2
FAN_TAC1
FAN_CTL1
FAN_TAC2/GP37
FAN_CTL2/GP33
DCD3#
RI3#
CTS3#
DTR3#/JP7
GNDD
RTS3#/JP9
DSR3#
SOUT3/JP8
SIN3
DCD4#
RI4#
CTS4#
DTR4#
SI/GP17/PCIRST3#
SCK/GP16/PCIRST2#
RTS4#
DSR4#
SOUT4
DTR6#/GP15
CE_N/FAN_CTL3/GP14
SIN4
RESETCON#/CTS5#/GP27
DTR5#/GP26
RTS5#/GP25
VCC
DSR5#/GP24
LRESET#
LDRQ#
8
IT8783F/E V0.5
Pin Description
Table 4-1. Pins Listed in Numeric Order
Signal
DTR5#/GP26
RTS5#/GP25
VCC
DSR5#/GP24
LRESET#
LDREQ#
SERIRQ
Pin
65
66
67
68
69
70
71
Signal
DSKCHG#/IRRX
SOUT5//GP22
VCCH
COPEN#
VBAT
RI5#/I/GP21
SUSB#/GP47
Pin
97
98
99
100
101
102
103
PWRON#/GP46
104
PME#/GP45
105
GNDD
106
PANSWH#/GP43
107
PSON#/GP42
SUSC#/SOUT6#/
GP35
PWROK1/GP41
3VSBSW#/GP40
KDAT/GP13
KCLK/GP12
MDAT/GP11
108
Signal
VIN1
VIN0
AVCC
SLCT/RI6#
PE/CTS6#
BUSY/DSR6#
ACK#/DTR6#
SLIN#/SMBD_R/S
IN6
INIT#/SMBD_M/S
OUNT6
ERR#/RTS6#
AFD#/SMBC_R/D
CD6#
STB#/SMBC_M
8
FAN_CTL1
40
LFRAME#
72
9
FAN_TAC2/GP37
41
LAD0
73
10
FAN_CTL2/GP33
42
LAD1
74
11
DCD3#
43
LAD2
75
12
RI3#
44
LAD3
76
13
CTS3#/
45
KRST#/GP36
77
109
PD0/GP60
14
15
16
17
18
DTR3#/JP7
GNDD
RTS3#/JP9
DSR3#/
SOUT3/JP8
46
47
48
49
50
78
79
80
81
82
19
SIN3/
51
20
DCD4#/
52
21
RI4#/
53
22
23
54
55
56
26
27
CTS4#/
DTR4#/
SI/GP17/PCIRST
3#
SCK/GP16/PCIRS
T2#
RTS4#
DSR4#/
GA20
PCICLK
SIN5#/GP23
CLKIN
GNDD
DENSEL#/PWRO
K2
MTRA#/GP50
SST/MTRB#/PCI
RST1#/PECIRQT
DRVA#/GP51
PECI/DRVB#
110
111
112
113
114
PD1/GP61
PD2/GP62
PD3/GP63
PD4/GP64
PD5/GP65
83
MCLK/GP10
115
PD6/GP66
84
116
PD7/GP67
117
GNDD
86
87
DCD5#/GP20
RSMRST#/RTS6#
/GP34/CIRRX1
GNDA
TMPIN3/RI6#
118
119
DCD1#
RI1#
WDATA#/GP52
88
TMPIN2
120
CTS1#
57
DIR#/GP53
89
TMPIN1
121
DTR1#/JP1
58
59
STEP#/GP54
HDSEL#/GP55
90
91
122
123
RTS1#/JP2
DSR1#
SOUT4/
60
WGATE#/GP56
92
124
SOUT1/JP3
29
DTR6#/GP15
61
RDATA#/GP57
93
VREF
VIN7/SO#/GP32
VIN6/CTS6#/GP3
1
VIN5/FAN_TAC3/
SIN6/GP30
28
125
SIN1
30
CE_N/FAN_CTL3/
GP14
62
TRK0#/CIRTX
94
VIN4//DCD6#
126
DCD2#
31
SIN4
63
INDEX#/CIRRX
95
VIN3/ATXPG/DS
R6#
127
RI2#
RESETCON#/CT
S5#/GP27
64
WPT#/IRTX
96
VIN2
128
CTS2#
24
O
N
25
85
C
32
TI
AL
Pin
33
34
35
36
37
38
39
EN
Signal
DTR2#/JP4
RTS2/JP5
DSR2#
VCC
SOUT2/JP6
SIN2
FAN_TAC1
FI
D
Pin
1
2
3
4
5
6
7
www.ite.com.tw
9
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 4-2. Pins Listed in Alphabetical Order
Signal
3VSBSW#/GP40
103
ACK#/DTR6#
Pin
106
Signal
ERR#/RTS6#
Pin
112
8
FAN_CTL1
113
10
FAN_CTL2/GP33
114
7
9
FAN_TAC1
FAN_TAC2/GP37
115
116
46
GA20
101
86
GNDA
55
Signal
PD3/GP63
Pin
100
Signal
SLCT/RI6#
SLIN#/SMBD_R/S
IN6
PD4/GP64
104
PD5/GP65
124
SOUT1/JP3
PD6/GP66
PD7/GP67
5
18
SOUT2/JP6
SOUT3/JP8
PE/CTS6#
28
SOUT4/
PECI/DRVB#
66
PME#/GP45
53
PSON#/GP42
PWROK1/GP41
PWRON#/GP46
108
58
71
SOUT5//GP22
SST/MTRB#/PCI
RST1#/PECIRQT
STB#/SMBC_M
STEP#/GP54
SUSB#/GP47
SUSC#/SOUT6#/
GP35
TI
AL
Pin
79
68
COPEN#
15
GNDD
73
120
128
13
CTS1#
CTS2#
CTS3#/
50
74
117
GNDD
GNDD
GNDD
76
78
72
22
CTS4#/
59
HDSEL#/GP55
61
RDATA#/GP57
77
118
DCD1#
63
INDEX#/CIRRX
32
RESETCON#/CT
S5#/GP27
89
TMPIN1
126
DCD2#
105
119
RI1#
88
TMPIN2
11
20
84
DCD3#
DCD4#/
DCD5#/GP20
DENSEL#/PWRO
K2
81
80
45
INIT#/SMBD_M/S
OUNT6
KCLK/GP12
KDAT/GP13
KRST#/GP36
127
12
21
RI2#
RI3#
RI4#/
87
62
69
TMPIN3/RI6#
TRK0#/CIRTX
VBAT
41
LAD0
70
RI5#/I/GP21
4
VCC
57
DIR#/GP53
42
LAD1
85
35
VCC
54
65
123
3
DRVA#/GP51
DSKCHG#/IRRX
DSR1#
DSR2#
43
44
38
40
LAD2
LAD3
LDREQ#
LFRAME#
122
2
16
26
RSMRST#/RTS6#
/GP34/CIRRX1
RTS1#/JP2
RTS2/JP5
RTS3#/JP9
RTS4#
67
98
97
96
17
DSR3#/
37
LRESET#
34
RTS5#/GP25
95
VCCH
VIN0
VIN1
VIN2
VIN3/ATXPG/DS
R6#
27
DSR4#/
83
MCLK/GP10
25
SCK/GP16/PCIRS
T2#
94
SERIRQ
93
30
N
51
FI
D
99
102
EN
49
AFD#/SMBC_R/D
CD6#
AVCC
BUSY/DSR6#
CE_N/FAN_CTL3/
GP14
CLKIN
107
DSR5#/GP24
82
MDAT/GP11
39
121
DTR1#/JP1
52
MTRA#/GP50
24
1
14
23
33
29
DTR2#/JP4
DTR3#/JP7
DTR4#/
DTR5#/GP26
DTR6#/GP15
75
47
109
110
111
PANSWH#/GP43
PCICLK
PD0/GP60
PD1/GP61
PD2/GP62
125
6
19
31
48
SI/GP17/PCIRST
3#
SIN1
SIN2
SIN3/
SIN4
SIN5#/GP23
92
91
90
56
60
64
VIN5/FAN_TAC3/
SIN6/GP30
VIN6/CTS6#/GP3
1
VIN7/SO#/GP32
VREF
WDATA#/GP52
WGATE#/GP56
WPT#/IRTX
C
O
36
VIN4//DCD6#
www.ite.com.tw
10
IT8783F/E V0.5
Pin Description
5.
Pin Description
Table 5-1. Pin Description of Supplies Signals
Symbol
VCC
AVCC
VCCH
VBAT
GNDD
Attribute
PWR
PWR
PWR
PWR
GND
Power
-
GNDA(D-)
GND
-
Pin(s) No.
37
Symbol
LRESET#
Attribute
DI
Power
VCC
38
LDRQ#
DO16
VCC
39
40
SERIRQ
LFRAME#
DIO16
DI
41-44
LAD[0:3]
DIO16
47
PCICLK
DI
73
PME#/
GP45
DOD8/
DIOD8
Description
+5V Power Supply
+5V Analog Power Supply
+5V VCC Help Supply
+3.3V Battery Supply
Digital Ground
TI
AL
Pin(s) No.
4, 35
99
67
69
15, 50,
74, 117
86
Analog Ground (D-)
Table 5-2. Pin Description of LPC Bus Interface Signals
EN
Description
LPC RESET #
EC block will not be reset by LRESET#, which is controlled by
VCC PWRGD.
LPC DMA Request #
An encoded signal for DMA channel select.
Serial IRQ
LPC Frame #
This signal indicates the start of the LPC cycle.
LPC Address / Data 0-3
4-bit LPC address/bi-directional data lines. LAD0 is the LSB
and LAD3 is the MSB.
PCI Clock
33 MHz PCI clock input for LPC I/F and SERIRQ.
Power Management Event # / General Purpose I/O 45
• The first function of this pin is the power management
event #. It supports the PCI PME# interface. This signal
allows the peripheral to request the system to wake up
from the D3 (cold) state.
• The second function of this pin is General Purpose I/O Port
4 Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
VCC
VCC
VCC
VCC
FI
D
VCCH
Table 5-3. Pin Description of Infrared Port Signals
Symbol
DSKCHG#/
IRRX
O
N
Pin(s) No.
65
WPT#/
IRTX
Power
VCC
DI/
DO8
VCC
Description
DSKCHG# / Infrared Receive Input
• The first function of this pin is FDD disk change input.
• The second function of this pin is Infrared Receive Input.
The function configuration of this pin is determined by
programming the software configuration registers.
WPT#/ Infrared Transmit Output
• The first function of this pin is FDC write protect input.
• The second function of this pin is Infrared Transmit Output.
The function configuration of this pin is determined by
programming the software configuration registers.
C
64
Attribute
DI/
DI
www.ite.com.tw
11
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 5-4. Pin Description of Serial Port 1 Signals
Attribute
DI
Power
VCC
124
SOUT1/
JP3
DO8/
DI
VCC
123
DSR1#
DI
VCC
122
RTS1#/
JP2
DO8/
DI
VCC
121
DTR1#/
JP1
DO8/
DI
CTS1#
DI
VCC
RI1#
DI
VCC
DI
VCC
N
119
VCC
FI
D
120
Description
Serial Data Input 1
This input receives serial data from the communications link.
Serial Data Output 1 / JP3
This output sends serial data to the communications link. This
signal is set to a marking state (logic 1) after a Master Reset
operation or when the device is in one of the Infrared
communications modes.
During LRESET#, this pin is input for JP3 power-on strapping
option.
Data Set Ready 1 #
When the signal is low, it indicates that the MODEM or data
set is ready to establish a communications link. The DSR#
signal is a MODEM status input whose condition can be
tested by reading the MSR register.
Request to Send 1 # / JP2
When this signal is low, this output indicates to the MODEM
or data set that the device is ready to send data. RTS# is
activated by setting the appropriate bit in the MCR register to
1. After a Master Reset operation or during the Loop mode,
RTS# is set to its inactive state.
The second function of this pin is H/W strapping JP2( at
internal VCC OK).
Data Terminal Ready 1 # / JP1
DTR# is used to indicate to the MODEM or data set that the
device is ready to exchange data. DTR# is activated by
setting the appropriate bit in the MCR register to 1. After a
Master Reset operation or during Loop mode, DTR# is set to
its inactive state.
During LRESET#, this pin is input for JP1 power-on strapping
option.
Clear to Send 1 #
When the signal is low, it indicates that the MODEM or data
set is ready to accept data. The CTS# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.
Ring Indicator 1 #
When the signal is low, it indicates that a telephone ring
signal has been received by the MODEM. The RI# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.
Data Carrier Detect 1 #
When the signal is low, it indicates that the MODEM or data
set has detected a carrier. The DCD# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.
TI
AL
Symbol
SIN1
EN
Pin(s) No.
125
DCD1#
C
O
118
www.ite.com.tw
12
IT8783F/E V0.5
Pin Description
Table 5-5. Pin Description of Serial Port 2 Signals
Attribute
DI
Power
VCC
5
SOUT2/
JP6
DO8/
DI
VCC
3
DSR2#
DI
VCC
2
RTS2#/
JP5
DO8/
DI
VCC
1
DTR2#/
JP4
DO8/
DI
CTS2#
DI
VCC
RI2#
DI
VCC
DI
VCC
N
127
VCC
FI
D
128
Description
Serial Data Input 2
This input receives serial data from the communications link.
Serial Data Output 2 / JP6
This output sends serial data to the communications link. This
signal is set to a marking state (logic 1) after a Master Reset
operation or when the device is in one of the Infrared
communications modes.
The second function of this pin is H/W strapping JP6( at
internal VCC OK).
Data Set Ready 2 #
When the signal is low, it indicates that the MODEM or data
set is ready to establish a communications link. The DSR#
signal is a MODEM status input whose condition can be
tested by reading the MSR register.
Request to Send 2 # / JP5
When this signal is low, this output indicates to the MODEM
or data set that the device is ready to send data. RTS# is
activated by setting the appropriate bit in the MCR register to
1. After a Master Reset operation or during Loop mode, RTS#
is set to its inactive state.
The second function of this pin is H/W strapping JP5( at
internal VCC OK).
Data Terminal Ready 2 # / JP4
DTR# indicates to the MODEM or data set that the device is
ready to exchange data and is activated by setting the
appropriate bit in the MCR register to 1. After a Master Reset
operation or during Loop mode, DTR# is set to its inactive
state.
The second function of this pin is H/W strapping JP4( at
internal VCC OK).
Clear to Send 2 #
When the signal is low, it indicates that the MODEM or data
set is ready to accept data. The CTS# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.
Ring Indicator 2 #
When the signal is low, it indicates that a telephone ring
signal has been received by the MODEM. The RI# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.
Data Carrier Detect 2 #
When the signal is low, it indicates that the MODEM or data
set has detected a carrier. The DCD# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.
TI
AL
Symbol
SIN2
EN
Pin(s) No.
6
DCD2#
C
O
126
www.ite.com.tw
13
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 5-6. Pin Description of Serial Port 3 Signals
Symbol
SIN3
Attribute
DI
Power
VCC
18
SOUT3/
JP8
DO8/
DI
VCC
Description
Serial Data Input 3
The function of this pin is to input the serial data received
from the communications link.
Serial Data Output 3/JP8
• The first function of this pin is to output the sent serial
TI
AL
Pin(s) No.
19
data to the communications link. This signal is set to
a marking state (logic 1) after a Master Reset
operation or when the device is in one of the Infrared
communications modes.
• The second function of this pin is H/W strapping JP8( at
internal VCC OK).
DSR3#
DI
16
RTS3#/
JP9
DO8/
DI
VCC
Data Set Ready 3 #
The function of this pin is Data Set Ready 3#. When the
signal is low, it indicates that the MODEM or data set is ready
to establish a communications link. The DSR# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.
Request to Send 3 #/JP9
• The first function of this pin is Request to Send 3#.
EN
17
VCC
DO8/
DI
VCC
DI
VCC
RI3#
DI
VCC
DCD3#
DI
VCC
DTR3#/
JP7
N
14
FI
D
When this signal is low, the output indicates to the
MODEM or data set that the device is ready to send
data. RTS# is activated by setting the appropriate bit
in the MCR register to 1. After a Master Reset
operation or during Loop mode, RTS# is set to its
inactive state.
• The second function of this pin is H/W strapping JP9( at
internal VCC OK).
CTS3#
O
13
C
12
11
www.ite.com.tw
Data Terminal Ready 3 # / JP7
• The first function of this pin is Data Terminal Ready 3#,
which indicates to the MODEM or data set that the device
is ready to exchange data. DTR# is activated by setting the
appropriate bit in the MCR register to 1. After a Master
Reset operation or during Loop mode, DTR# is set to its
inactive state.
• The second function of this pin is H/W strapping JP7
The function configuration of this pin is determined by
programming the software configuration registers.
Clear to Send 3 #
The function of this pin is Clear to Send 3 #. When the signal
is low, it indicates that the MODEM or data set is ready to
accept data. The CTS# signal is a MODEM status input
whose condition can be tested by reading the MSR register.
Ring Indicator 3 #
The function of this pin is Ring Indicator 3 #. When the signal
is low, it indicates that a telephone ring signal has been
received by the MODEM. The RI# signal is a MODEM status
input whose condition can be tested by reading the MSR
register.
Data Carrier Detect 3 #
The function of this pin is Data Carrier Detect 3 #. When the
signal is low, it indicates that the MODEM or data set has
detected a carrier. The DCD# signal is a MODEM status input
whose condition can be tested by reading the MSR register.
14
IT8783F/E V0.5
Pin Description
Table 5-7. Pin Description of Serial Port 4 Signals
Attribute
DI
Power
VCC
28
SOUT4
DO8
VCC
27
DSR4#
DI
VCC
26
RTS4#
DO8
VCC
23
DTR4#
DO8/
CTS4#
DI
VCC
RI4#
DI
VCC
DI
VCC
N
21
VCC
FI
D
22
Description
Serial Data Input 4
The function of this pin is to input the serial data received
from the communications link.
Serial Data Output 4
The function of this pin is to output the sent serial data to the
communications link. This signal is set to a marking state
(logic 1) after a Master Reset operation or when the device is
in one of the Infrared communications modes.
Data Set Ready 4 #
The function of this pin is Data Set Ready 4#. When the
signal is low, it indicates that the MODEM or data set is ready
to establish a communications link. The DSR# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.
Request to Send 4 #
The function of this pin is Request to Send 4#. When this
signal is low, this output indicates to the MODEM or data set
that the device is ready to send data. RTS# is activated by
setting the appropriate bit in the MCR register to 1. After a
Master Reset operation or during Loop mode, RTS# is set to
its inactive state.
Data Terminal Ready 4 #
The function of this pin is Data Terminal Ready 4#, which
indicates to the MODEM or data set that the device is ready
to exchange data. DTR# is activated by setting the
appropriate bit in the MCR register to 1. After a Master Reset
operation or during Loop mode, DTR# is set to its inactive
state.
Clear to Send 4 #
The function of this pin is Clear to Send 4 #. When the signal
is low, it indicates that the MODEM or data set is ready to
accept data. The CTS# signal is a MODEM status input
whose condition can be tested by reading the MSR register.
Ring Indicator 4 #
The function of this pin is Ring Indicator 4 #. When the signal
is low, it indicates that a telephone ring signal has been
received by the MODEM. The RI# signal is a MODEM status
input whose condition can be tested by reading the MSR
register.
Data Carrier Detect 4 #
The function of this pin is Data Carrier Detect 4 #. When the
signal is low, it indicates that the MODEM or data set has
detected a carrier. The DCD# signal is a MODEM status input
whose condition can be tested by reading the MSR register.
TI
AL
Symbol
SIN4
EN
Pin(s) No.
31
DCD4#
C
O
20
www.ite.com.tw
15
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 5-8. Pin Description of Serial Port 5 Signals
Attribute
DI/
DIOD8
Power
VCC
66
SOUT5 /
GP22
DO8/
DIOD8
VCC
36
DSR5#/
GP24
DI/
DIOD8
VCC
34
RESETCON#/
CTS5#/
GP27
N
32
DTR5#/
GP26
RI5#/
GP21
O
70
DCD5#/
GP20
C
84
DOD8/
DIOD8
DOD8/
DIOD8
VCC
VCC
FI
D
33
RTS5#/
GP25
Description
Serial Data Input 5 / General Purpose I/O 23
• The first function of this pin is Serial Data Input 5.
• The second function of this pin is General Purpose I/O Port
2 Bit 3
The function configuration of this pin is determined by
programming the software configuration registers.
SOUT5 / General Purpose I/O 22
• The first function of this pin is Serial Data Transmit output.
• The second function of this pin is General Purpose I/O Port
2 Bit 2.
The function configuration of this pin is determined by
programming the software configuration registers.
Data Set Ready 5# / General Purpose I/O 24
• The first function of this pin is Data Set Ready 5 #.
• The second function of this pin is General Purpose I/O Port
2 Bit 4.
The function configuration of this pin is determined by
programming the software configuration registers.
Request to Send 5# / General Purpose I/O 25
• The first function of this pin is Request to Send 5#.
• The second function of this pin is General Purpose I/O Port
2 Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
Data Terminal Ready 5# / General Purpose I/O 26
• The first function of this pin is Data Terminal Ready 5#.
• The second function of this pin is General Purpose I/O Port
2 Bit 6.
The function configuration of this pin is determined by
programming the software configuration registers.
RESETCONNECT / Clear to Send 5#/ General Purpose I/O
27
• The first function of this pin is RESET# Connect Input.
• The second function of this pin is Clear to Send 5#.
• The third function of this pin is General Purpose I/O Port 2
Bit 7.
The function configuration of this pin is determined by
programming the software configuration registers.
Ring Input 5 # / General Purpose I/O 21
• The first function of this pin is Ring Indicator 5#.
• The second function of this pin is General Purpose I/O Port
2 Bit 1.
The function configuration of this pin is determined by
programming the software configuration registers.
Data Carrier Detect 5# / General Purpose I/O 20
• The first function of this pin is Data Carrier Detect 5#.
• The second function of this pin is General Purpose I/O Port
2 Bit 0.
The function configuration of this pin is determined by
programming the software configuration registers.
TI
AL
Symbol
SIN5/
GP23
EN
Pin(s) No.
48
www.ite.com.tw
DI/
DI/
DIOD8
VCC
DI8/
DIOD8
VCC
DI/
DIOD8
VCC
16
IT8783F/E V0.5
Pin Description
Table 5-9. Pin Description of Serial Port 6 Signals
Attribute
AI/
DI/
DI/
DI
Power
VCC
92
VIN6/
CTS6#/
GP31
DO/
DI/
DI
VCC
85
RTS6#/
RSMRST#/
GP34/
CIRRX1
DO/
DOD8/
DIOD8/
DI
VCC
VCCH
VCC
VCCH
VIN3/
ATXPG/
DSR6#
AI/
DI/
DI
VCC
DTR6#/
GP15
DO8/
DIOD8
VCC
DI/
DO/
DOD8
VCCH
VCC
VCC
TMPIN3/
RI6#
AI/
DI8
VCC
VIN4/
DCD6#
AI/
DI
VCC
N
29
FI
D
95
SUSC#/
SOUT6/
GP35
O
77
C
87
Description
VIN5/FAN Tachometer input 3/Serial Data Input 6/ General
Purpose I/O 30
• The first function of this pin is Analog Voltage CH5 Input.
• The second function of this pin is FAN Tachometer Input 3.
• The third function of this pin is Serial Data Input 6.
• The fourth function of this pin is General Purpose I Port 3
Bit 0 (input mode only).
The function configuration of this pin is determined by
programming the software configuration registers.
VIN6/CTS6#/General Purpose I/O 31
• The first function of this pin Analog Voltage CH6 Input
• The second function of this pin is CTS6# Input.
• The third function of this pin is General Purpose I Port 3 Bit
1(input mode only).
The function configuration of this pin is determined by
programming the software configuration registers.
Request to Send 6/ Resume Reset # / General Purpose
I/O 34 / CIR Receiver input 1
• The first function of this pin is Request to Send 6.
• The second function of this pin is Resume Reset #. It is
power good signal of VCCH. The high threshold is 4V ±
0.2V, and the low threshold is 3.5V ± 0.2V.
• The third function of this pin is General Purpose I/O Port 3
Bit 4.
• The fourth function of this pin is CIR Receiver input 1
The function configuration of this pin is determined by
programming the software configuration registers.
VIN3/ATX Power Good/Data Set Ready 6#
• The first function of this pin is ADC Voltage Input of CH3.
• The second function of this pin is ATX Power Good Input.
• The third function of this pin is Data Set Ready 6 #.
The function configuration of this pin is determined by
programming the software configuration registers.
Data Terminal Ready 6#/General Purpose I/O 15
• The first function of this pin is Data Terminal Ready 6#.
• The third function of this pin is General Purpose I/O Port 1
Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
SUSC#/SOUT6/Purpose I/O 35
• The first function of this pin is SUSC# Input
• The second function of this pin is Serial Output Data 6.
• The third function of this pin is General Purpose I/O Port 3
Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
TMPIN3/Ring Indicator 6#
• The first function of this pin is Thermal input 3.
• The second function of this pin is Ring Indicator 6#.
The function configuration of this pin is determined by
programming the software configuration registers.
VIN4/Data Carrier Detect 6#
• The first function of this pin is ADC CH4 Input.
• The second function of this pin is Data Carrier Detect 6#.
The function configuration of this pin is determined by
TI
AL
Symbol
VIN5/
FAN_TAC3/
SIN6/
GP30
EN
Pin(s) No.
93
94
www.ite.com.tw
17
IT8783F/E V0.5
IT8783E/F (For A Version)
Pin(s) No.
Symbol
Attribute
Power
Description
programming the software configuration registers.
Table 5-10. Pin Description of Parallel Port Signals
Symbol
SLCT/
RI6#
Attribute
DI/
DI
Power
VCC
Description
Printer Select/Ring Indicator 6#
• The signal of the first function goes high when the line
printer has been selected.
• The second function of this pin is Ring Indicator 6#.
101
PE/
CTS6#
DI/
DI
VCC
Printer Paper End/Clear to Send 6#
• The signal of the first function is set high by the printer
when it runs out of paper.
• The second function of this pin is Clear to Send 6#.
102
BUSY/
DSR6#
DI/
DI
VCC
Printer Busy/Data Set Ready 6#
The signal of the first function goes high when the line printer
has a local operation in progress and cannot accept data.
The second function of this pin is Data Set Ready 6#.
103
ACK#/
DTR6#
DI/
DO
EN
TI
AL
Pin(s) No.
100
VCC
Printer Acknowledge #/Data Terminal Ready 6#
• The signal of the first function goes low to indicate
that the printer has already received a character and is
ready to accept another one.
• The second function of this pin is Data Terminal
Ready 6#.
DIO24/
IO_SW/
DI
VCC
INIT#/
SMBD_M/
SOUT6
DIO24/
IO_SW/
DO
VCC
Printer Initialize #/SMBD_M/ Serial Output Data 6
• The first function of this pin is INIT#.
When the signal is low, the printer is selected. This signal is
derived from the complement of bit 3 of the printer control
register.
• The second function of this pin is SMBus isolation.
• The third function of this pin is Serial Output Data 6.
ERR#/
RTS6#
DI/
DO
VCC
Printer Error #/ Request to Send 5#
When the signal is low, it indicates that the printer has
encountered an error. The error message can be read from
bit 3 of the printer status register.
• The second function of this pin is Request to Send
AFD#/
SMBC_R/
DCD6#
DIO24/
IO_SW/
DI
VCC
STB#/
SMBC_M
DI/
IO_SW
VCC
N
105
SLIN#/
SMBD_R/
SIN6
O
106
C
107
Printer Select Input #/SMBD_R/Serial Input Data 6
• The first function of this pin is SLIN#.
When the signal is low, the printer is selected. This signal is
derived from the complement of bit 3 of the printer control
register.
• The second function of this pin is SMBus isolation.
• The third function of this pin is Serial Input Data 6 .
FI
D
104
108
www.ite.com.tw
5#.
Printer Auto Line Feed #/SMBC_R/ Data Carrier Detect 6#
• The first function of this pin is AFD#. When the signal
is low, it is derived from the complement of bit 1 of
the printer control register and is used to advance
one line after each line is printed.
• The second function of this pin is SMBus isolation.
• The third function of this pin is Data Carrier Detect 6#
Printer Strobe #/SMBC_M
• The first function of this pin is STB#. When the signal
18
IT8783F/E V0.5
Pin Description
Pin(s) No.
Symbol
Attribute
Power
Description
109-116
DIO24/
DIOD8
PD[0:7]/
GP60-67
VCC
TI
AL
is low, it is the complement of bit 0 of the printer
control register and is used to strobe the printing data
into the printer.
• The second function of this pin is SMBus isolation.
Parallel Port Data [0:7] /General Purpose I/O 60-67
• The first function of these pins is PD[0:7]. This bus
provides a byte-wide input or output to the system.
The eight lines are held in a high impedance state
when the port is deselected.
• The second function of these pins is GP60-67.
Table 5-11. Pin Description of Floppy Disk Controller Signals
Symbol
Attribute
Power
51
DENSEL#/
PWROK2
DO24L/
DOD8
VCC
52
MTRA#/
GP50
DO24L/
DIOD8
Description
FDD Density Select #/PWROK2
• The first function of this pin is DENSEL#.
DENSEL# is high for high data rates (500 Kbps, 1 Mbps).
DENSEL# is low for low data rates (250 Kbps, 300 Kbps).
• The second function of this pin is Power OK 2.
The function configuration of this pin is determined by
programming the software configuration registers.
FDD Motor A Enable #/ General Purpose I/O 50
• The first function of this pin is MTRA#. This signal is
EN
Pin(s) No.
VCC
active low.
• The second function of this pin is General Purpose I/O Port
5 Bit 0.
SST/
MTRB#/
PCIRST1#/
PECIRQT
SST/
DO24L/
DOD8/
OD
VCC
External Thermal Sensor Data / FDD Motor B Enable #/
PCIRST1#/PECI Request
• The first function of this pin is SST.
• The second function of this pin is FDD Motor B #. This
signal is active low.
• The third function of this pin is PCIRST1# Output.
• The fourth function of this pin is PECI Request
FI
D
53
Output.
DRVA#/
GP51
DO24L/
DIOD8
VCC
55
PECI/
DRVB#
PECI/
DO24L
VCC
56
WDATA#/
GP52
DO24L/
DIOD8
VCC
C
O
N
54
57
www.ite.com.tw
The function configuration of this pin is determined by
programming the software configuration registers. When
External Thermal Sensor Host is enabled (bit<6:4> of EC
Index 0Ah), this pin is selected as SST or ETS_DAT.
FDD Drive A Enable #/ General Purpose I/O 51
• The first function of this pin is DRVA#. This signal is active
low.
• The second function of this pin is General Purpose I/O Port
5 Bit 1.
PECI / FDD Drive B Enable #
• The first function of this pin is PECI.
• The second function of this pin is FDD Drive B #. This
signal is active low.
The function configuration of this pin is determined by
programming the software configuration registers.
FDD Write Serial Data to the Drive #/ General Purpose I/O
52
• The first function of this pin is WDATA#. This signal
is active low.
• The second function of this pin is General Purpose
I/O Port 5 Bit 2.
DIR#/
DO24L/
VCC
FDD Head Direction #/ General Purpose I/O 53
19
IT8783F/E V0.5
IT8783E/F (For A Version)
Pin(s) No.
Symbol
Attribute
GP53
DIOD8
Power
Description
• The first function of this pin is DIR#. Step in when this
STEP#/
GP54
DO24L/
DIOD8
VCC
HDSEL#/
GP55
DO24L/
DIOD8
VCC
WGATE#/
GP56
DO24L/
DIOD8
VCC
RDATA#/
GP57
DI/
DIOD8
VCC
TRK0#/
CIRTX
DI/
DOD8
59
60
62
• The first function of this pin is STEP#. This signal is
active low.
• The second function of this pin is General Purpose
I/O Port 5 Bit 4.
FDD Head Select #/General Purpose I/O 55
• The first function of this pin is HDSEL#. This signal is
active low.
• The second function of this pin is General Purpose
I/O Port 5 Bit 5.
FDD Write Gage Enable #/ General Purpose I/O 56
• The first function of this pin is WGATE#. This signal
is active low.
• The second function of this pin is General Purpose
I/O Port 5 Bit 6.
FDD Read Disk Data #/ General Purpose I/O 57
• The first function of this pin is RDATA#. This signal is
active low. It is serial data input from FDD.
• The second function of this pin is General Purpose
I/O Port 5 Bit 7.
VCC
FDD Track 0 # /CIR Transmit Output
• The first function of this pin is TRK0#. This signal is
FI
D
61
FDD Step Pulse #/General Purpose I/O 54
EN
58
TI
AL
signal is low and step out when high during a SEEK
operation.
• The second function of this pin is General Purpose
I/O Port 5 bit 3.
active low. It indicates that the head of the selected
drive is on track 0.
• The second function of this pin is Consumer Infrared
Transmit Input.
63
INDEX#/
CIRRX
DI/
DI
VCC
FDD Index #/ CIR Receive Input
• The first function of this pin is INDEX#. This signal is
active low. It indicates the beginning of a disk track.
WPT#/
IRTX
O
N
64
DSKCHG#/
IRRX
C
65
www.ite.com.tw
DI/
DO8
VCC
• The second function of this pin is Consumer Infrared
Receive Input.
FDD Write Protect #/Infrared Transmit Output
• The first function of this pin is WPT#. This signal is
active low. It indicates that the disk of the selected
drive is write-protected.
• The second function of this pin is Infrared Transmit
Output.
DI/
DI
VCC
FDD Disk Change #/Infrared Receive Input
• The first function of this pin is DSKCHG#. This signal
is active low. It senses whether the drive door has
been opened or a diskette has been changed.
• The second function of this pin is Infrared Receive
Input.
20
IT8783F/E V0.5
Pin Description
Table 5-12. Pin Description of Keyboard Controller Signals
Attribute
DIOD24/
DIOD24
Power
VCCH
VCC
81
KCLK/
GP12
DIOD24/
DIOD24
VCCH
VCC
82
MDAT/
GP11
DIOD24/
DIOD24
VCCH
VCC
83
MCLK/
GP10
DIOD24/
DIOD24
KRST#/
GP36
DO16/
DIOD16
VCC
GA20
DO16
VCC
N
46
VCCH
VCC
FI
D
45
Description
Keyboard Data/ General Purpose I/O 13
• The first function of this pin is Keyboard Data.
• The second function of this pin is General Purpose I/O Port
1 Bit 3. This set only supports Simple I/O function.
The function configuration of this pin is determined by
programming the software configuration registers. This pin
doesn’t support internal pull-up.
Keyboard Clock/ General Purpose I/O 12
• The first function of this pin is Keyboard Clock.
• The second function of this pin is General Purpose I/O Port
1 Bit 2. This set only supports Simple I/O function.
The function configuration of this pin is determined by
programming the software configuration registers. This pin
doesn’t support internal pull-up.
PS/2 Mouse Data/ General Purpose I/O 11
• The first function of this pin is PS/2 Mouse Data.
• The second function of this pin is General Purpose I/O Port
1 Bit 1.
The function configuration of this pin is determined by
programming the software configuration registers. This pin
doesn’t support internal pull-up.
PS/2 Mouse Clock/ General Purpose I/O 10
• The first function of this pin is PS/2 Mouse Clock.
• The second function of this pin is General Purpose I/O Port
1 Bit 0.
The function configuration of this pin is determined by
programming the software configuration registers. This pin
doesn’t support internal pull-up.
Keyboard Reset #/ General Purpose I/O 36
• The first function of this pin is Keyboard Reset #.
• The second function of this pin is General Purpose I/O Port
3 Bit 6. This set only supports Simple I/O function.
The function configuration of this pin is determined by
programming the software configuration registers.
Gate Address 20
The function of this pin is CPU address 20.
TI
AL
Symbol
KDAT/
GP13
EN
Pin(s) No.
80
Table 5-13. Pin Description of Hardware Monitor Signals
Symbol
VIN[0:7]
O
Pin(s) No.
98-91
C
95
www.ite.com.tw
VIN3/
ATXPG/
DSR6#
Attribute
AI
Power
AVCC
AI/
DI/
DI
AVCC
Description
Voltage Analog Inputs [0:7]
The function of these pins is 0 to 4.096V FSR Analog Inputs.
Voltage Analog Input 3 / ATX Power Good/ Data Set
Ready 6#
• The first function of this pin is 0 to 4.096V Analog Inputs.
• The second function of this pin is Power Good Input #.
PWROK1/2 will be (VCC power-level-detect AND
RESETCON# AND SUSB# AND ATXPG) if bit0 of Index
2Ch is 1, or (VCC power-level-detect AND RESETCON#
AND SUSB#) if 0.
• The third function of this pin is DSR6#.
The function configuration of this pin is determined by
programming the software configuration registers.
21
IT8783F/E V0.5
IT8783E/F (For A Version)
Attribute
AO
Power
AVCC
89-88
TMPIN[1:2]
AI
AVCC
87
TMPIN3
RI6#
AI/
DI
AVCC
68
COPEN#
DO
7
FAN_TAC1
DI
VCCH
or VBAT
VCC
9
FAN_TAC2
DI
VCC
93
VIN5/
FAN_TAC3/
SIN6/
GP30
AI/
DI/
DI/
DI
VCC
Description
Reference Voltage Output
Regulated and referred voltage for three external temperature
sensors and negative voltage monitor.
External Thermal Inputs [1:2]
These pins are connected to thermistors [1:2] or thermal
temperature sensors.
External Thermal Inputs 3/RI6#
• For the first function, this pin is connected to thermistor 1 or
thermal temperature sensor.
• The second function of this pin is Ring Input 6.
Case Open Indication #
The function of this pin is Case Open Indication Output.
Fan Tachometer Input 1
0 to +5V amplitude Fan Tachometer Input.
Fan Tachometer Input 2
0 to +5V amplitude Fan Tachometer Input.
VIN5/FAN Tachometer Input 3/Serial Data Input 6/ General
Purpose I/O 30
• The first function of this pin is Analog Voltage CH5
TI
AL
Symbol
VREF
EN
Pin(s) No.
90
Input.
FI
D
• The second function of this pin is FAN Tachometer Input 3.
• The third function of this pin is Serial Data Input 6.
• The fourth function of this pin is General Purpose I Port 3
Bit 0 (input mode only).
The function configuration of this pin is determined by
programming the software configuration registers.
Table 5-14. Pin Description of Fan Controller Signals
Pin(s) No.
8
Symbol
FAN_CTL1
Attribute
DOD8
Power
VCC
10
FAN_CTL2
DOD8
VCC
CE_N/
FAN_CTL3/
GP14
DO/
DOD8/
DIOD8
VCC
C
O
N
30
Description
Fan Control Output 1
PWM output signal to Fan’s FET.
Fan Control Output 2
PWM output signal to Fan’s FET.
CE_N/FAN Control Output 3 / General Purpose I/O 14
• The first function of this pin is Flash Chip Select Output.
• The second function of this pin is Fan Control Output 3.
• The third function of this pin is General Purpose I/O Port 1
Bit 4.
The function configuration of this pin is determined by
programming the software configuration registers.
www.ite.com.tw
22
IT8783F/E V0.5
Pin Description
Table 5-15. Pin Description of SFI Signals
Symbol
SI/
GP17/
PCIRST3#
Attribute
DOD8/
DIOD8/
DIOD8
Power
VCC
Description
Serial Flash Data-In / General Purpose I/O 17/ PCI Reset
Output 3#
• The first function of this pin is Serial Flash Data-In Output.
• The second function of this pin is General Purpose I/O Port
1 Bit 7
• The third function of this pin is PCI Reset Output 3#.
TI
AL
Pin(s) No.
24
The function configuration of this pin is determined by
programming the software configuration registers.
DOD8/
DIOD8/
DIOD8
91
VIN7/
SO/
GP32
AI/
DI/
DI
30
CE_N/
FAN_CTL3/
GP14
DO/
DOD8/
DIOD8
VCC
Serial Flash Clock / General Purpose I/O 16 / PCI Reset
Output 2#
• The first function of this pin is Serial Clock for Serial Flash.
• The second function of this pin is General Purpose I/O Port
1 Bit 6.
• The third function of this pin is PCI Reset Output 2#.
The function configuration of this pin is determined by
programming the software configuration registers.
VIN7/Serial Flash Data-Out / General Purpose I/O 32
• The first function of this pin is Analog Voltage CH7 Input.
• The second function of this pin is Serial Flash Data-Out
Input.
• The third function of this pin is General Purpose I Port 3 Bit
2 (input mode only)
The function configuration of this pin is determined by
programming the software configuration registers.
CE_N/FAN Control Output 3 / General Purpose I/O 14
• The first function of this pin is Flash Chip Select Output.
• The second function of this pin is Fan Control Output 3.
• The third function of this pin is General Purpose I/O Port 1
Bit 4.
The function configuration of this pin is determined by
programming the software configuration registers.
EN
SCK/
GP16/
PCIRST2#
VCC
VCC
FI
D
25
Table 5-16. Pin Description of Miscellaneous Signals
Symbol
CLKIN
SUSB#/
GP47
O
N
Pin(s) No.
49
71
PWRON#/
GP46
C
72
www.ite.com.tw
Attribute
DI
DI/
DIOD8
Power
VCC
VCCH
DOD8/
DIOD8
VCCH
Description
24 or 48 MHz Clock Input
SUSB# Input/ GP47
• The first function of this pin is SUSB# Input.
• The second function of this pin is General Purpose I/O Port
4 Bit 7.
The function configuration of this pin is determined by
programming the software configuration registers.
Power On Request Output # / General Purpose I/O46
• The first function of this pin is Power On Request Output #.
• The second function of this pin is General Purpose I/O Port
4 Bit 6.
The function configuration of this pin is determined by
programming the software configuration registers.
23
IT8783F/E V0.5
IT8783E/F (For A Version)
Attribute
DOD8/
DIOD8
Power
VCCH
75
PANSWH#/
GP43
DI/
DIOD8
VCCH
76
PSON#/
GP42
DOD8/
DIOD8
VCCH
77
SUSC#/
SOUT6/
GP35
DI/
DI/
DIOD8
PWROK1/
GP41
3VSBSW#/
GP40
DOD8/
DIOD8
VCCH
DO8/
DIOD8
VCCH
N
79
VCCH
VCC
VCC
FI
D
78
Description
Power Management Event# / General Purpose I/O 45
• The first function of this pin is P Power Management Event
#.
• The second function of this pin is General Purpose I/O Port
4 Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
Main Power Switch Button Input# / General Purpose I/O
43
• The first function of this pin is Main Power Switch Button
Input#.
• The second function of this pin is General Purpose I/O Port
4 Bit 3.
The function configuration of this pin is determined by
programming the software configuration registers.
Power Supply On-Off Output # / General Purpose I/O 42
• The first function of this pin is Power Supply On-Off Control
Output #.
• The second function of this pin is General Purpose I/O Port
4 Bit 2.
The function configuration of this pin is determined by
programming the software configuration registers.
SUSC# Input /SOUT6/ General Purpose I/O 35
• The first function of this pin is SUSC# Input.
• The second function of this pin is Serial Output Data 6.
• The third function of this pin is General Purpose I/O Port 3
Bit 5.
The function configuration of this pin is determined by
programming the software configuration registers.
Power OK1 of VCC / General Purpose I/O 41
• The first function of this pin is Power OK1 of VCC.
• The second function of this pin is General Purpose I/O Port
4 Bit 1.
The function configuration of this pin is determined by
programming the software configuration registers.
3VSBSW# / General Purpose I/O 40
• The first function of this pin is 3VSBSW#.
• The second function of this pin is General Purpose I/O Port
4 Bit 0.
The function configuration of this pin is determined by
programming the software configuration registers.
TI
AL
Symbol
PME#/
GP45
EN
Pin(s) No.
73
C
O
Note 1: In addition to providing a highly integrated chip, ITE also implements a “SmartGuardian Utility”
hardware monitoring application, providing a total solution for customers. The “SmartGuardian Utility” and the
application note on the hardware monitoring circuit (the functional arrangement of VIN0-7, TMPIN1-3,
FAN_TAC1-3 and FAN_CTL1-3) are interdependent. That is to say, the “SmartGuardian Utility” is accurate
only when programmed according to the application note on the hardware monitoring circuit. ITE strongly
recommends customers follow the referenced application circuit of IT8783E/F to reduce the “time-to-market”
schedule.
Pin No.
Symbol
Recommended Function Arrangement
98
VIN0
2 Volt for VCORE1 of CPU
97
VIN1
2 Volt for VCORE2 of CPU
96
VIN2
-5 Volt for system
www.ite.com.tw
24
IT8783F/E V0.5
Pin Description
VIN3
3.3 Volt for system
94
VIN4
+12 Volt for system
93
VIN5
VCC for system
92
VIN6
VBAT for system
91
VIN7
5 Volt for VCCH
IO Cell:
DO8: 8mA Digital Output buffer
DOD8: 8mA Digital Open-Drain Output buffer
DO16: 16mA Digital Output buffer
DO24: 24mA Digital Output buffer
DO24L: 24mA shink/8mA drive Digital Output buffer
DI: Digital Input
AI: Analog Input
AO: Analog Output
EN
DIO8: 8mA Digital Input/Output buffer
DIOD8: 8mA Digital Open-Drain Input/Output buffer
DIO16: 16mA Digital Input/Output buffer
DIOD16: 16mA Digital Open-Drain Input/Output buffer
DIO24: 24mA Digital Input/Output buffer
DIOD24: 24mA Digital Open-Drain Input/Output buffer
TI
AL
95
C
O
N
FI
D
SST: special design for SST interface
PECI: special design for PECI interface
IO_SW: special type of input/output; this type of pins are connected in pairs through a switch.
www.ite.com.tw
25
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
26
IT8783F/E V0.5
List of GPIO Pins
6.
List of GPIO Pins
Table 6-1. General Purpose I/O Group 1 (Set 1)
81
80
30
29
25
24
Attribute
DIOD24/
DIOD24
DIOD24/
DIOD24
DIOD24/
DIOD24
DIOD24/
DIOD24
DO/
DO/
DIOD8
DO/
DIOD8
DOD8/
DIOD8/
DOD
DOD8/
DIOD8/
DOD
Description
PS/2 Mouse Clock/ General Purpose I/O 10
TI
AL
82
Symbol
MCLK/
GP10
MDAT/
GP11
KCLK/
GP12
KDAT/
GP13
CE_N/
FAN_CTL3/
GP14
DTR6#/
GP15
SCK/
GP16/
PCIRST2#
SI/
GP17/
PCIRST3#
PS/2 Mouse Data/ General Purpose I/O 11
Keyboard Clock/ General Purpose I/O 12
Keyboard Data/ General Purpose I/O 13
CE_N / FAN_CTL3 /General Purpose I/O 14
DTR6#/General Purpose I/O 15
Serial Flash Clock Output/General Purpose I/O 16/ PCI Reset Output
2#
EN
Pin(s) No.
83
Serial Flash In Data/ General Purpose I/O 17/ PCI Reset Output 3#
Table 6-2. General Purpose I/O Group 2 (Set 2)
70
66
48
36
N
34
Symbol
DCD5#/
GP20
RI5#/
GP21
SOUT5/
GP22
SIN5/
GP23
DSR5#/
GP24
RTS5#/
GP25
DTR5#/
GP26
RESETCON#/
CTS5#/
GP27
33
Description
Data Carrier Detect 5 #/ General Purpose I/O 20
Ring Indicator 5 #/ General Purpose I/O 21
Serial Data Output 5 / General Purpose I/O 22
Serial Data Input 5 / General Purpose I/O 23
Data Set Ready 5 #/ General Purpose I/O 24
Request to Send 5# / General Purpose I/O 25
Data Terminal Ready 5#/ General Purpose I/O 26
RESET Input Connect#/Clear to Send 5#/ General Purpose I/O 27
C
O
32
Attribute
DI/
DIOD8
DI/
DIOD8
DO8/
DIOD8
DI/
DIOD8
DI/
DIOD8
DO/
DIOD8
DO/
DIOD8
DI/
DI/
DIOD8
FI
D
Pin(s) No.
84
www.ite.com.tw
27
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 6-3. General Purpose I/O Group 3 (Set 3)
91
10
85
77
45
9
Attribute
AI/
DI/
DIOD8
AI/
DI/
DIOD8
AI/
DI/
DIOD8
DOD/
DIOD8
DOD8/
DO/
DIOD8/
DI
DI/
DO/
DIOD8
DO8/
DIOD8
DI/
DIOD8
Description
VIN5/FAN_TAC3 Input/ General Purpose I/O 30
TI
AL
92
Symbol
VIN5/
FAN_TAC3/
GP30
VIN6/
CTS6#/
GP31
VIN7/
SO/
GP32
FAN_CTL2/
GP33
RSMRST#/
RTS6#/
GP34/
CIRRX1
SUSC#/
SOUT6#/
GP35
KRST#/
GP36
FAN_TAC2/
GP37
VIN6/Clear to Send 6#/ General Purpose I/O 31
VIN7/Seral Flash SO Input/ General Purpose I/O 32
FAN Control Output 2/ General Purpose I/O 33
Resume Reset Output/Request to Send 6#/ General Purpose I/O 34/
CIR Receive Input 1
SUSC# Input/Serial Data Output 6# /General Purpose I/O 35
EN
Pin(s) No.
93
Keyboard Reset Output# / General Purpose I/O 36
Fan Tachometer Input 2 / General Purpose I/O 37
Table 6-4. General Purpose I/O Group 4 (Set 4)
78
76
75
N
73
Symbol
3VSBSW#/
GP40
DTR6#/
PWROK/
GP41
PSON#/
GP42
PANSWH#/
GP43
PME#/
GP45
PWRON#/
GP46
SUSB#/
GP47
72
Description
3VSBSW# / General Purpose I/O 40
Data Terminal Ready 6#/Power OK of VCC / General Purpose I/O 41
Power Supply On-Off Output# / General Purpose I/O 42
Main Power Switch Button Input# / General Purpose I/O 43
Power Management Event Output# / General Purpose I/O 45
Power On Request Output# / General Purpose I/O 46
SUSB# Input/ General Purpose I/O 47
C
O
71
Attribute
DO8/
DIOD8
DOD8/
DO8/
DIOD8
DOD8/
DIOD8
DI/
DIOD8
DOD8/
DIOD8
DOD8/
DIOD8
DI/
DIOD8
FI
D
Pin(s) No.
79
www.ite.com.tw
28
IT8783F/E V0.5
List of GPIO Pins
Table 6-5. General Purpose I/O Group 5 (Set 5)
56
57
58
59
60
61
Attribute
DO24/
DIOD24
DO24/
DIOD24
DO24/
DIOD24
DO24/
DIOD24
DO24/
DIOD24
DO24/
DIOD24
DIO24/
DIOD24
DI/
DIOD24
Description
FDD Motor A Enable# / General Purpose I/O 50
TI
AL
54
Symbol
MTRA#/
GP50
DRVA#/
GP51
WDATA#/
GP52
DIR#/
GP53
STEP#/
GP54
HDSEL#/
GP55
WGATE#/
GP56
RDATA#/
GP57
FDD Drive A Enable# / General Purpose I/O 51
FDD Write Select to Drive# / General Purpose I/O 52
FDD Head Direction # / General Purpose I/O 53
FDD Step Pulse # / General Purpose I/O 54
FDD Head Select # / General Purpose I/O 55
FDD Write Gage Enable/ General Purpose I/O 56
FDD Read Disk Data # / General Purpose I/O 57
EN
Pin(s) No.
52
Table 6-6. General Purpose I/O Group 6 (Set 6)
Pin(s) No.
109
111
112
113
114
115
Description
Parallel Port Data 0 / General Purpose I/O 60
Parallel Port Data 1 / General Purpose I/O 61
Parallel Port Data 2 / General Purpose I/O 62
Parallel Port Data 3 / General Purpose I/O 63
Parallel Port Data 4 / General Purpose I/O 64
Parallel Port Data 5 / General Purpose I/O 65
Parallel Port Data 6 / General Purpose I/O 66
Parallel Port Data 7 / General Purpose I/O 67
C
O
N
116
Attribute
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
DIO24/
DIO24
FI
D
110
Symbol
PD0/
GP60
PD1/
GP61
PD2/
GP62
PD3/
GP63
PD4/
GP64
PD5/
GP65
PD6/
GP66
PD7/
GP67
www.ite.com.tw
29
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
30
IT8783F/E V0.5
Power On Strapping Options
7.
Power On Strapping Options
Table 7-1. Power On Strapping Options
Pin 121
1
Disable
0
Flash I/F Address Segment FFF0_0000~FFFF_FFFF &
000E_0000~000F_FFFF is enabled.
1
When there are two IT8783E/F chips in a system, and CS(bit 7 of
configuration select and chip version register) is set to ‘1’, the chip with
JP3=1 will be configured and chip with JP3=0 will exit the configuration
mode.
0
When there are two IT8783E/F chips in a system, and CS(bit 7 of
configuration select and chip version register) is set to ‘0’, the chip with
JP3=0 will be configured and chip with JP3=1 will exit the configuration
mode.
1
JP2=1; unlock LPC memory/FWM write to Serial Flash
0
JP2=0; lock LPC memory/FWM write to Serial Flash
1
JP4 =1; pin100-106 for parallel port
0
JP4=0; move UART6 to pin100~106
1
JP6=1; normal FDC function
0
JP6=0; enable POWROK2
Flashseg1_EN
JP3
JP2
Pin 122
JP4
Pin 1
JP6
Pin 5
CHIP_SEL
SPI WR LOCK
MOVE UART6
Enable GPIO 5
FI
D
Pin 124
JP8, JP9 Enable PCIRST#
Out
Pin18, 16
JP5, JP7
FAN_CTL_SEL
N
Pin 2, 14
JP7
1
0
JP8=1; disable PCIRST#1 output
JP9=1; disable PCIRST#2, 3 output
JP8=0; enable PCIRST1# output
JP9=0; enable PCIRST2, 3# output
11
The default value of EC index 15/16/17h is 00h.
10
The default value of EC index 15/16/17h is 20h.
01
The default value of EC index 15/16/17h is 40h.
00
The default value of EC index 15/16/17h is 60h.
1
Disable WDT to rest PWROK.
0
Enable WDT to rest PWROK.
WDT_EN
C
O
Pin 14
Description
TI
AL
JP1
Value
EN
Symbol
www.ite.com.tw
31
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
32
IT8783F/E V0.5
Configuration
8.
Configuration
8.1
Description of Configuring Sequence
TI
AL
After a hardware reset or power-on reset, the IT8783E/F enters the normal mode with all logical devices
disabled except KBC. The initial state (enable bit) of this logical device (KBC) is “1”.
Hardware Reset
Any other I/O transition cycle
Wait for key string
I/O write to 2Eh
N
Is the data
"87h" ?
Y
Any other I/O transition cycle
EN
Check Pass key
I/O write to 2Eh
N
Next Data?
FI
D
Y
N
Last Data?
Y
MB PnP Mode
N
There are three steps to completing the configuration setup: (1) Enter the MB PnP Mode; (2) Modify the data
of configuration registers; (3) Exit the MB PnP Mode. The undesired result may occur if the MB PnP Mode is
not exited properly.
O
(1) Enter the MB PnP Mode
C
To enter the MB PnP Mode, four special I/O write operations are to be performed during the Wait for Key
state. To ensure the initial state of the key-check logic, it is necessary to perform four write operations to the
Special Address port (2Eh). Two different enter keys are provided to select configuration ports (2Eh/2Fh or
4Eh/4Fh) of the next step.
87h, 01h, 55h, 55h;
or 87h, 01h, 55h, AAh;
www.ite.com.tw
Address port Data port
2Eh
2Fh
4Eh
4Fh
33
IT8783F/E V0.5
IT8783E/F (For A Version)
(2) Modify the Data of configuration registers
TI
AL
All configuration registers can be accessed after entering the MB PnP Mode. Before accessing a selected
register, the content of Index 07h must be changed to the LDN to which the register belongs, except some
Global registers.
(3) Exit the MB PnP Mode
C
O
N
FI
D
EN
Set bit 1 of the configure control register (Index=02h) to “1” to exit the MB PnP Mode.
www.ite.com.tw
34
IT8783F/E V0.5
Configuration
8.2
Description of Configuration Registers
All registers except APC/PME’ registers will be reset to the default state when RESET is activated.
TI
AL
Table 8-1. Global Configuration Registers
LDN
Index
R/W
Reset
All
02h
W
NA
Configure Control
All
07h
R/W
NA
Logical Device Number (LDN)
All
20h
R
87h
Chip ID Byte 1
All
21h
R
83h
Chip ID Byte 2
All
22h
W-R
00h
Configuration Select and Chip Version
All
23h
R/W
00h
Clock Selection Register
All
0ss0s0s0b
R/W
00h
Software Suspend and Flash I/F Control Register
07h Note1
25h
R/W
00h
07h Note1
26h
R/W
Note1
27h
R/W
07h Note1
28h
R/W
07h Note1
29h
R/W
07h Note1
2Ah
R/W
00h
All
2Bh
R/W
00h
07h Note1
2Ch
R/W
03h
07h
Note1
2Dh
R/W
00h
GPIO Set 6 Enable Register
F4h
Note1
2Eh
R/W
00h
Test 1 Register
F4h
Note1
2Fh
R/W
00h
Test 2 Register
GPIO Set 1 Multi-Function Pin Selection Register
EN
Bit 0 powered by VCCH.
00h
00h
00h
00h
GPIO Set 2 Multi-Function Pin Selection Register
Bit 7-0 powered by VCCH.
GPIO Set 3 Multi-Function Pin Selection Register
GPIO Set 4 Multi-Function Pin Selection Register
Bit 7-0 powered by VCCH.
GPIO Set 5 Multi-Function Pin Selection Register
FI
D
N
07h
Configuration Register or Action
Bit 3-5 powered by VCCH.
Extended 1 Multi-Function Pin Selection Register
Bit 7-0 powered by VCCH.
Logical Block Lock Register
Extended 2 Multi-Function Pin Selection Register
Bit 7-0 powered by VCCH.
C
O
Note 1: These registers can be read from all LDNs.
www.ite.com.tw
35
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 8-2. FDC Configuration Registers
Index
R/W
Reset
Configuration Register or Action
00h
30h
R/W
00h
FDC Activate
00h
60h
R/W
03h
FDC Base Address MSB Register
00h
61h
R/W
F0h
FDC Base Address LSB Register
00h
70h
R/W
06h
FDC Interrupt Level Select
00h
74h
R/W
02h
FDC DMA Channel Select
00h
F0h
R/W
00h
FDC Special Configuration Register 1
00h
F1h
R/W
00h
FDC Special Configuration Register 2
TI
AL
LDN
Table 8-3. Serial Port 1 Configuration Registers
R/W
01h
30h
R/W
01h
60h
R/W
01h
61h
R/W
01h
70h
R/W
01h
F0h
R/W
Reset
Configuration Register or Action
EN
Index
00h
Serial Port 1 Activate
03h
Serial Port 1 Base Address MSB Register
F8h
Serial Port 1 Base Address LSB Register
04h
Serial Port 1 Interrupt Level Select
00h
Serial Port 1 Special Configuration Register 1
FI
D
LDN
Table 8-4. Serial Port 2 Configuration Registers
LDN
02h
02h
02h
02h
R/W
Reset
30h
R/W
00h
Serial Port 2 Activate
60h
R/W
02h
Serial Port 2 Base Address MSB Register
61h
R/W
F8h
Serial Port 2 Base Address LSB Register
70h
R/W
03h
Serial Port 2 Interrupt Level Select
F0h
R/W
00h
Serial Port 2 Special Configuration Register 1
Configuration Register or Action
C
O
N
02h
Index
www.ite.com.tw
36
IT8783F/E V0.5
Configuration
Table 8-5. Parallel Port Configuration Registers
Index
R/W
Reset
03h
30h
R/W
00h
Parallel Port Activate
03h
60h
R/W
03h
Parallel Port Primary Base Address MSB Register
03h
61h
R/W
78h
Parallel Port Primary Base Address LSB Register
03h
62h
R/W
07h
Parallel Port Secondary Base Address MSB Register
03h
63h
R/W
78h
Parallel Port Secondary Base Address LSB Register
03h
70h
R/W
07h
Parallel Port Interrupt Level Select
03h
74h
R/W
03h
Parallel Port DMA Channel Select
03h
F0h
R/W
03h
Note2
Configuration Register or Action
TI
AL
LDN
Parallel Port Special Configuration Register
EN
Note 2: When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP mode
cannot be enabled. Bit 0 of this register is always 0.
Table 8-6. Environment Controller Configuration Registers
LDN
Index
R/W
04h
30h
R/W
04h
60h
R/W
04h
61h
R/W
04h
62h
R/W
04h
63h
R/W
70h
Reset
Configuration Register or Action
Environment Controller Activate
02h
Environment Controller Base Address MSB Register
90h
Environment Controller Base Address LSB Register
02h
PME Direct Access Base Address MSB Register
30h
PME Direct Access Base Address LSB Register
R/W
09h
Environment Controller Interrupt Level Select
F0h
R/W
00h
APC/PME Event Enable Register
F1h
R/W
00h
APC/PME Status Register
F2h
R/W
00h
APC/PME Control Register 1
F3h
R/W
00h
Environment Controller Special Configuration Register
F4h
R-R/W
00h
APC/PME Control Register 2
F5h
R/W
-
APC/PME Special Code Index Register
04h
F6h
R/W
-
APC/PME Special Code Data Register
04h
F7h
R/W
-
APC/PME Control (PCR 7) Data Register
04h
04h
04h
04h
04h
04h
C
O
N
04h
FI
D
00h
www.ite.com.tw
37
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 8-7. KBC(Keyboard) Configuration Registers
Index
R/W
Reset
Configuration Register or Action
05h
30h
R/W
01h
KBC(Keyboard) Activate
05h
60h
R/W
00h
KBC(Keyboard) Data Base Address MSB Register
05h
61h
R/W
60h
KBC(Keyboard) Data Base Address LSB Register
05h
62h
R/W
00h
KBC(Keyboard) Command Base Address MSB Register
05h
63h
R/W
64h
KBC(Keyboard) Command Base Address LSB Register
05h
70h
R/W
01h
KBC(Keyboard) Interrupt Level Select
05h
71h
R-R/W
02h
KBC(Keyboard) Interrupt Type Note3
05h
F0h
R/W
08h
KBC(Keyboard) Special Configuration Register
TI
AL
LDN
LDN
Index
R/W
06h
30h
R/W
06h
70h
R/W
06h
71h
R-R/W
06h
F0h
R/W
EN
Table 8-8. KBC(Mouse) Configuration Registers
Reset
Configuration Register or Action
00h
KBC(Mouse) Activate
0Ch
KBC(Mouse) Interrupt Level Select
02h
KBC(Mouse) Interrupt Type Note3
00h
KBC(Mouse) Special Configuration Register
FI
D
Note 3: These registers are read only unless the write enable bit (Index=F0h) is asserted.
Table 8-9. GPIO Configuration Registers
LDN
Index
R/W
Reset
60h
R/W
00h
SMI# Normal Run Access Base Address MSB Register
61h
R/W
00h
SMI# Normal Run Access Base Address LSB Register
62h
R/W
00h
Simple I/O Base Address MSB Register
63h
R/W
00h
Simple I/O Base Address LSB Register
64h
R/W
00h
Serial Flash I/F Base Address MSB Register
07h
65h
R/W
00h
Serial Flash I/F Base Address LSB Register
07h
70h
R/W
00h
Panel Button De-bounce Interrupt Level Select Register
07h
71h
R/W
00h
Watch Dog Timer 1 Control Register
07h
72h
R/W
07h
73h
R/W
38h
Watch Dog Timer 1 Time-out Value (LSB) Register
07h
74h
R/W
00h
Watch Dog Timer 1 Time-out Value (MSB) Register
07h
81h
R/W
00h
Watch Dog Timer 2 Control Register
07h
82h
R/W
07h
83h
R/W
38h
Watch Dog Timer 2 Time-out Value (LSB) Register
07h
84h
R/W
00h
Watch Dog Timer 2 Time-out Value (MSB) Register
07h
91h
R/W
00h
Watch Dog Timer 3 Control Register
07h
07h
07h
07h
C
O
N
07h
www.ite.com.tw
Configuration Register or Action
001s0000b Watch Dog Timer 1 Configuration Register
001s0000b Watch Dog Timer 2 Configuration Register
38
IT8783F/E V0.5
Configuration
LDN
Index
R/W
07h
92h
R/W
07h
93h
R/W
38h
Watch Dog Timer 3 Time-out Value (LSB) Register
07h
94h
R/W
00h
Watch Dog Timer 3 Time-out Value (MSB) Register
07h
B0h
R/W
00h
GPIO Set 1 Pin Polarity Register
07h
B1h
R/W
00h
GPIO Set 2 Pin Polarity Register
07h
B2h
R/W
00h
GPIO Set 3 Pin Polarity Register
07h
B3h
R/W
00h
GPIO Set 4 Pin Polarity Register
07h
B4h
R/W
00h
GPIO Set 5 Pin Polarity Register
07h
B8h
R/W
00h
GPIO Set 1 Pin Internal Pull-up Enable Register
07h
B9h
R/W
00h
GPIO Set 2 Pin Internal Pull-up Enable Register
07h
BAh
R/W
00h
GPIO Set 3 Pin Internal Pull-up Enable Register
07h
BBh
R/W
00h
GPIO Set 4 Pin Internal Pull-up Enable Register
07h
BCh
R/W
07h
C0h
R/W
07h
C1h
R/W
07h
C2h
R/W
07h
07h
07h
07h
EN
TI
AL
001s0000b Watch Dog Timer 3 Configuration Register
00h
01h
00h
00h
GPIO Set 5 Pin Internal Pull-up Enable Register
Simple I/O Set 1 Enable Register
Bit 7-0 powered by VCCH.
Simple I/O Set 2 Enable Register
Bit 7-0 powered by VCCH.
Simple I/O Set 3 Enable Register
Simple I/O Set 4 Enable Register
C3h
R/W
40h
C4h
R/W
00h
C8h
R/W
01h
Simple I/O Set 1 Output Enable Register
C9h
R/W
00h
Simple I/O Set 2 Output Enable Register
CAh
R/W
00h
Simple I/O Set 3 Output Enable Register
CBh
R/W
40h
CCh
R/W
00h
R/W
00h
N
07h
Configuration Register or Action
FI
D
07h
Reset
O
07h
CDh
Simple I/O Set 5 Enable Register
Bit 7-0 powered by VCCH.
Simple I/O Set 4 Output Enable Register
Bit 7-0 powered by VCCH.
Simple I/O Set 5 Output Enable Register
Bit 7-0 powered by VCCH.
Simple I/O Set 6 Output Enable Register
Bit 7-0 powered by VCCH.
C
07h
Bit 7-0 powered by VCCH.
www.ite.com.tw
39
IT8783F/E V0.5
IT8783E/F (For A Version)
E0h
R/W
00h
Panel Button De-bounce 0 Input Pin Mapping Register
07h
E1h
R/W
00h
Panel Button De-bounce 1 Input Pin Mapping Register
07h
E2h
R/W
00h
IRQ External Routing 0 Input Pin Mapping Register
07h
E3h
R/W
00h
IRQ External Routing 1 Input Pin Mapping Register
07h
E4h
R/W
00h
IRQ External Routing 1-0 Interrupt Level Selection
Registers
07h
EFh
R/W
00001s0
07h
F0h
R/W
00h
SMI# Control Register 1
07h
F1h
R/W
00h
SMI# Control Register 2
07h
F2h
R/W
00h
SMI# Status Register 1
07h
F3h
R/W
00h
SMI# Status Register 2
07h
F4h
R/W
00h
SMI# Pin Mapping Register
07h
F5h
R/W
07h
F6h
R/W
07h
F7h
R/W
07h
F8h
R/W
EN
SPI Function Pin Selection Register
00h
Hardware Monitor Thermal Output Pin Mapping Register
Bit 7-0 powered by VCCH.
00h
Hardware Monitor Alert Beep Pin Mapping Register
00h
Keyboard Lock Pin Mapping Register
00h
GP LED Blinking 1 Pin Mapping Register
Bit 7-0 powered by VCCH.
GP LED Blinking 1 Control Register
FI
D
07h
TI
AL
07h
F9h
R/W
00h
FAh
R/W
00h
FBh
R/W
00h
FCh
R/W-R
--h
Reserved
FDh
R/W
00h
Reserved
07h
FEh
R/W
00h
Reserved
07h
FFh
R/W
00h
Reserved
07h
07h
07h
O
N
07h
Bit 7-0 powered by VCCH.
GP LED Blinking 2 Pin Mapping Register
Bit 7-0 powered by VCCH.
GP LED Blinking 2 Control Register
Bit 7-0 powered by VCCH.
Table 8-10. Serial Port 3 Configuration Registers
Index
R/W
Reset
08h
30h
R/W
00h
Serial Port 3 Activate
08h
60h
R/W
03h
Serial Port 3 Base Address MSB Register
08h
61h
R/W
F8h
Serial Port 3 Base Address LSB Register
08h
70h
R/W
04h
Serial Port 3 Interrupt Level Select
08h
F0h
R/W
00h
Serial Port 3 Special Configuration Register 1
08h
F1h
R/W
50h
Serial Port 3 Special Configuration Register 2
C
LDN
www.ite.com.tw
Configuration Register or Action
40
IT8783F/E V0.5
Configuration
Index
R/W
Reset
08h
F2h
R/W
00h
Configuration Register or Action
Serial Port 3 Special Configuration Register 3
C
O
N
FI
D
EN
TI
AL
LDN
www.ite.com.tw
41
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 8-11. Serial Port 4 Configuration Registers
Index
R/W
Reset
Configuration Register or Action
09h
30h
R/W
00h
Serial Port 4 Activate
09h
60h
R/W
02h
Serial Port 4 Base Address MSB Register
09h
61h
R/W
F8h
Serial Port 4 Base Address LSB Register
09h
70h
R/W
04h
Serial Port 4 Interrupt Level Select
09h
F0h
R/W
00h
Serial Port 4 Special Configuration Register 1
09h
F1h
R/W
50h
Serial Port 4 Special Configuration Register 2
09h
F2h
R/W
00h
Serial Port 4 Special Configuration Register 3
TI
AL
LDN
Index
R/W
0Ah
30h
R/W
0Ah
60h
R/W
0Ah
61h
R/W
0Ah
70h
R/W
0Ah
F0h
R/W
0Ah
0Ah
Reset
Configuration Register or Action
00h
Serial Port 5 Activate
03h
Serial Port 5 Base Address MSB Register
F8h
Serial Port 5 Base Address LSB Register
04h
Serial Port 5 Interrupt Level Select
00h
Serial Port 5 Special Configuration Register 1
FI
D
LDN
EN
Table 8-12. Serial Port 5 Configuration Registers
F1h
R/W
50h
Serial Port 5 Special Configuration Register 2
F2h
R/W
00h
Serial Port 5 Special Configuration Register 3
Table 8-13. Serial Port 6 Configuration Registers
LDN
Index
R/W
Reset
30h
R/W
00h
Serial Port 6 Activate
60h
R/W
02h
Serial Port 6 Base Address MSB Register
0Bh
61h
R/W
F8h
Serial Port 6 Base Address LSB Register
0Bh
70h
R/W
04h
Serial Port 6 Interrupt Level Select
0Bh
F0h
R/W
00h
Serial Port 6 Special Configuration Register 1
0Bh
C
O
N
0Bh
Configuration Register or Action
www.ite.com.tw
42
IT8783F/E V0.5
Configuration
Table 8-14. Consumer IR Configuration Registers
Index
R/W
Reset
0Ch
30h
R/W
00h
Consumer IR Activate
0Ch
60h
R/W
03h
Consumer IR Base Address MSB Register
0Ch
61h
R/W
10h
Consumer IR Base Address LSB Register
0Ch
70h
R/W
0Bh
Consumer IR Interrupt Level Select
0Ch
F0h
R/W
06h
Consumer IR Special Configuration Register
8.2.1
Configuration Register or Action
Logical Device Base Address
TI
AL
LDN
The base I/O range of logical devices shown below is located in the base I/O address range of each logical
device.
Table 8-15. Base Address of Logical Devices
Address
Notes
EN
Logical Devices
Base + (2 - 5) and + 7
LDN=1 SERIAL PORT 1
Base + (0 -7)
UART1
LDN=2 SERIAL PORT 2
Base1 + (0 -7)
UART2
LDN=3
PARALLEL PORT
Base1 + (0 -3)
SPP
Base1 + (0 -7)
SPP+EPP
Base1 + (0 -3) and Base2 + (0 -3)
SPP+ECP
Base1 + (0 -7) and Base2 + (0 -3)
SPP+EPP+ECP
Base3
POST data port
LDN=4
Environment Controller
Base1 + (0 -7)
Environment Controller
Base2 + (0 -3)
PME#
LDN=5 KBC
Base1 + Base2
KBC
LDN=8, Serial Port 3
Base + (0 -7)
UART3
LDN=9, Serial Port 4
Base + (0 -7)
UART4
LDN=A, Serial Port 5
Base + (0 -7)
UART5
LDN=B, Serial Port 6
Base + (0 -7)
UART6
LDN=C, Consumer IR
Base + (0 -7)
CIR
C
O
N
FI
D
LDN=0 FDC
www.ite.com.tw
43
IT8783F/E V0.5
IT8783E/F (For A Version)
Global Configuration Registers (LDN: All)
8.3.1
Configure Control (Index=02h)
TI
AL
8.3
This register is write only. Its values are not sticky; that is to say, a hardware reset will automatically clear
the bits, which does not require the software to clear them.
Bit
7-2
1
0
8.3.2
Description
Reserved
Returns to the “Wait for Key” state. This bit is used when the configuration sequence is
completed.
Resets all logical devices and restores configuration registers to their power-on states.
Logical Device Number (LDN, Index=07h)
8.3.3
EN
This register is read/write, which is used to select the current logical devices. By reading from or writing to
the configuration of I/O, Interrupt, DMA and other special functions, all registers of the logical devices can be
accessed. In addition, ACTIVATE command is only effective for the selected logical devices.
Chip ID Byte 1 (Index=20h, Default=87h)
This register is Chip ID Byte 1 and is read only. Bits [7:0]=87h when read.
8.3.4
Chip ID Byte 2 (Index=21h, Default=83h)
8.3.5
Configuration Select and Chip Version (Index=22h, Default=00h)
Description
Configuration Select(CS)
This bit is to determine which chip to be configured.
The chip with JP3=1 (power-on strapping value of SOUT1) will be configured and chip with JP3=0
will exit the configuration mode when there are two IT8783F/E chips in a system and this bit is
written into '1'.
Conversely, the chip with JP3=0 (power-on strapping value of SOUT1) will be configured and chip
with JP3=1 will exit the configuration mode when this bit is written into '0'.
Reserved
Version ID(VID )
N
Bit
7
FI
D
This register is Chip ID Byte 2 and is read only. Bits [7:0]= 83h when read.
O
6-4
3-0
8.3.6
C
Bit
7-6
5
Clock Selection Register (Index=23h, Default=00h)
Description
XLOCK Select(XS)
These two bits determine the XLOCK function.
00: Software XLOCK (default)
01: Reserved
10: Pin 52 (GP50)
11: Pin 9 (GP37)
Reserved
www.ite.com.tw
44
IT8783F/E V0.5
Configuration
8.3.7
Bit
7
6
5
4
3
Software Suspend and Flash I/F Control Register (Index=24h, Default=0ss0s0s0b, MB PnP)
Description
Reserved
(Must be 0)
PCIRST2/3# Selection
0: Disable PCIRST2/3# output
1: Pin 25/24
The initial value of this bit is set to “1” when JP9 pull-down at internal VCC is OK, and PCIRST#2
is output from pin 25, PCIRST#3 is output from pin 24.
Function Selection of Pin 53 (FSP53)
0: Disable PCIRST#1
1: Enable PCIRST#1
The initial value of this bit is set to “1” when JP8 pull-down at internal VCC is OK, and PCIRST#1
is output to pin 53.
LPC Memory/FWM Write to Serial Flash I/F Enable (LMWSE)
0: Disable (Default)
1: Enable
Flash I/F Address Segment 3 (FAS3)
Range FFF0_0000h-FFFD_FFFFh, FFFE_0000h-FFFE_FFFFh)
0: Disable
1: Enable
Flash I/F Address Segment 2 (FAS2)
Range (FFEF_0000h-FFEF_FFFFh, FFEE_0000h-FFEE_FFFFh)
0: Disable (Default)
1: Enable
Flash I/F Address Segment 1 (FAS1)
Range (FFFE_0000h_FFFF_FFFFh, 000E_0000h-000F_FFFFh)
0: Disable
1: Enable
Software Suspend (SS)
When bit 0 is set, the IT8783E/F enters the “Software Suspend” state. All the devices, except
KBC, remain inactive until this bit is cleared or when the wake-up event occurs. The wake-up
event occurs at any transition on signals RI1# (pin 119) and Rl2# (pin 127).
0: Normal
1: Software Suspend
N
2
TI
AL
1
0
EN
3-2
Description
Clock Source Select of Watch Dog Timer(CSSWDT)
0: Internal oscillating clock (Default)
1: External CLKIN
Delay Select of PWROK (SDP)
00: PWROK will be delayed for 300~600ms from VCC5V > 4.0V.
01: PWROK will not be delayed from VCC5V > 4.0V.
10: PWROK will be delayed for 150 ~300ms from VCC5V > 4.0V.
11: Reserved.
Reserved
CLKIN Frequency(CF)
0: 48 MHz
1: 24 MHz
FI
D
Bit
4
O
1
C
0
www.ite.com.tw
45
IT8783F/E V0.5
IT8783E/F (For A Version)
8.3.8
GPIO Set 1 Multi-function Pin Selection Register (Index=25h, Default=00h)
5
4
3
2
1
0
8.3.9
Function Selection of Pin 24 (FSP)
0: SI/PCIRST3#
If bit 6 of index 24h is “1”, pin 24 is PCIRST3# output; otherwise select SI output.
1: General Purpose I/O 17 (GP17)
Function Selection of Pin 25 (FSP)
0: SCK/PCIRST2#
If bit 6 of index 24h is “1”, pin 25 is PCIRST2# output; otherwise select SCK output.
1: General Purpose I/O 16 (GP16)
Function Selection of Pin 29 (FSP)
If bit 5 of index 24h is “1”, select SO input from this pin; otherwise select DTR6# output.
0: DTR6#
1: General Purpose I/O 15 (GP15)
Function Selection of Pin 30 (FSP)
If bit 1 of index 2Ah is “0” when bit 0 of index EFh is set to “1”, pin 30 is CE_N (Default); otherwise
select FAN_CTL3.
0: CE_N/FAN_CTL3
1: General Purpose I/O 14 (GP14)
Reserved
Function Selection of Pin 81, Pin 80 (FSP)
0: KCLK/KDAT
1: General Purpose I/O 12 (GP12)/1: General Purpose I/O 13 (GP13)
Reserved
Function Selection of Pin 83, Pin 82 (FSP)
0: MCLK/MDAT
1: General Purpose I/O 10 (GP10)/General Purpose I/O 11 (GP11)
EN
6
Description
FI
D
Bit
7
TI
AL
If the enabled bits are not set, the multi-function pins will perform the original function. Conversely, if they are
set, they will perform the GPIO function. This register can be read from any LDN, but can only be written if
LDN=07h.
GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h)
N
If the enabled bits are not set, the multi-function pins will perform the original function. Conversely, if they are
set, they will perform the GPIO function. This register can be read from any LDN, but can only be written if
LDN=07h.
O
Bit
7
C
6
5
4
Description
Function Selection of Pin 32 (FSP)
0: RESETCON#/CTS5#
If bit 5 of index 2Ah is set to “1”, RESETCON# input will be disabled.
1: General Purpose I/O 27 (GP27) if bit 5 of index 2Ah is set to 1 and bit 3 of index 2Ah is set to 0
Function Selection of Pin 33 (FSP)
0: DTR5#
1: General Purpose I/O 26 (GP26)
Function Selection of Pin 34 (FSP)
0: RTS5#
1: General Purpose I/O 25 (GP25)
Function Selection of Pin 36 (FSP)
www.ite.com.tw
46
IT8783F/E V0.5
Configuration
Bit
1
0
8.3.10
TI
AL
2
0: DSR5#
1: General Purpose I/O 24 (GP24)
Function Selection of Pin 48 (FSP)
0: SIN5# (if bit 3 of index 2Ah is 1)
1: General Purpose I/O 23 (GP23)
Function Selection of Pin 66 (FSP)
0: SOUT5 (if bit 3 of index 2Ah is 1)
1: General Purpose I/O 22 (GP22)
Function Selection of Pin 70 (FSP)
0: RI5#
1: General Purpose I/O 21 (GP21)
Function Selection of Pin 84 (FSP)
0: DCD5#
1: General Purpose I/O 20 (GP20)
GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)
EN
3
Description
If the enabled bits are not set, the multi-function pins will perform the original function. Conversely, if they are
set, they will perform the GPIO function. This register can be read from any LDN, but can only be written if
LDN=07h.
6
5
Function Selection of Pin 9 (FSP)
0: FAN_TAC2 (Fan Tachometer Input 2)
1: General Purpose I/O 37 (GP37)
Function Selection of Pin 45 (FSP)
0: KRST#
1: General Purpose I/O 36 (GP36)
Function Selection of Pin 77 (FSP)
0: SUSC#/SOUT6
If bit 3 of index 2Ch is 1, SOUT6 output is enabled; otherwise select SUSC# input.
1: General Purpose I/O 35 (GP35)
Function Selection of Pin 85 (FSP)
0: RSMRST#/RTS6#
If bit 3 of index 2C is 1, RTS6# output is enabled; otherwise select RSMRST# output.
1: General Purpose I/O 34 (GP34)
Function Selection of Pin 10 (FSP)
0: FAN_CTL2
1: General Purpose I/O 33 (GP33)
Function Selection of Pin 91 (FSP)
0: VIN7/SO
If bit 2 of index 2Ch is 1, SO input (bit 5 of index24h =0) is enabled; otherwise select VIN7 input.
1: General Purpose I/O 32 (GP32)
Function Selection of Pin 92 (FSP)
0: VIN6/CTS6#
If bit 2 of index 2Ch is 1, CTS6# input is enabled; otherwise select VIN6 input.
1: General Purpose I/O 31 (GP31)
Function Selection of Pin 93 (FSP)
0: VIN5/FAN_TAC3/SIN6
If bit 2 of index 2Ch is 1, FAN_TAC3/SIN6 input is enabled; otherwise select VIN5 input.
1: General Purpose I/O 30 (GP30)
N
4
Description
FI
D
Bit
7
3
O
2
C
1
0
www.ite.com.tw
47
IT8783F/E V0.5
IT8783E/F (For A Version)
8.3.11
GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=00h)
5
4
3
2
1
0
8.3.12
Function Selection of Pin 71 (FSP)
0: SUSB#
1: General Purpose I/O 47 (GP47)
Function Selection of Pin 72 (FSP)
0: PWRON#
1: General Purpose I/O 46 (GP46)
Function Selection of Pin 73 (FSP)
0: PME#
1: General Purpose I/O 45 (GP45)
Reserved
0: (must be 0)
1: Reserved
Function Selection of Pin 75 (FSP)
0: Main Power Switch Button Input # (PANSWH#)
1: General Purpose I/O 43 (GP43)
Function Selection of Pin 76 (FSP)
0: Power Supply On-Off Control Output (PSON# )
1: General Purpose I/O 42 (GP42)
Function Selection of Pin 78 (FSP)
0: PWROK1
1: General Purpose I/O 41 (GP41)
Function Selection of Pin 79 (FSP)
0: 3VSBSW#
1: General Purpose I/O 40 (GP40)
EN
6
Description
FI
D
Bit
7
TI
AL
If the enabled bits are not set, the multi-function pins will perform the original function. Conversely, if they are
set, they will perform the GPIO function. This register can be read from any LDN, but can only be written if
LDN=07h.
GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h)
N
If the enabled bits are not set, the multi-function pins will perform the original function. Conversely, if they are
set, they will perform the GPIO function. This register can be read from any LDN, but can only be written if
LDN=07h.
Description
Function Selection of Pin 61 (FSP)
0: RDATA#
1: General Purpose I/O 57 (GP57); FDC disabled.
Function Selection of Pin 60 (FSP)
0: WGATE#
1: General Purpose I/O 56 (GP56); FDC disabled.
Function Selection of Pin 59 (FSP)
0: HDSEL#
1: General Purpose I/O 55 (GP55); FDC disabled.
Function Selection of Pin 58 (FSP)
0: STEP#
1: General Purpose I/O 54 (GP54); FDC disabled.
O
Bit
7
C
6
5
4
www.ite.com.tw
48
IT8783F/E V0.5
Configuration
2
1
0
8.3.13
Description
Function Selection of Pin 57 (FSP)
0: DIR#
1: General Purpose I/O 53 (GP53); FDC disabled.
Function Selection of Pin 56 (FSP)
0: WDATA#
1: General Purpose I/O 52 (GP52); FDC disabled.
Function Selection of Pin 54 (FSP)
0: DRVA#
1: General Purpose I/O 51 (GP51); FDC disabled.
Function Selection of Pin 52 (FSP)
0: MTRA#
1: General Purpose I/O 50 (GP50); FDC disabled.
TI
AL
Bit
3
Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h)
6
5
N
4
3
Description
Enable 3VSBSW# (E3VSBSW)
This function is for System Suspend-to-RAM.
0: Always inactive
1: Enabled
It will be (NOT SUSB#) NAND SUSC#.s
Multi-Function Selection of Pin 53 (MSP)
0: MTRB#/PECIRQT#/PCIRST1#
When bit 5 of index 24h is set to “1”, select PCIRST1# output, and bit 6 of index 2Ch is set to “1”,
select PECIRQT# output; otherwise select MTRB#.
1: External Thermal Sensor Data/THERM_O#
When bit 6-4 of EC index 0Ah is not equal to “000b”, the external thermal sensor host is enabled,
and pin 53 becomes external thermal function.
Extended Multi-Function Selection of Pin 32 (EMSP)
0: RESETCON# enabled
1: RESETCON# disabled
Reserved
Function Selection of Pin 66 (FSP)
0: UART 5 pin selection disabled
1: Pin 66 determined by bit 2 of GPIO Set 2 Multi-function Selection Register (Index 26h) GPIO
or SOUT5
Function Selection of Pin 23 (FSP)
0: UART 4 pin selection disabled
1: DTR4#
SCR Reserved
0: UART or GPIO (must be 0)
1: Reserved
3VSBSW# Timing Control (3VSBSWTC)
0: 3VSBSW# goes high leading PWROK for about 1ms.
1: 3VSBSW# goes high leading PWROK for about 120~160ms.
Note: When E3VSBSW (bit7 of index 2Ah) is set to “1”, SDP(bit 3-2 of index 23h) are not
allowed to be set to “01”.
FI
D
Bit
7
EN
This register can be read from any LDN, but can only be written if LDN=07h.
O
2
1
C
0
www.ite.com.tw
49
IT8783F/E V0.5
IT8783E/F (For A Version)
8.3.14
Logical Block Lock Register (Index=2Bh, Default=00h)
5
4
3
2
1
C
O
N
0
Software Lock Enable(SLE)
Once this bit is set to 1 by software, it only can be cleared by hardware reset.
0: The configuration lock is controlled by XLOCK#. (Default)
1: The logic blocks of the configuration register are selected by bit 6-0 and this register is
read-only.
GPIO Select (GPIOS)
0: GPIO configuration registers are programmable.
1: GPIO configuration registers are read-only if LOCK is enabled.
KBC(Keyboard) and KBC(Mouse) Select (KMS)
0: KBC(Keyboard) and KBC(Mouse) configuration registers are programmable.
1: KBC(Keyboard) and KBC(Mouse) configuration registers are read-only if LOCK is enabled.
EC Select (ECS)
0: EC configuration registers are programmable.
1: EC configuration registers are read-only if LOCK is enabled.
Parallel Port Select (PPS)
0: Parallel Port configuration registers are programmable.
1: Parallel Port configuration registers are read-only if LOCK is enabled.
Serial Port 2, 4, 6 Select (SP2S)
0: Serial Port 2, 4, 6 configuration registers are programmable.
1: Serial Port 2, 4, 6 configuration registers are read-only if LOCK is enabled.
Serial Port 1, 3, 5 Select (SP1S)
0: Serial Port 1, 3, 5 configuration registers are programmable.
1: Serial Port 1, 3, 5 configuration registers are read-only if LOCK is enabled.
FDC Select (FDCS)
The lock function will not affect bit 0 of FDC special configuration register (software write protect).
0: FDC configuration registers are programmable.
1: FDC configuration registers are read-only (except Software Write Protect bit) if LOCK is
enabled.
EN
6
Description
FI
D
Bit
7
TI
AL
When the lock function is enabled (bit7=1 or XLOCK# is low), configuration registers of the selected logical
block and clock selection register (index = 23h), and this register will be read-only.
www.ite.com.tw
50
IT8783F/E V0.5
Configuration
8.3.15
Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=03h)
This register can be read from any LDN, but can only be written if LDN=07h.
3
2
1
0
8.3.16
GPIO Set 6 Enable Register (Index=2Dh, Default=00h)
Description
0: PD7
1: General Purpose I/O 67 (GP67)
0: PD6
1: General Purpose I/O 66 (GP66)
0: PD5
1: General Purpose I/O 65 (GP65)
0: PD4
1: General Purpose I/O 64 (GP64)
0: PD3
1: General Purpose I/O 63 (GP63)
0: PD2
1: General Purpose I/O 62 (GP62)
0: PD1
1: General Purpose I/O 61 (GP61)
0: PD0
1: General Purpose I/O 60 (GP60)
N
Bit
7
TI
AL
5
4
EN
6
Description
Enable SMB_D/C Switching On (ESMBSO)
1: Disable
0: Enable SMB_ON (SMBD_M switch into SMBD_R, and SMBC_M switch into SMBC_R) when
Parallel PORT is disabled.
Enable PECI Request (EPECIRQT)
0: Disable
1: Enable
Reserved
Extended Multi-Function Selection of Pin 12 (EMSP)
0: Reserved
1: Enable RI3# input
Extended Multi-Function Selection of Pin 29, 77, 85 (EMSP)
This bit enables DTR6, SOUT6 RTS6 output of UART 6.
0: Disable
1: Enable
Enable UART 6 Input of Pin 87, 92, 93, 94, 95 (EUI)
0: Disable
1: Enable RI6#, CTS6#, SIN6, DCD6#, DSR6# input to UART 6 block.
Enable VIN7 Internal Voltage Divider (EVIVD)
This bit enables and switches VIN7 (pin 91) to the internal voltage divider for VCCH5V.
0: Disable
1: Enable
Enable ATXPG, VIN3 Internal Voltage Divider (EAVIVD)
This bit enables ATXPG (pin 95) and switches the VIN3 function to the internal voltage divider for
VCC5V
0: Disable
1: Enable
FI
D
Bit
7
6
O
5
4
C
3
2
1
0
www.ite.com.tw
51
IT8783F/E V0.5
IT8783E/F (For A Version)
8.3.17
Test 1 Register (Index=2Eh, Default=00h)
8.3.18
TI
AL
This register cannot be configured because it is a test register and reserved for ITE only.
Test 2 Register (Index=2Fh, Default=00h)
C
O
N
FI
D
EN
This register cannot be configured because it is a test register and reserved for ITE only.
www.ite.com.tw
52
IT8783F/E V0.5
Configuration
FDC Configuration Registers (LDN=00h)
8.4.2
Bit
7-4
3-0
8.4.3
Bit
7-3
2-0
8.4.4
Bit
7-4
3-0
Description
Reserved
FDC Enable(FDCE)
1: Enable
0: Disable
FDC Base Address MSB Register (Index=60h, Default=03h)
Description
Base Address [15:12](BA)
Read only, with “0h” for Base Address [15:12].
Base Address [11:8] (BA)
Mapped as Base Address [11:8].
FDC Base Address LSB Register (Index=61h, Default=F0h)
Description
Base Address [7:3](BA)
Read/write, mapped as Base Address [7:3].
Reserved
Read only as “000b”.
FDC Interrupt Level Select (Index=70h, Default=06h)
Description
Reserved
With default “0h”.
Select Interrupt Level for FDC(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
FDC DMA Channel Select (Index=74h, Default=02h)
N
8.4.5
Description
Reserved
With default “00h”
Select DMA Channel for FDC (SDMA)
Please refer to Table 8-17 DMA Channel Mapping Table on page 79.
O
Bit
7-3
TI
AL
Bit
7-1
0
FDC Activate (Index=30h, Default=00h)
EN
8.4.1
FI
D
8.4
2-0
C
8.4.6
Bit
7-5
4
FDC Special Configuration Register 1 (Index=F0h, Default=00h)
Description
Reserved
With default “00h”.
FDD I/F Input Pin Internal Pull-up Control (FIPU)
0: Disable
1: Enable
www.ite.com.tw
53
IT8783F/E V0.5
IT8783E/F (For A Version)
1
0
8.4.7
Bit
7-4
3-2
FDC Special Configuration Register 2 (Index=F1h, Default=00h)
Description
Reserved
With default “00h”.
FDD B Data Rate Table Select (FBDRTS)
(DRT1-0)
FDD A Data Rate Table Select (FADRTS)
(DRT1-0)
C
O
N
FI
D
1-0
TI
AL
2
Description
IRQ Type (IT)
1: IRQ sharing
0: Normal IRQ
Swap Floppy Drive A, B Enable(SFDE)
1: Swap Floppy Drive A, B
0: Normal
Floppy Operation Mode(FOM)
1: 3-mode
0: AT-mode
Software Write Protect Enable(SWPE)
1: Software Write Protect
0: Normal
EN
Bit
3
www.ite.com.tw
54
IT8783F/E V0.5
Configuration
Serial Port 1 Configuration Registers (LDN=01h)
8.5.2
Bit
7-4
3-0
8.5.3
Bit
7-3
2-0
8.5.4
Bit
7-4
Description
Reserved
Serial Port 1 Enable (SP1E)
1: Enable
0: Disable
Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)
Description
Base Address[7:3] (BA)
Read/write, mapped as Base Address[7:3]
Reserved
Read only as “000b”
Serial Port 1 Interrupt Level Select (Index=70h, Default=04h)
Description
Reserved
With default “0h”.
Select Interrupt Level for Serial Port 1(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
C
O
N
3-0
TI
AL
Bit
7-1
0
Serial Port 1 Activate (Index=30h, Default=00h)
EN
8.5.1
FI
D
8.5
www.ite.com.tw
55
IT8783F/E V0.5
IT8783E/F (For A Version)
Bit
7
6-4
3
2-1
Description
RS485 Direction Control Enable(RS485DCE)
0: Disable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
1: Enable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
Reserved
Reserved
With default “0”
Clock Source(CS)
00: 24 MHz/13 (Standard)
01: 24 MHz/12
10: 24 MHz
11: 24 MHz/1.625
IRQ Type (IT)
1: IRQ sharing
0: Normal
C
O
N
FI
D
EN
0
Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h)
TI
AL
8.5.5
www.ite.com.tw
56
IT8783F/E V0.5
Configuration
Serial Port 2 Configuration Registers (LDN=02h)
8.6.2
Bit
7-4
3-0
8.6.3
Bit
7-3
2-0
8.6.4
Bit
7-4
Description
Reserved
Serial Port 2 Enable(SP2E)
1: Enable
0: Disable
Serial Port 2 Base Address MSB Register (Index=60h, Default=02h)
Description
Base Address[15:12] (BA)
Read only with “0h” for Base Address [15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address [11:8]
Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)
Description
Base Address[7:3] (BA)
Read/write, mapped as Base Address [7:3]
Reserved
Read only as “000b”
Serial Port 2 Interrupt Level Select (Index=70h, Default=03h)
Description
Reserved
With default “0h”
Select Interrupt Level for Serial Port 2(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
C
O
N
3-0
TI
AL
Bit
7-1
0
Serial Port 2 Activate (Index=30h, Default=00h)
EN
8.6.1
FI
D
8.6
www.ite.com.tw
57
IT8783F/E V0.5
IT8783E/F (For A Version)
Bit
7
6-4
3
2-1
Description
RS485 Direction Control Enable(RS485DCE)
0: Disable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
1: Enable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
Reserved
Reserved
With default “0”
Clock Source (CS)
00: 24 MHz/13 (Standard)
01: 24 MHz/12
10: 24 MHz
11: 24 MHz/1.625
IRQ Type(IT)
1: IRQ sharing
0: Normal
C
O
N
FI
D
EN
0
Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)
TI
AL
8.6.5
www.ite.com.tw
58
IT8783F/E V0.5
Configuration
Parallel Port Configuration Registers (LDN=03h)
Bit
7-1
0
8.7.2
Bit
7-4
3-0
8.7.3
Parallel Port Activate (Index=30h, Default=00h)
TI
AL
8.7.1
Description
Reserved
Parallel Port Enable (PPE)
1: Enable
0: Disable
Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
EN
8.7
Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)
If bit 2 is set to “1”, the EPP mode is disabled automatically.
1-0
8.7.4
Bit
7-4
Base Address[7:2] (BA)
Read/write, mapped as Base Address[7:2]
Reserved
Read only as “00b”
Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
N
3-0
Description
FI
D
Bit
7-2
8.7.5
Description
O
Bit
7-2
Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h)
C
1-0
Base Address[7:2] (BA)
Read/write, mapped as Base Address[7:2]
Reserved
Read only as “00b”
www.ite.com.tw
59
IT8783F/E V0.5
IT8783E/F (For A Version)
8.7.7
Bit
7-3
2-0
8.7.8
Bit
7-4
3
2
Parallel Port DMA Channel Select (Index=74h, Default=03h)
Description
Reserved
With default “00h”
Select DMA Channel for Parallel Port(SDMA)
Please refer to Table 8-17 DMA Channel Mapping Table on page 79.
Parallel Port Special Configuration Register (Index=F0h, Default=03h)
Description
Reserved
POST Data Port Enable (PDPE)
1: Disable
0: Enable
IRQ Type (IT)
1: IRQ sharing
0: Normal
Parallel Port Mode (PPM)
00 : Standard Parallel Port mode (SPP)
01 : EPP mode
10 : ECP mode
11 : EPP mode & ECP mode
These bits are independent.
If bit 1 is set, ECP mode is enabled.
If bit 0 is set, EPP mode is enabled except when Parallel Port Primary Base Address LSB
Register bit 2 is set to “1” in accordance with the EPP specification.
C
O
N
1-0
TI
AL
3-0
Description
Reserved
With default “0h”
Select Interrupt Level for Parallel Port (SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
EN
Bit
7-4
Parallel Port Interrupt Level Select (Index =70h, Default=07h)
FI
D
8.7.6
www.ite.com.tw
60
IT8783F/E V0.5
Configuration
Environment Controller Configuration Registers (LDN=04h)
8.8.2
Bit
7-4
3-0
8.8.3
Bit
7-3
2-0
8.8.4
Bit
7-4
Description
Reserved
Environment Controller Enable (ECE)
1: Enable
0: Disable
This is a read/write register.
Environment Controller Base Address MSB Register (Index=60h, Default=02h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
Environment Controller Base Address LSB Register (Index=61h, Default=90h)
Description
Base Address[7:3] (BA)
Read/write, mapped as Base Address[7:3]
Reserved
Read only as “000b”
PME Direct Access Base Address MSB Register (Index=62h, Default=02h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
N
3-0
8.8.5
PME Direct Access Base Address LSB Register (Index=63h, Default=30h)
Description
Base Address[7:3] (BA)
Read/write, mapped as Base Address[7:3]
Reserved
Read only as “000b”
O
Bit
7-3
TI
AL
Bit
7-1
0
Environment Controller Activate Register (Index=30h, Default=00h)
EN
8.8.1
FI
D
8.8
2-0
C
8.8.6
Environment Controller Interrupt Level Select (Index=70h, Default=09h)
Bit
7-4
Description
Reserved
With default “0h”
3-0
Select Interrupt Level for Environment Controller (SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
www.ite.com.tw
61
IT8783F/E V0.5
IT8783E/F (For A Version)
4
3
2-1
0
8.8.8
Bit
7
6
5
4
3
APC/PME Status Register (PSR) (Index=F1h, Default=00h)
Description
VCC Power On(VCCPO)
It is set to 1 when VCC is on at the previous AC power failure and 0 when VCC is off.
Reserved
Reserved
PS2 Mouse Event Detect(PMED)
0: No event detected
1: Event detected
Keyboard Event Detect
0: No event detected
1: Event detected
Reserved
With default “00”
CIR Event Detect
0: No event detected
1: Event detected
N
2-1
TI
AL
6
5
Description
VCCH Power Off(VPO)
This bit is set to “1” when VCCH is off. Write 1 to clear it. This bit will become ineffective if 0 is
written to it.
Reserved
Reserved
With default “0h”
PS2 Mouse Event Enable(PMEE)
1: Enable
0: Disable
Keyboard Event Enable(KEE)
1: Enable
0: Disable
Reserved
With default “00”
CIR Event Enable (CIREE)
1: Enable
0: Disable
EN
Bit
7
APC/PME Event Enable Register (PER) (Index=F0h, Default=00h)
FI
D
8.8.7
O
0
8.8.9
Description
PER/PSR Normal Run Access Enable(PPNRAE)
0: Enable
1: Disable
6
PME# Output Control(POC)
0: Enable
1: Disable
5
Previous VCC State(PVS)
This bit is automatically restored to the previous VCC state before the power failure occurs.
www.ite.com.tw
IT8783F/E V0.5
62
C
Bit
7
APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)
Configuration
Bit
0
8.8.10
Bit
7-6
5-1
0
8.8.11
Environment Controller Special Configuration Register (Index=F3h, Default=00h)
Description
Scan Frequency of H/W Monitor(SFHM)
00: 1Hz
01: 2Hz
10: 4Hz
11: 8Hz
Reserved
IRQ Type(IT)
1: IRQ sharing
0: Normal
APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)
Description
Disable KCLK/KDAT and MCLK/MDAT Auto-Swap(DKMA)
0: Enable
1: Disable
Reserved
PSON# State at VCCH Switched from off to on(PSVS)
0: High-Z
The default is power-off.
1: Inverting of PSIN
Mask PANSWH# Power-on Event(MPPOE)
1: Enable
0: Disable
Key Number of Keyboard Power-up Event(KNKPUE)
00: 5 key string mode, 3 keys simultaneous mode
01: 4 key string mode, 2 keys simultaneous mode
10: 3 key string mode, 1 key simultaneous mode
11: 2 key string mode, Reserved (Not Valid for Simultaneous mode)
Keyboard Power-up Event Mode Selection(KPEMS)
00: KCLK falling edge
N
Bit
7
TI
AL
1
EN
2
1: Enable
0: Disable
Reserved
Keyboard Event Selection(KES)
This bit is for Keyboard event mode selection when VCC is on (KEMSVO).
1: Determined by PCR 2
0: Pulse falling edge on KCLK
Mouse Event at VCC Off(MEVF)
1: Click key twice sequentially
0: Pulse falling edge on MCLK
Mouse Event at VCC On(MEVO)
1: Click key twice sequentially
0: Pulse falling edge on MCLK
CIRRX Pin Selection(CIRRXPS)
1: Pin 63 selected
0: Pin 85 selected
FI
D
4
3
Description
O
6
5
4
C
3-2
1-0
www.ite.com.tw
63
IT8783F/E V0.5
IT8783E/F (For A Version)
C
O
N
FI
D
EN
TI
AL
01: Key string mode
10: Simultaneous key stroke mode
11: Reserved
www.ite.com.tw
64
IT8783F/E V0.5
Configuration
5-0
8.8.13
Bit
7-0
8.8.14
Reserved
Must be “00”.
CIR Key Code Index[5:0](CKCI)
Indicate which identification key code or CIR code register to be read/written via 0xF6.
APC/PME Special Code Data Register (Index=F6h)
Description
CIR Key Code Data[7:0](CKCD)
There are 5 bytes for the key string mode, 3 bytes for stroke key at the same time mode and CIR
event codes.
APC/PME Control (PCR 7) Data Register (Index=F7h)
Description
PCR 7 DATA[7:0] (PCR7DD)
Bit 7-0 are supplied by VBAT, and can be read/written directly.
C
O
N
FI
D
Bit
7-0
Description
TI
AL
Bit
7-6
APC/PME Special Code Index Register (Index=F5h)
EN
8.8.12
www.ite.com.tw
65
IT8783F/E V0.5
IT8783E/F (For A Version)
KBC(Keyboard) Configuration Registers (LDN=05h)
8.9.2
Bit
7-4
3-0
8.9.3
Bit
7-0
8.9.4
Bit
7-4
3-0
Description
Reserved
KBC(Keyboard) Enable(KBCE)
1: Enable
0: Disable
KBC (Keyboard) Data Base Address MSB Register (Index=60h, Default=00h)
Description
Base Address[15:12](BA)
Read only as “0h” for Base Address [15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address [11:8]
KBC (Keyboard) Data Base Address LSB Register (Index=61h, Default=60h)
Description
Base Address[7:0] (BA)
Read/write, mapped as Base Address[7:0]
KBC (Keyboard) Command Base Address MSB Register (Index=62h, Default=00h)
Description
Base Address[15:12] (BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
KBC (Keyboard) Command Base Address LSB Register (Index=63h, Default=64h)
N
8.9.5
Bit
7-0
C
Bit
7-4
3-0
Description
Base Address[7:0] (BA)
Read/write, mapped as Base Address[7:0]
KBC (Keyboard) Interrupt Level Select (Index=70h, Default=01h)
O
8.9.6
TI
AL
Bit
7-1
0
KBC(Keyboard) Activate (Index=30h, Default=01h)
EN
8.9.1
FI
D
8.9
Description
Reserved
With default “0h”
Select Interrupt Level for KBC(Keyboard)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
www.ite.com.tw
66
IT8783F/E V0.5
Configuration
8.9.7
KBC(Keyboard) Interrupt Type (Index=71h, Default=02h)
8.9.8
Bit
7-5
4
3
2
1
Description
Reserved
IRQ Type(IT)
1: IRQ sharing
0: Normal
KBC Clock(KC)
1: 8 MHz
0: 12 MHz
KBC Key Lock(KKL)
1: Enable
0: Disable
Interrupt Type Change Enable(ITCE)
1: The interrupt type of KBC(Keyboard) can be changed.
0: The interrupt type of KBC(Keyboard) is fixed.
Reserved
C
O
N
0
KBC(Keyboard) Special Configuration Register (Index=F0h, Default=08h)
EN
0
Description
Reserved
Interrupt Level(IL)
1: High level
0: Low level
Interrupt Type(IT)
1: Level type
0: Edge type
FI
D
Bit
7-2
1
TI
AL
This register indicates the interrupt type set for KBC(Keyboard) and is read only as “02h” when bit 0 of the
KBC(Keyboard) Special Configuration Register is cleared. When bit 0 is set, the interrupt type can be
selected as level or edge trigger.
www.ite.com.tw
67
IT8783F/E V0.5
IT8783E/F (For A Version)
KBC(Mouse) Configuration Registers (LDN=06h)
Bit
7-1
0
8.10.2
Bit
7-4
3-0
8.10.3
KBC(Mouse) Activate (Index=30h, Default=00h)
TI
AL
8.10.1
Description
Reserved
KBC(Mouse) Enable(KE)
1: Enable
0: Disable
KBC(Mouse) Interrupt Level Select (Index=70h, Default=0Ch)
Description
Reserved
With default “0h”
Select Interrupt Level for KBC(Mouse)(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
EN
8.10
KBC(Mouse) Interrupt Type (Index=71h, Default=02h)
This register indicates the interrupt type used for KBC(Mouse) and is read only as “02h” when bit 0 of the
KBC(Mouse) Special Configuration Register is cleared. When bit 0 is set, the interrupt type can be selected
as level or edge trigger.
0
Reserved
Interrupt Level(IL)
1: High level
0: Low level
Interrupt Type(IT)
1: Level type
0: Edge type
KBC (Mouse) Special Configuration Register (Index=F0h, Default=00h)
N
8.10.4
Description
FI
D
Bit
7-2
1
Bit
7-2
Reserved
With default “00h”
IRQ Type(IT)
1: IRQ sharing
0: Normal
Interrupt Type Change Enable(ITCE)
1: The interrupt type of KBC(Mouse) can be changed.
0: The interrupt type of KBC(Mouse) is fixed.
O
1
Description
C
0
www.ite.com.tw
68
IT8783F/E V0.5
Configuration
3-0
8.11.2
Bit
7-2
1-0
8.11.3
Bit
7-4
3-0
8.11.4
Bit
7-0
8.11.5
Base Address [15:12] (BA)
Read only as “0h” for Base Address [15:12]
Base Address [11:8] (BA)
Read/write, mapped as Base Address [11:8]
SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)
Description
Base Address [7:2] (BA)
Read/write, mapped as Base Address [7:2]
Read only as “00b”
Simple I/O Base Address MSB Register (Index=62h, Default=00h)
Description
Base Address [15:12] (BA)
Read only as “0h” for Base Address [15:12]
Base Address [11:8] (BA)
Read/write, mapped as Base Address [11:8]
Simple I/O Base Address LSB Register (Index=63h, Default=00h)
Description
Base Address [7:0] (BA)
Read/write, mapped as Base Address[7:0]
Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h)
Description
Base Address [15:12] (BA)
Read only as “0h” for Base Address [15:12]
Base Address [11:8] (BA)
Read/write, mapped as Base Address [11:8]
N
Bit
7-4
Description
TI
AL
Bit
7-4
SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)
EN
8.11.1
GPIO Configuration Registers (LDN=07h)
FI
D
8.11
3-0
Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h)
O
8.11.6
Bit
7-3
C
2-0
Description
Base Address [7:3] (BA)
Read/write, mapped as Base Address [7:3]
Read only as “000b”
www.ite.com.tw
69
IT8783F/E V0.5
IT8783E/F (For A Version)
Bit
7
6
5
4
3-2
1
0
8.11.9
Bit
7
Watch Dog Timer 1, 2, 3 Control Register (Index=71h, 81h, 91h Default=00h)
Description
Reserved
WDT Reset upon Mouse Interrupt(WRKMI)
0: Disable
1: Enable
WDT Reset upon Keyboard Interrupt(WRKBI)
0: Disable
1: Enable
Reserved
Reserved
Force Time-out(FTO)
This bit is self-cleared.
WDT Status(WS)
1: WDT value is equal to 0.
0: WDT value is not equal to 0.
Watch Dog Timer 1, 2, 3 Configuration Register (Index=72h, 82h, 92h Default=001s0000b)
Description
WDT Time-out Value Select 1 (WTVS)
1: Second
0: Minute
WDT Output through KRST (Pulse) Enable(WOKE)
1: Enable
0: Disable
WDT Time-out Value Extra Select(WTVES)
1: 64ms x WDT Timer-out value (default = 4s)
0: Determined by WDT Time-out Value Select 1 (bit 7 of this register)
WDT Output through PWROK (Pulse) Enable(WOPE)
1: Enable
0: Disable
During LRESET#, this bit is selected by JP7 power-on strapping option.
Select Interrupt Level for WDT(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
N
6
TI
AL
8.11.8
Description
Reserved
Select Interrupt Level for Panel Button De-bounce(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
EN
Bit
7-4
3-0
Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h)
FI
D
8.11.7
5
O
4
C
3-0
8.11.10
Bit
7-0
Watch Dog Timer 1, 2, 3 Time-Out Value (LSB) Register (Index=73h, 83h, 93h, Default=38h)
Description
WDT Time-out Value 7-0(WTV)
www.ite.com.tw
70
IT8783F/E V0.5
Configuration
Bit
7-0
8.11.12
Watch Dog Timer 1, 2, 3 Time-Out Value (MSB) Register (Index=74h, 84h, 94h Default=00h)
Description
WDT Time-out Value 15-8(WTV)
TI
AL
8.11.11
GPIO Pin Set 1, 2, 3, 4, and 5 Polarity Registers (Index=B0h, B1h, B2h, B3h, and B4h ,
Default=00h)
These registers are used to program the GPIO pin type as polarity inverting or non-inverting.
8.11.13
Description
GPIO Polarity Select( GPIOPS)
1: Inverting
0: Non-inverting
GPIO Pin Set 1, 2, 3, 4, and 5 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh,
BBh, and BCh, Default=00h)
EN
Bit
7-0
These registers are to enable the GPIO pin internal pull-up.
8.11.14
Description
GPIO Pin Internal Pull-up(GPIOPIP)
1: Enable
0: Disable
Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h, and C4h,
Default=01h, 00h, 00h, 40h, and 00h)
FI
D
Bit
7-0
These registers are to select the function as the Simple I/O function or the Alternate function.
Bit
7-0
Simple I/O Set 1, 2, 3, 4, 5, and 6 Output Enable Registers (Index=C8h, C9h, CAh, CBh, CCh,
and CDh Default=01h, 00h, 00h, 40h, 00h, and 00h)
N
8.11.15
Description
1: Simple I/O function
0: Alternate function
These registers are to determine the direction of the Simple I/O.
Description
0: Input mode
1: Output mode
GP30(P93), GP31(P92), GP32(P91) are GPI only
C
O
Bit
7-0
www.ite.com.tw
71
IT8783F/E V0.5
IT8783E/F (For A Version)
8.11.17
Bit
7-6
5-0
8.11.18
Bit
7
6
5-0
8.11.19
Bit
7-4
Panel Button De-bounce 1 Input Pin Mapping Register (Index=E1h, Default=00h)
Description
Reserved
Input Pin Location(IPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h)
Description
Reserved
IRQ Enable(IE)
1: Enable
0: Disable
Input Pin Location(IPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
IRQ External Routing 1-0 Interrupt Level Selection Registers (Index=E4h, Default=00h)
Description
Routing 1 Interrupt Level Select(R1ILS)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
Routing 0 Interrupt Level Select(R0ILS)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
N
3-0
TI
AL
5-0
Description
Reserved
IRQ Enable(IRQE)
1: Enable
0: Disable
Input Pin Location(IPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
EN
Bit
7
6
Panel Button De-bounce 0 Input Pin Mapping Register (Index=E0h, Default=00h)
FI
D
8.11.16
8.11.20
Description
C
O
Bit
7-2
1-0
SPI Function Pin Selection Register (Index=EFh, Default=00001s0)
Reserved
SPI Chip-Sel Select(SPICSS)
Bit 1 and bit 0 need to be kept at the same polarity.
11: Pin 30 is CE_N output and pin 25 is SCK output (Default).
00: Reserved
www.ite.com.tw
72
IT8783F/E V0.5
Configuration
8.11.22
Bit
7
6
SMI# Control Register 2 (Index=F1h, Default=00h)
Description
Reserved
SMI Trigger Type(STT)
0: Edge trigger
1: Level trigger
Enable Generation of SMI# due to Serial Port 6, 5’s IRQ (EN_S6,5IRQ)
Reserved
Enable Generation of SMI# due to WDT’s IRQ (EN_WDT)
Enable Generation of SMI# due to Serial Port 4’s IRQ (EN_S4IRQ)
Enable Generation of SMI# due to PBD’s IRQ (EN_PBD)
C
O
N
FI
D
5-4
3
2
1
0
Description
Enable Generation of SMI# due to Serial Port 3’s IRQ (EN_S3IRQ)
Enable Generation of SMI# due to KBC(Mouse)’s IRQ (EN_MIRQ)
Enable Generation of SMI# due to KBC(Keyboard)’s IRQ (EN_KIRQ)
Enable Generation of SMI# due to Environment Controller’s IRQ (EN_ECIRQ)
Enable Generation of SMI# due to Parallel Port’s IRQ (EN_PIRQ)
Enable Generation of SMI# due to Serial Port 2’s IRQ (EN_S2IRQ)
Enable Generation of SMI# due to Serial Port 1’s IRQ (EN_S1IRQ)
Enable Generation of SMI# due to FDC’s IRQ (EN_FIRQ)
TI
AL
Bit
7
6
5
4
3
2
1
0
SMI# Control Register 1 (Index=F0h, Default=00h)
EN
8.11.21
www.ite.com.tw
73
IT8783F/E V0.5
IT8783E/F (For A Version)
8.11.23
SMI# Status Register 1 (Index=F2h, Default=00h)
5
4
3
2
1
0
8.11.24
EN
6
Description
Serial Port 3’s IRQ(SP3I)
0: None detected
1: Detected
KBC(PS/2 Mouse)’s IRQ(KMI)
0: None detected
1: Detected
KBC(Keyboard)’s IRQ(KBI)
0: None detected
1: Detected
Environment Controller’s IRQ(ECI)
0: None detected
1: Detected
Parallel Port’s IRQ(PPI)
0: None detected
1: Detected
Serial Port 2’s IRQ(SP2I)
0: None detected
1: Detected
Serial Port 1’s IRQ(SP1I)
0: None detected
1: Detected
FDC’s IRQ(FI)
0: None detected
1: Detected
FI
D
Bit
7
TI
AL
This register is used to read the status of SMI# input.
SMI# Status Register 2 (Index=F3h, Default=00h)
This register is used to read the status of SMI# input.
Description
Panel Button De-bounce Status 1-0(PBDS)
Writing 1 will reset the status
0: None detected
1: Detected
Serial Port 6,5’s IRQ(SP65I)
0: None detected
1: Detected
Reserved
WDT’s IRQ(WI)
0: None detected
1: Detected
Serial Port 4’s IRQ(SP4I)
0: None detected
1: Detected
PBD’s IRQ(PBDI)
0: None detected
1: Detected
N
Bit
7-6
O
5-4
C
3
2
1
0
www.ite.com.tw
74
IT8783F/E V0.5
Configuration
8.11.26
Bit
7-6
5-0
8.11.27
Bit
7-6
5-0
8.11.28
Bit
7-6
5-0
8.11.29
Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h)
Description
Reserved
Thermal Output Pin Location(TOPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)
Description
Reserved
Alert Beep Pin Location(ABPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h)
Description
Reserved
Keyboard Lock Pin Location(KLPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h)
Description
Reserved
GP LED Blinking 1 Location(GLB1L)
Please refer to Table 8-18 Location Mapping Table on page 80.
C
O
N
Bit
7-6
5-0
Reserved
SMI Normal Access Enable(SNAE)
1: Enable (may directly access base_address + F0h ~ F3h)
0: Disable
SMI# Pin Location(SPL)
Please refer to Table 8-18 Location Mapping Table on page 80.
TI
AL
5-0
Description
EN
Bit
7
6
SMI# Pin Mapping Register (Index=F4h, Default=00h)
FI
D
8.11.25
www.ite.com.tw
75
IT8783F/E V0.5
IT8783E/F (For A Version)
0
8.11.31
Bit
7-6
5-0
8.11.32
Bit
7-4
3
GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h)
Description
Reserved
GP LED Blinking 2 Location(GLB2L)
Please refer to Table 8-18 Location Mapping Table on page 80.
GP LED Blinking 2 Control Register (Index=FBh, Default=00h)
Description
Reserved
GP LED Blinking 2 Short Low Pulse Enable(GLB2SLPE)
1: Enable
0: Disable
GP LED 2 Frequency Control (GL2FC)
00: 4 Hz
01: 1 Hz
10: 1/4 Hz
11: 1/8 Hz
GP LED Blinking 2 Output Low Enable(GLB2OLE)
1: Enable
0: Disable
N
2-1
TI
AL
2-1
Description
Reserved
GP LED Blinking 1 Short Low Pulse Enable(GLB1SLPE)
1: Enable
0: Disable
GP LED 1 Frequency Control(GL1FC)
00: 4 Hz
01: 1 Hz
10: 1/4 Hz
11: 1/8 Hz
GP LED Blinking 1 Output Low Enable(GLB1OLE)
1: Enable
0: Disable
EN
Bit
7-4
3
GP LED Blinking 1 Control Register (Index=F9h, Default=00h)
FI
D
8.11.30
C
O
0
www.ite.com.tw
76
IT8783F/E V0.5
Configuration
8.12.2
Bit
7-4
3-0
8.12.3
Bit
7-3
2-0
8.12.4
Bit
7-4
3-0
Reserved
Serial Port 3, 4, 5, 6 Enable(SPE)
1: Enable
0: Disable
Serial Port 3, 4, 5, 6 Base Address MSB Register (Index=60h, Default= 03h, 02h, 03h, 02h)
Description
Base Address[15:12](BA)
Read only as “0h” for Base Address[15:12]
Base Address[11:8] (BA)
Read/write, mapped as Base Address[11:8]
Serial Port 3, 4, 5, 6 Base Address LSB Register (Index=61h, Default= F8h)
Description
Base Address[7:3] (BA)
Read/write, mapped as Base Address[7:3]
Reserved
Read only as “000b”
Serial Port 3, 4, 5, 6 Interrupt Level Select Register (Index=70h, Default= 04h, 03h, 04h, 03h)
Description
Reserved
With default “0h”
Select Interrupt Level for Serial Port 3(SIL)
Please refer to Table 8-16 Interrupt Level Mapping Table on page 79.
Serial Port 3, 4, 5, 6 Special Configuration Register 1 (Index=F0h, Default=00h)
N
8.12.5
Description
TI
AL
Bit
7-1
0
Serial Port 3, 4, 5, 6 Activate (Index=30h, Default=00h)
EN
8.12.1
Serial Port 3, 4, 5, 6 Configuration Registers (LDN=08h, 09h, 0Ah, 0Bh)
FI
D
8.12
Description
RS485 Direction Control Enable(RS485DCE)
0: Disable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
1: Enable RTSN asserted for RS485 automatic direction control when transmitting data to or
receiving data from RS485 transceiver.
Note: Function supported by Serial Port 1, 2, 3, 4 only
6-4
Serial Port 3, 4, 5, 6 Mode(SPM) Note3
000: Standard (Default)
001: IrDA 1.0 (HP SIR)
010 : ASKIR
100 : Reserved
else : Reserved
Note: Except the standard mode, COM1 and COM2 cannot be selected in the same mode.
3
Reserved
With default “0”
www.ite.com.tw
IT8783F/E V0.5
77
C
O
Bit
7
IT8783E/F (For A Version)
C
O
N
FI
D
EN
0
Description
Clock Source(CS)
00: 24 MHz/13 (Standard)
01: 24 MHz/12
10: 24 MHz
11: 24 MHz/1.625
IRQ Type(IT)
1: IRQ sharing
0: Normal
TI
AL
Bit
2-1
www.ite.com.tw
78
IT8783F/E V0.5
Configuration
8.13.2
Bit
7-4
3-0
8.13.3
Bit
7-3
2-0
8.13.4
Bit
7-4
3-0
8.13.5
Reserved
Consumer IR Enable
1: Enable
0: Disable
Consumer IR Base Address MSB Register (Index=60h, Default=03h)
Description
Read only with “0h” for Base Address[15:12]
Read/write, mapped as Base Address[11:8]
Consumer IR Base Address LSB Register (Index=61h, Default=10h)
Description
Read/write, mapped as Base Address[7:3]
Read only as “000b”
Consumer IR Interrupt Level Select (Index=70h, Default=0Bh)
Description
Reserved with default “0h”
Select the interrupt level Note1 for Consumer IR
Consumer IR Special Configuration Register (Index=F0h, Default=06h)
Description
Reserved with default “00h”
1: IRQ sharing
0: Normal
C
O
N
Bit
7-1
0
Description
TI
AL
Bit
7-1
0
Consumer IR Activate (Index=30h, Default=00h)
EN
8.13.1
Consumer IR Configuration Registers (LDN=0Ch)
FI
D
8.13
www.ite.com.tw
Table 8-16 Interrupt Level Mapping Table
Value
Fh-Dh
Ch
3h
2h
1h
0h
Description
Invalid
IRQ12
IRQ3
Invalid
IRQ1
No Interrupt Selected
Table 8-17 DMA Channel Mapping Table
Value
7h-5h
4h
3h
2h
Description
Invalid
Invalid
DMA3
DMA2
79
IT8783F/E V0.5
IT8783E/F (For A Version)
Value
1h
0h
Description
TI
AL
DMA1
DMA0
Table 8-18 Location Mapping Table
EN
GP10 (pin
GP11 (pin
GP12 (pin
GP13 (pin
GP14 (pin
GP15 (pin
GP16 (pin
GP17 (pin
GP20 (pin
GP21 (pin
GP22 (pin
GP23 (pin
GP24 (pin
GP25 (pin
GP26 (pin
GP27 (pin
GP33 (pin
GP34 (pin
GP35 (pin
GP36 (pin
GP37 (pin
GP40 (pin
GP41 (pin
GP42 (pin
GP43 (pin
GP45 (pin
GP46 (pin
GP47 (pin
GP50 (pin
GP51 (pin
GP52 (pin
GP53 (pin
GP54 (pin
GP55 (pin
GP56 (pin
GP57 (pin
Reserved
Description
83). Powered by VCCH.
82). Powered by VCCH.
81).
80).
30).
29)
25).
24)
84). Powered by VCCH
70).
66).
48).
36).
34).
33).
32)
10).
85).
77).
45).
9 ).
79). Powered by VCCH.
78). Powered by VCCH.
76). Powered by VCCH.
75). Powered by VCCH.
73)
72). Powered by VCCH.
71).
52).
54).
56).
57).
58).
59).
60).
61).
C
O
N
FI
D
Location
001 000
001 001
001 010
001 011
001 100
001 101
001 110
001 111
010 000
010 001
010 010
010 011
010 100
010 101
010 110
010 111
011 011
011 100
011 101
011 110
011 111
100 000
100 001
100 010
100 011
100 101
100 110
100 111
101 000
101 001
101 010
101 011
101 100
101 101
101 110
101 111
Else
www.ite.com.tw
80
IT8783F/E V0.5
C
O
N
FI
D
EN
TI
AL
Configuration
www.ite.com.tw
81
IT8783F/E V0.5
N
O
C
TI
AL
EN
FI
D
Functional Description
9.
9.1
Functional Description
LPC Interface
9.1.1
TI
AL
The IT8783E/F supports the peripheral side of the LPC I/F as described in the LPC Interface Specification
Rev.1.1. In addition to the required signals (LAD3-0, LFRAME#, LRESET#, LCLK (the same as PCICLK.)),
the IT8783E/F also supports LDRQ#, SERIRQ and PME#.
LPC Transactions
The IT8783E/F supports the required transfer cycle types described in the LPC I/F specification. Memory
read and Memory write cycles are used for the Flash I/F. I/O read and I/O write cycles are used for the
programmed I/O cycles. DMA read and DMA write cycles are used for DMA cycles. All of these cycles are
characteristic of the single byte transfer.
EN
For LPC host I/O read or write transactions, the Super I/O module processes a positive decoding, and the
LPC interface can respond to the result of the current transaction by sending out SYNC values on LAD[3:0]
signals or leave LAD[3:0] tri-state depending on its result.
For DMA read or write transactions, the LPC interface will react according to the DMA requests from the DMA
devices in the Super I/O modules, and decide whether to ignore the current transaction or not.
The FDC and ECP are 8-bit DMA devices, so if the LPC Host initializes a DMA transaction with data size of
16/32 bits, the LPC interface will process the first 8-bit data and respond with an SYNC ready (0000b) which
will terminate the DMA burst. The LPC interface will then re-issue another LDRQ# message to assert DREQn
after finishing the current DMA transaction.
LDRQ# Encoding
FI
D
9.1.2
The Super I/O module provides two DMA devices: the FDC and the ECP. The LPC Interface provides LDRQ#
encoding to reflect the DREQ[3:0] status. Two LDRQ# messages or different DMA channels may be issued
back-to-back to trace DMA requests quickly. Nevertheless, four PCI clocks will be inserted between two
LDRQ# messages of the same DMA channel to guarantee that there are at least 10 PCI clocks for one DMA
request to change its status. (The LPC host will decode these LDRQ# messages, and send those decoded
DREQn to the legacy DMA controller which runs at 4 MHz or 33/8 MHz).
9.2
Serialized IRQ
O
N
The IT8783E/F follows the specification of Serialized IRQ Support for PCI System, Rev. 6.0, September 1,
1995, to support the serialized IRQ feature, and is able to interface most PC chipsets. The IT8783E/F
encodes the parallel interrupts to an SERIRQ, which will be decoded by the chipset with built-in Interrupt
Controllers (two 8259 compatible modules).
9.2.1
Continuous Mode
C
When in the Continuous mode, the SIRQ host initiates the Start frame of each SERIRQ sequence after
sending out the Stop frame by itself. (The next Start frame may or may not begin immediately after the turnaround state of the current Stop frame.) The SERIRQ is always activated and SIRQ host keeps polling all the
IRQn and system events, even though no IRQn status is changed. The SERIRQ enters the Continuous mode
following a system reset.
www.ite.com.tw
83
IT8783F/E V0.5
IT8783E/F (For A Version)
9.2.2
Quiet Mode
9.2.3
TI
AL
In the Quiet mode, when the situation that one SIRQ Slave detects its input IRQn/events have been changed
happens, it may initiate the first clock of Start frame. The SIRQ host can then follow to complete the SERIRQ
sequence. In the Quiet mode, the SERIRQ has no activity following the Stop frame until it is initiated by SIRQ
Slave, which implies low activity = low mode power consumption.
Waveform Samples of SERIRQ Sequence
Figure 9-1. Start Frame Timing
Start Frame
S/H
H
IRQ0 Frame
R
T
S
R
T
IRQ1 Frame
S
R
SERIRQ
(4/6/8)T
S: Slave drive
H: Host drive
T
S
R
IRQ3 Frame
T
S
EN
PCICLK
SMI# Frame
R: Recovery
T: Turn-around
R
T
IRQ4 Frame
S
R
T
S/H: Slave drive when in Quiet mode, Host drive when in Continuous mode
Figure 9-2. Stop Frame Timing
Last Frame
Stop Frame
S
I
R
T
H
SERIRQ
R
T
W
Start Frame
Last Frame
S
S
FI
D
PCICLK
(Quiet)
H
R
T
0~n Tclk idle state
R: Recovery
Waiting
(Continuous)
R
T
H1
0~n T, depends on master
T: Turn-around
I: Idle
W:
C
O
N
H: Host drive
H
3 Tclk
2 Tclk
S: Slave drive
Stop Frame
www.ite.com.tw
84
IT8783F/E V0.5
Functional Description
SERIRQ Sampling Slot
IRQn/
Event
#of Clocks
Past Start
IT8783E/F
1
IRQ0
2
-
2
IRQ1
5
Y
3
SMI#
8
Y
4
IRQ3
11
Y
5
IRQ4
14
Y
6
IRQ5
17
Y
7
IRQ6
20
Y
8
IRQ7
23
Y
9
IRQ8
26
Y
10
IRQ9
29
Y
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
14
IRQ13
41
15
IRQ14
44
16
IRQ15
47
18
19
20
21
Y
Y
-
Y
Y
IOCHCK#
50
-
INTA#
53
-
INTB#
56
-
INTC#
59
-
INTD#
62
-
Unassigned
95 / 65
-
C
O
N
32:22
Y
FI
D
17
EN
Slot
Number
TI
AL
9.2.4
www.ite.com.tw
85
IT8783F/E V0.5
IT8783E/F (For A Version)
9.3
General Purpose I/O
TI
AL
The IT8783E/F provides five sets of flexible I/O control and special functions for the system designers via a
set of multi-functional General Purpose I/O pins (GPIO). The GPIO functions will not be performed unless the
related enable bits of the GPIO Multi-function Pin Selection registers (Index 25h, 26h, 27h, 28h and 29h of
the Global Configuration Registers) are set. The GPIO functions include the simple I/O function and alternate
function, and the function selection is determined by the Simple I/O Enable Registers (LDN=07h, Index=C0h,
C1h, C2h, C3h and C4h).
The Simple I/O function includes a set of registers, which correspond to the GPIO pins. All control bits are
divided into five registers. The accessed I/O ports are programmable and are five consecutive I/O ports (Base
Address+0, Base Address+1, Base Address+2, Base Address+3, Base Address+4). Base Address is
programmed on the registers of GPIO Simple I/O Base Address LSB and MSB registers (LDN=07h,
Index=60h and 61h).
EN
The Alternate function provides several special functions for users, including Watch Dog Timer, SMI# output
routing, External Interrupt routing, Panel Button De-bounce, Keyboard Lock input routing, LED Blinking,
Thermal output routing, and Beep output routing. The last two are the sub-functions of the Hardware Monitor.
The Panel Button De-bounce is an input function. After it is enabled, a related status bit will be set when an
active low pulse is detected on the GPIO pin. The status bits will be cleared by writing 1’s to them. Panel
Button De-bounce Interrupt will be issued if any of the status bit is set. However, the newly set status will not
issue another interrupt unless the previous status bit is cleared before being set.
FI
D
The Key Lock function locks the keyboard to inhibit the keyboard interface. The way pf programming is by
setting bit 2 on the register Index F0h of KBC(Keyboard) (LDN=5). The pin location mapping, Index F7h also
must be programmed correctly.
The Blinking function provides a low frequency blink output. By connecting to some external components, it
can be used to control a power LED. There are several frequencies for selection.
O
N
The Watch Dog Timer (WDT) function is constituted by a time counter, a time-out status register, and the
timer reset control logic. The time-out status bit may be mapped to an interrupt or KRST# through the WDT
configuration register. The WDT has a programmable time-out ranging from 1 to 65535 minutes or 1 to 65535
seconds. The unit, either a minute or a second, is also programmable via bit 7 of the WDT configuration
register. In real time, the clock divider provides 68.8 msec per timer cycle to WDT operation when the time
unit is selected as 64 ms, 1.1 sec per timer cycle to WDT operation when the time unit is selected as 1 sec,
and 1.1 minute per timer cycle to WDT operation when the time unit is selected as 1 minute. When the WDT
Time-out Value register is set to a non-zero value, the WDT loads the value and begins counting down from
the value. When the value reaches to 0, the WDT status register will be set. There are two system events
including a Keyboard Interrupt and a Mouse Interrupt that can reload the non-zero value into the WDT. The
effect on the WDT for each of the events may be enabled or disabled through bits in the WDT control register.
No matter what the value is in the time counter, the host may force a time-out to occur by writing a “1” to the
bit 1 of the WDT configuration register.
C
The External Interrupt routing function provides a useful feature for motherboard designers. Through this
function, the parallel interrupts of other on-board devices can be easily re-routed into the Serial IRQ.
The SMI# is a non-maskable interrupt dedicated to the transparent power management. It consists of
different enabled interrupts generated from each of the functional blocks in the IT8783E/F. The interrupts are
redirected as the SMI# output via the SMI# Control Register 1 and SMI# Control Register 2. The SMI# Status
Register 1 and 2 are used to read the status of the SMI input event. All the SMI# Status Register bits can be
cleared when the corresponding source events become invalidated. These bits can also be cleared by writing
1 to bit 7 of SMI# Control Register 2 no matter whether the events of the corresponding sources are
invalidated or not. The SMI# events can be programmed as the pulse mode or level mode whenever an SMI#
www.ite.com.tw
86
IT8783F/E V0.5
Functional Description
event occurs. The logic equation of the SMI# event is described below:
TI
AL
SMI# event = (EN_FIRQ and FIRQ) or (EN_S1IRQ and S1IRQ) or (EN_S2IRQ and S2IRQ) or (EN_PIRQ
and PIRQ) or (EN_EC and EC_SMI) or (EN_PBDIRQ or PBDIRQ) or (EN_KIRQ and KIRQ) or (EN_MIRQ
and MIRQ) or (EN_WDT and WDT_IRQ) or (EN_STPCLK and STPCLK_IRQ)
Figure 9-3. General Logic of GPIO Function
Thermal Output
1
LED Blinking 1
2
3
LED Blinking 2
4
Beep#
SMI#
5
Simple I/O
Polarity
enable
SD-bus
WR#
EN
Simple I/O Register Bit-n
D-
Pull-up
enable
0
TYPE
1
Output
enable
1
0
RD_
GPIO
PIN
De-bounce
enable
FI
D
Interrupt
SD-bus
status
De-bounce circuit
Panel Button De-bounce Bit-n
RD_(IDX=64h, 65h)
External IRQ Routing
(Level 3 - 7, 9 - 11, 14-15)
C
O
N
Keyboard lock
www.ite.com.tw
87
IT8783F/E V0.5
IT8783E/F (For A Version)
9.4
Advanced Power Supply Control and Power Management Event (PME#)
1.
2.
TI
AL
The circuit for advanced power supply control (APC) provides two power-up events, Keyboard and Mouse.
When any of these two events is true, PWRON# will perform a low state until VCC is switched to the ON state.
The two events include the followings:
Detection of KCLK edge or special pattern of KCLK and KDAT. The special pattern of KCLK means
pressing pre-set key string sequentially, and KDAT means pressing pre-set keys simultaneously.
Detection of MCLK edge or special pattern of MCLK and MDAT. The special pattern of MCLK and MDAT
means clicking on any mouse button twice sequentially.
The PANSWH# and PSON# are especially designed for the system. PANSWH# serves as a main power
switch input, which is wire-AND to the APC output PWRON#. PSON# is the ATX Power control output, which
is a power-failure gating circuit. The power-failure gating circuit is responsible for gating the PSIN input until
PANSWH# becomes active when the VCCH is switched from OFF to ON.
EN
The power-failure gating circuit can be disabled by setting the APC/PME Control Register 2 (LDN=04h, index
F4h, bit 5). The gating circuit also provides an auto-restore function. After bit 5 of PCR1 is set, the previous
PSON# state will be restored when the VCCH is switched from OFF to ON.
The Mask PWRON# Activation bit (bit 4 of PCR 1) is used to mask all power-up events except switch-on
event when the VCCH state is just switched from FAIL to OFF. In other words, when this bit is set and the
power state is switched from FAIL to OFF, the only validated function is PANSWH#.
FI
D
The PCR2 register is responsible for determining the keyboard power-up event and APC condition. Bit 4 is
used to mask the PANSWH# power-on event on the PWRON# pin. To enable this bit, the keyboard power-up
event should be enabled and set by (1) pressing pre-set key string sequentially or (2) stroking pre-set keys
simultaneously. The APC/PME# special code index and data registers are used to specify the special key
codes in the special power-up events of (1) pressing pre-set key string sequentially or (2) stroking pre-set
keys simultaneously.
All APC registers (Index=F0h, F2h, F4h, F5h and F6h) are powered by back-up power (VBAT) when VCCH is
OFF.
C
O
N
PME# is used to wake up the system from low-power states (S1-S5). Except the five events of the APC, there
will be other events to generate PME#: They are RI1# and RI2# events. RI1# and RI2# are Ring Indicator of
Modem status in ACPI S1 or S2 state. A falling edge on these pins issues PME# events if the enable bits are
set.
www.ite.com.tw
88
IT8783F/E V0.5
Functional Description
9.5
SPI Serial Flash Controller
9.5.1
Overview
9.5.2
Features
SPI Interface
LPC memory cycle and firmware memory cycle supported
9.5.3
Register Description
TI
AL
The SPI Serial Flash controller is a LPC to the serial Flash I/F controller.
Table 9-1. Memory Stick Register List
R/W
Default
Base + 0h
R/W
20h
Control Register (SPI_CTRL)
Base + 1h
R/W
00h
Command Register (SPI_CMD)
Base + 2h
R/W
00h
Address 0 Register (SPI_ADDR0)
Base + 3h
R/W
00h
Address 1 Register (SPI_ADDR1)
Base + 4h
R/W
00h
Address 2 Register (SPI_ADDR2)
Base + 5h
R
--
Input Data 0 Register (SPI_IDATA0)
Base + 6h
R
--
Input Data 1 Register (SPI_IDATA1)
Base + 7h
R/W-R
00h/--
Output Data Register (SPI_ODATA)/ Input Data 2 Register
(SPI_IDATA2)
FI
D
9.5.3.1
Name
EN
Address
Control Register (SPI_CTRL)
R/W
R
Default
-
R/W
0b
O
Address: Base address + 0h
Bit
7
N
6
R/W
1b
4
R/W
0b
C
5
www.ite.com.tw
Description
SPI Status(SPIS)
This bit reports the SPI I/F status.
0: Idle.
1: Busy.
Start IO Transfer(SIOT)
This bit starts the SPI cycle with the instruction/parameter given through I/O
port.
0: No Start IO
1: Enable Start IO/going
Multiple Byte Mode(MBM)
This bit enables the multiple byte mode in LPC memory write/read cycle.
0: Disable
1: Enable
SCK Selection(SCKS)
This bit selects the SCK frequency.
0: 33MHz/2.
1: 33MHz.
89
IT8783F/E V0.5
IT8783E/F (For A Version)
R/W
R/W
Default
00b
1-0
R/W
00b
Command Register (SPI_CMD)
Address: Base address + 1h
Bit
7-0
9.5.3.3
R/W
R/W
Default
00h
FI
D
9.5.3.4
Description
Command Register (SPI_CMD [7:0])
This register will set the Instruction command code in the Start IO mode.
(The first byte)
Address 0 Register (SPI_ADDR0)
Address: Base address + 2h
Bit
7-0
EN
9.5.3.2
Description
Input Data Byte(IDB)
These bits determine the byte number of the input data in the Start IO mode.
00: None.
01: 1 byte. (SPI_DATAI0)
10: 2 bytes. (SPI_DATAI0, SPI_DATAI1).
11: 3 bytes. (SPI_DATAI0, SPI_DATAI1, SPI_DATAI2).
Output Data Byte(ODB)
These bits determine the byte number of the output data (including
Instruction, Address, Data) in the Start IO mode.
00: 1 byte. (SPI_CMD)
01: 2 bytes. (SPI_CMD, SPI_DATAO)
10: 4 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0)
11: 5 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0, SPI_DATAO)
TI
AL
Bit
3-2
R/W
R/W
Default
00h
Description
Address 0 Register (SPI_ADDR0 [7:0])
This register will set the Address [7:0] in the Start IO mode.
Address 1 Register (SPI_ADDR1)
Address: Base address + 3h
R/W
R/W
Default
00h
N
Bit
7-0
Address 2 Register (SPI_ADDR2)
O
9.5.3.5
Description
Address 1 Register (SPI_ADDR1 [7:0])
This register will set the Address [15:8] in the Start IO mode.
Address: Base address + 4h
R/W
R/W
C
Bit
7-0
www.ite.com.tw
Default
00h
Description
Address 2 Register (SPI_ADDR2 [7:0])
This register will set the Address [23:16] in the Start IO mode.
90
IT8783F/E V0.5
Functional Description
9.5.3.6
Input Data 0 Register (SPI_IDATA0)
Bit
7-0
R/W
R
9.5.3.7
Default
--
Description
Input Data 0 Register (SPI_IDATA0 [7:0])
This register will set the Input Data 0 byte in the Start IO mode.
Input Data 1 Register (SPI_IDATA1)
Address: Base address + 6h
R/W
R
9.5.3.8
Default
--
Description
Input Data 1 Register (SPI_IDATA1 [7:0])
This register will set the Input Data 1 byte in the Start IO mode.
Output Data/Input Data 2 Register (SPI_ODATA/ SPI_IDATA2)
EN
Bit
7-0
Address: Base address + 7h
R/W
R/W
9.5.4
Default
00h
Description
Output Data Register/Input Data 2 Register
(SPI_ODATA [7:0]/SPI_IDATA2 [7:0])
This register will set the Output Data byte in the Start IO mode, or Input Data
2 when the input data byte number is 3.
FI
D
Bit
7-0
TI
AL
Address: Base address + 5h
Function Descriptions
Programming sequence: For the instruction code and byte number, please refer to the Serial Flash product
specification.
Start IO mode:
// 1: Check SPI I/F
IOR [SPI_CTRL];
Set the parameters in any order of write sequence.
N
// 2:
// check bit7 SPI status
O
IOW [SPI_CMD]
IOW [SPI_ADDR0]
IOW [SPI_ADDR1]
IOW [SPI_ADDR2]
IOW [SPI_ODATA]
XXh:
XXh:
XXh:
XXh:
XXh:
C
// 3: Start SPI I/F
IOW [SPI_CTRL]
// Set SPI Instruction
// Set SPI Address0, if necessary
// Set SPI Address1, if necessary
// Set SPI Address2, if necessary
// Set SPI Output Data, if necessary
{4’h1, Input_data_byte, Output_data_byte};
LPC memory cycle:
When the host issues a LPC memory read cycle with the matching memory space, the controller will
issue a corresponding SPI read cycle automatically. The controller will pre-read from 0 to 3 byte(s) of
data into the read buffers. The number of pre-read data byte(s) is determined by the starting address 0
and 1. The byte number will be 3 bytes if the two addresses are 00b. The number will be 2 bytes if the
two addresses are 01b. The number will be 1 byte if the two addresses are 10b. There is no pre-read
data if the two addresses are 11b.If the address of the next coming LPC memory cycle matches the
www.ite.com.tw
IT8783F/E V0.5
91
IT8783E/F (For A Version)
buffers’ address, no SPI read cycle will be issued.
TI
AL
For most types of serial flash products, the Write-Enable instruction through the Start IO mode should be
given before issuing the LPC memory writes cycle. Normally, each LPC memory cycle will issue a one
byte SPI programming cycle (Instruction, Addresses, 1 Data byte). If the Multiple Byte mode is enabled, a
multi-byte SPI programming cycle will be issued. For example:
// LPC Memory Write Multiple byte mode
// 1: Write-Enable command
IOR [SPI_CTRL];
// check bit7 SPI status
IOW [SPI_CMD]
06h:
// Set SPI Instruction
IOW [SPI_CTRL]
{4’h3, 2’b00, 2’b00};
// Start IO SPI cycle and enable the LPC memory Multiple Byte mode
FI
D
// 3: Terminate SPI I/F
IOW [SPI_CTRL]
EN
// 2: LPC memory write cycles: The first LPC memory cycle will start an SPI cycle and determine the
//
Programming page address. The following LPC memory write cycles must be contiguous
addresses.
// And, the total bytes cannot exceed 256 – [starting address 7-0]. These conditions should be
// confirmed by the programmer. The controller will not check them. During this period, the SPI cycle
// will not be finished. Between the two MEMW cycles, the HOLD# pin will be asserted and SCK will be
forced low.
MEMW [Starting address]:
// Set SPI Address and the first byte data.
MEMW [Starting address+1]:
// Set SPI second byte data.
MEMW [Starting address+2]:
// Set SPI third byte data.
:
MEMW [Starting address+N]:
// Set SPI Nth byte data.
{4’h0, 2’b00, 2’b00};
// Terminate LPC memory write Page Program mode and SPI cycle
// LPC Memory Read Multiple byte mode
// 1: Write-Enable command
IOW [SPI_CTRL]
{4’h2, 2’b00, 2’b00};
// Enable LPC memory Multiple Byte mode
O
N
// 2: LPC memory read cycles: The first LPC memory cycle will start the SPI cycle and determine the
//
reading address. The following LPC memory read cycles must be the contiguous addresses.
// And, the total bytes will not be limited. The programmer should confirm these conditions.
// The controller will not check them. During this period, the SPI cycle will not be finished. Between the
two // MEMR cycles, the HOLD# pin will be asserted and SCK will be forced low.
MEMR
[Starting address]:
// Set SPI Address and the first byte data.
MEMR
[Starting address+1]:
// Set SPI second byte data.
MEMR
[Starting address+2]:
// Set SPI third byte data.
:
MEMR
[Starting address+N]:
// Set SPI Nth byte data.
C
// 3: Terminate SPI I/F
IOW [SPI_CTRL]
www.ite.com.tw
{4’h0, 2’b00, 2’b00};
// Terminate LPC memory Read Multiple Byte mode and SPI cycle
92
IT8783F/E V0.5
Functional Description
9.6
Environment Controller
TI
AL
The Environment Controller (EC), built in the IT8783E/F, includes eight voltage inputs, three temperature
sensor inputs, five FAN Tachometer inputs, and three sets of advanced FAN Controllers. The EC monitors
the hardware environment and implements the environmental control for personal computers.
The IT8783E/F contains an 8-bit ADC (Analog-to-Digital Converter), which is responsible for monitoring the
voltages and temperatures. The ADC converts the analog inputs ranging from 0V to 4.096V into 8-bit digital
byte. With additional external components, the analog inputs can be made to monitor different voltage ranges,
in addition to monitoring the fixed input range of 0V to 4.096V. Through external thermistors or thermal diodes,
the temperature sensor inputs can be converted into 8-bit digital byte, enabling the sensor inputs to
monitoring the temperature of various components. A built-in ROM is also provided to adjust the non-linear
characteristics of thermistors.
FAN Tachometer inputs are digital inputs with an acceptable input range of 0V to 5V, and are responsible for
measuring the FAN’s Tachometer pulse periods.
9.6.1
EN
The EC of the IT8783E/F provides multiple internal registers and an interrupt generator for programmers to
monitor the environment and control the FANs. Both of LPC Bus and Serial Bus interfaces are supported to
accommodate the needs for various applications.
Interfaces
LPC Bus: The Environment Controller of the IT8783E/F decodes two addresses.
Table 9-2. Address Map on LPC Bus
Address
Address register of EC
Base+05h
Data register of EC
Base+06h
FI
D
Register or Port
N
Note 1: The Base Address is determined by Environment Controller Base Address MSB Register
(Index=60h, Default=02h) (refer to page 61) and Environment Controller Base Address LSB Register
(Index=61h, Default=90h) (refer to page 61).
To access an EC register, the address of the register is written to the address port (Base+05h). Read or write
data from or to that register via data port (Base+06h).
9.6.2
9.6.2.1
Address Port (Base+05h, Default=00h)
O
Bit
7
Registers
Outstanding; read only
This bit is set when a data write is performed to Address Port via the LPC Bus.
Index
Internal Address of RAM and Registers.
C
6-0
Description
www.ite.com.tw
93
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 9-3. Environment Controller Registers
R/W
Default
Registers or Action
00h
R/W
18h
Configuration Register
01h
R
00h
Interrupt Status c 1
02h
R
00h
Interrupt Status Register 2
03h
R
00h
Interrupt Status Register 3
04h
R/W
00h
SMI# Mask Register 1
05h
R/W
00h
SMI# Mask Register 2
06h
R/W
00h
SMI# Mask Register 3
07h
R/W
00h
Interrupt Mask Register 1
08h
R/W
00h
Interrupt Mask Register 2
09h
R/W
80h
Interrupt Mask Register 3
0Ah
R/W
54h
Interface Selection Register
0Bh
R/W
09h
Fan PWM Smoothing Step Frequency Selection Register
0Ch
R/W
00h
Fan Tachometer 16-bit Counter Enable Register
0Dh
R
-
Fan Tachometer 1 Reading Register
0Eh
R
-
Fan Tachometer 2 Reading Register
0Fh
R
-
Fan Tachometer 3 Reading Register
10h
R/W
-
Fan Tachometer 1 Limit Register
11h
R/W
-
Fan Tachometer 2 Limit Register
12h
R/W
-
Fan Tachometer 3 Limit Register
13h
R/W
07h
Fan Controller Main Control Register
14h
R/W
50h
FAN_CTL Control Register
15h
R/W
00h/20h/40h/60h
16h
R/W
00h/20h/40h/60h
N
FI
D
EN
TI
AL
Index
FAN_CTL1 PWM Control Register
Bit7 must be 0.
FAN_CTL2 PWM Control Register
Bit7 must be 0.
FAN_CTL3 PWM Control Register
R/W
00h/20h/40h/60h
18h
R
-
Fan Tachometer 1 Extended Reading Register
19h
R
-
Fan Tachometer 2 Extended Reading Register
1Ah
R
-
Fan Tachometer 3 Extended Reading Register
1Bh
R/W
-
Fan Tachometer 1 Extended Limit Register
1Ch
R/W
-
Fan Tachometer 2 Extended Limit Register
1Dh
R/W
-
Fan Tachometer 3 Extended Limit Register
20h
R
-
VIN0 Voltage Reading Register
21h
R
-
VIN1 Voltage Reading Register
22h
R
-
VIN2 Voltage Reading Register
23h
R
-
VIN3 Voltage Reading Register
C
O
17h
www.ite.com.tw
Bit7 must be 0.
94
IT8783F/E V0.5
Functional Description
R/W
Default
Registers or Action
24h
R
-
VIN4 Voltage Reading Register
25h
R
-
VIN5 Voltage Reading Register
26h
R
-
VIN6 Voltage Reading Register
27h
R
-
VIN7 Voltage Reading Register
28h
R
-
VBAT Voltage Reading Register
29h
R
-
TMPIN1 Temperature Reading Register
2Ah
R
-
TMPIN2 Temperature Reading Register
2Bh
R
-
TMPIN3 Temperature Reading Register
30h
R/W
-
VIN0 High Limit Register
31h
R/W
-
VIN0 Low Limit Register
32h
R/W
-
VIN1 High Limit Register
33h
R/W
-
VIN1 Low Limit Register
34h
R/W
-
VIN2 High Limit Register
35h
R/W
-
VIN2 Low Limit Register
36h
R/W
-
VIN3 High Limit Register
37h
R/W
-
VIN3 Low Limit Register
38h
R/W
-
VIN4 High Limit Register
39h
R/W
-
VIN4 Low Limit Register
3Ah
R/W
-
VIN5 High Limit Register
3Bh
R/W
-
VIN5 Low Limit Register
3Ch
R/W
-
VIN6 High Limit Register
3Dh
R/W
-
VIN6 Low Limit Register
3Eh
R/W
-
VIN7 High Limit Register
3Fh
R/W
-
VIN7 Low Limit Register
40h
R/W
-
TMPIN1 High Limit Register
41h
R/W
-
TMPIN1 Low Limit Register
N
FI
D
EN
TI
AL
Index
R/W
-
TMPIN2 High Limit Register
43h
R/W
-
TMPIN2 Low Limit Register
44h
R/W
-
TMPIN3 High Limit Register
45h
R/W
-
TMPIN3 Low Limit Register
50h
R/W
00h
ADC Voltage Channel Enable Register
51h
R/W
00h
ADC Temperature Channel Enable Register
52h
R/W
7Fh
TMPIN1 Thermal Output Limit Register
53h
R/W
7Fh
TMPIN2 Thermal Output Limit Register
54h
R/W
7Fh
TMPIN3 Thermal Output Limit Register
55h
R/W
00h
ADC Temperature Extra Channel Enable Register
56h
R/W
00h
Thermal Diode 1 Zero Degree Adjust Register
57h
R/W
00h
Thermal Diode 2 Zero Degree Adjust Register
C
O
42h
www.ite.com.tw
95
IT8783F/E V0.5
IT8783E/F (For A Version)
R/W
Default
Registers or Action
58h
R
90h
ITE Vendor ID Register
59h
R/W
00h
Thermal Diode 3 Zero Degree Adjust Register
5Bh
R
12h
Core ID Register
5Ch
R/W
60h
Beep Event Enable Register
5Dh
R/W
00h
Beep Frequency Divisor of Fan Event Register
5Eh
R/W
00h
Beep Frequency Divisor of Voltage Event Register
5Fh
R/W
00h
Beep Frequency Divisor of Temperature Event Register
60h
R/W
7Fh
FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of OFF
Register
61h
R/W
7Fh
FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of Fan
Start Register
63h
R/W
00h
FAN_CTL1 SmartGuardian Automatic Mode Start PWM Register
64h
R/W
00h
FAN_CTL1 SmartGuardian Automatic Mode Control Register
65h
R/W
7Fh
FAN_CTL1 SmartGuardian Automatic Mode △-Temperature Register
68h
R/W
7Fh
FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of OFF
Register
69h
R/W
7Fh
FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of Fan
Start Register
6Ah
R/W
7Fh
Reserved
6Bh
R/W
00h
FAN_CTL2 SmartGuardian Automatic Mode Start PWM Register
6Ch
R/W
00h
FAN_CTL2 SmartGuardian Automatic Mode Control Register
6Dh
R/W
7Fh
FAN_CTL2 SmartGuardian Automatic Mode △-Temperature Register
70h
R/W
7Fh
FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of OFF
Register
71h
R/W
7Fh
FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of Fan
Start Register
72h
R/W
7Fh
Reserved
N
FI
D
EN
TI
AL
Index
R/W
00h
FAN_CTL3 SmartGuardian Automatic Mode Start PWM Register
74h
R/W
00h
FAN_CTL3 SmartGuardian Automatic Mode Control Register
75h
R/W
7Fh
FAN_CTL3 SmartGuardian Automatic Mode △-Temperature Register
88h
R/W
---00000b
89h
R/W
00h
External Temperature Sensor Host Target Address Register
8Ah
R/W
00h
External Temperature Sensor Host Write Length Register
8Bh
R/W
00h
External Temperature Sensor Host Read Length Register
8Ch
R/W
00h
External Temperature Sensor Host Command (Write Data 1) Register
8Dh
R/W
--h
External Temperature Sensor Write Data (2-8) Register
8Eh
R/W
02h
External Temperature Sensor Host Control Register
8Fh
R
00h
External Temperature Sensor Read Data (1-16) Register
C
O
73h
www.ite.com.tw
External Temperature Sensor Host Status Register
96
IT8783F/E V0.5
Functional Description
Configuration Register (Index=00h, Default=18h)
R/W
R/W
6
5
R/W
R/W
4
R
3
R/W
2
R/W
1
R/W
0
R/W
Description
Initialization(INIT)
A “1” restores all registers to their individual default values, except the Serial Bus
Address register. This bit clears itself when the default value is “0”.
Update VBAT Voltage Reading(UVVR)
COPEN# Cleared(CCW)
Write “1” to clear COPEN#.
Note: The Case Open Status register (Index 01h<bit4>) will be cleared when first writing
this register and then reading Index 01h<bit4>.
Reserved
Read only; always “1”
INT_Clear(INTC)
A “1” disables the SMI# and IRQ outputs while the contents of interrupt status bits
remain unchanged.
IRQ Enable (IRQE)
This bit is to enable the IRQ Interrupt output.
SMI# Enable(SMIE)
A “1” enables the SMI# Interrupt output.
Start(START)
A “1” enables the startup of monitoring operations and a “0” sets the monitoring
operation in the STANDBY mode.
C
O
N
FI
D
Bit
7
TI
AL
9.6.2.2.1
Register Description
EN
9.6.2.2
www.ite.com.tw
97
IT8783F/E V0.5
IT8783E/F (For A Version)
9.6.2.2.2
Interrupt Status Register 1 (Index=01h, Default=00h)
Bit
7
6
5
4
R/W
R
R
R
R
3
2-0
R
R
Description
Reserved
Reserved
Reserved
Case Open Status(COS)
A “1” indicates a Case Open event has occurred.
Note: The Case Open Status register (Index 01h<bit4>) will be cleared when first
writing Index 00h<bit5> and then reading this register.
Reserved
Count Limit Reached(CLR)
A “1” indicates the FAN_TAC3-1 Count limit has been reached.
Interrupt Status Register 2 (Index=02h, Default=00h)
EN
9.6.2.2.3
TI
AL
Reading this register will clear itself following a read access.
Reading this register will clear itself after the read operation is completed.
9.6.2.2.4
R/W
R
Description
VIN7-0 Limit Reached(VLR)
A “1” indicates a High or Low limit of VIN7-0 has been reached.
Interrupt Status Register 3 (Index=03h, Default=00h)
FI
D
Bit
7-0
Reading this register will clear itself following a read access.
Bit
7-3
2-0
Description
Reserved
Temperature limit Reached (TLR)
A “1” indicates a High or Low limit of Temperature 3-1 has been reached.
SMI# Mask Register 1 (Index=04h, Default=00h)
N
9.6.2.2.5
R/W
R
R
R/W
R/W
R/W
R/W
R/W
3
2-0
R/W
R/W
C
O
Bit
7
6
5
4
9.6.2.2.6
Bit
7-0
Description
Reserved
Reserved
Reserved
Case Open Interrupt SMI#(COISMI)
A “1” disables the Case Open Intrusion interrupt status bit for SMI#.
Reserved
FAN_TAC3-1 Interrupt SMI#(FISMI)
A “1” disables the FAN_TAC3-1 interrupt status bit for SMI#.
SMI# Mask Register 2 (Index=05h, Default=00h)
R/W
R/W
www.ite.com.tw
Description
VIN7-0 Interrupt SMI#(VISMI)
A “1” disables the VIN7-0 interrupt status bit for SMI#.
98
IT8783F/E V0.5
Functional Description
9.6.2.2.8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3
2-0
R/W
R/W
9.6.2.2.10
Bit
7
Reserved
Reserved
Reserved
Case Open Interrupt IRQ(COIIRQ)
A “1” disables the Case Open Intrusion interrupt status bit for IRQ.
Reserved
FAN_TAC3-1 Interrupt IRQ(FIIRQ)
A “1” disables the FAN_TAC3-1 interrupt status bit for IRQ.
Interrupt Mask Register 2 (Index=08h, Default=00h)
R/W
R/W
Description
VIN7-0 Interrupt IRQ(VIIRQ)
A “1” disables the VIN7-0 interrupt status bit for IRQ.
Interrupt Mask Register 3 (Index=09h, Default=80h)
R/W
R/W
R/W
R/W
Description
Ext Thermal Interrupt(ETI)
A “1” disables the External Thermal Sensor interrupt.
Reserved
Temperature3-1 Interrupt IRQ(TIIRQ)
A “1” disables the Temperature3-1 interrupt status bit for IRQ.
N
6-3
2-0
Description
FI
D
Bit
7-0
Reserved
Temperature3-1 Interrupt SMI#(TISMI)
A “1” disables the Temperature 3-1 interrupt status bit for SMI#.
Interrupt Mask Register 1 (Index=07h, Default=00h)
Bit
7
6
5
4
9.6.2.2.9
Description
TI
AL
Bit
7-3
2-0
SMI# Mask Register 3 (Index=06h, Default=00h)
EN
9.6.2.2.7
9.6.2.2.11
R/W
R/W
O
Bit
7
Interface Selection Register (Index=0Ah, Default=54h)
C
6-4
3
R/W
R/W
www.ite.com.tw
Description
Pseudo-EOC (End of conversion of ADC)(PEOC)
A Pseudo-EOC bit can speed up the setup time of FAN speed in the SmartGuardian
automatic mode. (Write 1 to the bit then write 0.)
External Thermal Sensor Host Selection(ETSHS)
000: Disable
100: Reserved
101: SST Slave Device
110: PECI
111: SST Host
Others: Reserved
SST/PECI Host Controller Clock Selection(HCS)
0: 32 MHz generated internally
1: 24 MHz
99
IT8783F/E V0.5
IT8783E/F (For A Version)
R/W
R/W
1
R/W
1-0
R
Bit
7-0
9.6.2.2.13
Fan PWM Smoothing Step Frequency Selection Register (Index=0Bh, Default=09h)
R/W
R/W
6
R/W
Description
TMPIN3 Enhanced Interrupt Mode Enable(T3EIME)
0: Original mode
1: The interrupt will be generated when the TMPIN3 is higher than the high limit or
lower than the low limit.
TMPIN2 Enhanced Interrupt Mode Enable(T2EIME)
0: Original mode
1: The interrupt will be generated when the TMPIN2 is higher than the high limit or
lower than the low limit.
Reserved
TMPIN1 Enhanced Interrupt Mode Enable(T1EIME)
0: Original mode.
1: The interrupt will be generated when the TMPIN1 is higher than the high limit or
lower than the low limit.
FAN_TAC3 16-bit Counter Divisor Enable(F3CDE)
1: Enable
0: Disable
FAN_TAC2 16-bit Counter Divisor Enable(F2CDE)
1: Enable
0: Disable
FAN_TAC1 16-bit Counter Divisor Enable(F1CDE)
1: Enable
0: Disable
FI
D
R/W
R/W
R/W
R/W
R/W
N
2
Reserved
Fan Tachometer 16-bit Counter Enable Register (Index=0Ch, Default=00h)
Bit
7
5-4
3
Description
EN
9.6.2.2.12
Description
SST/PECI Host Controller (Auto speed no-change tolerance) tbit 1 Setting(HCTB)
0: (2 host clocks) no less than 1 host clock
1: (1 host clock) less than 1 host clock
Reserved
(must be 0)
SST/PECI Host Controller Transition Speed Mode Selection(HCTSMS)
00: Auto
01: Fixed at 1 MHz
10: Fixed at 0.5 MHz
11: Fixed at 0.25 MHz
TI
AL
Bit
2
R/W
0
R/W
C
O
1
www.ite.com.tw
100
IT8783F/E V0.5
Functional Description
9.6.2.2.15
Bit
7-0
9.6.2.2.16
R/W
R
R/W
R/W
Limit Value(LV)
R/W
2-0
R/W
Description
Reserved
FAN_TAC3-1 Enable(FE)
1: Enable
0: Disable
Full Speed Control of FAN_CTL Automatic Mode(FSCFAM)
0: The full speeds of FAN_CTL1-3 automatic mode are independent.
1: All FAN_CTL1-3 will enter their respective full speeds when the temperature exceeds
the full Speed Temperature Limit.
FAN_CTL3-1 Output Mode Selection(FCOMS)
0: ON/OFF mode
1: SmartGuardian mode
FI
D
3
FAN_CTL Control Register (Index=14h, Default=50h)
R/W
R/W
R/W
Description
FAN_CTL Polarity (For all FANs)(FP)
0: Active low
1: Active high
FAN_CTL PWM Base Clock Selection(PBCS)
000: 48 MHz(PWM Frequency=375 kHz)
001: 24 MHz(PWM Frequency=187.5 kHz)
010: 12 MHz(PWM Frequency=93.75 kHz)
011: 8 MHz(PWM Frequency=62.5 kHz)
100: 6 MHz(PWM Frequency=46.875 kHz)
101: 3 MHz(PWM Frequency=23.43 kHz)
110: 1.5 MHz(PWM Frequency=11.7 kHz)
111: 0.75 MHz(PWM Frequency=5.86 kHz)
Reserved
(Must be 0)
FAN_CTL ON/OFF Mode Control (FCOFMC)
These bits are only available when the relative output modes are selected in the
ON/OFF mode.
0: OFF
1: ON
O
N
6-4
Description
Fan Controller Main Control Register (Index=13h, Default=07h)
R/W
R
R/W
Bit
7
Tachometer Reading Value(TRV)
The count number of the internal clock per revolution
Fan Tachometer 1-3 Limit Registers (Index=10h-12h)
Bit
7
6-4
9.6.2.2.17
Description
TI
AL
Bit
7-0
Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh)
EN
9.6.2.2.14
R/W
2-0
R/W
C
3
www.ite.com.tw
101
IT8783F/E V0.5
IT8783E/F (For A Version)
9.6.2.2.18
FAN_CTL1 PWM Control Register (Index=15h, Default=00h/20h/40h/60h)
Bit
7
R/W
R/W
6-0
R/W
9.6.2.2.19
Description
FAN_CTL1 PWM Mode Automatic/Software Operation Selection (F1PASOS)
0: Software operation
1: Automatic operation
PWM Control Temperature Input Selection (PCTIS)
128 steps of PWM control when in Software operation (bit 7=0)
FAN_CTL2 PWM Control Register (Index=16h, Default=00h/20h/40h/60h)
The default value of this register is selected by JP5 and JP7.
6-0
R/W
Description
FAN_CTL2 PWM Mode Automatic/Software Operation Selection(F2PASOS)
0: Software Operation
1: Automatic operation
PWM Control Temperature Input Selection (PCTIS)
128 steps of PWM control when in Software operation (bit 7=0)
00: TMPIN1
01: TMPIN2
10: TMPIN3
11: Reserved
EN
R/W
R/W
FI
D
Bit
7
9.6.2.2.20
TI
AL
The default value of this register is selected by JP5 and JP7.
FAN_CTL3 PWM Control Register (Index=17h, Default=00h/20h/40h/60h)
The default value of this register is selected by JP5 and JP7.
Bit
7
R/W
Description
FAN_CTL3 PWM mode Automatic/Software Operation Selection(F3PASOS)
0: Software Operation
1: Automatic operation
PWM Control Temperature Input Selection(PCTIS)
128 steps of PWM control when in Software operation (bit 7=0)
Bit [1:0]:
00: TMPIN1
01: TMPIN2
10: TMPIN3
11: Reserved
O
N
6-0
R/W
R/W
9.6.2.2.21
C
Bit
7-0
9.6.2.2.22
Bit
7-0
Fan Tachometer 1-3 Extended Reading Registers (Index=18h, 19h, 1Ah)
R/W
R
Description
Count Number of Internal Clock Per Revolution [15:8]
Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh, 1Ch, 1Dh)
R/W
R/W
www.ite.com.tw
Description
Limit Value [15:8]
102
IT8783F/E V0.5
Functional Description
VIN7-0 Voltage Reading Registers (Index=27h-20h)
Bit
7-0
R/W
R
9.6.2.2.24
R/W
R
TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h)
Bit
7-0
R/W
R
9.6.2.2.25.1
9.6.2.2.27
Bit
7-0
9.6.2.2.28
Temperature Reading Value (TRV)
VIN7-0 High Limit Registers (Index=3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h)
R/W
R/W
Description
High Limit Value(HLV)
VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h, 33h, 31h)
R/W
R/W
Description
Low Limit Value(LLV)
TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h)
R/W
R/W
Description
High Limit Value(HLV)
TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h)
R/W
R/W
Description
N
Bit
7-0
Description
FI
D
Bit
7-0
Description
VBAT Voltage Reading Value (VVRV)
EN
9.6.2.2.25
9.6.2.2.26
Voltage Reading Value (VRV)
VBAT Voltage Reading Register (Index=28h)
Bit
7-0
Bit
7-0
Description
TI
AL
9.6.2.2.23
ADC Voltage Channel Enable Register (Index=50h, Default=00h)
O
9.6.2.2.29
R/W
R/W
Description
ADC VIN7-0 Scan Enable(ADCVSE)
1: Enable
0: Disable
C
Bit
7-0
Low Limit Value(LLV)
www.ite.com.tw
103
IT8783F/E V0.5
IT8783E/F (For A Version)
9.6.2.2.30
ADC Temperature Channel Enable Register (Index=51h, Default=00h)
Bit
7-6
5-3
R/W
R/W
R/W
2-0
R/W
9.6.2.2.32
Bit
7
R/W
R/W
Description
Thermal Output Limit Value(TOLV)
ADC Temperature Extra Channel Enable Register (Index=55h, Default=00h)
R/W
R/W
Description
TEMPIN3 Temperature Reading Source Selection(TTRSS)
0: TEMPIN3 thermal sensor
1: External Temperature Sensor Host
FAN_CTRL2 PWM Base Clock Selection (FPWMCLKS)
000: 48MHz (PWM Frequency=375kHz)
001: 24MHz(PWM Frequency=187.5kHz)
010: 12MHz(PWM Frequency=93.75kHz)
011: 8MHz(PWM Frequency=62.5kHz)
100: 6MHz(PWM Frequency=46.875kHz)
101: 3MHz(PWM Frequency=23.43kHz)
110: 1.5MHz(PWM Frequency=11.7kHz)
111: 0.75MHz(PWM Frequency=5.86kHz)
Reserved
(Must be 0)
VIN6-4 Thermal Resistor Mode(VTRM)
VIN6-4 is enabled in the Thermal Resistor mode.
0: Disable
1: Enable
R/W
N
6-4
TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h, Default=7Fh)
EN
Bit
7-0
Description
Reserved
TMPIN Enable Thermal Mode(TETM)
TMPIN3-1 is enabled in the Thermal Resistor mode.
1: Enable
0: Disable
TMPIN Enable Diode Mode(TEDM)
TMPIN3-1 is enabled in the Thermal Diode (or Diode-connected Transistor) mode.
1: Enable
0: Disable
FI
D
9.6.2.2.31
TI
AL
TMPIN3-1 cannot be enabled in both Thermal Resistor mode and Thermal Diode (Diode connected
Transistor) mode.
R/W
2-0
R/W
C
O
3
www.ite.com.tw
104
IT8783F/E V0.5
Functional Description
9.6.2.2.33
Thermal Diode 1 Zero Degree Adjust Register (Index=56h, Default=00h)
Bit
7-0
9.6.2.2.34
R/W
R/W
Description
Thermal Diode 1 Zero Degree Voltage Value(T1DZDV)
Thermal Diode 2 Zero Degree Adjust Register (Index=57h, Default=00h)
This register is read only unless bit 7 of 5Ch is set.
9.6.2.2.35
Bit
7-0
9.6.2.2.36
R/W
R/W
Description
Thermal Diode 2 Zero Degree Voltage Value(T2DZDV)
Vendor ID Register (Index=58h, Default=90h)
R/W
R
EN
Bit
7-0
TI
AL
This register is read only unless bit 7 of 5Ch is set.
Description
ITE Vendor ID; read only (IVID)
Thermal Diode 3 Zero Degree Adjust Register (Index=59h, Default=00h)
This register is read only unless bit 7 of 5Ch is set.
9.6.2.2.37
Bit
7-0
Description
Thermal Diode 3 Zero Degree Voltage Value(T3DZDV)
Code ID Register (Index=5Bh, Default=12h)
R/W
R
Description
ITE Vendor ID; read only (IVID)
Beep Event Enable Register (Index=5Ch, Default=60h)
N
9.6.2.2.38
R/W
R/W
FI
D
Bit
7-0
R/W
R/W
6-4
R/W
C
O
Bit
7
3
2
R/W
R/W
www.ite.com.tw
Description
Thermal Diode Zero Degree Adjust Register Write Enable(TDZDARWA)
1: Enable
0: Disable
ADC Clock Selection (ADCS).
000: 500kHz
001: 250kHz
010: 125K
011: 62.5kHz
100: 31.25kHz
101: 24MHz
110: 1MHz(Default)
111: 2MHz
Reserved
Beep Enable TMPIN Exceed(BETE)
This bit can enable the beep action when TMPINs exceed the limit.
105
IT8783F/E V0.5
IT8783E/F (For A Version)
R/W
1
R/W
0
R/W
Beep Frequency Divisor of Fan Event Register (Index=5Dh, Default=00h)
Bit
7-4
R/W
R/W
3-0
R/W
9.6.2.2.40
3-0
R/W
Beep Frequency Divisor of Temperature Event Register (Index=5Fh, Default=00h)
R/W
R/W
R/W
Description
Tone Divisor(TD)
Tone=500/(bits[7:4]+1)
Frequency Divisor(FD)
Frequency=10K/(bits[3:0]+1)
N
3-0
Description
Tone Divisor(TD)
Tone=500/(bits[7:4]+1)
Frequency Divisor(FD)
Frequency=10K/(bits[3:0]+1)
FI
D
R/W
R/W
Bit
7-4
Tone Divisor(TD)
Tone=500/(bits[7:4]+1)
Frequency Divisor(FD)
Frequency=10K/(bits[3:0]+1)
Beep Frequency Divisor of Voltage Event Register (Index=5Eh, Default=00h)
Bit
7-4
9.6.2.2.41
Description
EN
9.6.2.2.39
Description
1: Enable
0: Disable
Beep Enable VIN Exceed(BEVE)
This bit can enable the beep action when VINs exceed the limit.
1: Enable
0: Disable
Beep Enable FAN_TAC Exceed(BEFE)
This bit can enable the beep action when FAN_TACs exceed the limit.
1: Enable
0: Disable
TI
AL
Bit
9.6.2.2.42
R/W
R/W
O
Bit
7-0
FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of OFF Registers
(Index=70h, 68h, 60h, Default=7Fh)
C
9.6.2.2.43
Bit
7-0
Description
Temperature Limit Value of Fan OFF(TLVFO)
FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers
(Index=71h, 69h, 61h, Default=7Fh)
R/W
R/W
www.ite.com.tw
Description
Temperature Limit Value of Fan Start(TLVFS)
106
IT8783F/E V0.5
Functional Description
9.6.2.2.44
FAN_CTL3-1 SmartGuardian Automatic Mode Start PWM Registers (Index=73h, 6Bh, 63h,
Default=00h)
FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers (Index=74h, 6Ch, 64h,
Default=00h)
Bit
7
R/W
R/W
6
5-0
R/W
R/W
Bit
7
6-5
4-0
9.6.2.2.47
FAN_CTL3-1 SmartGuardian Automatic Mode △-Temperature Registers (Index=75h, 6Dh,
65h, Default=7Fh)
R/W
R/W
R/W
Description
Reserved
Reserved
△-Temperature Interval [4:0](DeltaTI)
External Temperature Sensor Host Status Register (Index=88h, Default=---00000b)
R/W
R/W
R/WC
Description
Reserved
SST Bus Abnormal/Contention Error(SSTBAE)
This bit reports the SST/PECI line status.
0: No error
1: Abnormal/Contention error
SST Slave Message Phase T-bit Extends over Error(SSMTOE)
This bit reports the SST/PECI line status and receives error code (8000h-81FFh).
0: No error
1: Error found
SST/PECI Line High-Z Status/Failed(SLHS)
This bit reports the SST/PECI line High-Z status.
0: SST/PECI line does not drive High-Z.
1: SST/PECI line drives High-Z.
Write_FCS_ERR/ Bus Error(WFCSBE)
Writing “1” clears this bit. In the SST/PECI mode, it reports Write FCS error.
0: No Error
1: Write FCS error
N
Bit
7
6
FAN Smoothing(FANSMT)
This bit enables the FAN PWM smoothing change.
1: Enable
0: Disable
Reserved
Slope PWM Bit[5:0](SPWMB)
Slope = (Slope PWM bit[6:3] + Slope PWM bit[2:0] / 8) PWM value/℃
FI
D
9.6.2.2.46
Description
EN
9.6.2.2.45
TI
AL
For Original Fan Control Mode:
Bit
R/W
Description
7
R/W
Slope PWM Bit[6]
Please refer to FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers
(Index=74h, 6Ch, 64h, Default=00h) on page 107 for the detail.
6-0
R/W
Start PWM Value (SPWMV)
R/WC
4
R/WC
C
O
5
3
R/WC
www.ite.com.tw
107
IT8783F/E V0.5
IT8783E/F (For A Version)
R/W
R/WC
1
R/WC
0
R
9.6.2.2.49
Bit
7-0
9.6.2.2.50
Bit
7-0
9.6.2.2.51
Description
Host Target Address Register (HAddr [7:0])
This register is the Target Address field of the SST/PECI protocol.
External Temperature Sensor Host Write Length Register (Index=8Ah, Default=00h)
R/W
R/W
Description
Host Write Length Register (HW_length [7:0])
This register is the Write Length field of the SST/PECI protocol.
External Temperature Sensor Host Read Length Register (Index=8Bh, Default=00h)
R/W
R/W
Description
Host Read Length Register (HR_length [7:0])
This register is the Read Length field of the SST/PECI protocol.
External Temperature Sensor Host Command (Write Data 1) Register (Index=8Ch,
Default=00h)
R/W
R/W
Description
Host Command Register (HCMD [7:0])
This register is the command field of the protocol. In the PECI/SST mode, it is the
command (Write Data 1) byte.
O
N
Bit
7-0
R/W
R/W
EN
Bit
7-0
External Temperature Sensor Host Target Address Register (Index=89h, Default=00h)
FI
D
9.6.2.2.48
Description
Read_FCS_ERR/ Device Error(RFEE)
In the SST/PECI mode, it reports Read FCS error.
0: No Error
1: Read FCS error
Finish (FNSH)
Writing “1” clears this bit.
0: None
1: This bit is set when the stop condition is detected.
Host Busy (BUSY)
0: The current transaction is completed.
1: This bit is set while the command is in operation.
TI
AL
Bit
2
9.6.2.2.52
R/W
R/W
C
Bit
7-0
External Temperature Sensor Write Data (2-8) Register (Index=8Dh, Default=--h)
www.ite.com.tw
Description
Write Data (2-8) [7:0] (in SST/PECI mode)
This is a 7-byte FIFO register and only valid in the PECI/SST mode.
108
IT8783F/E V0.5
Functional Description
9.6.2.2.53
External Temperature Sensor Host Control Register (Index=8Eh, Default=01h)
R/W
Description
R/W
5
R/W
4
R/W
3
R/W
Auto-Start Control (Auto-START)
The host will start the transaction in a regular rate automatically.
00: 32 Hz
01: 16 Hz
10: 8 Hz
11: 4 Hz
Auto-Start (Auto-START)
1: Enable
0: Disable
The host will start the transaction in a regular rate, which is determined by bit 7-6
automatically.
SST/PECI Host Auto-abort at FCS Error(HAA)
This bit enables the SST/PECI host to abort the transaction when an error occurs to
FCS.
1: Enable
0: Disable
Data FIFO Pointer Clear(DFPC)
Writing “1” clears the Read/Write Data FIFO pointers.
0: No action
It always reports 0 when reading it.
1: Both Read and Write Data FIFO pointers cleared
Read Data register will point to Read Data 1, and Write Data register will point to Write
Data 2.
SST Contention Control(SCC)
This bit enables the SST bus contention control.
0: Disable
1: Enable
When the SST bus is contentious, the host will abort the transaction.
SST_idel_high
This bit sets the SST bus idle-high in the SST host mode.
0: SST idle low
1: SST idle high
Start (START)
This bit is write-only. Writing 0 to it during transaction will issue a “kill process” and bit 4
of 8Bh register will be set. Writing 1 to it during the “NOT BUSY” state (bit 0 of 88h=0)
will start a transaction. Writing 1 to it during the “BUSY” state (bit 0 of 88h=1) will not
issue any transaction. So, the programmer should check the “BUSY” status before
issuing a transaction.
0: This bit always returns 0 at read.
1: When this bit is set, the host controller will perform the transaction.
1
R/W
R/W
R/W
EN
C
O
N
0
FI
D
2
TI
AL
Bit
7-6
www.ite.com.tw
109
IT8783F/E V0.5
IT8783E/F (For A Version)
9.6.3.1
Operation
Power on Reset and Software Reset
TI
AL
9.6.3
When the system power is first applied, the Environment Controller performs “power on reset” on the
registers, making them return to their individual default values during a system hardware reset, and the EC
will acquire a monitored value before it goes inactive. The ADC is activated to monitor the VBAT pin and then
goes inactive. A software reset through bit 7 of Configuration Register (Index=00h, Default=18h) (refer to
page 97) performs the same functions as the hardware reset except the function of the Serial Bus Interface
Address register.
9.6.3.2
Starting Conversion
1.
2.
3.
EN
The monitoring function in the EC is activated when bit 3 of Configuration Register is cleared (low) and bit 0
of Configuration Register is set (high). Otherwise, this function will be enabled by setting several enabled bits,
which are categorized into three groups, positive voltages, temperatures and FAN Tachometer inputs. Before
the EC monitoring function is able to be executed then the monitoring process can then be started.
Set the limits.
Set the interrupt masks.
Set the enable bits.
Figure 9-4. Application Example
VREF
+
VREF
FI
D
Rc=10
K
Constant Voltage
Tin
Tin
TD
C
VS
TMPIN1
TMPIN2
TMPIN3
TD-
Vin
N
O
(-12V,-5V)
Rt
TD
TD-
VS
Tin
Vin
Rin
Rf
VREF
Vin
Ra
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
ADC and
MUX
VBAT
Rb
Battery Voltage
Note: The resistor should provide approximately 2V at the Analog Inputs.
www.ite.com.tw
110
IT8783F/E V0.5
Functional Description
9.6.3.3
Voltage and Temperature Inputs
C
O
N
FI
D
EN
TI
AL
The 8-bit ADC has a 16mV LSB with an input range from 0V to 4.096V. The 2.5V and 3.3V supplies of PC
applications can be directly connected to the inputs. It is necessary to divide the 5V and 12V inputs into an
acceptable range. When the divided circuit is used to measure the positive voltage, the recommended range
for Ra and Rb is from 10KΩ to 100KΩ. The negative voltage can be measured by the same divider, which is
connected to VREF (constant voltage, 4.096V), and do not attempt to measure it with the divider connected
to the ground. The EC temperature measurement system converts the voltage of the TMPINs to 8-bit two’scomplement. The system also includes an OP amp providing a constant voltage, an external thermistor, a
constant resistance, the ADC and a conversion table ROM..
www.ite.com.tw
111
IT8783F/E V0.5
IT8783E/F (For A Version)
Temperature
Digital Output Format
Hex
+ 125°C
01111101
7Dh
+ 25°C
00011001
+ 1° C
00000001
+ 0° C
00000000
- 1° C
11111111
- 25°C
11100111
- 55°C
11001001
TI
AL
Binary
19h
01h
00h
FFh
E7h
C9h
With the addition of the external application circuit, the actual voltages are calculated below:
EN
Positive Voltage: Vs = Vin X (Ra+Rb) / Rb
Negative Voltage: Vs = (1+Rin/Rf) X Vin – (Rin/Rf) X VREF
All the analog inputs are equipped with the internal diodes that clamp the input voltage exceeding the power
supply and ground; nevertheless, the current limiting input resistor is recommended since no dividing circuit is
available.
9.6.3.4
Layout and Grounding
FI
D
A separate and low-impedance ground plane for analog ground is essential to achieve accurate
measurement. The analog ground also provides a ground point for the voltage dividers including the
temperature loops and analog components. Analog components such as voltage dividers, feedback resistors
and the constant resistors of the temperature loops should be located as closely as possible to IT8783E/F.
However, the thermistors of the temperature loops should be positioned within the measuring area. In
addition, the power supply bypass and the parallel combination of 10μF and 0.1μF bypass capacitors
connected between VCC and analog ground also need to be located as closely as possible to IT8783E/F.
Due to the small differential voltage of thermal diode (diode-connected transistor), designers should adhere to
the following PCB layout:
Position the sensor as closely as possible to the EC.
The sensor ground should be directly shorted to GNDA with excellent noise immunity.
Keep traces away from any noise sources. (High voltage, fast data bus, fast clock , CRTs …)
Use trace width of 10 mil minimum and provide guard ground (flanking and under)
Position 0.1μF bypass capacitors as closely as possible to IT8783E/F.
N
−
−
−
−
O
−
9.6.3.5
Fan Tachometer
C
The Fan Tachometer inputs gate a 22.5 kHz clock into an 8-bit or 16-bit counter (maximum count=255 or
65535) for one period of the input signals. Counts are based on two pulses per revolution for tachometer
output.
RPM = 1.35 X 106 / (Count X Divisor) ; (Default Divisor = 2)
The maximum input signal range is from 0 to VCC. An additional external circuit is needed to clamp the input
voltage and current.
www.ite.com.tw
112
IT8783F/E V0.5
Functional Description
9.6.3.6
Interrupt of the EC
TI
AL
The EC generates interrupts as a result of each of its Limit registers on the analog voltage, temperature, and
FAN monitor. All the interrupts are indicated in two Interrupt Status Registers. The IRQ and SMI# outputs
have individual mask registers. These two Interrupts can also be enabled/disabled by Configuration Register
(Index=00h, Default=18h) (refer to page 97). The Interrupt Status Registers will be reset after a read
operation. When the Interrupt Status Registers are cleared, the Interrupt lines will also be cleared. When a
read operation is completed before the completion of the monitoring loop sequence, it indicates an Interrupt
Status Register has been cleared. It takes EC 1.5 seconds to allow all the EC Registers to be safely updated
between completed read operations. When bit 3 of the Configuration Register is set to high, the Interrupt lines
are cleared and the monitoring loop will be stopped. The loop will resume after this bit is cleared.
All analog voltage inputs have both high and low Limit Registers to generate interrupts whereas FAN
monitoring inputs only have low Limit Register to warn the host. The IT8783E/F provides three modes
dedicated to temperature interrupts in the EC: “Interrupt” mode, “Enhanced Interrupt” mode and “Comparator”
mode.
EN
Interrupt Mode
An interrupt will be generated whenever the temperature exceeds Th limit, and the corresponding interrupt
status bits will be set to high until being reset by reading Interrupt Status Register 3 (Index=03h, Default=00h)
(refer to page 98). Once an interrupt event occurs by exceeding Th limit, an interrupt will only occur again
when the temperature goes below TL limit after being reset. Again, it will set the corresponding status bit to
high until being reset by reading Interrupt Status Register 3 (Index=03h, Default=00h) (refer to page 98).
FI
D
Enhanced Interrupt Mode
When the enhanced interrupt mode is enabled (bit 3, 6 and 7 of EC index 0Ch for TMPIN1, 2, and 3
respectively), an interrupt will be generated when the temperature is higher than the high limit or lower than
the low limit.
When the enhanced interrupt mode is enabled (bit 3, 6 and 7 of Fan Tachometer 16-bit Counter Enable
Register (Index=0Ch, Default=00h) for TMPIN1, 2, and 3 respectively) (refer to page 100), an interrupt will be
generated when the temperature is higher than the high limit or lower than the low limit.
C
O
N
Comparator Mode
This mode is entered when the TL limit register is set to 127°C. In this mode, an interrupt will be generated
whenever the temperature exceeds the Th limit. The interrupt will also be cleared by reading Interrupt Status
Register 3 (Index=03h, Default=00h) (refer to page 98), but the interrupt will be set again following the
completion of another measurement cycle. It will remain set until the temperature goes below the Th limit.
www.ite.com.tw
113
IT8783F/E V0.5
IT8783E/F (For A Version)
Figure 9-5. Temperature Interrupt Response Diagram
TI
AL
Th
TL
Temperature
Interrupt
Time
(a) Interrupt Mode
TL
Temperature
Interrupt
EN
Th
FI
D
Time
(b) Enhanced Interrupt Mode
o
TL = 127 C
Th
N
Temperature
Interrupt
FAN Controller FAN_CTL’s ON-OFF and SmartGuardian Modes
O
9.6.3.7
Time
(c) Comparator Mode
C
The IT8783E/F provides an advanced FAN Controller. Two modes, ON_OFF and SmartGuardian, are
provided for each controller. The former is a logical ON or OFF, and the latter is a PWM output. With the
addition of external application circuits, the FAN’s voltage values can be varied easily.
In the SmartGuardian Mode, there is only one operational choice, software control.
While under software control, the PWM value is subject to the changes in the values of bit 6-0 of FAN_CTL 13 PWM Control Registers (Index=15h, 16h, 17h). With the application circuits, FAN_CTL can generate 128
steps of voltage. So, FAN_CTL 1-3 PWM Control Registers can vary the voltage by changing the PWM value.
Fan speeds or other voltage control cooling devices can be varied in 128 steps.
www.ite.com.tw
114
IT8783F/E V0.5
Functional Description
9.7
9.7.1
Floppy Disk Controller (FDC)
Introduction
TI
AL
The Floppy Disk Controller provides the interface between a host processor and up to two floppy disk drives.
It integrates a controller and a digital data separator with write precompensation, data rate selection logic,
microprocessor interface, and a set of registers.
The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It operates in the
PC/AT mode and supports the 3-mode type drive. Additionally, the FDC is software compatible with the
82077.
The FDC can be configured by software and a set of configuration registers. The status, data, and control
registers facilitate the interface between the host microprocessor and the disk drive, providing information
about the condition and/or state of the FDC. These configuration registers can select the data rate, enable
interrupts, drives, and DMA modes, and indicate errors of the data or operation of the FDC/FDD.
9.7.2
Reset
EN
The controller manages data transfer using a set of data transfer and control commands, which are
processed in three phases, Command, Execution, and Result, but not all of them will be utilized.
The IT8783E/F device implements both software and hardware reset options for the FDC. Either option will
reset the FDC, terminating all operations and making the FDC entering an idle state. A reset during a write to
the disk will disorder the data and the corresponding CRC.
Hardware Reset (LRESET# Pin)
FI
D
9.7.3
When the FDC receives an LRESET# signal, all registers of the FDC core will be cleared, except those
programmed by the SPECIFY command. To exit the reset state, the host must clear the DOR bit.
9.7.4
Software Reset (DOR Reset and DSR Reset)
When the reset bit in the DOR or the DSR is set, all registers of the FDC core will be cleared. A reset
performed by setting the reset bit in the DOR has a higher priority over a reset performed by setting the reset
bit in the DSR. In addition, to exit the reset state, the DSR bit will be self-cleared when the host clears the
DOR bit.
Digital Data Separator
N
9.7.5
O
The internal digital data separator is comprised of a digital PLL and associated support circuitry. It is
responsible for synchronizing the raw data signal read from the floppy disk drive. The synchronized signal is
to separate the encoded clock from data pulses.
9.7.6
Write Precompensation
C
Write precompensation is a method to adjust the effects of bit shifting on data as it is written to the disk. It is
harder for the data separator to read data that have been subject to bit shifting. Soft read errors can occur
due to such bit shifting. Write precompensation predicts where the bit shifting might occur within a data
pattern and shifts the individual data bits back to their nominal positions.
Write precompensation can be selected by bit 4-2 of Data Rate Select Register (DSR, FDC Base Address +
04h) (refer to page 117).
www.ite.com.tw
115
IT8783F/E V0.5
IT8783E/F (For A Version)
9.7.7
Data Rate Selection
9.7.8
9.7.8.1
TI
AL
Selecting one of the four possible data rates for the floppy disk can be achieved by setting bit 1-0 of Data
Rate Select Register (DSR, FDC Base Address + 04h) (refer to page 117) or Diskette Control Register (DCR,
FDC Base Address + 07h) (refer to page 119). The data rate is determined by the last value written to either
DSR or DCR. After the data rate is set, the data separator clock will be scaled appropriately.
Status, Data and Control Registers
Digital Output Register (DOR, FDC Base Address + 02h)
This is a read/write register, which controls drive selection as well as motor, software reset, and DMA enable.
The I/O interface reset may be used anytime to clear DOR’s contents.
4
MOTA EN
3
DMAEN
2
RESET#
1
0
9.7.8.2
Description
Reserved
Drive B Motor Enable(MOTBEN)
1: Enable
0: Disable
Drive A Motor Enable(MOTAEN)
1: Enable
0: Disable
Disk Interrupt and DMA Enable(DMAEN)
1: Enable
0: Disable (DRQx, DACKx#, TC and INTx)
FDC Function Reset(RESET)
0: Function reset
1: Function of reset cleared
This reset has no impact on the DSR, DCR or DOR.
Reserved
Drive Selection(DVSEL)
0: Drive A selected
1: Drive B selected
EN
Symbol
MOTB EN
FI
D
Bit
7-6
5
DVSEL
Tape Drive Register (TDR, FDC Base Address + 03h)
N
This is a read/write register compatible with 82077 software. The contents of this register are not used
internally for the device.
Symbol
Reserved
TP_SEL[1:0] Tape Drive Selection(TPSEL)
TP_SEL[1:0]: Drive selected
00: None
01: 1
10: 2
11: 3
Description
C
O
Bit
7-2
1-0
9.7.8.3
Main Status Register (MSR, FDC Base Address + 04h)
This is a read only register, which indicates the general status of the FDC, and is able to receive data from
the host. The MSR should be read before each byte is sent to or received from the Data register, except
www.ite.com.tw
116
IT8783F/E V0.5
Functional Description
when it is in the DMA mode.
DIO
5
NDM
4
CB
3-2
1
DBB
0
DAB
9.7.8.4
Request for Master(RQM)
0: The FDC is busy and cannot receive data from the host.
1: The FDC is ready and can receive data from the host.
Data I/O Direction(DIO)
It indicates the direction of data transfer once an RQM has been set.
0: Write
1: Read
Non-DMA Mode(NDM)
0: DMA mode selected
1: Non-DMA mode selected
This mode is selected via the SPECIFY command during the command Execution
phase.
Diskette Control Busy(CB)
It indicates whether a command is in progress (FDD busy) or not.
0: A command has been executed and the end of the Result phase reached.
1: A command is being executed.
Reserved
Drive B Busy(DBB)
It indicates whether Drive B is in the SEEK portion of a command.
0: Not busy
1: Busy
Drive A Busy(DAB)
It indicates whether Drive A is in the SEEK portion of a command.
0: Not busy
1: Busy
TI
AL
6
Description
EN
Symbol
RQM
FI
D
Bit
7
Data Rate Select Register (DSR, FDC Base Address + 04h)
N
This is a write only register, which determines the data rate, write precompensation selection,
power-down mode, and software reset. The data rate of the FDC is determined by the last value written to
either DSR or DCR. The DSR is unaffected by a software reset and can be set to “02h” by a hardware reset.
The “02h” represents the default precompensation, and 250 Kbps indicates the data transfer rate.
Symbol
Description
S/W RESET Software Reset(SWRESET)
It is active high and has the same function as the RESET# of the DOR except that this bit
is self-cleared.
POWER
Power-Down(POWERDOWN)
DOWN
When “1” is written to this bit, the FDC will enter the manually low-power mode. The
clocks of the FDC and data separator circuits will be turned off until software reset, Data
Register or Main Status Register is accessed.
Reserved
PREPrecompensation Select(PRECOMP)
COMP 2-0 These three bits are to determine the value of write precompensation that will be applied
to the WDATA# pin. Track 0 is the default of the starting track number, which can be
changed by the CONFIGURE command for precompensation.
O
Bit
7
6
C
5
4-2
PRE_COMP
www.ite.com.tw
Precompensation Delay
117
IT8783F/E V0.5
IT8783E/F (For A Version)
Symbol
Description
111
001
010
011
100
101
110
000
0.0 ns
41.7 ns
83.3 ns
125.0 ns
166.7 ns
208.3 ns
250.0 ns
Default
TI
AL
Bit
1-0
DRATE1-0
EN
Default Precompensation Delay
Data Rate
Precompensation Delay
1 Mbps
41.7 ns
500 Kbps
125.0 ns
300 Kbps
125.0 ns
250 Kbps
125.0 ns
Data Rate Select(DRATE)
Data Transfer Rate
500 Kbps
300 Kbps
250 Kbps (Default)
1 Mbps
C
O
N
FI
D
Bit 1-0
00
01
10
11
www.ite.com.tw
118
IT8783F/E V0.5
Functional Description
9.7.8.5
Data Register (FIFO, FDC Base Address + 05h)
Bit
7-0
9.7.8.6
Symbol
-
TI
AL
This is an 8-bit read/write register, which transfers command information, diskette drive status information,
and the result phase status between the host and the FDC. The FIFO consists of several registers in a stack.
Only one register in the stack is permitted to transfer the information or status to the data bus at a time.
Description
Data(DATA)
Command information, diskette drive status, or result phase status data.
Digital Input Register (DIR, FDC Base Address + 07h)
This is a read only register, which shares this address with Diskette Control Register (DCR, FDC Base
Address + 07h).
Symbol
DSKCHG
6-0
-
9.7.8.7
Description
EN
Bit
7
Diskette Change(DSKCHG)
It indicates the inverting value of the bit monitored from the input of the Floppy Disk
Change pin (DSKCHG#).
Reserved
Diskette Control Register (DCR, FDC Base Address + 07h)
Bit
7-2
Symbol
-
DRATE1-0
Description
Reserved
Always 0
Data Rate Select(DRATE)
Bit 1-0
Data Transfer Rate
00
500 Kbps
01
300 Kbps
10
250 Kbps
11
1 Mbps
N
1-0
FI
D
This is a write only register, which shares this address with Digital Input Register (DIR, FDC Base Address +
07h) and controls the data transfer rate for the FDC.
9.7.9
Controller Phases
O
The FDC is to process data transfer and control commands in three phases, Command, Execution and
Result, and not all of them will be utilized.
9.7.9.1
Command Phase
C
Upon reset, the FDC enters the Command phase and is ready to receive commands from the host. The host
must verify that Main Status Register (MSR, FDC Base Address + 04h) bit 7 (RQM) = 1 and bit 6 (DIO) = 0
(refer to page 116), indicating the FDC is ready to receive data. For each command, a defined set of
command code and parameter bytes must be transferred to the FDC in a given order. Refer to section 9.7.11
Data Transfer Command on page 132 and 9.7.12 Control Command on page 135 for details of various
commands. RQM is set false (0) after each byte-Read cycle, and set true (1) when a new parameter byte is
required. The Command phase is completed when this set of bytes has been received by the FDC. The FDC
automatically enters the next controller phase and the FIFO is disabled.
www.ite.com.tw
IT8783F/E V0.5
119
IT8783E/F (For A Version)
9.7.9.2
Execution Phase
9.7.9.3
TI
AL
Upon the completion of the Command phase, the FDC enters the Execution phase. It is in this phase that all
data transfer occurs between the host and the FDC. The SPECIFY command indicates whether this data
transfer occurs in the DMA or non-DMA mode. Each data byte is transferred via an IRQx or DRQx# based
upon the DMA mode. On reset, the CONFIGURE command can automatically enable or disable the FIFO.
The Execution phase is completed when all data bytes have been received. If the command executed does
not require a Result phase, the FDC is ready to receive the next command.
Result Phase
9.7.9.4
EN
For commands that require data written to the FIFO, the FDC enters the Result phase when the IRQ or DRQ
is activated. Bit 7 (RQM) and bit 6 (DIO) of Main Status Register (MSR, FDC Base Address + 04h) must
equal 1 to read the data bytes. The Result phase is completed when the host has read each of the defined
set of result bytes for the given command. Right after the completion of the phase, RQM is set to 1, DIO is set
to 0, and the MSR bit 4 (CB) is cleared, indicating the FDC is ready to receive the next command.
Result Phase Status Registers
For commands containing a Result phase, these read only registers indicate the status of the latest executed
command.
Table 9-4. Status Register 0 (ST0)
5
4
Description
Interrupt Code(IC)
00: The execution of the command has been completed successfully.
01: The execution of the command is activated but fails to be completed
successfully.
10: It means an invalid command.
11: The execution of the command is not completed successfully due to a polling
error.
Seek End(SE)
The FDC executes a SEEK or RE-CALIBRATE command.
Equipment Check(EC)
The TRK0# pin is not set after a RE-CALIBRATE command is issued.
Not Used(NU)
Head Address(HA)
The current head address
Drive B Select(DSB)
0: Disable
1: Enable
Drive A Select(DSA)
0: Disable
1: Enable
SE
EC
NU
H
N
3
2
Symbol
IC
FI
D
Bit
7-6
DSB
O
1
DSA
C
0
www.ite.com.tw
120
IT8783F/E V0.5
Functional Description
Table 9-5. Status Register 1 (ST1)
NU
DE
4
OR
3
2
NU
ND
1
NW
0
MA
End of Cylinder(EN)
It indicates the FDC attempts to access a sector beyond the final sector of the track.
This bit will be set if the Terminal Count (TC) signal is not issued after a READ
DATA or WRITE DATA command.
Not Used(NU)
Data Error(DE)
A CRC error occurs in either the ID field or the data field of a sector.
Overrun / Underrun(OR)
An overrun on a READ operation or underrun on a WRITE operation occurs when
the FDC is not serviced by CPU or DMA within the required time interval.
Not Used(NU)
No Data(ND)
No data are available for the FDC when any of the following conditions occurs:
• The floppy disk cannot find the indicated sector while the READ DATA or READ
DELETED DATA commands are being executed.
• While a READ ID command is being executed, an error occurs upon reading the
ID field.
• While a READ A TRACK command is being executed, the FDC cannot find the
starting sector.
Not Writeable(NW)
It is set when WRITE DATA, WRITE DELETED DATA, or FORMAT A TRACK
command is being executed on a write-protected diskette.
Missing Address Mark(MA)
This flag bit is set when either of the following conditions is met:
• The FDC cannot find a Data Address Mark or a Deleted Data Address Mark on
the specified track.
• The FDC cannot find any ID address on the specified track after two index pulses
are detected from the INDEX# pin.
TI
AL
6
5
Description
EN
Symbol
EN
FI
D
Bit
7
Table 9-6. Status Register 2 (ST2)
Symbol
NU
CM
Description
Not Used(NU)
Control Mark(CM)
This flag bit is set when either of the following conditions is met:
• The FDC finds a Deleted Data Address Mark during a READ DATA command.
• The FDC finds a Data Address Mark during a READ DELETED DATA command.
Data Error in Data Field(DD)
This flag bit is set when a CRC error is found in the data field.
Wrong Cylinder(WC)
This flag bit is set when the track address in the ID field is different from the track
address specified in the FDC.
Scan Equal Hit(SH)
This flag bit is set when the condition of "equal" is satisfied during a SCAN
command.
Scan Not Satisfied(SN)
This flag bit is set when the FDC cannot find a sector on the cylinder during a SCAN
command.
N
Bit
7
6
DD
O
5
WC
3
SH
C
4
2
SN
www.ite.com.tw
121
IT8783F/E V0.5
IT8783E/F (For A Version)
Symbol
BC
0
MD
Description
Bad Cylinder(BC)
This flag bit is set when the track address equals to “FFh” and is different from the
track address in the FDC.
Missing Data Address Mark(MD)
This flag bit is set when the FDC cannot find a Data Address Mark or Deleted Data
Address Mark.
TI
AL
Bit
1
Table 9-7. Status Register 3 (ST3)
6
WP
5
RDY
4
TK0
3
TS
2
HD
1-0
US1, US0
9.7.10
Description
Fault(FT)
It indicates the current status of the Fault signal from the FDD.
Write Protect(WP)
It indicates the current status of the Write Protect signal from the FDD.
Ready(RDY)
It indicates the current status of the Ready signal from the FDD.
Track 0(TK0)
It indicates the current status of the Track 0 signal from the FDD.
Two Side(TS)
It indicates the current status of the Two Side signal from the FDD.
Head Address(HD)
It indicates the current status of the Head Address signal to the FDD.
Unit Select(US)
It indicates the current status of the Unit Select signal to the FDD.
EN
Symbol
FT
FI
D
Bit
7
Command Set
The FDC utilizes a defined set of commands to communicate with the host. Each command is comprised of a
unique first byte containing the op-code and a series of additional bytes containing the required set of
parameters and results. For the description of the common set of parameter byte symbols, please refer to the
following table. The FDC commands may be executed whenever it is in the Command phase and will check
whether the first byte is a valid command or not. If yes, it will proceed. If not, an interrupt will be issued.
Table 9-8. Command Set Symbol
Description
Cylinder Number(CN)
The current/selected cylinder (track) number, 0-255.
D
Data(D)
The data pattern to be written into a sector.
DC3−DC0 Drive Configuration Bit3-0(DC)
Designate which drives are the perpendicular drives on the PERPENDICULAR MODE
command.
DIR
Direction Control(DIR)
Head Step Direction Control of Read/Write.
0: Step out
1: Step in
DR0, DR1 Disk Drive Selection(DR)
The selected drive number, 0 or 1.
DTL
Data Length(DTL)
When N is defined as 00h, DTL designates the number of data bytes to be read out or written
into the Sector. When N is not 00h, DTL is undefined.
www.ite.com.tw
IT8783F/E V0.5
122
C
O
N
Symbol
C
Functional Description
EOT
GAP2
GPL
H
HD
HLT
HUT
LOCK
MFM
N
MT
TI
AL
EIS
Disable FIFO(DFIFO)
0: Enable
1: Disable (Default)
Enable Count(EC)
If EC=1, DTL of VERIFY command will be SC.
Enable Implied Seek(EIS)
If EIS=1, a SEEK operation will be performed before executing any READ or WRITE command
that requires the C parameter.
End of Track(EOT)
This is the final sector number on a cylinder. During a READ or WRITE operation, the FDC stops
data transfer after the sector number is equal to EOT.
Gap 2 Length(GAP)
By PERPENDICULAR MODE command, this parameter changes the length format of Gap 2.
Gap Length(GPL)
During a FORMAT command, it determines the length of Gap 3.
Head Address(H)
The Head number, 0 or 1, as specified in the sector ID field. (H = HD in all command words.)
Head(HD)
The selected Head number, 0 or 1. It also controls the polarity of HDSEL#. (H = HD in all
command words.)
Head Load Time(HLT)
The Head Load Time in the FDD (2 to 254 ms in 2 ms increments).
Head Unload Time(HUT)
The Head Unload Time after a READ or WRITE operation has been executed (16 to 240 ms in
16 ms increments).
LOCK(LOCK)
If LOCK=1, DFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command will not
be affected by a software reset. If LOCK=0 (default), the above parameters will be set to their
default values following a software reset.
FM or MFM Mode(MFM)
If MFM is low, FM mode (single density) is selected. If MFM is high, MFM mode (double density)
is selected.
Multi-Track(MT)
If MT is high, a Multi-Track operation will be performed. In this mode, the FDC will automatically
start searching for sector 1 on side 1 after finishing a READ/WRITE operation in the last sector
on side 0.
Number(N)
The number of data bytes written into a sector, where:
00: 128 bytes (PC standard)
01: 256 bytes
02: 512 bytes
…
07: 16 Kbytes
New Cylinder Number(NCN)
A new cylinder number, which is to be reached as a result of the SEEK operation. Desired
position of Head.
Non-DMA Mode(ND)
When ND is high, the FDC operates in the Non-DMA mode.
Overwrite(OW)
If OW=1, DC3-0 of the PERPENDICULAR MODE command can be modified. Otherwise, those
bits cannot be changed.
EN
EC
Description
FI
D
Symbol
DFIFO
O
N
C
NCN
ND
OW
www.ite.com.tw
123
IT8783F/E V0.5
IT8783E/F (For A Version)
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
C
O
N
STP
TI
AL
PRETRK
EN
POLLD
Description
Present Cylinder Number(PCN)
This is the cylinder number at the completion of a SENSE INTERRUPT STATUS command,
indicating the present head position
Polling Disable(POLLD)
If POLLD=1, the internal polling routine is disabled.
Precompensation Starting Track Number(PRETRK)
Programmable from track 0-255.
Record(R )
The sector number to be read or written.
Relative Cylinder Number(RCN)
To determine the relative cylinder offset from the present cylinder used by the RELATIVE SEEK
command.
Number of Sector Per Cylinder(SC)
Skip(SK)
If SK=1, the Read Data operation will skip sectors with a Deleted Data Address Mark. Otherwise,
the Read Deleted Data operation only accesses sectors with a Deleted Data Address Mark.
Step Rate Time(SRT)
The Stepping Rate for the FDD (1 to 16 ms in 1 ms increments). The stepping rate is applied to
all drives (F=1 ms, E=2 ms, etc.).
Status 0(ST0)
Status 1(ST1)
Status 2(ST2)
Status 3(ST3)
ST0-3 stand for one of four registers that store the status information after a command has been
executed. This information is available during the Result phase after command execution. These
registers should not be confused with the Main Status Register (MSR, FDC Base Address + 04h)
(refer to page 116) (selected by A0 = 0). ST0-3 may be read only after a command has been
executed and contains information associated with that particular command.
STP
If STP = 1 during a SCAN operation, the data in contiguous sectors are compared byte by byte
with data sent from the processor (or DMA). If STP = 2, alternate sectors are read and
compared.
FI
D
Symbol
PCN
www.ite.com.tw
124
IT8783F/E V0.5
Functional Description
Table 9-9. Command Set Summary
Command
D7
D6
D5
W
MT
MFM
SK
0
0
1
W
0
0
0
0
0
HDS
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
ST1
R
ST2
R
C
R
Sector ID information after command
execution
H
R
R
N
FI
D
R
READ DELETED DATA
Data Bus
D4
D3
D2
D1
D7
D6
D5
W
MT
MFM
SK
0
W
0
0
0
0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
N
Command
O
C
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
www.ite.com.tw
D0
1
1
0
0
0
HDS
DR1
DR0
Execution
Result
Command Codes
Data transfer between the FDD and
the main system
Status information after command
execution
ST0
R
Phase R/W
0
DR0
EN
R
1
DR1
Sector ID information before the
command execution
Execution
Result
Remarks
D0
TI
AL
Phase R/W
READ DATA
Data Bus
D4
D3
D2
D1
Remarks
Command Codes
Sector ID information before the
command execution
Data transfer between the FDD and
the main system
Status information after command
execution
Sector ID information after command
execution
125
IT8783F/E V0.5
IT8783E/F (For A Version)
Command
D7
D6
D5
W
0
MFM
0
0
W
0
0
0
0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
0
0
0
HDS
ST2
R
C
R
Sector ID information after command
execution
H
R
R
N
FI
D
R
WRITE DATA
Data Bus
D4
D3
D2
D1
D7
D6
D5
W
MT
MFM
0
0
W
0
0
0
0
W
C
W
H
W
R
N
W
1
0
1
0
HDS
DR1
DR0
EOT
W
GPL
W
DTL
O
C
Remarks
Command Codes
Sector ID information before the
command execution
N
W
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
www.ite.com.tw
D0
0
Execution
Result
DR0
ST1
R
Command
DR1
Command Codes
Data transfer between the FDD and
main system cylinder's contents from
index hole to EOT
Status information after command
execution
ST0
R
Phase R/W
0
EN
R
1
Sector ID information before the
command execution
Execution
Result
Remarks
D0
TI
AL
Phase R/W
READ A TRACK
Data Bus
D4
D3
D2
D1
Data transfer between the FDD and
the main system
Status information after command
execution
Sector ID information after command
execution
126
IT8783F/E V0.5
Functional Description
Command
D7
D6
D5
W
MT
MFM
0
0
1
0
W
0
0
0
0
0
HDS
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
ST0
R
ST1
R
R
N
D7
D6
D5
W
0
MFM
0
0
1
1
0
1
W
0
0
0
0
0
HDS
DR1
DR0
W
N
Remarks
D0
Command Codes
Bytes/Sector
SC
W
GPL
Gap 3
W
W
W
W
W
R
D
C
H
R
N
ST0
Filler Byte
Input Sector Parameters per-sector
FDC formats an entire cylinder
R
ST1
N
W
O
C
FORMAT A TRACK
Data Bus
D4
D3
D2
D1
FI
D
R
Result
Sector ID information after command
execution
H
R
Execution
Data transfer between the FDD and
the main system
Status information after command
execution
C
R
Command
Command Codes
ST2
R
Phase R/W
1
DR0
EN
R
0
DR1
Sector ID information before the
command execution
Execution
Result
Remarks
D0
TI
AL
Phase R/W
WRITE DELETED DATA
Data Bus
D4
D3
D2
D1
R
ST2
R
Undefined
R
Undefined
R
Undefined
R
Undefined
www.ite.com.tw
Sectors/Cylinder
Status information after command
execution
127
IT8783F/E V0.5
IT8783E/F (For A Version)
Command
D7
D6
D5
W
MT
MFM
SK
1
W
0
0
0
0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
0
0
0
HDS
ST2
R
C
R
Sector ID information after command
execution
H
R
R
N
FI
D
R
SCAN LOW OR EQUAL
Data Bus
D4
D3
D2
D1
D7
D6
D5
W
MT
MFM
SK
1
W
0
0
0
0
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
N
W
O
C
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
www.ite.com.tw
D0
1
0
0
1
0
HDS
DR1
DR0
Execution
Result
DR0
ST1
R
Command
DR1
Command Codes
Data transferred from the system to
controller is compared to data read
from disk
Status information after command
execution
ST0
R
Phase R/W
1
EN
R
0
Sector ID information before the
command execution
Execution
Result
Remarks
D0
TI
AL
Phase R/W
SCAN EQUAL
Data Bus
D4
D3
D2
D1
Remarks
Command Codes
Sector ID information before the
command execution
Data transferred from the system to
controller is compared to data read
from disk
Status information after command
execution
Sector ID information after command
execution
128
IT8783F/E V0.5
Functional Description
Command
D7
D6
D5
W
MT
MFM
SK
1
1
1
W
0
0
0
0
0
HDS
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
0
1
DR1
DR0
Command Codes
Sector ID information before the
command execution
Data transferred from the system to
controller is compared to data read
from disk
Status information after command
execution
EN
Execution
Result
Remarks
D0
TI
AL
Phase R/W
SCAN HIGH OR EQUAL
Data Bus
D4
D3
D2
D1
R
ST0
R
ST1
R
ST2
R
C
R
Sector ID information after command
execution
H
R
R
N
FI
D
R
VERIFY
Phase R/W
D6
D5
W
MT
MFM
SK
1
W
EC
0
0
0
W
C
W
H
N
Command
Data Bus
D4
D3
D7
W
N
W
EOT
O
W
D1
D0
0
1
1
0
0
HDS
DR1
DR0
C
Sector ID information before the
command execution
GPL
No data transfer takes place
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
www.ite.com.tw
Command Codes
DTL/SC
Execution
Result
Remarks
R
W
W
D2
Status information after command
execution
Sector ID information after command
execution
129
IT8783F/E V0.5
IT8783E/F (For A Version)
Command
D7
D6
D5
W
0
MFM
0
0
1
0
W
0
0
0
0
0
HDS
Execution
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
Phase R/W
Command
D7
D6
D5
W
0
0
0
W
0
0
W
0
EIS
0
D0
1
0
DR1
DR0
Remarks
Command Codes
The first correct ID information on the
Cylinder is stored in the Data Register
Status information after command
execution
Sector ID information during execution
phase
CONFIGURE
Data Bus
D4
D3
D2
D1
EN
Result
D1
TI
AL
Phase R/W
READ ID
Data Bus
D4
D3
D2
D0
1
0
0
1
1
0
0
0
0
0
DFIFO POLLD
Remarks
Configure Information
FIFOTHR
PRETRK
FI
D
Execution
Phase R/W
Command
D7
D6
D5
W
0
0
0
0
0
1
1
1
W
0
0
0
0
0
0
DR1
DR0
N
Execution
Phase R/W
D0
Command Codes
SEEK
Data Bus
D4
D3
D6
D5
W
0
0
0
0
1
1
1
1
W
0
0
0
0
0
HDS
DR1
DR0
W
Remarks
Head retracted to Track 0
D7
O
Command
RE-CALIBRATE
Data Bus
D4
D3
D2
D1
D2
D1
D0
Remarks
Command Codes
NCN
Head is positioned over proper
cylinder on diskette
C
Execution
www.ite.com.tw
130
IT8783F/E V0.5
Functional Description
Command
D7
D6
D5
W
1
DIR
0
0
W
0
0
0
0
W
1
1
0
HDS
RCN
Execution
D7
D6
D5
0
0
0
W
DUMPREG
Data Bus
D4
D3
D2
0
1
1
Execution
1
DR1
DR0
Command Codes
D1
D0
1
0
Remarks
Command Codes
Registers placed in FIFO
R
PCN-Drive 0
EN
Result
1
Head is stepped in or out a
programmable number of tracks
Phase R/W
Command
Remarks
D0
TI
AL
Phase R/W
RELATIVE SEEK
Data Bus
D4
D3
D2
D1
R
PCN-Drive 1
R
PCN-Drive 2
R
PCN-Drive 3
R
SRT
HUT
R
ND
SC/EOT
LOCK
0
0
DIS
DC3
DC2
DC1
DFIFO POLLD
PRETRK
DC0
GAP
FIFOTHR
FI
D
R
R
R
R
HLT
WG
LOCK
Phase R/W
Command
D6
D5
W
LOCK
0
0
1
R
0
0
0
LOCK
N
Result
Data Bus
D4
D3
D7
Phase R/W
D7
D6
D5
D2
D1
D0
0
1
0
0
0
0
0
0
D1
D0
VERSION
Data Bus
D4
D3
D2
Remarks
Command Codes
Remarks
W
0
0
0
1
0
0
0
0
Command Codes
Result
R
1
0
0
1
0
0
0
0
Enhanced Controller
O
Command
Phase R/W
D7
D6
D5
0
0
0
SENSE INTERRUPT STATUS
Data Bus
D4
D3
D2
D1
D0
W
Result
R
ST0
R
PCN
C
Command
www.ite.com.tw
0
1
0
0
0
Remarks
Command Codes
Status information at the end of each
SEEK operation
131
IT8783F/E V0.5
IT8783E/F (For A Version)
Result
D6
D5
W
0
0
0
0
W
0
0
0
0
R
D7
D6
0
0
W
W
D5
0
D6
D5
W
0
0
0
W
OW
0
DC3
0
0
D6
DR1
DR0
Command Codes
D1
D0
1
1
Remarks
Command Codes
D5
ND
PERPENDICULAR MODE
Data Bus
D4
D3
D2
D1
W
R
D0
1
0
0
1
0
DC2
DC1
DC0
GAP
WG
D1
D0
INVALID
Data Bus
D4
D3
D2
Invalid codes
FI
D
9.7.11
D7
0
Status information about FDD
SPECIFY
Data Bus
D4
D3
D2
0
0
HUT
D7
Phase R/W
Result
HDS
HLT
Phase R/W
Command
0
SRT
W
Command
1
ST3
Phase R/W
Command
0
Remarks
D0
EN
Command
D7
TI
AL
Phase R/W
SENSE DRIVE STATUS
Data Bus
D4
D3
D2
D1
ST0
Remarks
Command Codes
Remarks
INVALID Command Codes (NO-OP:
FDC goes into the standby state)
ST0 = 80h
Data Transfer Command
N
All data transfer commands utilize bytes with the same parameter (except for FORMAT A TRACK command)
and return data bytes with the same result. The only difference between them is the five bits (bit0 - bit4) of the
first byte.
9.7.11.1 READ DATA Command
C
O
The READ DATA command contains nine command bytes that make the FDC enter the Read Data mode.
Each READ operation is initialized by a READ DATA command. The FDC locates the sector to be read by
matching ID Address Marks and ID fields from the command with the information on the diskette. The FDC
then transfers the data to the FIFO. After the data from the given sector are read, the READ DATA command
is completed and the sector address is automatically incremented by 1. The data from the next sector are
read and transferred to the FIFO in the same manner. Such a continuous read function is called a "MultiSector Read Operation".
If a TC or an implied TC (FIFO overrun/underrun) is received, the FDC stops sending data, but continues
reading data from the current sector and checks the CRC bytes until the end of the sector is reached and the
READ operation is completed.
The sector size is determined by the N parameter value as calculated in the equation below:
(7+N value)
Sector Size = 2
www.ite.com.tw
bytes.
132
IT8783F/E V0.5
Functional Description
TI
AL
The DTL parameter determines the number of bytes to be transferred. Therefore, if N = 00h, set the sector
size to 128 and the DTL parameter value is less than this, the remaining bytes will be read and checked for
CRC errors by the FDC. If it occurs to a WRITE operation, the remaining bytes will be filled with 0. If the
sector size is not 128 (N > 00h), DTL should be set to FFh.
In addition to performing Multi-Sector Read operations, the FDC can also perform Multi-Track Read
operations. When the MT parameter is set, the FDC can read both sides of a disk automatically.
The combination of N and MT parameter values determines the amount of data that can be transferred during
either type of READ operation. Table 9-10 shows the maximum data transfer capacity and the final sector the
FDC reads based on these parameters.
Table 9-10. Effects of MT and N Bit
N
Maximum Data Transfer Capacity
Final Sector Read from Disk
0
1
256 X 26 = 6656
26 on side 0 or side 1
1
1
256 X 52 = 13312
26 on side 1
0
2
512 X 15 = 7680
15 on side 0 or side 1
1
2
512 X 30 = 15360
15 on side 1
0
3
1024 X 8 = 8192
8 on side 0 or side 1
1
3
1024 X16 =16384
16 on side 1
EN
MT
9.7.11.2 READ DELETED DATA Command
FI
D
The READ DELETED DATA command is the same as the READ DATA command, except that a Deleted
Data Address Mark (as opposed to a Data Address Mark) is read at the beginning of the Data Field. This
command is typically used to mark a bad sector on a diskette.
9.7.11.3 READ A TRACK Command
N
After receiving a pulse from the INDEX# pin, the READ A TRACK command reads the entire data field from
each sector of the track as a continuous block. If any ID or Data Field CRC error is found, the FDC continues
to read data from the track and indicates the error at the end. Because the Multi-Track [and Skip] operation[s]
is[are] not allowable under this command, the MT and SK bits should be low (0) during the command
execution.
O
This command terminates normally when the number of sectors specified by EOT has not been read. If,
however, no ID Address Mark is found by the second occurrence of the INDEX pulse, the FDC will set the IC
code in the ST0 to 01, indicating an abnormal termination, and then finish the command.
9.7.11.4 WRITE DATA Command
C
The WRITE DATA command contains nine command bytes that make the FDC enter the Write Data mode.
Each WRITE operation is initialized by a WRITE DATA command. The FDC locates the sector to be written
by reading ID fields and matching the sector address from the command with the information on the diskette.
Then the FDC reads the data from the host via the FIFO and writes the data into the sector’s data field.
Finally, the FDC computes the CRC value, storing it in the CRC field and increments the sector number
(stored in the R parameter) by 1. The next data field is written into the next sector in the same manner. Such
a continuous write function is called a "Multi-Sector Write Operation".
If a TC or an implied TC (FIFO overrun/underrun) is received, the FDC stops writing data and fills the
remaining data fields with 0s. If a check of the CRC value indicates an error in the sector ID Field, the FDC
www.ite.com.tw
133
IT8783F/E V0.5
IT8783E/F (For A Version)
TI
AL
will set the IC code in the ST0 to 01 and the DE bit in the ST1 to 1, indicating an abnormal termination, and
then terminate the WRITE DATA command. The maximum data transfer capacity and the DTL, N, and MT
parameters are the same as in the READ DATA command.
9.7.11.5 WRITE DELETED DATA Command
The WRITE DELETED DATA command is the same as the WRITE DATA command, except that a Deleted
Data Address Mark (instead of a Data Address Mark) is written at the beginning of the Data Field. This
command is typically used to mark a bad sector on a diskette.
9.7.11.6 FORMAT A TRACK Command
EN
The FORMAT A TRACK command is to format an entire track. Initialized by an INDEX pulse, it writes data to
the Gaps, Address Marks, ID fields and Data fields according to the density mode selected (FM or MFM). The
Gap and Data field values are controlled by the host-specified values programmed into N, SC, GPL, and D
during the Command phase. The Data field is filled with the data byte specified by D. The four data bytes per
sector (C, H, R, and N) required to fill the ID field are supplied by the host. The C, R, H, and N values must be
renewed for each new sector of a track. Only the R parameter value must be changed when a sector is
formatted, allowing the disk to be formatted with non-sequential sector addresses. These steps are repeated
until a new INDEX pulse is received, at which point the FORMAT A TRACK command is terminated.
9.7.11.7 SCAN Command
The SCAN command allows the data read from the disk to be compared with the data sent from the system.
Followings are three SCAN commands:
FI
D
SCAN EQUAL Disk Data = System Data
SCAN HIGH OR EQUAL Disk Data ≥ System Data
SCAN LOW OR EQUAL Disk Data ≤ System Data
N
The execution of SCAN command will not be terminated until the scan condition has been met, EOT has
been reached, or TC is asserted. Read errors on the disk have the same error condition as that for the READ
DATA command. If the SK bit is set, sectors with Deleted Data Address Marks are ignored. If all sectors’ read
is skipped, the command terminates with D3 bit of the ST2 being set. The Result phase of the command is
shown below:
Table 9-11. SCAN Command Result
C
O
Command
www.ite.com.tw
SCAN EQUAL
SCAN HIGH OR EQUAL
SCAN LOW OR EQUAL
Status Register
D2
D3
Condition
0
1
Disk = System
1
0
Disk ≠ System
0
1
Disk = System
0
0
Disk > System
1
0
Disk < System
0
1
Disk = System
0
0
Disk < System
1
0
Disk > System
134
IT8783F/E V0.5
Functional Description
9.7.11.8 VERIFY Command
TI
AL
The VERIFY command is to read logical sectors containing a Normal Data Address Mark from the selected
drive without transferring the data to the host. This command acts like a READ DATA command except that
no data are transferred to the host. This command is designed for post-format or post-write verification. Data
are read from the disk, as the controller checks for valid Address Marks in the Address and Data Fields. The
CRC is computed and checked against the previously stored value. Because no data are transferred to the
host, the TC (Terminal Count of DMA) cannot be used to terminate this command. An implicit TC will be
issued to the FDC by setting the EC bit. This implicit TC will occur when the SC value has been decremented
to 0. This command can also be terminated by clearing the EC bit and when the EOT value is equal to the
final sector to be checked.
Table 9-12. VERIFY Command Result
MT
EC
0
0
SC/EOT
SC = DTL
No Error
EOT ≤ # Sectors per side
0
SC = DTL
Abnormal Termination
EN
0
Termination Result
EOT > # Sectors per side
0
1
SC ≤ # Sectors Remaining
AND
No Error
EOT ≤ # Sectors per side
0
1
SC > # Sectors Remaining
OR
Abnormal Termination
FI
D
EOT > # Sectors per side
1
0
SC = DTL
No Error
EOT > # Sectors per side
1
0
SC = DTL
Abnormal Termination
EOT > # Sectors per side
1
1
SC ≤ # Sectors Remaining
AND
No Error
EOT ≤ # Sectors per side
N
1
SC > # Sectors Remaining
OR
Abnormal Termination
EOT > # Sectors per side
Control Command
O
9.7.12
1
C
The control commands do not transfer any data and are used to monitor and manage the data transfer
instead. Three of them, READ ID, RE-CALIBRATE and SEEK, will generate an interrupt after data transfer is
completed. It is strongly recommended that a SENSE INTERRUPT STATUS command be issued after these
commands to capture their valuable interrupt information. The RE-CALIBRATE, SEEK, and SPECIFY
commands do not return any result bytes.
www.ite.com.tw
135
IT8783F/E V0.5
IT8783E/F (For A Version)
9.7.12.1 READ ID Command
TI
AL
The READ ID command is to find the actual recording head position. It stores the first readable ID field value
into the FDC registers. If the FDC cannot find an ID Address Mark before the second INDEX pulse is
received, an abnormal termination will be generated by setting the IC code in the ST0 to 01.
9.7.12.2 CONFIGURE Command
The CONFIGURE command determines some specific operation modes of the controller and does not need
to be issued if the default values of the controller meet the system requirements.
DFIFO: Disable FIFO.
0: Enable
1: Disable (Default)
EN
EIS: Enable Implied Seek. A SEEK operation is performed before a READ, WRITE, SCAN, or VERIFY
command.
0: Disable (Default)
1: Enable
POLLD: Disable polling of drives.
0: Enable (Default) When enabled, a single interrupt is generated after a reset.
1: Disable
FI
D
FIFOTHR: The FIFO threshold in the execution phase of data transfer commands. They are programmable
from 00 to 0F hex (1 byte to 16 bytes). The default is 1 byte.
PRETRK: The Precompensation Start Track Number. They are programmable from track 0 to FF hex (track 0
to track 255). The default is track 0.
9.7.12.3 RE-CALIBRATE Command
N
The RE-CALIBRATE command retracts the FDC read/write head to the track 0 position, resetting the value of
the PCN counter and checking the TRK0# status. If TRK0# is low, the DIR# pin remains low and step pulses
are issued. If TRK0# is high, SE [and EC bits] of the ST0 are set high, and the command is terminated. When
TRK0# remains low for 79 step pulses, the RE-CALIBRATE command is terminated by setting SE and EC
bits of ST0 to high. Consequently, for disks that can accommodate more than 80 tracks, more than one RECALIBRATE command is required to retract the head to the physical track 0.
The FDC is in a non-busy state during the Execution phase of this command, making it possible to issue
another RE-CALIBRATE command in parallel with the current command.
O
On power-up, software must issue a RE-CALIBRATE command to properly initialize the FDC and the drives
attached.
9.7.12.4 SEEK Command
C
The SEEK command controls the FDC read/write head movement from one track to the other. The FDC
compares the current head position, stored in PCN, with NCN values after each step pulse to determine what
direction to move the head if required. The direction of movement is determined by the followings:
PCN < NCN ⎯ Step In: Sets DIR# signal to 1 and issues step pulses.
PCN > NCN ⎯ Step Out: Sets DIR# signal to 0 and issues step pulses.
PCN = NCN ⎯ Terminate the command by setting the ST0 SE bit to 1.
www.ite.com.tw
136
IT8783F/E V0.5
Functional Description
TI
AL
The impulse rate of step pulse is controlled by Stepping Rate Time (SRT) bit in the SPECIFY command. The
FDC is in a non-busy state during the Execution phase of this command, making it possible to issue another
SEEK command in parallel with the current command.
9.7.12.5 RELATIVE SEEK Command
The RELATIVE SEEK command steps the selected drive in or out in a given number of steps. The DIR bit is
to determine whether to step in or out. RCN (Relative Cylinder Number) is to determine how many tracks to
step the head in or out from the current track. After the step operation is completed, the controller generates
an interrupt, but the command has no Result phase. No other commands except the SENSE INTERRUPT
STATUS command should be issued while a RELATIVE SEEK command is in progress.
9.7.12.6 DUMPREG Command
9.7.12.7 LOCK Command
EN
The DUMPREG command is designed for system run-time diagnostics, application software development,
and debug. This command has one byte of Command phase and 10 bytes of Result phase, which return the
values of the parameter set in other commands.
The LOCK command allows the programmer to fully control the FIFO parameters after a hardware reset. If
the LOCK bit is set to 1, the parameters of DFIFO, FIFOTHR, and PRETRK in the CONFIGURE command
are not affected by a software reset. If the bit is set to 0, those parameters are set to default values after a
software reset.
FI
D
9.7.12.8 VERSION Command
The VERSION command is to determine the controller being used. In Result phase, a value of 90 hex is
returned in order to be compatible with the 82077.
9.7.12.9 SENSE INTERRUPT STATUS Command
The SENSE INTERRUPT STATUS command resets the interrupt signal (IRQ) generated by the FDC, and
identifies the cause of the interrupt via the IC code and SE bit of the ST0, as shown in Table 9-13. Interrupt
Identification below.
N
It is necessary to generate an interrupt under any of the following conditions:
Before any Data Transfer or READ ID command
After SEEK or RE-CALIBRATE commands (without Result phase)
When a data transfer is required during Execution phase in the non-DMA mode
C
O
•
•
•
Table 9-13. Interrupt Identification
SE
IC Code
0
11
Polling
1
00
Normal termination of SEEK or RE-CALIBRATE command
1
01
Abnormal termination of SEEK or RE-CALIBRATE command
9.7.12.10
Cause of Interrupt
SENSE DRIVE STATUS Command
The SENSE DRIVE STATUS command is to acquire drive status information and there is no Execution phase
for this command.
www.ite.com.tw
137
IT8783F/E V0.5
IT8783E/F (For A Version)
9.7.12.11
SPECIFY Command
TI
AL
The SPECIFY command sets the initial values for the HUT (Head Unload Time), HLT (Head Load Time),
SRT (Step Rate Time), and ND (Non-DMA mode) parameters. The possible values for HUT, SRT, and HLT
are shown in the following three tables respectively. The FDC is operated in DMA or non-DMA mode based
on the value specified by the ND parameters.
Table 9-14. HUT Value
1 Mbps
500 Kbps
0
128
256
1
8
16
-
-
-
E
112
224
F
120
240
300 Kbps
250 Kbps
426
512
26.7
32
-
-
373
448
400
480
EN
Parameter
Table 9-15. SRT Value
1 Mbps
0
8
1
7.5
-
-
E
1
500 Kbps
300 Kbps
250 Kbps
16
26.7
32
15
25
30
-
-
-
2
3.33
4
1.67
2
FI
D
Parameter
F
0.5
1
Table 9-16. HLT Value
1 Mbps
500 Kbps
300 Kbps
250 Kbps
00
128
256
426
512
01
1
2
3.33
4
02
2
4
6.7
8
-
-
-
-
-
7E
126
252
420
504
7F
127
254
423
508
N
Parameter
PERPENDICULAR MODE Command
O
9.7.12.12
C
The PERPENDICULAR MODE command is to support the unique READ/WRITE/FORMAT commands of
Perpendicular Recording disk drives (4 Mbytes unformatted capacity). This command configures each of the
four logical drives as a perpendicular or conventional disk drive via DC3-DC0 bits, or with the GAP and WG
control bits. Perpendicular Recording drives operate in “Extra High Density” mode at 1 Mbps, and are
downward compatible with 1.44 Mbyte and 720 kbyte drives at 500 Kbps (High Density) and 250 Kbps
(Double Density) respectively. This command should be issued during the initialization of the floppy disk
controller. Then, when a drive is accessed for a FORMAT A TRACK or WRITE DATA command, the
controller adjusts the format or Write Data parameters based on the data rate. If WG and GAP are used (not
set to 00), the operation of the FDC is based on the values of GAP and WG. If WG and GAP are set to 00,
setting DCn to 1 will set drive n to the Perpendicular mode. DC3-DC0 are unaffected by a software reset, but
www.ite.com.tw
138
IT8783F/E V0.5
Functional Description
WG and GAP are both cleared to 0 after a software reset.
Table 9-17. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands
WG
Mode
Length of GAP2
FORMAT FIELD
Portion of GAP2 Re-Written by WRITE
DATA Command
0
0
Conventional
22 bytes
0 bytes
0
1
1
0
1
1
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
22 bytes
22 bytes
41 bytes
TI
AL
GAP
19 bytes
0 bytes
38 bytes
Table 9-18. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands
Drive Mode
250/300/500 Kbps
Conventional
Perpendicular
1 Mbps
Conventional
Perpendicular
Portion of GAP2 Re-Written by
WRITE DATA Command
22 bytes
0 bytes
22 bytes
19 bytes
22 bytes
0 bytes
41 bytes
38 bytes
FI
D
9.7.12.13 INVALID Command
Length of GAP2
FORMAT FIELD
EN
Data Rate
The INVALID command indicates when an undefined command has been sent to FDC. The FDC will set
Main Status Register (MSR, FDC Base Address + 04h) bit 7 (RQM) and bit 6 (DIO) to 1 (refer to page 116)
and terminate the command without issuing an interrupt.
9.7.13
DMA Transfer
DMA transfer is enabled by the SPECIFY command and initiated by the FDC by activating the LDRQ# cycle
during a DATA TRANSFER command. The FIFO is enabled directly by asserting the LPC DMA cycle.
Low-Power Mode
N
9.7.14
C
O
When writing “1” to bit 6 of Data Rate Select Register (DSR, FDC Base Address + 04h) (refer to page 117),
the controller will enter the low-power mode immediately. All the clock sources including Data Separator,
Microcontroller, and Write precompensation unit, will be gated. The FDC can be resumed from the low-power
state in two ways. One is a software reset via the DOR or DSR, and the other is a read or write to either the
Data Register or Main Status Register. The latter is preferred since all internal register values are retained.
www.ite.com.tw
139
IT8783F/E V0.5
IT8783E/F (For A Version)
9.8
Serial Port (UART)
TI
AL
The IT8783E/F incorporates two enhanced serial ports that perform serial to parallel conversion on received
data, and parallel to serial conversion on transmitted data. Each of the serial channels individually contains a
programmable baud rate generator which is capable of dividing the input clock by a number ranging from 1 to
65535. The data rate of each serial port can also be programmed from 115.2K baud down to 50 baud. The
character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity; and
privileged interrupts.
Table 9-19. Serial Channel Registers
DLAB*
Data
0
Base + 0h RBR (Receiver Buffer Register)
TBR (Transmitter Buffer
Register)
0
Base + 1h IER (Interrupt Enable Register)
IER
x
Base + 2h IIR (Interrupt Identification Register) FCR (FIFO Control Register)
x
Base + 3h LCR (Line Control Register)
LCR
x
Base + 4h MCR (Modem Control Register)
MCR
1
Base + 0h DLL (Divisor Latch LSB)
DLL
1
Base + 1h DLM (Divisor Latch MSB)
DLM
x
Base + 5h LSR (Line Status Register)
LSR
x
Base + 6h MSR (Modem Status Register)
MSR
Control
Status
Address
READ
SCR
FI
D
x
Base + 7h SCR (Scratch Pad Register)
* DLAB is bit 7 of the Line Control Register.
9.8.1
WRITE
EN
Register
Data Registers
The Receiver Buffer Register (RBR) and Transmitter Buffer Register (TBR)individually hold five to eight data
bits. If the transmitted data are less than eight bits, it aligns to the LSB. Either received or transmitted data
are buffered by a shift register, and are latched first by a holding register. Bit 0 of any word is first received
and transmitted.
Receiver Buffer Register (RBR) (Read only, Address offset=0, DLAB=0)
N
9.8.1.1
This register receives and holds the incoming data. It contains a non-accessible shift register which converts
the incoming serial data stream into a parallel 8-bit word.
Transmitter Buffer Register (TBR) (Write only, Address offset=0, DLAB=0)
O
9.8.1.2
This register holds and transmits the data via a non-accessible shift register, and converts the outgoing
parallel data into a serial stream before data transmission.
C
9.8.2
9.8.2.1
Control Register
Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0)
The IER is to enable or disable four active high interrupts which activate the interrupt outputs with its lower
four bits: IER(0), IER(1), IER(2), and IER(3).
Bit
Default
www.ite.com.tw
Description
140
IT8783F/E V0.5
Functional Description
0
2
0
1
0
0
0
9.8.2.2
Reserved
Enable Modem Status Interrupt(EMSI)
Set this bit high to enable the modem status interrupt when one of the modem status
registers changes its bit status.
Enable Receiver Line Status Interrupt(ERLSI)
Set this bit high to enable the receiver line status interrupt, which happens when
overrun, parity, framing or break occurs.
Enable Transmitter Holding Register Empty Interrupt(ETHREI)
Set this bit high to enable the transmitter holding register empty interrupt.
Enable Received Data Available Interrupt(ERDAI)
Set this bit high to enable the received data available interrupt and time-out interrupt in
the FIFO mode.
TI
AL
7-4
3
Interrupt Identification Register (IIR) (Read only, Address offset=2)
4.
5.
6.
7.
EN
This register facilitates the host CPU to determine the interrupt priority and its source. The four existing
interrupts are listed below in priority order.
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
Modem Status (lowest priority)
C
O
N
FI
D
When a privileged interrupt is pending and the interrupt type is stored in the IIR which is accessed by the
Host, the serial channel holds back all interrupts and indicates the pending interrupts with the highest priority
to the Host. Any new interrupts will not be acknowledged until the Host access is completed. Please refer to
Table 9-20. Interrupt Identification Register on page 142 for the detail.
www.ite.com.tw
141
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 9-20. Interrupt Identification Register
Bit 3
Interrupt
Identification
Register
Bit 2 Bit 1 Bit 0
Interrupt Set and Reset Function
Priority
Interrupt Type
Interrupt Source
Interrupt Reset
Control
X
X
1
-
0
1
1
0
First
Receiver Line
Status
0
1
0
0
Second
Received Data
Available
1
1
0
0
Second
Character Time-out No characters have Read RBR
Indication
been removed from
or input to the RCVR
FIFO during the last
four character times
and there is at least
one character in it
during this period.
0
0
1
0
Third
0
0
Fourth
-
OE, PE, FE, or BI
Read LSR
Received Data
Available
Read RBR or FIFO
drops below the trigger
level
Transmitter Holding Transmitter Holding
Register Empty
Register Empty
FI
D
0
None
EN
0
0
None
TI
AL
FIFO
Mode
Modem Status
CTS#, DSR#, RI#,
DCD#
Read IIR if THRE is the
Interrupt Source
Write THR
Read MSR
C
O
N
Note: X = Not Defined
IIR(7), IIR(6): Set when FCR(0) = 1.
IIR(5), IIR(4): Always logic 0.
IIR(3): In the non-FIFO mode, this bit is a logic 0. In the FIFO mode, this bit is set along with bit 2 when a
time-out Interrupt is pending.
IIR(2), IIR(1): Used to identify the highest priority interrupt pending.
IR(0): Used to indicate a pending interrupt in either a hard-wired prioritized or polled environment with a logic
0 state. In such a case, IIR contents may be used as a pointer that points to the appropriate interrupt service
routine.
www.ite.com.tw
142
IT8783F/E V0.5
Functional Description
9.8.2.3
FIFO Control Register (FCR) (Write Only, Address offset=2)
This register is used to not only enable and clear the FIFO but also set the RCVR FIFO trigger level.
5-4
3
0
0
2
0
1
0
0
0
Description
TI
AL
Default
-
Receiver Trigger Level Selection
These bits are to set the trigger level for the RCVR FIFO interrupt.
Reserved
Reserved
(This bit does not affect the Serial Channel operation. RXRDY and TXRDY functions
are not available on this chip.)
Transmitter FIFO Reset(TFR)
This self-cleared bit clears all contents of the XMIT FIFO and resets its related counter
to 0 via a logic "1".
Receiver FIFO Reset(RFR)
Setting this self-cleared bit to a logic "1” will clear all contents of the RCVR FIFO and
resets its related counter to “0” (except the shift register).
FIFO Enable(FIFOE)
XMIT and RCVR FIFOs are enabled when this bit is set high. XMIT whereas disabled
and cleared respectively when this bit is cleared to low. This bit must be a logic "1" if
data are written to the other bits of the FCR, or they will not be properly programmed.
When this register is switched to the non-FIFO mode, all of its contents will be cleared.
EN
Bit
7-6
Table 9-21. Receiver FIFO Trigger Level Encoding
FCR (7)
FCR (6)
RCVR FIFO Trigger Level
0
1 byte
0
1
4 bytes
1
0
8 bytes
1
1
14 bytes
9.8.2.4
FI
D
0
Divisor Latches (DLL, DLM) (Read/Write, Address offset=0,1 DLAB=0)
N
Two 8-bit Divisor Latches (DLL and DLM) store the divisor values in 16-bit binary format. They are loaded
during initialization to generate a desired baud rate.
9.8.2.5
Baud Rate Generator (BRG)
Each serial channel contains a programmable BRG, which can take any clock input (from DC to 8 MHz) to
generate standard ANSI/CCITT bit rates for the channel clocking with an external clock oscillator. The
O
16
to obtain the desired
C
number of DLL or DLM is in 16-bit format, providing the divisor ranging from 1 to 2
baud rate. The output frequency is 16X data rate.
www.ite.com.tw
143
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 9-22. Baud Rate Using (24 MHz ÷ 13) Clock
Divisor Used
50
2304
TI
AL
Desired Baud Rate
75
1536
110
1047
134.5
857
150
768
300
384
600
192
1200
96
1800
64
2000
58
48
EN
2400
32
4800
24
7200
16
9600
12
19200
6
38400
3
57600
2
115200
1
FI
D
9.8.2.6
3600
Scratch Pad Register (Read/Write, Address offset=7)
This 8-bit register does not control the UART operation in any way. It is intended as a scratch pad register to
be used by programmers to temporarily hold general purpose data.
9.8.2.7
Line Control Register (LCR) (Read/Write, Address offset=3)
N
LCR controls the format of the data character and supplies the information of the serial line.
Default
0
6
0
C
O
Bit
7
5
0
4
0
www.ite.com.tw
Description
Divisor Latch Access Bit (DLAB)
This bit must be set high to access the Divisor Latches of the baud rate generator
during READ or WRITE operation whereas set low to access Data Registers (refer to
page 140) or Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0)
(refer to page 140).
Set Break(SB)
This bit forces the Serial Output (SOUT) to the spacing state (logic 0) by a logic 1,
which will be preserved until a low level resetting LCR(6), enabling the serial port to
alert the terminal in a communication system.
Stick Parity(SP)
When this bit and LCR(3) are high at the same time, the parity bit is transmitted and
then detected by a receiver in an opposite state by LCR(4) to force the parity bit into a
known state and to check the parity bit in a known state.
Even Parity Selection(EPS)
144
IT8783F/E V0.5
Functional Description
0
2
0
1-0
00
TI
AL
3
When the parity is enabled (LCR(3) = 1),
0: Odd parity
1: Even parity
Parity Enable(PE)
A parity bit, located between the last data word bit and stop bit, will be generated or
checked (transmit or receive data) when LCR(3) is high.
Number of Stop Bit (NSB)
This bit specifies the number of stop bit in each serial character, as summarized in
Table 9-23. Stop Bit Number Encoding on page 145.
Word Length Select [1:0](WLS)
11: 8 bits
10: 7 bits
01: 6 bits
00: 5 bits
Table 9-23. Stop Bit Number Encoding
0
1
1
1
1
EN
LCR (2) Word Length No. of Stop Bit
-
1
5 bits
1.5
6 bits
2
7 bits
2
8 bits
2
9.8.2.8
FI
D
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmission.
Modem Control Register (MCR) (Read/Write, Address offset=4)
This register controls the interface by the modem or data set (or device emulating a modem).
Default
0
Description
Reserved
Internal Loopback(IL)
This bit provides a loopback feature for diagnostic test of the serial channel when set
high. Serial Output (SOUT) is set to the Marking State Shift Register output loops back
into the Receiver Shift Register. All Modem Control inputs (CTS#, DSR#, RI# and
DCD#) are disconnected. The four Modem Control outputs (DTR#, RTS#, OUT1 and
OUT2) are internally connected to the four Modem Control inputs and forced to
inactive high then the transmitted data are immediately received, allowing the
processor to verify the transmitted and received data path of the serial channel.
OUT2(OUT2)
The Output 2 bit enables the serial port interrupt output by a logic 1.
OUT1(OUT1)
This bit does not have an output pin and can only be read or written by CPU.
Request to Send (RTS)
This bit controls the Request to Send (RTS#), which is in an inverse logic state with
that of MCR(1).
Data Terminal Ready (DTR)
This bit controls the Data Terminal Ready (DTR#), which is in an inverse logic state
with that of the MCR(0).
O
N
Bit
7-5
4
0
2
0
1
0
0
0
C
3
www.ite.com.tw
145
IT8783F/E V0.5
IT8783E/F (For A Version)
9.8.3.1
Status Register
Line Status Register (LSR) (Read/Write, Address offset=5)
TI
AL
9.8.3
This register provides the status indication and is usually the first register read by the CPU to determine the
cause of an interrupt or to poll the status of each serial channel.
6
1
5
1
4
0
3
0
0
N
2
Description
Error in Receiver FIFO(ERF)
In the 16450 mode, this bit is always 0 whereas in FIFO mode, it is set high when
there is at least one parity error, framing or break interrupt in the FIFO. This bit will be
cleared when CPU reads LSR if there are no subsequent errors in FIFO.
Transmitter Empty(TE)
This read only bit indicates that the Transmitter Holding Register (THR) and
Transmitter Shift Register are both empty. Otherwise, this bit is "0" and has the same
function as that in FIFO mode.
Transmitter Holding Register Empty(THRE)
This read only bit indicates that the Transmitter Buffer Register (TBR) is empty and
ready to accept a new character for transmission. It is set high when a character is
transferred from Transmitter Holding Register (THR) into Transmitter Shift Register,
causing priority 3 interrupt (THRE) of Interrupt Identification Register (IIR) (Read only,
Address offset=2) (refer to page 141), which is cleared by a read of IIR. In FIFO mode,
it is set when XMIT FIFO is empty whereas cleared when at least one byte is written to
XMIT FIFO.
Line Break(LB)
The Line Break (LB) Interrupt status bit indicates that the last character received is a
break character, which is invalid but complete. It includes parity and stop bits. This
situation occurs when the received data input is held in the spacing (logic 0) for longer
than a full word transmission time (start bit + data bits + parity + stop bit). When any of
these error conditions is detected (LSR(1) to LSR(4)), a Receiver Line Status interrupt
(priority 1) will be generated in IIR, with bit 2 of Interrupt Enable Register (IER)
(Read/Write, Address offset=1, DLAB=0) previously enabled(refer to page 140).
Framing Error(FE)
A logic 1 indicates that the stop bit in the received character is not valid. It will be reset
low when CPU reads the contents of the LSR.
Parity Error(PE)
A logic 1 indicates that the received data character does not have the correct even or
odd parity, as selected by LCR(4). It will be reset to "0" whenever LSR is read by CPU.
Overrun Error(OE)
A logic 1 indicates that the RBR has been overwritten by the next character before it
had been read by CPU. In the FIFO mode, OE occurs when FIFO is full and the next
character has been completely received by the Shift Register. It will be reset when
LSR is read by the CPU.
Data Ready(DR)
A "1" indicates a character has been received by the RBR. A logic "0" indicates all the
data in RBR or RCVR FIFO have been read.
EN
Default
0
FI
D
Bit
7
0
O
1
C
0
9.8.3.2
0
Modem Status Register (MSR) (Read/Write, Address offset=6)
This 8-bit register indicates the current state of the control lines with modems or the peripheral devices in
addition to this current state information. Four of these eight bits, MSR(4) - MSR(7), can provide the state
change information when the modem control input changes the state. It is reset low when the Host reads the
MSR.
www.ite.com.tw
IT8783F/E V0.5
146
Functional Description
0
5
0
4
0
3
0
2
0
1
0
0
0
Data Carrier Detect(DCD)
It indicates the complement status of Data Carrier Detect (DCD#) input. If MCR(4) = 1,
MSR(7) is equivalent to OUT2 of the MCR.
Ring Indicator(RI)
It indicates the complement status to the RI# input. If MCR(4)=1, MSR(6) is equivalent
to OUT1 in the MCR.
Data Set Ready(DSR)
It indicates that the modem is ready to provide received data to the serial channel
receiver circuitry. If the serial channel is in the loop mode (MCR(4) = 1), MSR(5) is
equivalent to DTR# of MCR.
Clear to Send(CTS)
It indicates the complement of CTS# input. When the serial channel is in the Loop
mode (MCR(4)=1), MSR(5) is equivalent to RTS# of MCR.
Delta Data Carrier Detect(DDCD)
It indicates that the DCD# input state has been changed since being read by the Host
last time.
Trailing Edge Ring Indicator(TERI)
It indicates that the RI input state to the serial channel has been changed from low to
high since being read by the Host last time. The change in a logic “1” does not activate
the TERI.
Delta Data Set Ready(DDSR)
A logic "1" indicates that the DSR# input state to the serial channel has been changed
since being read by the Host last time.
Delta Clear to Send(DCTS)
This bit indicates the CTS# input to the chip has changed the state since MSR was
read last time.
TI
AL
6
Description
EN
Default
0
C
O
N
FI
D
Bit
7
www.ite.com.tw
147
IT8783F/E V0.5
IT8783E/F (For A Version)
9.8.4
Reset
TI
AL
The reset of the IT8783F/E should be held to an idle mode reset high for 500 ns until initialization, which
causes the initialization of the internal clock counters of transmitter and receiver.
Table 9-24. Reset Control of Register and Pinout Signal
Register/Signal
Reset Control
Reset
Interrupt Identification Register
Reset
FIFO Control Register
Reset
Line Control Register
Reset
Modem Control Register
Reset
Line Status Register
Reset
Modem Status Register
Reset
SOUT1, SOUT2
Reset
RTS1#, RTS2#, DTR1#, DTR2#
IRQ of Serial Port
All bits Low
Bit 0 is high and bits 1-7 are low
All bits Low
All bits Low
All bits Low
Bits 5 and 6 are high; others are
low
Bits 0-3 low; bits 4-7 input signals
EN
Interrupt Enable Register
Reset Status
Reset
High
Reset
High
High Impedance
9.8.5
Programming
9.8.6
FI
D
Each serial channel of the IT8783E/F is programmed by control registers, whose contents define the
character length, number of stop bits, parity, baud rate and modem interface. Even though these control
registers can be written in any given order, the IER should be the last register written because it controls
whether the interrupt is enabled or not. After the port is programmed, these registers still can be updated
whenever the port does not transfer data.
Software Reset
N
This approach allows the serial port to return to a completely known state without a system reset. It is
achieved by writing the required data to the LCR, DLL, DLM and MCR. The LSR and RBR must be read
before interrupts are enabled to clear out any residual data or status bits that may be invalid for subsequent
operations.
9.8.7
Clock Input Operation
C
O
The input frequency of the Serial Channel is 24 MHz ÷ 13, not exactly 1.8432 MHz.
www.ite.com.tw
148
IT8783F/E V0.5
Functional Description
9.8.8
FIFO Interrupt Mode Operation
TI
AL
(1) RCVR Interrupt
By setting bit 0 of FIFO Control Register (FCR) (Write Only, Address offset=2) (refer to page 143) and bit 0 of
Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0) (refer to page 140) high, the RCVR
FIFO and receiver interrupts are enabled. The RCVR interrupt occurs under the following conditions:
The receive data available interrupt will be issued only when the FIFO has reached its programmed trigger
level and cleared as soon as the FIFO drops below its trigger level.
The receiver line status interrupt has higher priority over the received data available interrupt.
The time-out timer will be reset after receiving a new character or after the Host reads RCVR FIFO whenever a
time-out interrupt occurs. The timer will be reset when the Host reads one character from RCVR FIFO.
EN
For the RCVR FIFO time-out interrupt, it will occur under the following conditions by enabling the RCVR FIFO
and receiver interrupts:
The RCVR FIFO time-out interrupt will occur only if there is at least one character in FIFO whenever the
interval between the most recently received serial character and the most recent Host READ from the FIFO is
longer than four consecutive character times.
The time-out timer will be reset after receiving a new character or after the Host reads RCVR FIFO whenever a
time-out interrupt occurs. The timer will be reset when the Host reads one character from RCVR FIFO.
FI
D
(2) XMIT Interrupt
By setting bit 0 of FIFO Control Register (FCR) (Write Only, Address offset=2) (refer to page 143) and bit 1 of
Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0) (refer to page 140) high, the XMIT
FIFO and transmitter interrupts are enabled. The XMIT interrupt occurs under the following conditions:
a. The transmitter interrupt occurs when the XMIT FIFO is empty, and it will be reset if the THR is written or
the IIR is read.
N
b. The transmitter FIFO empty indications will be delayed for one character time minus the last stop bit time
whenever the following condition occurs:
O
THRE = 1 and there have not been at least two bytes in the transmitter FIFO at the same time since the
last THRE = 1. The transmitter interrupt after changing FCR(0) will be immediate if it is enabled. Once the
first transmitter interrupt is enabled, the THRE indication will be delayed for one character time minus the
last stop bit time.
The character time-out and RCVR FIFO trigger level interrupts have the same priority as the received data
available interrupt. The XMIT FIFO empty has the same priority as the transmitter holding register empty
interrupt.
C
FIFO Polled Mode Operation [FCR(0)=1, and IER(0), IER(1), IER(2), IER(3) or all are 0].
Either or both XMIT and RCVR can be in this operation mode. The operation mode can be programmed by
users and is responsible for checking the RCVR and XMIT status via LSR described below:
LSR(7): RCVR FIFO error indication
LSR(6): XMIT FIFO and Shift register empty
LSR(5): The XMIT FIFO empty indication
www.ite.com.tw
149
IT8783F/E V0.5
IT8783E/F (For A Version)
9.9
Consumer Remote Control (TV Remote) IR (CIR)
9.9.1
Overview
TI
AL
LSR(4) - LSR(1): Specify that errors have occurred. The character error status is handled in the same way as
that in the interrupt mode. The IIR is not affected since IER(2)=0.
LSR(0): High whenever RCVR FIFO contains at least one byte.
No trigger level is reached or time-out condition indicated in FIFO Polled Mode.
CIR is applied to the consumer remote control equipment, and is a programmable amplitude shift keyed (ASK)
serial communication protocol. By adjusting frequencies, baud rate divisors and sensitivity ranges, the CIR
registers are able to support the popular protocols such as RC-5, NEC, and RECS-80. Software driver
programming can support new protocols.
9.9.2
Supports 30 kHz - 57 kHz (low frequency) or 400 kHz – 500 kHz (high frequency) carrier transmission
Baud rate up to 115200 BPS (high frequency)
Demodulation optional
Supports transmission run-length encoding and deferral function
32-byte FIFO for data transmission or data reception
9.9.3
Block Diagram
EN
„
„
„
„
„
Features
FI
D
CIR consists of two parts, transmitter and receiver. Regarding the transmitter, it is responsible for transmitting
data to FIFO, processing FIFO data by serialization and modulation and sending out data through the LED
device. As for the receiver, it is responsible for receiving data, processing data by demodulation and
deserialization and storing data in the Receiver FIFO.
C
O
N
Figure 9-6. CIR Block Diagram
www.ite.com.tw
150
IT8783F/E V0.5
Functional Description
00000000
11110000
Transmitter
Transmitter
FIFO
data
Host Interface
Modulator
TI
AL
Serialization
Interface &
Registers
Baud Rate Gen.
EN
data
Receiver
Interrupt Gen.
Receiver
FIFO
Deserialization
Demodulator
C
O
N
FI
D
00000000
11110000
www.ite.com.tw
151
IT8783F/E V0.5
IT8783E/F (For A Version)
9.9.4
Transmit Operation
TI
AL
The data written to the Transmitter FIFO will be exactly serialized from LSB to MSB, modulated with the
carrier frequency and sent to the CIRTX output. The data are either in bit-string format or run-length decode.
Before the data transmission can be started, code byte write operation must be performed to the Transmitter
FIFO DR. The bit TXRLE in the TCR1 should be set to “1” before the run-length decode data can be written
into the Transmitter FIFO. Setting TXENDF in the TCR1 will enable the data transmission deferral, and avoid
the transmitter FIFO underrun. The bit width of the serialized bit string is determined by the value
programmed in the baud rate divisor registers, BDLR and BDHR. When the two bits, HCFS and CFQ[4:0],
are set, either the high-speed or low-speed carrier range is selected, and the corresponding carrier frequency
will also be determined. Bit TXMPM[1:0] and TXMPW[2:0] specify the pulse numbers in a bit width and the
required duty cycles of the carrier pulse according to the communication protocol. Only a logic “0” can
activate the Transmitter LED in the format of a series of modulating pulses.
9.9.5
Receive Operation
9.9.6
EN
The Receiver function will be enabled if bit RXEN in RCR is set to “1”. Either demodulated or modulated RX#
signal is loaded into Receiver FIFO, and bit RXEND in RCR determines whether the demodulation logic
should be used or not. It determines the baud rate by programming the baud rate divisor registers BDLR and
BDHR, and the carrier frequency by programming bit HCFS and CFQ[4:0]. Set RDWOS to “0” to sync. Bit
RXACT in RCR is set to “1” when the serial data or the selected carrier is incoming, and the sampled data will
then be kept in Receiver FIFO. Write “1” to bit RXACT to stop the Receiver operation; “0” to bit RXEN to
disable the Receiver.
Register Description and Address
FI
D
Table 9-25. List of CIR Registers
R/W
Address
Default
CIR Data Register (DR)
R/W
Base + 0h
FFh
CIR Interrupt Enable Register (IER)
R/W
Base + 1h
00h
CIR Receiver Control Register (RCR)
R/W
Base + 2h
01h
CIR Transmitter Control Register 1 (TCR1)
R/W
Base + 3h
00h
CIR Transmitter Control Register 2 (TCR2)
R/W
Base + 4h
5Ch
CIR Transmitter Status Register (TSR)
R
Base + 5h
00h
CIR Receiver Status Register (RSR)
R
Base + 6h
00h
CIR Baud Rate Divisor Low Byte Register (BDLR)
R/W
Base + 5h
00h
CIR Baud Rate Divisor High Byte Register (BDHR)
R/W
Base + 6h
00h
R
Base + 7h
01h
O
N
Register Name
C
CIR Interrupt Identification Register (IIR)
www.ite.com.tw
152
IT8783F/E V0.5
Functional Description
9.9.6.1
CIR Data Register (DR)
TI
AL
The DR, an 8-bit read/write register, is the data port for CIR. Data are transmitted and received through this
register.
Address: Base Address + 0h
Bit
7-0
9.9.6.2
R/W
R/W
Default
FFh
Description
CIR Data Register (DR[7:0])
Writing data to this register causes data to be written to Transmitter
FIFO.
Reading data from this register causes data to be received from
Receiver FIFO.
CIR Interrupt Enable Register (IER)
Address: Base Address + 1h
R/W
R/W
Default
0b
6
R/W
0b
5
4
R/W
0b
R/W
0b
R/W
0b
R/W
0b
N
3
O
2
R/W
C
1
Description
Transmitter Data Output Select (TX_sel)
This bit is used to select transmitter data output.
0: CIRTX1 (Default)
1: CIRTX2
Receiver Data Input Select (RX_sel)
This bit is used to select receiver data input.
0: CIRRX1 (Default)
1: CIRRX2
Reset (Reset)
This bit is for software reset. Writing “1” to this bit resets register DR,
IER, TCR1, BDLR, BDHR and IIR. This bit is then cleared to the initial
value automatically.
Baud Rate Register Enable Function Enable (BR)
This bit is used to control whether the baud rate register can enable
read/write function.
Set this bit to “1” to enable the baud rate registers for CIR.
Set this bit to “0” to disable the baud rate registers for CIR.
Interrupt Enable Function Control (IEC)
This bit is used to control whether the interrupt function can be enabled.
Set this bit to “1” to enable the interrupt request for CIR.
Set this bit to “0” to disable the interrupt request for CIR.
Receiver FIFO Overrun Interrupt Enable (RFOIE)
This bit is used to control Receiver FIFO Overrun Interrupt request.
Set this bit to “1” to enable Receiver FIFO Overrun Interrupt request.
Set this bit to “0” to disable Receiver FIFO Overrun Interrupt request.
Receiver Data Available Interrupt Enable (RDAIE)
This bit is used to enable Receiver Data Available Interrupt request. The
Receiver will generate this interrupt when the data available in FIFO
exceed the FIFO threshold level.
Set this bit to “1” to enable Receiver Data Available Interrupt request.
Set this bit to “0” to disable Receiver Data Available Interrupt request.
FI
D
Bit
7
EN
The IER, an 8-bit read/write register, is used to enable the CIR interrupt request.
www.ite.com.tw
0b
153
IT8783F/E V0.5
IT8783E/F (For A Version)
9.9.6.3
R/W
R/W
Default
0b
Description
Transmitter Low Data Level Interrupt Enable (TLDLIE)
This bit is used to enable Transmitter Low Data Level Interrupt request.
The Transmitter will generate this interrupt when the data available in
FIFO are less than the FIFO threshold Level.
Set this bit to “1” to enable Transmitter Low Data Level Interrupt request.
Set this bit to “0” to disable Transmitter Low Data Level Interrupt request.
TI
AL
Bit
0
CIR Receiver Control Register (RCR)
The RCR, an 8-bit read/write register, is used to control the CIR Receiver.
Address: Base Address + 2h (Powered by VBAT)
Default
0b
6
R/W
0b
5
R/W
0b
4
R/W
0b
R/W
0b
N
3
R/W
C
O
2-0
Description
Receiver Data without Sync. (RDWOS)
This bit is used to control the sync. logic for receiving data.
Set this bit to “1” to obtain the receiving data without sync. logic.
Set this bit to “0” to obtain the receiving data in sync. logic.
High-Speed Carrier Frequency Select (HCFS)
This bit is used to select whether the carrier frequency is the high-speed
or low-speed.
0: 30-58 kHz (Default)
1: 400-500 kHz
Receiver Enable (RXEN)
This bit is used to enable the Receiver function. Receiver Enable and
RXACT will be activated if the selected carrier frequency is received.
Set this bit to ”1” to enable the Receiver function.
Set this bit to “0” to disable the Receiver function.
Receiver Demodulation Enable (RXEND)
This bit is used to control the Receiver Demodulation logic. If the
Receiver device can not demodulate the correct carrier, set this bit to “1”.
Set this bit to “1” to enable Receiver Demodulation logic.
Set this bit to “0” to disable Receiver Demodulation logic.
Receiver Active (RXACT)
This bit is used to control the Receiver operation. It is set to “0” when the
Receiver is inactive. This bit will be set to “1” when the Receiver detects
a pulse (RXEND=0) or pulse-train (RXEND=1) with the correct carrier
frequency. The Receiver then starts to sample the input data when
Receiver Active is set. Write a “1” to this bit to clear the Receiver Active
condition and make it enter the inactive mode.
Receiver Demodulation Carrier Range (RXDCR[2:0])
These three bits are used to set the tolerance of the Receiver. For the
detailed demodulation carrier frequency, please refer to Table 9-27.
Receiver Demodulation Low Frequency (HCFS = 0) and Table 9-28.
Receiver Demodulation High Frequency (HCFS = 1) on page 158 and
159.
EN
R/W
R/W
FI
D
Bit
7
www.ite.com.tw
001b
154
IT8783F/E V0.5
Functional Description
9.9.6.4
CIR Transmitter Control Register 1 (TCR1)
The TCR1, an 8-bit read/write register, is used to control the Transmitter.
R/W
R/W
Default
0b
6
R/W
0b
5-4
R/W
0b
2
0b
R/W
0b
R/W
0b
16-Byte Mode
32-Byte Mode
00
1
1 (Default)
01
3
7
10
7
17
11
13
25
Transmitter Run Length Enable (TXRLE)
This bit controls the Transmitter Run Length encoding/decoding mode,
which condenses a series of “1” or “0” into one byte with the bit value
stored in bit 7 and number of bits minus 1 in bit 6-0.
Set this bit to “1” to enable the Transmitter Run Length mode.
Set this bit to “0” to disable the Transmitter Run Length mode.
Transmitter Deferral (TXENDF)
This bit is used to avoid Transmitter underrun condition. When it is set to
“1”, the Transmitter FIFO data will be kept until the transmitter time-out
condition occurs, or FIFO reaches full.
Transmitter Modulation Pulse Mode (TXMPM[1:0])
These two bits are used to define the Transmitter modulation pulse
mode.
TXMPM[1:0]
Modulation Pulse Mode
C_pls mode (Default): Pulses are generated continuously for the entire
logic 0 bit time.
8_pls mode: 8 pulses are generated for each logic 0 bit.
6_pls mode: 6 pulses are generated for each logic 0 bit.
11: Reserved.
C
O
N
1-0
R/W
FIFO Clear (FIFOCLR)
Writing a “1” to this bit clears FIFO. This bit is then cleared to “0”
automatically.
Internal Loopback Enable (ILE)
This bit is used to execute internal loopback for test and must be “0” in
normal operation.
Set this bit to “0” to disable the Internal Loopback mode.
Set this bit to “1” to enable the Internal Loopback mode.
FIFO Threshold Level (FIFOTL)
These two bits are used to set the FIFO threshold level. The FIFO length
is 32 bytes for TX or RX function (ILE = 0) in normal operation and 16
bytes for both TX and RX in the internal loopback mode (ILE = 1).
FI
D
3
Description
EN
Bit
7
TI
AL
Address: Base Address + 3h
www.ite.com.tw
155
IT8783F/E V0.5
IT8783E/F (For A Version)
9.9.6.5
CIR Transmitter Control Register (TCR2)
TI
AL
The TCR2, an 8-bit read/write register, is used to determine the carrier frequency.
C
O
N
FI
D
EN
Address: Base Address + 4h (Powered by VBAT)
Bit
R/W
Default
Description
7-3
R/W
01011b
Carrier Frequency (CFQ[4:0])
These five bits are used to determine the modulation carrier frequency.
Please refer to the following table.
2-0
R/W
100b
Transmitter Modulation Pulse Width (TXMPW[2:0])
These three bits are used to set the Transmitter Modulation pulse width.
The duty cycle of the carrier will be determined according to the settings
of the carrier frequency and the selection of Transmitter Modulation
pulse width.
TXMPW[2:0]
HCFS = 0
HCFS = 1
000
Reserved
Reserved
001
Reserved
Reserved
010
6 μs
0.7 μs
011
7 μs
0.8 μs
100
8.7 μs
0.9 μs (Default)
101
10.6 μs
1.0 μs
110
13.3 μs
1.16 μs
111
Reserved
Reserved
www.ite.com.tw
156
IT8783F/E V0.5
Functional Description
Table 9-26. Modulation Carrier Frequency
Low Frequency
(HCFS =0)
High Frequency
(HCFS = 1)
00000
27 kHz
-
00010
29 kHz
00011
30 kHz
00100
31 kHz
00101
32 kHz
00110
33 kHz
00111
34 kHz
01000
35 kHz
01001
36 kHz
01010
01011
01100
37 kHz
38 kHz (default)
39 kHz
01110
01111
10000
400 kHz
-
450 kHz
-
500 kHz
41 kHz
-
42 kHz
-
43 kHz
-
44 kHz
-
45 kHz
-
10011
46 kHz
-
10100
47 kHz
-
10101
48 kHz
-
10110
49 kHz
-
10111
50 kHz
-
11000
51 kHz
-
11001
52 kHz
-
11010
53 kHz
-
11011
54 kHz
-
11100
55 kHz
-
11101
56 kHz
-
11110
57 kHz
-
11111
58 kHz
-
N
10010
C
O
480 kHz (default)
-
40 kHz
FI
D
10001
-
EN
01101
TI
AL
CFQ
www.ite.com.tw
157
IT8783F/E V0.5
IT8783E/F (For A Version)
Table 9-27. Receiver Demodulation Low Frequency (HCFS = 0)
CFQ
001
Min.
010
Max.
Min.
Max.
Min.
100
Max.
Min.
Max.
Min.
110
Max.
Min.
Max.
(Hz)
26.25 29.75
00010
27.19 30.81 25.38 32.63 23.56 34.44 21.75 36.25 19.94 38.06 18.13 39.88 29k
00011
28.13 31.88 26.25 33.75 24.38 35.63
00100
29.06 32.94 27.13 34.88 25.19 36.81 23.25 38.75 21.31 40.69 19.38 42.63 31k
30
34
28
31.5 22.75 33.25
101
00001
00101
24.5
011
TI
AL
RXDCR
36
26
38
21
22.5
24
35 19.25 36.75
17.5
38.5 28k
37.5 20.63 39.38 18.75 41.25 30k
40
22
42
20
44 32k
00110
30.94 35.06 28.88 37.13 26.81 39.19 24.75 41.25 22.69 43.31 20.63 45.38 33k
00111
31.88 36.13 29.75 38.25 27.63 40.38
01000
32.81 37.19 30.63 39.38 28.44 41.56 26.25 43.75 24.06 45.94 21.88 48.13 35k
01001
33.75 38.25
01010
34.69 39.31 32.38 41.63 30.06 43.94 27.75 46.25 25.44 48.56 23.13 50.88 37k
01011
35.63 40.38 33.25 42.75 30.88 45.13
01100
36.56 41.44 34.13 43.88 31.69 46.31 29.25 48.75 26.81 51.19 24.38 53.63 39k
37.5
42.5
35
40.5 29.25 42.75
27
42.5 23.38 44.63 21.25 46.75 34k
45 24.75 47.25
EN
01101
31.5
25.5
45
32.5
47.5
28.5
30
22.5
49.5 36k
47.5 26.13 49.88 23.75 52.25 38k
50
27.5
52.5
25
55 40k
38.44 43.56 35.88 46.13 33.31 48.69 30.75 51.25 28.19 53.81 25.63 56.38 41k
01111
39.38 44.63 36.75 47.25 34.13 49.88
10000
40.31 45.69 37.63 48.38 34.94 51.06 32.25 53.75 29.56 56.44 26.88 59.13 43k
FI
D
01110
41.25 46.75
10010
42.19 47.81 39.38 50.63 36.56 53.44 33.75 56.25 30.94 59.06 28.13 61.88 45k
10011
43.13 48.88 40.25 51.75 37.38 54.63
10100
44.06 49.94 41.13 52.88 38.19 55.81 35.25 58.75 32.31 61.69 29.38 64.63 47k
45
51
42
49.5 35.75 52.25
54
39
57
33
52.5 28.88 55.13 26.25 57.75 42k
10001
10101
38.5
31.5
34.5
36
55 30.25 57.75
27.5
60.5 44k
57.5 31.63 60.38 28.75 63.25 46k
60
33
63
30
66 48k
45.94 52.06 42.88 55.13 39.81 58.19 36.75 61.25 33.69 64.31 30.63 67.38 49k
10111
46.88 53.13 43.75 56.25 40.63 59.38
11000
47.81 54.19 44.63 57.38 41.44 60.56 38.25 63.75 35.06 66.94 31.88 70.13 51k
11001
49.18 54.55 46.88 57.69 44.78 61.22 42.86 65.22
11010
49.69 56.31 46.38 59.63 43.06 62.94 39.75 66.25 36.44 69.56 33.13 72.88 53k
11011
50.63 57.38 47.25 60.75 43.88 64.13
O
N
10110
11100
40.5
62.5 34.38 65.63 31.25 68.75 50k
41.1 69.77 39.47
75 52k
67.5 37.13 70.88 33.75 74.25 54k
51.56 58.44 48.13 61.88 44.69 65.31 41.25 68.75 37.81 72.19 34.38 75.63 55k
11101
52.5
59.5
49
63
45.5
66.5
42
70
38.5
73.5
35
77 56k
53.44 60.56 49.88 64.13 46.31 67.69 42.75 71.25 39.19 74.81 35.63 78.38 57k
C
11110
37.5
www.ite.com.tw
158
IT8783F/E V0.5
Functional Description
Table 9-28. Receiver Demodulation High Frequency (HCFS = 1)
CFQ
001
Min.
00011
01000
375
9.9.6.6
Max.
Min.
425
350
011
Max.
450
Min.
100
Max.
325
Min.
475
300
101
Max.
500
Min.
275
110
Max.
525
Min.
250
Max. (Hz)
550 400k
421.9 478.1 393.8 506.3 365.6 534.4 337.5 562.5 309.4 590.6 281.3 618.8 450k
01011
01011
010
TI
AL
RXDCR
450
510
420
540
390
570
360
600
330
630
300
660 480k
468.8 531.3 437.5 562.5 406.3 593.8
375
625 343.8 656.3 312.5 687.5 500k
CIR Baud Rate Divisor Low Byte Register (BDLR)
The BDLR, an 8-bit read/write register, is used to program the CIR Baud Rate clock.
Address: Base Address + 5h (when BR = 1)
9.9.6.7
R/W
R/W
Default
00h
Description
Baud Rate Divisor Low Byte (BDLR[7:0])
These bits are the low byte of the register, which is to divide the Baud
Rate clock.
EN
Bit
7-0
CIR Baud Rate Divisor High Byte Register (BDHR)
The BDHR, an 8-bit read/write register, is used to program the CIR Baud Rate clock.
Address: Base Address + 6h (when BR = 1)
Description
Baud Rate Divisor High Byte (BDHR[7:0])
These bits are the high byte of the register, which is to divide the Baud
Rate clock.
Baud rate divisor = 115200 / baud rate
Ex1: 2400 bps Æ 115200 /2400 = 48 Æ 48(d) = 0030(h) Æ BDHR = 00h, BDLR = 30h
Ex2: bit width = 0.565 ms ( 1770 bps ( 115200 / 1770 = 65(d) = 0041(h) ( BDHR = 00(h), BDLR = 41(h)
9.9.6.8
R/W
R/W
Default
00h
FI
D
Bit
7-0
CIR Transmitter Status Register (TSR)
N
The TSR, an 8-bit read only register, provides the Transmitter FIFO status.
Address: Base Address + 5h
R/W
R
R
Default
000000b
Description
Reserved
Transmitter FIFO Byte Count (TXFBC[5:0])
Return the number of bytes left in the Transmitter FIFO.
C
O
Bit
7-6
5-0
www.ite.com.tw
159
IT8783F/E V0.5
IT8783E/F (For A Version)
9.9.6.9
CIR Receiver FIFO Status Register (RSR)
TI
AL
The RSR, an 8-bit read only register, provides the Receiver FIFO status.
Address: Base Address + 6h
R/W
R
Default
0b
6
5-0
R
000000b
Description
Receiver FIFO Time-out (RXFTO)
This bit will be set to “1” when a Receiver FIFO time-out condition
occurs.
Following is the condition required for the occurrence of Receiver FIFO
time-out:
When at least one byte of data is queued in the Receiver FIFO for more
than 64 ms and the receiver has been inactive (RXACT=0) for more than
64 ms.
Reserved
Receiver FIFO Byte Count (RXFBC)
Return the number of bytes left in Receiver FIFO.
EN
Bit
7
9.9.6.10 CIR Interrupt Identification Register (IIR)
The IIR, an 8-bit register, is used to identify the pending interrupts.
Address: Base address + 7h
Default
00b
R
1b
Description
Reserved
Interrupt Identification
These two bits are used to identify the source of the pending interrupt.
IIR[1:0] Interrupt Source
00
No interrupt
01
Transmitter Low Data Level Interrupt
10
Receiver Data Stored Interrupt
11
Receiver FIFO Overrun Interrupt
Interrupt Pending
This bit will be set to “1” while an interrupt is pending.
C
O
N
0
R/W
R
FI
D
Bit
7-3
2-1
www.ite.com.tw
160
IT8783F/E V0.5
Functional Description
9.10
Parallel Port
TI
AL
The IT8783E/F incorporates one multi-mode high performance parallel port, which supports the IBM AT, PS/2
compatible bi-directional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP) and the Extended
Capabilities Port (ECP). For enabling/ disabling, changing the base address of the parallel port, and operation
mode selection, please refer to configuration registers for the detail.
Table 9-29. Parallel Port Connector in Different Modes
Host Connector
Pin No.
SPP
EPP
ECP
1
11
STB#
WRITE#
NStrobe
2-9
12- 19
PD0 - 7
PD0 - 7
PD0-7
10
6
ACK#
INTR
11
5
BUSY
WAIT#
Busy PeriphAck(2)
12
4
PE
(NU) (1)
PError nAckReverse(2)
13
3
SLCT
(NU) (1)
Select
14
10
15
9
16
8
17
7
EN
nAck
AFD#
DSTB#
nAutoFd HostAck(2)
ERR#
(NU) (1)
nFault nPeriphRequest(2)
INIT#
(NU) (1)
nInit nReverseRequest(2)
SLIN#
ASTB#
nSelectIn
9.10.1
FI
D
Note 1: NU: Not used.
Note 2: Fast mode.
Note 3: For more information, please refer to the IEEE 1284 standard.
SPP and EPP Modes
Table 9-30. Address Map and Bit Map for SPP and EPP Modes
Register
Data Port
Address
I/O
Base 1+0h R/W
D1
D2
D3
D4
D5
D6
D7
Mode
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SPP/EPP
TMOUT
1
1
Status Port
Base 1+1h
Control Port
Base 1+2h R/W
STB
AFD
INIT
SLIN IRQE PDDIR
EPP Address Port Base 1+3h R/W
PD0
PD1
PD2
PD3
PD4
N
R
D0
ERR# SLCT
PE
ACK# BUSY# SPP/EPP
1
1
SPP/EPP
PD5
PD6
PD7
EPP
Base 1+4h R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port1
Base 1+5h R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port2
Base 1+6h R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
Base 1+7h R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
O
EPP Data Port0
EPP Data Port3
Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60,
0X61).
C
9.10.1.1 Data Port (Base Address 1 + 00h)
This is a bi-directional 8-bit data port. The direction of data flow is determined by the bit 5 of the logic state of
the control port register, which forwards the direction when the bit is low and reverses the direction when the
bit is high.
www.ite.com.tw
161
IT8783F/E V0.5
IT8783E/F (For A Version)
9.10.1.2 Status Port (Base Address 1 + 01h)
TI
AL
This is a read only register. Writing to this register has no effects. The contents of this register are latched
during an IOR cycle.
EN
Bit 7 - BUSY#: Inverse of printer BUSY signal; a logic "0" means that the printer is busy and cannot accept
another character. A logic "1" means that it is ready to accept the next character.
Bit 6 - ACK#: Printer acknowledge; a logic "0" means that the printer has received a character and is ready to
accept another. A logic "1" means that it is still processing the last character.
Bit 5 - PE: Paper end; a logic "1" indicates the paper end.
Bit 4 - SLCT: Printer selected; a logic "1" means that the printer is on line.
Bit 3 - ERR#: Printer error signal; a logic "0" means an error has been detected.
Bits 2, 1 - Reserved: These bits are always "1" at read.
Bit 0 - TMOUT: This bit is valid only in the EPP mode and indicates that a 10-msec time-out has occurred in
EPP operation. A logic "0" means no time-out occurs and a logic “1” means that a time-out error has been
detected. This bit is cleared by an LRESET# or by writing a logic “1” to it. When the IT8783E/F is selected as
the non-EPP mode (SPP or ECP), this bit is always a logic "1" at read.
9.10.1.3 Control Port (Base Address 1 + 02h)
FI
D
This port provides all output signals to control the printer. The register can be read and written.
Bit 6, 7- Reserved: These two bits are always "1" at read.
Bit 5 - PDDIR: Data port direction control. This bit determines the direction of the data port register. Set this
bit "0" to output the data port to PD bus, and "1" to input from PD bus.
Bit 4 - IRQE: Interrupt request enable. Setting this bit "1" enables the interrupt request from the parallel port to
the Host. An interrupt request is generated by a "0" to "1" transition of the ACK# signal.
Bit 3 - SLIN: Inverse of SLIN# pin; setting this bit to "1" selects the printer.
Bit 2 - INIT: Initiate printer; setting this bit to "0" initializes the printer.
Bit 1 - AFD: Inverse of the AFD# pin; setting this bit to "1" causes the printer to automatically advance one
line after each line is printed.
Bit 0 - STB: Inverse of the STB# pin; this pin controls the data strobe signal to the printer.
9.10.1.4 EPP Address Port (Base Address 1 + 03h)
N
The EPP Address Port is only available in the EPP mode. When the Host writes data to this port, the contents
of D0 -D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active when LPC
I/O WRITE cycle is at this address) causes an EPP ADDRESS WRITE cycle. When the Host reads data from
this port, the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active when LPC I/O
READ cycle is at this address) causes an EPP ADDRESS READ cycle.
9.10.1.5 EPP Data Ports 0-3 (Base Address 1 + 04-07h)
C
O
The EPP Data Ports are only available in the EPP mode. When the Host writes data to these ports, the
contents of D0 - D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active
when LPC I/O WRITE cycle is at this address) causes an EPP DATA WRITE cycle. When the Host reads
data from these ports, the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active
when LPC I/O READ cycle is at this address) causes an EPP DATA READ cycle.
9.10.2
EPP Mode Operation
When the parallel port of the IT8783E/F is set in the EPP mode, the SPP mode is also available. If no EPP
Address/Data Port address is decoded (Base address + 03h- 07h), the PD bus is in the SPP mode, and the
output signals such as STB#, AFD#, INIT#, and SLIN# are set by the SPP control port. The direction of the
data port is controlled by bit 5 of the control port register. There is a 10-msec time required to prevent the
system from lockup. The time has elapsed from the beginning of the IOCHRDY (Internal signal: When active,
www.ite.com.tw
162
IT8783F/E V0.5
Functional Description
TI
AL
the IT8783E/F will issue Long Wait in SYNC field) high (EPP READ/WRITE cycle) to WAIT# being deasserted. If a time-out occurs, the current EPP READ/WRITE cycle will be aborted and a logic "1" will be read
in the bit 0 of the status port register. The Host must write 0 to bit 0, 1, 3 of the control port register before any
EPP READ/WRITE cycle (EPP spec.). Pin STB#, AFD# and SLIN# are controlled by hardware for the
hardware handshaking during EPP READ/WRITE cycle.
9.10.2.1 EPP ADDRESS WRITE
1.
2.
3.
4.
The Host writes a byte to the EPP Address Port (Base address + 03h). The chip drives D0 - D7 onto
PD0 - PD7.
The chip asserts WRITE# (STB#) and ASTB# (SLIN#) after IOW becomes active.
The peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then,
the chip de-asserts ASTB#, latches the address from D0 - D7 to PD bus, allowing the Host to complete
the I/O WRITE cycle.
The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the
chip de-asserts WRITE to terminate the cycle.
2.
3.
4.
The Host reads a byte from the EPP Address Port. The chip drives PD bus to tri-state for the peripheral
to drive.
The chip asserts ASTB# after IOR becomes active.
The peripheral drives the PD bus valid and de-asserts WAIT#, indicating that the chip may begin the
termination of this cycle. Then, the chip de-asserts ASTB#, latches the address from PD bus to D0 -D7,
allowing the Host to complete the I/O READ cycle.
The peripheral drives the PD bus to tri-state and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
FI
D
1.
EN
9.10.2.2 EPP ADDRESS READ
9.10.2.3 EPP DATA WRITE
1.
2.
3.
N
4.
The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto
PD0 -PD7.
The chip asserts WRITE# (STB#) and DSTB# (AFD#) after IOW becomes active.
The peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then,
the chip de-asserts DSTB#, latches the data from D0 - D7 to the PD bus, allowing the Host to complete
the I/O WRITE cycle.
The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the
chip de-asserts WRITE to terminate the cycle.
9.10.2.4 EPP DATA READ
1.
O
2.
3.
The Host reads a byte from the EPP DATA Port. The chip drives PD bus to tri-state for the peripheral to
drive.
The chip asserts DSTB# after IOR becomes active.
The peripheral drives PD bus valid and de-asserts WAIT#, indicating that the chip may begin the
termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from PD bus to D0 - D7,
allowing the host to complete the I/O READ cycle.
The peripheral tri-states the PD bus and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
C
4.
9.10.3
ECP Mode Operation
This mode is both software and hardware compatible with the existing parallel ports, allowing ECP to be used
as a standard LPT port when the ECP mode is not required. It provides an automatic high-burst-bandwidth
channel that supports DMA or the ECP mode in both forward and reverse directions. A 16-byte FIFO is
www.ite.com.tw
163
IT8783F/E V0.5
IT8783E/F (For A Version)
TI
AL
implemented in both forward and reverse directions to smooth data flow and enhance the maximum
bandwidth requirement allowed. The port supports automatic handshaking for the standard parallel port to
improve compatibility and expedite the mode transfer. It also supports run-length encoded (RLE)
decompression in hardware. Compression is accomplished by counting identical bytes and transmitting an
RLE byte that indicates how many times a byte has been repeated. The IT8783E/F does not support
hardware RLE compression. For the detailed description, please refer to "Extended Capabilities Port Protocol
and ISA Interface Standard".
Table 9-31. Bit Map of ECP Register
Register
D7
D6
D5
D4
data
PD7
PD6
PD5
PD4
ecpAFifo
Addr/RLE
dsr
nBusy
nAck
PError
Select
dcr
1
1
PDDIR
IRQE
D3
D2
D1
D0
PD3
PD2
PD1
PD0
Address or RLE field
1
1
1
SelectIn
nInit
AutoFd
Strobe
cFifo
Parallel Port Data FIFO
ecpDFifo
EN
nFault
ECP Data FIFO
tFifo
Test FIFO
cnfgA
0
0
cnfgB
0
intrValue
ecr
mode
0
1
0
0
0
0
0
0
0
0
0
0
nErrIntrEn
dmaEn
ServiceIntr
full
empty
FI
D
9.10.3.1 ECP Register Definitions
Table 9-32. ECP Register Definitions
Name
Address
I/O
ECP Mode
Base 1 +000H
R/W
000-001
Base 1 +000H
R/W
011
ECP FIFO (Address)
Base 1 +001H
R/W
All
Status Register
Base 1 +002H
R/W
All
Control Register
Base 2 +000H
R/W
010
Parallel Port Data FIFO
Base 2 +000H
R/W
011
ECP FIFO (DATA)
tFifo
Base 2 +000H
R/W
110
Test FIFO
cnfgA
Base 2 +000H
R
111
Configuration Register A
cnfgB
Base 2 +001H
R/W
111
Configuration Register B
Base 2 +002H
R/W
All
Extended Control Register
data
ecpAFifo
dsr
dcr
cFifo
O
N
ecpDFifo
ecr
Function
Data Register
C
Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60,
0X61).
Note 2: The Base address 2 depends on the Logical Device configuration registers of Parallel Port (0X62,
0X63).
www.ite.com.tw
164
IT8783F/E V0.5
Functional Description
9.10.3.2 ECP Mode Description
Table 9-33. ECP Mode Description
Description
000
Standard Parallel Port Mode
001
PS/2 Parallel Port Mode
010
Parallel Port FIFO Mode
011
ECP Parallel Port Mode
110
Test Mode
111
Configuration Mode
TI
AL
Mode
Note: For the mode selection, please refer to the ECP Register Description for the detail.
9.10.3.3 ECP Pin Description
Table 9-34. ECP Pin Description
EN
Attribute
Description
Used for handshaking with Busy to write data and addresses into the
O
peripheral device.
Address or data or RLE data.
PD0-PD7
I/O
Used for handshaking with nAutoFd to transfer data from the peripheral
nAck (PeriphClk)
I
device to the Host.
The peripheral uses this signal for flow control in the forward direction
Busy (PeriphACK)
I
(handshaking with nStrobe). In the reverse direction, this signal is used to
determine whether a command or data information is present on PD0-PD7.
Used to acknowledge nInit from the peripheral which drives this signal low,
Perror
I
allowing the host to drive the PD bus.
(nAckReverse)
Printer On-Line Indication.
Select
I
In the reverse direction, this signal is used for handshaking between the nAck
nAutoFd (HostAck)
O
and the Host. When it is asserted, a peripheral data byte is requested. In the
forward direction, this signal is used to determine whether a command or data
information is present on PD0 - PD7.
In the forward direction (only), the peripheral is allowed (but not required) to
nFault
I
assert this signal (low) to request a reverse transfer while entering the ECP
(nPeriphRequest)
mode. The signal provides a mechanism for peer-to-peer communication. It is
typically used to generate an interrupt to the host, which has the ultimate
control over the transfer direction.
The host may drive this signal low to place the PD bus in the reverse
nInit
O
direction. In the ECP mode, the peripheral is permitted to drive the PD bus
(nReverseRequest)
when nInit is low, and nSelectIn is high.
NSelectIn
O
Always inactive (high) in the ECP mode.
(1284 Active)
O
N
FI
D
Name
nStrobe (HostClk)
9.10.3.4 Data Port (Base 1+00h, Modes 000 and 001)
C
Its contents will be cleared by a RESET. In a WRITE operation, the contents of the LPC data fields are
latched by the Data Register. The contents are then sent without being inverted to PD0-PD7. In an READ
operation, the contents of data ports are read and sent to the host.
www.ite.com.tw
165
IT8783F/E V0.5
IT8783E/F (For A Version)
9.10.3.5 ecpAFifo Port (Address/RLE) (Base 1 +00h, Mode 011)
TI
AL
Any data byte written to this port is placed in FIFO and tagged as an ECP Address/RLE. The hardware then
automatically sends these data to the peripheral. Operation of this port is only valid in the forward direction
(dcr(5)=0).
9.10.3.6 Device Status Register (dsr) (Base 1 +01h, Mode All)
Bit 0, 1 and 2 of this register are not implemented. The states of these bits remain high in a READ operation
of the Printer Status Register.
dsr(7): This bit is the inverted level of the Busy input.
dsr(6): This bit is the state of the nAck input.
dsr(5): This bit is the state of the PError input.
dsr(4): This bit is the state of the Select input.
dsr(3): This bit is the state of the nFault input.
dsr(2)-dsr(0): These bits are always 1.
EN
9.10.3.7 Device Control Register (dcr) (Base 1+02h, Mode All)
FI
D
Bit 6 and 7 of this register have no function. They are set high during the READ operation, and cannot be
written any data. Contents in bit 0-5 are initialized to 0 when the RESET pin is active.
dcr(7)-dcr(6): These two bits are always high.
dcr(5): Except in mode 000 and 010, setting this bit low means that the PD bus is in output operation
whereas setting it high means that it is in input operation. This bit will be forced to low in mode 000.
dcr(4): Setting this bit high enables the interrupt request from peripheral to the host due to a rising edge
of the nAck input.
dcr(3): It is inverted and output to SelectIn.
dcr(2): It is output to nInit without inversion.
dcr(1): It is inverted and output to nAutoFd.
dcr(0): It is inverted and output to nStrobe.
9.10.3.8 Parallel Port Data FIFO (cFifo) (Base 2+00h, Mode 010)
Bytes written or DMA transferred from the Host to this FIFO are sent by a hardware handshaking to the
peripheral according to the Standard Parallel Port protocol. This operation is only defined for the forward
direction.
N
9.10.3.9 ECP Data FIFO (ecpDFifo) (Base 2+00h, Mode 011)
O
When the direction bit dcr(5) is 0, bytes written or DMA transferred from the Host to this FIFO are sent by
hardware handshaking to the peripheral according to the ECP parallel port protocol. When dcr(5) is 1, data
bytes from the peripheral to this FIFO are read in an automatic hardware handshaking. The Host can receive
these bytes by performing READ operation or DMA transfer from this FIFO.
9.10.3.10 Test FIFO (tFifo) (Base 2+00h, Mode 110)
C
The host may operate READ/WRITE or DMA transfer to this FIFO in any directions. Data in this FIFO will be
displayed on the PD bus without using hardware protocol handshaking. The tFifo will not accept new data
after it is full. Making a READ from an empty tFifo causes the last data byte to return.
www.ite.com.tw
166
IT8783F/E V0.5
Functional Description
9.10.3.11 Configuration Register A (cnfgA) (Base 2+00h, Mode 111)
TI
AL
This read only register indicates to the system that interrupts are ISA-Pulses compatible. This is an 8-bit
implementation by returning a 10h.
9.10.3.12 Configuration Register B (cnfgB) (Base 2+01h, Mode 111)
This register is read only.
cnfgB(7): A logic “0” read indicates that the chip does not support hardware RLE compression.
cnfgB(6): Reserved.
cnfgB(5)-cnfg(3): A value 000 read indicates that the interrupt must be selected with jumpers.
cnfgB(2)-cnfg(0): A value 000 read indicates that the DMA channel is set to 8-bit DMA.
9.10.3.13 Extended Control Register (ecr) (Base 2+02h, Mode All)
EN
This is an ECP function control register.
ecr(7)-ecr(5): These bits are used for READ/WRITE and mode selection.
Table 9-35. Mode and Description of Extended Control Register (ECR)
Mode and Description
Standard Parallel Port Mode(SPPM)
000
The FIFO is reset and the direction bit dcr(5) is always 0 (forward direction) in this mode.
PS/2 Parallel Port Mode(PPPM)
It is similar to the SPP mode, except that the dcr(5) is read/write. When dcr(5) is 1, the PD bus is
001
tri-state. Reading the data port returns the value on the PD bus instead of the value of the data
register.
Parallel Port Data FIFO Mode(PPDFM)
This mode is similar to the 000 mode, except that the Host writes or DMA transfers the data bytes to
010
FIFO. The FIFO data are then transmitted to the peripheral using the standard parallel port protocol
automatically. This mode is only valid in the forward direction (dcr(5)=0).
ECP Parallel Port Mode(EPPM)
In the forward direction, bytes in the ecpDFifo and ecpAFifo are placed in a single FIFO and
011
automatically transmitted to the peripheral under the ECP protocol. In the reverse direction, bytes
are transmitted to the ecpDFifo from the ECP port.
100, 101 Reserved; undefined
Test Mode(TM )
110
In this mode, FIFO may be read from or written to, but it cannot be sent to the peripheral.
Configuration Mode(CM)
111
In this mode, the cnfgA and cnfgB registers are accessible at 0x400 and 0x401.
O
N
FI
D
ECR
ecr(4): nErrIntrEn, READ/WRITE, Valid in ECP(011) Mode
1: Disable the interrupt generated on the asserting edge of the nFault input.
0: Enable the interrupt pulse on the asserting edge of the nFault. An interrupt pulse will be generated if
nFault is asserted or if this bit is written from 1 to 0 in the low-level nFault.
C
ecr(3): dmaEn, READ/WRITE
1: Enable DMA. DMA is started when serviceIntr (ecr(2)) is 0.
0: Disables DMA unconditionally.
ecr(2): ServiceIntr, READ/WRITE
1: Disable DMA and all service interrupts.
0: Enable the service interrupts. This bit will be set to “1” by hardware when one of the three service
www.ite.com.tw
167
IT8783F/E V0.5
IT8783E/F (For A Version)
TI
AL
interrupts occurs.
Writing “1” to this bit will not generate an interrupt.
Case 1: dmaEn=1
During DMA, this bit will be set to 1 (a service interrupt generated) if the terminal count is reached.
Case 2: dmaEn=0, dcr(5)=0
This bit is set to 1 (a service interrupt generated) whenever there is writeIntrThreshold or more bytes
space free in FIFO.
9.10.3.14 Mode Switching Operation
EN
Case 3: dmaEn=0, dcr(5)=1
This bit is set to 1 (a service interrupt generated) whenever there is readIntrThreshold or more valid bytes
to be read from FIFO.
ecr(1): full, read only
1: FIFO is full and cannot accept another byte.
0: FIFO has at least one free data byte space.
ecr(0): empty, read only
1: FIFO is empty.
0: FIFO contains at least one data byte.
In programmed I/O control (mode 000 or 001), P1284 negotiation and all other tasks that happen before data
transmission are software-controlled. Setting the mode to 011 or 010 will cause the hardware to perform an
automatic control-line handshaking, transferring information between the FIFO and the ECP port.
For mode 000 and 001, they may be immediately switched. To change the direction, the mode must be set to
001 first.
FI
D
In the extended forward mode, FIFO must be cleared and all the signals must be de-asserted before
returning to mode 000 or 001. In the ECP reverse mode, all data must be read from FIFO before returning to
mode 000 or 001. Usually, unneeded data are accumulated during ECP reverse handshaking when the mode
is changed during a data transfer. In such a condition, nAutoFd will be de-asserted regardless of the transfer
state. To avoid bugs during handshaking signals, these guidelines must be followed.
9.10.3.15 Software Operation (ECP)
N
Before the ECP operation can be started, it is necessary for the host to switch the mode to 000 first in order
to negotiate with the parallel port. During this process, the Host determines whether the peripheral supports
the ECP protocol.
After this negotiation is completed, the mode is set to 011 (ECP). To enable the drivers, the direction must be
set to 0. Both strobe and autoFd are set to 0, causing nStrobe and nAutoFd signals to be de-asserted.
O
All FIFO data transfer is PWord-wide and PWord aligned. Permitted only in the forward direction,
Address/RLE transfers are byte-wide. The ECP Address/RLE bytes may be automatically sent by writing to
the ecpAFifo. Similarly, data PWords may be automatically sent via the ecpDFifo.
C
To change the direction, the host has to switch the mode to 001. It then negotiates either the forward or
reverse channel, sets the direction to 1 or 0, and finally switches the mode to 001. If the direction is set to 1,
the hardware performs the handshaking for each ECP data byte read, and then tries to fill FIFO. At this time,
PWords may be read from the ecpDFifo while retaining data. It is also possible to perform the ECP transfer
by handshaking with individual bytes under programmed control in mode 001 or 000 even though this is a
comparatively time-consuming approach.
9.10.3.16 Hardware Operation (DMA)
www.ite.com.tw
168
IT8783F/E V0.5
Functional Description
TI
AL
The Standard PC DMA protocol (through LDRQ#) is followed. As in the programmed I/O case, software sets
the direction and state. Next, the desired count and memory addresses are programmed into DMA controller.
The dmaEn is set to 1, and the serviceIntr is set to 0. To complete the process, the DMA channel with the
DMA controller is unmasked. The contents of FIFO are emptied or filled by DMA using the right mode and
direction.
DMA is always transferred to or from FIFO located at 0 x 400. By generating an interrupt and asserting a
serviceIntr, DMA is disabled when the DMA controller reaches the terminal count. By not asserting LDRQ#
for more than 32 consecutive DMA cycles, blocking of refresh requests is eliminated.
When it is necessary to disable a DMA while performing transfer, the host DMA controller is disabled,
serviceIntr is then set to 1, and dmaEn is next set to 0. If the contents in FIFO are empty or full, DMA will start
again. This is first done by enabling the host DMA controller, and then setting dmaEn to 1. Finally, serviceIntr
is set to 0. Upon completion of a DMA transfer in the forward direction, the software program must wait until
the contents in FIFO are empty and the busy line is low, ensuring that all data successfully reach the
peripheral device.
EN
9.10.3.17 Interrupt
FI
D
It is necessary to generate an interrupt when any of the following states is reached.
1. serviceIntr = 0, dmaEn = 0, direction = 0, and the number of PWords in the FIFO is greater than or equal
to writeIntrThreshold.
2. serviceIntr = 0, dmaEn = 0, direction = 1, and the number of PWords in the FIFO is greater than or equal
to readIntrThreshold.
3. serviceIntr = 0, dmaEn = 1, and DMA reaches the terminal count.
4. nErrIntrEn = 0 and nFault goes from high to low or when nErrIntrEn is set from 1 to 0 and nFault is
asserted.
5. ackIntEn = 1. In current implementation of using existing parallel ports, the generated interrupt may be
either edge or level trigger type.
9.10.3.18 Interrupt-driven Programmed I/O
N
It is also possible to use an interrupt-driven programmed I/O to execute either ECP or parallel port FIFOs. An
interrupt will occur in the forward direction when serviceIntr is 0 and the number of free PWords in the FIFO is
equal to or greater than writeIntrThreshold. If either of these conditions is not met, it may be filled with
writeIntrThreshold PWords. An interrupt will occur in the reverse direction when serviceIntr is 0 and the
number of available PWords in the FIFO is equal to readIntrThreshold. If it is full, the FIFO can be completely
emptied in a single burst. If it is not full, only a number of PWords equal to readIntrThreshold may be read
from the FIFO in a single burst. In the Test mode, software can determine the values of writeIntrThreshold,
readIntrThreshold, and FIFO depth while accessing the FIFO.
O
For any PC LPC bus implementation adjusted to expedite DMA or I/O transfer, it is necessary to ensure that
the bandwidth on ISA is maintained on the interface. Although the LPC (even PCI) bus of PC cannot be
directly controlled, the interface bandwidth of ECP port can be constrained to perform at the optimum speed.
(19) Standard Parallel Port
C
In the forward direction with DMA, the standard parallel port is run at or close to the permitted peak bandwidth
of 500 KB/sec. The state machine does not examine nAck, but just begins the next DMA based on the Busy
signal.
www.ite.com.tw
169
IT8783F/E V0.5
IT8783E/F (For A Version)
9.11
Keyboard Controller (KBC)
TI
AL
The keyboard controller is implemented using an 8-bit microcontroller that is capable of executing the 8042
instruction set. For general information, please refer to the description of the 8042 in the 8-bit controller
handbook. In addition, the microcontroller can enter the power-down mode by executing two types of
power-down instructions.
Figure 9-7. Keyboard and Mouse Interface
Keyboard P20
Controller P21
GATEA20
KCLK
EN
P26
T0
KRST*
KDAT
P23
T1
MCLK
P22
P11
MDAT
P24
KIRQ
P25
MIRQ
FI
D
9.11.1
P27
P10
Host Interface
N
The keyboard controller interfaces with the system through the 8042 style host interface. The following table
shows how the interface decodes the control signals.
Table 9-36. Data Register READ/WRITE Controls
R/W*
60h
R
READ DATA
60h
W
WRITE DATA, (Clear F1)
64h
R
READ Status
64h
W
WRITE Command, (Set F1)
Function
C
O
Host Address Note
Note:
These are the default values of LDN5, 60h and 61h (DATA); LDN5, 62h and 63h (Command). All these
registers are programmable.
READ DATA: This is an 8-bit read only register. When read, the KIRQ output is cleared and OBF flag in the
status register is cleared.
WRITE DATA: This is an 8-bit write only register. When written, the F1 flag of the Status register is cleared
www.ite.com.tw
170
IT8783F/E V0.5
Functional Description
9.11.2
TI
AL
and the IBF bit is set.
READ Status: This is an 8-bit read only register. Refer to the description of the Status register for more
information.
WRITE Command: This is an 8-bit write only register. When written, both F1 and IBF flags of the Status
register are set.
Data Registers and Status Register
The keyboard controller provides two data registers: one is DBIN for data input, and the other is DBOUT for
data output. Both are 8-bit wide. A write (microcontroller) to the DBOUT will load Keyboard Data Read Buffer,
set OBF flag and set the KIRQ output. A read (microcontroller) of the DBIN will read the data from the
Keyboard Data or Command Write Buffer and clear the IBF flag.
EN
The status register holds information concerning the status of the data registers, the internal flags, and some
user-defined status bits. Please refer to Table 9-37. Status Register on page 171. The bit 0 OBF is set to “1”
when the microcontroller writes data into DBOUT, and is cleared when the system initiates a DATA READ
operation. The bit 1 IBF is set to “1” when the system initiates a WRITE operation, and is cleared when the
microcontroller executes an “IN A, DBB” instruction. The F0 and F1 flags can be set or reset when the
microcontroller executes clear and complement flag instructions. F1 also holds the system WRITE
information when the system performs the WRITE operation.
Table 9-37. Status Register
6
5
4
3
2
1
0
ST7
ST6
ST5
ST4
F1
F0
IBF
OBF
Keyboard and Mouse Interface
FI
D
9.11.3
7
N
KCLK is the keyboard clock pin. Its output is the inversion of pin P26 of the microcontroller, and the input of
KCLK is connected to the T0 pin of the microcontroller. KDAT is the keyboard data pin; its output is the
inversion of pin P27 of the microcontroller, and the input of KDAT is connected to the P10 of the
microcontroller. MCLK is the mouse clock pin; its output is the inversion of pin P23 of the microcontroller, and
the input of MCLK is connected to the T1 pin of the microcontroller. MDAT is the Mouse data pin; its output is
the inversion of pin P22 of the microcontroller, and the input of MDAT is connected to the P11 of the
microcontroller. KRST# is pin P20 of the microcontroller. GATEA20 is the pin P21 of the microcontroller.
These two pins are used as software controlled or user defined outputs. External pull-ups may be required for
these pins.
9.11.4
KIRQ and MIRQ
C
O
KIRQ is the interrupt request for the keyboard (Default IRQ1), and MIRQ is the interrupt request for the
mouse (Default IRQ12). KIRQ is internally connected to P24 pin of the microcontroller, and MIRQ is internally
connected to pin P25 of the microcontroller.
www.ite.com.tw
171
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
172
IT8783F/E V0.5
DC Electrical Characteristics
10. DC Electrical Characteristics
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to this device. These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied or intended. Exposure to the absolute
maximum rating conditions for extended periods
may
affect
device
reliability.
TI
AL
Applied Voltage ....................................-0.5V to 5.5V
Input Voltage (Vi)....................... -0.5V to VCC+0.5V
Output Voltage (Vo)................. -0.5V to VCC + 0.3V
Operation Temperature (Topt) ....... -40°C to +100°C
Storage Temperature .................... -55°C to +100°C
Power Dissipation ........................................ 300mW
DC Electrical Characteristics (VCC = 5V ± 5%, Ta = -40°C to + 100°C)
Parameter
DOD8 Buffer
VOL
Low Output Voltage
DO16 Buffer
VOL
Low Output Voltage
VOH
High Output Voltage
VOH
High Output Voltage
DO24L Buffer
VOL
Low Output Voltage
VOH
High Output Voltage
DIO8 Type Buffer
VOL
Low Output Voltage
High Output Voltage
N
VOH
IOH = -8 mA
Typ.
Max.
Unit
0.4
V
2.4
V
IOL = 8 mA
0.4
V
IOL = 16 mA
0.4
V
IOH = -16 mA
2.4
V
IOL = 24 mA
IOH = -16 mA
0.4
2.4
IOH = -8 mA
0.4
2.4
Low Input Voltage
VIH
High Input Voltage
IIL
Low Input Leakage
VIN = 0
IIH
High Input Leakage
VIN = VCC
IOZ
3-state Leakage
V
V
IOL = 8 mA
IOH = -8 mA
V
V
IOL = 24 mA
VIL
0.4
2.4
V
V
0.8
2.2
V
V
μA
10
-10
μA
20
μA
C
O
Min.
IOL = 8 mA
FI
D
DO24 Buffer
VOL
Low Output Voltage
Condition
EN
Symbol
DO8 Buffer
VOL
Low Output Voltage
VOH
High Output Voltage
www.ite.com.tw
173
IT8783F/E V0.5
IT8783E/F (For A Version)
DC Electrical Characteristics (VCC = 5V ± 5%, Ta = -40°C to + 100°C)[cont’d]
Parameter
VIL
Low Input Voltage
VIH
High Input Voltage
IIL
Low Input Leakage
IIH
High Input Leakage
Condition
VIN = 0
VIN = VCC
VOL
Low Output Voltage
IOL = 16 mA
VOH
High Output Voltage
IOH = -16 mA
VIL
Low Input Voltage
VIH
High Input Voltage
IIL
Low Input Leakage
IIH
High Input Leakage
Low Input Voltage
VIH
IIL
IIH
VOH
-10
μA
20
μA
0.4
V
High Input Leakage
VIN = VCC
Low Output Voltage
IOL = 24 mA
High Output Voltage
IOH = -16 mA
IIL
Low Input Leakage
VIN = 0
IIH
High Input Leakage
VIN = VCC
μA
10
-10
μA
20
μA
0.4
V
0.8
V
2.2
V
μA
10
-10
μA
20
μA
0.4
V
2.4
V
Low Input Voltage
High Input Voltage
0.8
2.2
Low Input Voltage
VIH
High Input Voltage
IIL
Low Input Leakage
VIN = 0
IIH
High Input Leakage
VIN = VCC
μA
10
-10
μA
20
μA
0.8
V
2.2
174
V
V
IOZ
3-state Leakage
DI Type Buffer
VIL
V
V
IOL = 16 mA
VIN = 0
O
μA
V
VIN = VCC
VIH
C
V
2.4
VIN = 0
Low Input Leakage
www.ite.com.tw
0.8
2.2
High Input Voltage
N
VIL
V
V
IOZ
3-state Leakage
DIO24 Type Buffer
VOL
0.4
10
EN
VIL
Unit
0.8
FI
D
Low Output Voltage
Max.
2.2
3-state Leakage
DIO16 Type Buffer
VOL
Typ.
IOL = 8 mA
IOZ
IOZ
3-state Leakage
DIOD16 Type Buffer
Min.
TI
AL
Symbol
DIOD8 Type Buffer
VOL
Low Output Voltage
V
μA
10
-10
μA
IT8783F/E V0.5
AC Characteristics
11. AC Characteristics (VCC = 5V ± 5%, Ta = -40°C to + 100°C)
Clock Input Timings
Symbol
t1
Parameter
Min.
Clock High Pulse Width when CLKIN=48 MHz
t2
Clock Low Pulse Width when CLKIN=48 MHz
t3
Clock Period when CLKIN=48 MHz
t4
1
1
Clock Low Pulse Width when CLKIN=24 MHz
t6
Clock Period when CLKIN=24 MHz
Not tested. Guaranteed by design.
1
1
1
Typ.
Max.
Unit
8
nsec
8
nsec
20
Clock High Pulse Width when CLKIN=24 MHz
t5
1
TI
AL
11.1
21
22
nsec
18
nsec
18
nsec
40
42
44
nsec
Typ.
Max.
Unit
Figure 11-1. Clock Input Timings
t2 ,t5
EN
t1 , t 4
2.2V
0.8V
t3 ,t6
LCLK (PCICLK) and LRESET Timings
Symbol
t1
t2
t3
t4
FI
D
11.2
Parameter
Min.
LCLK Cycle Time
28
nsec
LCLK High Time
11
nsec
LCLK Low Time
11
nsec
LRESET# Low Pulse Width
1.5
μsec
t2
0.6VCC
t3
0.4VCC p-to-p
(minimum)
0.2VCC
t1
C
O
N
Figure 11-2. LCLK (PCICLK) and LRESET Timings
www.ite.com.tw
175
IT8783F/E V0.5
IT8783E/F (For A Version)
LPC and SERIRQ Timings
Symbol
Parameter
t1
Float to Active Delay
t2
Output Valid Delay
t3
Active to Float Delay
t4
Input Setup Time
t5
Input Hold Time
Min.
Typ.
Max.
3
Unit
nsec
TI
AL
11.3
12
nsec
6
nsec
9
nsec
3
nsec
Figure 11-3. LPC and SERIRQ Timings
LCLK
LPC Signals/
SERIRQ
(Input)
t3
t1
EN
LPC Signals/
SERIRQ
(Output)
t2
Input
Valid
11.4
t5
FI
D
t4
Modem Control Timings
Symbol
t1
Parameter
Min.
Typ.
Float to active delay
Max.
Unit
40
nsec
Figure 11-4. Modem Control Timings
N
CTS1#, DSR1#, DCD1#,
CTS2#, DSR2#, DCD2#
t1
t1
(Read MSR)
(Read MSR)
t1
RI1#, RI2#
C
O
Interrupt
(Internal signal)
www.ite.com.tw
176
IT8783F/E V0.5
AC Characteristics
Floppy Disk Drive Timings
Symbol
Parameter
t1
DIR# active to STEP# low
t2
STEP# active time (low)
t3
DIR# hold time after STEP#
t4
STEP# cycle time
t5
INDEX# low pulse width
t6
RDATA# low pulse width
t7
WDATA# low pulse width
Min.
Typ.
Note1
Max.
Unit
TI
AL
11.5
4X tmclk
nsec
24X tmclk
nsec
Note2
msec
tSRT
tSRT
msec
2X tmclk
nsec
40
nsec
1X tmclk
nsec
EN
Note 1: tmclk is the cycle of main clock for the microcontroller of FDC. tmclk =8M/ 4M/ 2.4M/ 2M for 1M/
500K/ 300K/ 250 Kbps transfer rates respectively.
Note 2: tSRT is the cycle of the Step Rate Time. Please refer to the functional description of the SPECIFY
command of the FDC.
Figure 11-5. Floppy Disk Drive Timings
t3
DIR#
t2
t4
t1
FI
D
STEP#
t5
INDEX#
t6
RDATA#
N
t7
C
O
WDATA#
www.ite.com.tw
177
IT8783F/E V0.5
IT8783E/F (For A Version)
EPP Address or Data Write Cycle Timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
TI
AL
11.6
t1
WRITE# asserted to PD[7:0] valid
50
nsec
t2
ASTB# or DSTB# asserted to WAIT# de-asserted
0
10
μsec
t3
WAIT# de-asserted to ASTB# or DSTB# de-asserted
65
135
nsec
t4
ASTB# or DSTB# de-asserted to WAIT# asserted
0
nsec
t5
WAIT# asserted to WRITE# de-asserted
65
nsec
t6
PD[7:0] invalid after WRITE# de-asserted
0
nsec
Figure 11-6. EPP Address or Data Write Cycle Timings
WRITE#
t2
WAIT#
t1
t6
t5
C
O
N
FI
D
PD[ 7:0 ]
t4
EN
t3
ASTB#
DSTB#
www.ite.com.tw
178
IT8783F/E V0.5
AC Characteristics
11.7
EPP Address or Data Read Cycle Timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
10
μsec
ASTB# or DSTB# asserted to WAIT# de-asserted
t2
ASTB# or DSTB# asserted to PD[7:0] Hi-Z
t3
PD[7:0] valid to WAIT# de-asserted
t4
WAIT# de-asserted to ASTB# or DSTB# de-asserted
65
t5
ASTB# or DSTB# de-asserted to WAIT# asserted
0
nsec
t6
PD[7:0] invalid after ASTB# or DSTB# de-asserted
20
nsec
TI
AL
t1
0
nsec
0
nsec
135
nsec
Figure 11-7. EPP Address or Data Read Cycle Timings
ASTB#
DSTB#
EN
WRITE#
t1
WAIT#
t2
t3
t5
t6
C
O
N
FI
D
PD[ 7:0 ]
t4
www.ite.com.tw
179
IT8783F/E V0.5
IT8783E/F (For A Version)
ECP Parallel Port Forward Timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
TI
AL
11.8
t1
PD[7:0] and nAutoFd valid to nStrobe asserted
50
t2
nStrobe asserted to Busy asserted
t3
Busy asserted to nStrobe de-asserted
t4
nStrobe de-asserted to Busy de-asserted
t5
Busy de-asserted to PD[7:0] and nAutoFd changed
80
180
nsec
t6
Busy de-asserted to nStrobe asserted
70
170
nsec
0
nsec
nsec
70
170
0
nsec
nsec
Figure 11-8. ECP Parallel Port Forward Timings
PD[7:0],
nAutoFd
nStrobe
t5
EN
t1
t2
t4
t6
C
O
N
FI
D
Busy
t3
www.ite.com.tw
180
IT8783F/E V0.5
AC Characteristics
ECP Parallel Port Backward Timings
Symbol
Parameter
Min.
t1
PD[7:0] valid to nAck asserted
t2
nAck asserted to nAutoFd asserted
t3
nAutoFd asserted to nAck de-asserted
t4
nAck de-asserted to nAutoFd de-asserted
t5
nAutoFd de-asserted to PD[7:0] changed
t6
nAutoFd de-asserted to nAck asserted
Typ.
Max.
0
Unit
nsec
TI
AL
11.9
70
170
0
nsec
nsec
70
170
nsec
0
nsec
0
nsec
Figure 11-9. ECP Parallel Port Backward Timings
PD[7:0]
t1
EN
nAck
t5
t2
t4
t6
C
O
N
FI
D
nAutoFd
t3
www.ite.com.tw
181
IT8783F/E V0.5
IT8783E/F (For A Version)
RSMRST#, PWROK1/2, and ACPI Power Control Signal Timings
Symbol
Parameter
Min.
t1
RSMRST# de-actives delay from VCCH5V=4V
t2
PWROK1/2 active delay from VCC5V=4V
t3
Overlap of PSON# and 3VSBSW#
t4
3VSBAW# rising to PWROK1/2 delay time (2A bit 0
=0 )
t4
3VSBAW# rising to PWROK1/2 delay time (2A bit 0
=1 )
t5
3VSBAW# falling to PWROK1/2 delay time
Unit
13
16
19
msec
350
400
450
msec
8.5
10
11.5
msec
1
120
Figure 11-11. RSMRST# Timings
VCCH5V=4+- 0.2V
<-t1
-->
usec
140
160
msec
1
2
msec
VCCH5V=3.5+- 0.2V
Figure 11-12. PWROK1/2 Timings
VC C5V=4+- 0.2V
<--
t2
VCC5V=3.5+- 0.2V
-->
FI
D
VCC5V
RESETCON#
PWROK1/2
Max.
EN
VCCH5V
RSMRST#
Typ.
TI
AL
11.10
C
O
N
Figure 11-13. ACPI Power Signal Timings
www.ite.com.tw
182
IT8783F/E V0.5
Package Information
12. Package Information
unit: inches/mm
LQFP 128L Outline Dimensions
EN
HE
TI
AL
HD
y
Dimensions in
inches
Min. Nom. Max.
0.063
0.002
0.053 0.055 0.057
0.005 0.007 0.009
0.004
0.008
0.547 0.551 0.555
0.547 0.551 0.555
0.016 BSC
0.624 0.630 0.636
0.624 0.630 0.636
0.018 0.024 0.030
0.039 REF
0.004
0°
3.5°
7°
FI
D
Symbol
C
O
N
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
www.ite.com.tw
Dimensions in mm
Min.
0.05
1.35
0.13
0.09
13.90
13.90
Nom.
1.40
0.18
14.00
14.00
0.40 BSC
15.85 16.00
15.85 16.00
0.45
0.60
1.00 REF
0°
3.5°
Max.
1.60
1.45
0.23
0.20
14.10
14.10
16.15
16.15
0.75
0.10
7°
Notes:
1.Dimensions D and E do not include mold protrusion.
2.Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
3.Controlling dimension : Millimeter
4.Reference document : JEDEC MS-026
DI-LQFP128(14*14)v4
183
IT8783F/E V0.5
IT8783E/F (For A Version)
QFP 128L Outline Dimensions
unit: inches/mm
D
D1
102
65
64
TI
AL
103
b
WITH PLATING
E1
E
C
39
128
1
e
38
b
C
0.10 y
Dimension in inches
Min.
Nom.
C
O
N
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
y
θ
www.ite.com.tw
L1
DETAIL "B"
DETAIL "A"
Max.
FI
D
Symbol
EN
SEATING PLANE
D
A1
A
A2
SEE DETAIL "B"
y
BASE METAL
DETAIL "A"
0.134
0.010
0.107 0.112 0.117
0.007 0.009 0.011
0.004
0.008
0.906 0.913 0.921
0.783 0.787 0.791
0.669 0.677 0.685
0.547 0.551 0.555
0.020 BSC
0.029 0.035 0.041
0.063 BSC
0.004
0°
7°
L
O
GAGE PLANE
Dimension in mm
Min.
Nom.
Max.
0.25
2.73
0.17
0.09
23.00
19.90
17.00
13.90
3.40
2.85 2.97
0.22 0.27
0.20
23.20 23.40
20.00 20.10
17.20 17.40
14.00 14.10
0.5 BSC
0.73 0.88 1.03
1.60 BSC
0.10
0°
7°
Notes:
1. Dimensions D1 and E1 do not include mold protrusion.
But mold mismatch is included.
2. Dimensions b does not include dambar protrusion.
3. Controlling dimension: millimeter
DI-QFP128(14*20)v2
184
IT8783F/E V0.5
Ordering Information
Part No.
Package
IT8783E
LQFP 128L
IT8783F
QFP 128L
TI
AL
13. Ordering Information
C
O
N
FI
D
EN
ITE also provides RoHS compliant component. Please mark "-L" at the end of the Part No. when the
parts ordered are RoHS compliant."
www.ite.com.tw
185
IT8783F/E V0.5
EN
TI
AL
IT8783E/F (For A Version)
C
O
N
FI
D
This page is intentionally left blank.
www.ite.com.tw
186
IT8783F/E V0.5
Top Marking Information
PART NO.
DATE CODE
(The seventh week of the year 2006)
0607-XXX
XXXXXX L
TRACKING CODE
FOR LEAD-FREE PACKAGE
(OPTIONAL)
FI
D
EN
LOTID
IT8783E
TI
AL
14. Top Marking Information
PART NO.
DATE CODE
(The seventh week of the year 2006)
0607-XXX
TRACKING CODE
XXXXXX L
FOR LEAD-FREE PACKAGE
(OPTIONAL)
C
O
N
LOTID
IT8783F
www.ite.com.tw
187
IT8783F/E V0.5
N
O
C
TI
AL
EN
FI
D