Datasheet

MC-ACT-DVBMOD
Digital Video Broadcast Modulator
April 23, 2004
Datasheet v1.2
3721 Valley Centre Drive
San Diego, CA 92130 USA
Americas:
+1 800-752-3040
Europe:
+41 (0) 32 374 32 00
Asia:
+(852) 2410 2720
E-mail: [email protected]
URL: www.memecdesign.com/actel
Product Summary
Intended Use
•
DVB Satellite Modulator
•
Microwave Transmitter
Key Features
•
Compatible with DVB standards
•
Conforms to European Telecommunications Standard (ETSI) EN 300 421 v1.1.2
•
Byte wide data path
•
Test points at the output of each block and at the input to the Baseband Shaping block
•
204/188 Reed-Solomon Outer Coder
•
Selectable convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8
•
Supports uncoded (1/1) operation
•
DC to 45+ MHz symbol rate (RS)
•
DC to 70+ MHz bit rate (at 7/8 code rate). Supports SONET STS-1 bit rate at code rates of 7/8 down to 2/3
•
Fully synchronous operation
Targeted Devices
•
Axcelerator Family
•
ProASIC plus
•
ProASIC3
•
ProASIC3E
General Description
The MC-ACT-DVBMOD is a "core" logic module specifically designed for Actel FPGAs that performs the digital
baseband functions required for the transmit side of a DVB satellite link. It accepts MPEG-2 formatted transport
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January 16, 2003
MC-ACT-DVBMOD
Digital Video Broadcast Modulator
April 23, 2004
Datasheet v1.2
packets as input and outputs filtered I/Q symbols suitable for digital to analog conversion and subsequent QPSK
modulation. This core implements five of the functions required for a satellite channel adapter as described by the
DVB standard ETSI EN 300 421 v1.1.2 and shown in Figure 1 of that standard.
Core Deliverables
•
Netlist Version
o Compiled RTL simulation model, compliant with the Actel Libero environment
o Netlist compatible with the Actel Designer place and route tool
•
RTL Version
o Verilog Source Code
•
All
o
o
User Guide
Test Bench
Synthesis and Simulation Support
•
Synthesis: Synplicity
•
Simulation: ModelSim
•
Other tools supported upon request
Verification
•
Test Bench
•
Test Vectors
January 16, 2003
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Digital Video Broadcast (DVB) Modulator
Transmit Data Input
TPD_IN[7:0]
Memec Design
BCLKEN
Byte Timing
Output
SYNC1
Timing Inputs
SYNC_BYT
E
IY0[9:0]
RS_CALC
IY1[9:0]
IY2[9:0]
Control
Inputs
IOFFSET[7:0]
IY3[9:0]
QOFFSET[7:0]
QY0[9:0]
RANDOM_DIS
QY1[9:0]
SYNC_INV_DIS
QY2[9:0]
INTLVR_BYPAS
S
QY3[9:0]
Nyquist Filter
Outputs
UNCODED_EN
RATE_SEL[2:0]
NYQ_TEST
RANDOM_OUT[7:0]
RS_OUT[7:0]
INTLVR_OUT[7:0]
Clock & Reset
Inputs
CLK
IBIT_OUT
RST
QBIT_OUT
Test
Points
IBIT_IN
QBIT_IN
MDS2009b
Figure 1: MC-ACT-DVBMOD Logic Symbol
January 16, 2003
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Digital Video Broadcast (DVB) Modulator
External Logic
Memec Design
MOD-DVB Core
External Logic
IOFFSET[7:0]
IPAD
QOFFSET[7:0]
IPAD
NYQ_TEST
IPAD
IBIT_IN
IPAD
QBIT_IN
IPAD
RATE_SEL[2:0]
IPAD
UNCODED_EN
IPAD
INTLVR_BYPASS
IPAD
IPAD
IPAD
SYNC_INV_DIS
IY0[9:0]
RANDOM_DIS
IY1[9:0]
IY2[9:0]
TPD_IN[7:0]
IPAD
Sync Inversion
&
Randomization
Outer Coder:
Reed-Solomon
RS(204,188,T=8)
Convolutional
Interleaver:
Forney
I=12, M=17
Inner Coder:
Convolutional
Rate 1/2, K=7
Punctured to
2/3,3/4,5/6,7/8
Baseband
Shaping
(Nyquist Filter):
Square Root
Raised Cosine
α = 0.35
IY3[9:0]
QY0[9:0]
QY1[9:0]
QY2[9:0]
QY3[9:0]
SYNC1
IPAD
SYNC_BYTE
IPAD
BCLKEN
OPAD
OPAD
OPAD
OPAD
OPAD
OPAD
OPAD
OPAD
OPAD
RS_CALC
IPAD
CLK
IPAD
RST
STARTUP
IBIT_OUT
QBIT_OUT
INTLVR_OUT[7:0]
IPAD
RS_OUT[7:0]
RANDOM_OUT[7:0]
OPAD
OPAD
OPAD
OPAD
OPAD
MDS2018c
Figure 2: Block Diagram
Functional Description
The MC-ACT-DVBMODr core is partitioned into modules as shown in Figure 2 and as described below.
Sync Inversion and Randomization
The Sync Inversion and Randomization block is the first processing block in the chain. It takes an MPEG-2 transport packet stream as input and produces a randomized data stream with every eighth sync byte inverted.
The DVB standard, ETSI document EN 300 421 v1.1.2, describes a data randomizer to "ensure adequate binary
transitions". The randomizer is a pseudo random binary sequence (PRBS) generator whose output is XORed with
the clear data stream on the transmitter side and with the randomized data on the receiver side. The PRBS
polynomial is specified as: 1 + x14 + x15.
The DVB standard describes a procedure called "Transport Multiplex Adaptation". This is a fancy title for inverting
the sync byte of the first transport packet in a group of eight packets. The sync byte of the first packet is bit-wise
inverted from 0x47 to 0xb8, whereas the sync bytes of the next seven packets remain 0x47. During the inverted
sync byte interval (SYNC 1), the PRBS generator is loaded with a seed value of "100101010000000". After the
seed is loaded, the PRBS generator runs continuously through eight transport packets (8 packets * 188
bytes/packet – 1 byte period/load = 1,503 bytes). During all sync byte intervals, the PRBS output is disabled,
leaving the sync bytes unrandomized.
Outer Coder
The Outer Coder block sits between the output of the Randomizer and the input to the Convolutional Interleaver in
the processing chain. It is a Reed-Solomon encoder, RS(204, 188), that takes the 188-byte randomized transport
packets as input and calculates 16 parity symbols (check bytes) which it appends to the end of each packet to
produce 204-byte error protected packets as output.
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Digital Video Broadcast (DVB) Modulator
Memec Design
8
4
3
2
The Reed-Solomon encoder implements the primitive polynomial, P(x) = x +x +x +x +1, and generator polynomial,
G(x) = (x-a0)(x-a1)…(x-a15), over a Galois field of GF(256).
Convolutional Interleaver
The Convolutional Interleaver block sits between the output of the Outer Coder and the input to the Inner Coder in
the processing chain. It takes 204-byte Reed-Solomon error-protected packets as input and produces 204-byte
interleaved frames as output.
The interleaver is implemented with RAM and a special addressing mechanism to access the RAM as 12 delay
pipes, each one 17 bytes deeper than the previous one. That is, the first delay pipe (branch 0) is 0 bytes deep (no
delay), the second (branch 1) is 17 bytes deep, the third (branch 2) is 34 bytes, and the twelfth (branch 11) is 187
bytes. The total number of byte storage locations required is 1,122. The sync byte of each 204-byte packet is
passed through branch 0 (the zero delay path) and is therefore passed straight through the interleaver without being
written into the RAM. The next byte is written into branch 1, followed by branch 2, etc.; each consecutive byte is
written to the next branch. The branch ordering is, 0, 1, 2, … 10, 11, 0, 1, 2, …
Thus, the sequence repeats every 12 bytes. Note that the 204 byte packets are divisible by 12 (204/12 = 17) and
therefore, sync byte will always pass through the zero delay path (branch 0).
See Figure 4 in the DVB standard, EN 300 421 V1.1.2, for a conceptual diagram of the operation.
Inner Coder
The Inner Coder block sits between the output of the Convolutional Interleaver and the input to the Baseband
Shaping block in the processing chain. It takes bytes from the 204-byte interleaved frames as input and produces
I/Q symbol pairs as output.
The Inner Coder performs three functions: convolutionally encodes input data; optionally punctures certain bits to
obtain higher code rates; and serializes I/Q symbols to be transmitted. The convolutional encoder and puncturing
logic can be disabled with the UNCODED_EN control input, in which case the block only serializes the I/Q symbols
to be transmitted.
See Table 2 in the DVB standard, EN 300 421 V1.1.2, for the definition of punctured codes.
Baseband Shaping
The Baseband Shaping block is the last block in the processing chain. Its input comes from the Inner Coder and its
output goes out of the core, typically through a parallel to serial stage and then to the digital to analog converters
(DACs). It is basically two identical 4x interpolating polyphase FIR filters, one for I and one for Q. Each filter takes a
1-bit input stream and generates four 10-bit filtered output streams. The filtering operation spans 8 symbols.
Device Requirements
Family
Axcelerator
ProASIC plus
ProASIC3
ProASIC3E
Device
Utilization
COMB
54%
57%
47%
21%
AX250-3
APA150
A3P250
A3PE600
Performance
SEQ
55%
13%
14%
6%
Total
54%
70%
61%
27%
80 MHz
34 MHz
54 MHz
54 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
Functional and timing simulation has been performed on the MC-ACT-DVBMOD core using ModelSim. Simulation
vectors used for verification are provided with the core.
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Digital Video Broadcast (DVB) Modulator
Memec Design
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction Description
TPD_IN[7:0]
Input
Transport Packet Data In. This is the byte wide MPEG-2 transport packet data.
The first byte in every transport packet must be a sync byte (0x47).
SYNC1
Input
Sync Byte 1 Indicator. This signal is asserted (high) to indicate that the first sync
byte in a group of eight packets is present on the TPD_IN bus
SYNC_BYTE
Input
Sync Byte Indicator. This signal is asserted (high) to indicate that a sync byte is
present on the TPD_IN bus.
RS_CALC
Input
Parity Calculate. This signal controls whether the Outer Coder block is
calculating the parity (check bytes) or shifting them out.
IOFFSET[7:0]
Input
I-Channel DC Offset Control. This sign extended two’s compliment value is
added to the output of each Nyquist (baseband shaping) filter LUT.
QOFFSET[7:0]
Input
Q-Channel DC Offset Control. Same as IOFFSET above, except this is added to
the Q-channel Nyquist filter outputs.
RANDOM_DIS
Input
Randomizer Disable Control. When asserted (high), the output of the PRBS
generator is not XORed with the data stream. This is used for debug only.
SYNC_INV_DIS
Input
Sync Inversion Disable Control. When asserted (high), inversion of every eighth
sync byte is disabled. This is used for debug only.
INTLVR_BYPASS
Input
Interleaver Bypass Control. Whan asserted (high), the Reed Solomon output
(see RS_OUT below) passes directly to the input of the Convolutional Encoder.
This is used for test purposes only.
UNCODED_EN
Input
Uncoded (1/1) Enable. When asserted (high), the convolutional encoder and
puncturing logic are bypassed and the data bits are sent out in pairs on I_BIT
and Q_BIT. This is strictly a test mode.
RATE_SEL[2:0]
Input
Code Rate Select. These inputs select which of the five puncture patterns to
apply to the output of the convolutional encoder.
NYQ_TEST
Input
Nyquist Filter Test. When asserted (high), the input to the Baseband Shaping
block (Nyquist filter) is sourced from external pins, IBIT_IN and QBIT_IN. This
test mode can be used for system level testing and alignment. When deasserted,
the output of the Inner Coder is the source to the Baseband Shaping block. This
is the normal operating mode.
IBIT_IN
Input
I-Channel Nyquist Filter Test Input. This test input is used when NYQ_TEST is
asserted (see above). When NYQ_TEST is deasserted, this input is ignored.
QBIT_IN
Input
Q-Channel Nyquist Filter Test Input. Similar to IBIT_IN above, but drives the QChannel input to the Nyquist filter.
RST
Input
Reset. Asynchronous reset to every register in the block.
CLK
Input
Clock input. The clock input to every register in the block. This clock is
continuous and operates at the punctured symbol rate, Rs. One I/Q symbol pair
is output on each rising edge.
BCLKEN
Output Byte Clock Enable. This output is asserted (high) when the puncturing logic
needs the next byte. This enable qualifies the clock input to all of the byte wide
blocks.
IY0[9:0], IY1[9:0],
Output I-Channel Nyquist Filter Out, Phases 0-3. These are the outputs of an M=4
polyphase FIR filter.
IY2[9:0], IY3[9:0]
QY0[9:0], QY1[9:0],
QY2[9:0], QY3[9:0]
RANDOM_OUT[7:0]
Output
Q-Channel Nyquist Filter Out, Phases 0-3. Same as the IYn_[9:0] outputs above,
except these feed the Q-channel DAC.
Output
RS_OUT[7:0]
Output
Randomized Packet Data (Test Point). The randomized transport packets come
out here.
Reed Solomon Output (Test Point). The 204-byte error protected packets come
out here.
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Digital Video Broadcast (DVB) Modulator
INTLVR_OUT[7:0]
Output
IBIT_OUT
Output
QBIT_OUT
Output
Memec Design
Interleaved Frame Data Out (Test Point). This data is formatted as shown in
figure 3d of the DVB standard, EN 300 421.
I Channel Output Bit (Test Point). The punctured result of the X output (171o) of
the convolutional encoder.
Q Channel Output Bit (Test Point). The punctured result of the Y output (133o) of
the convolutional encoder.
Table 2: MOD-DVB Signal List
Timing
CLK
BCLKEN
TPD_IN[7:0]
Byte 1
Byte 2
Byte 3
Byte 188
Byte 1
Byte 2
Byte 3
0x47
d1
d2
d187
0x47
d1
d2
SYNC1
SYNC_BYTE
RS_CALC
188 BCLKENs
16 BCLKENs
MDS2020
Figure 3: Data Input and Timing Signals
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Digital Video Broadcast (DVB) Modulator
Memec Design
Recommended Design Experience
For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar
with Actel Libero v2.2 Integrated Design Environment (IDE) and preferably with Synplify and ModelSim.
Ordering Information
Part Number
MC-ACT-DVBMOD-NET
MC-ACT-DVBMOD-VLOG
Description
DVB Modulator Netlist
DVB Modulator Verilog
Table 3: Core Part Numbers
The CORE is provided under license from Memec Design for use in Actel programmable logic devices. Please
contact Memec Design for pricing and more information.
Information furnished by Memec Design is believed to be accurate and reliable. Memec Design reserves the right to
change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or
design, and assumes no responsibility for any errors within this document. Memec Design does not make any
commitment to update this information.
Memec Design assumes no obligation to correct any errors contained herein or to advise any user of this text of any
correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed
features or parameters. Memec Design will not assume any liability for the accuracy or correctness of any support
or assistance provided to a user.
Memec Design does not represent that products described herein are free from patent infringement or from any
other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Memec
Design.
MemecCore products are not intended for use in life support appliances, devices, or systems. Use of a MemecCore
product in such application without the written consent of the appropriate Memec Design officer is prohibited.
All trademarks, registered trademarks, or service marks are property of their respective owners.
Datasheet Revision History
Version
Datasheet 1.1
Datasheet 1.0
January 16, 2003
Date
April 23, 2003
January 16, 2003
Description
Changed corporate address, added CompanionCore logo
First Release
8