SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
•
•
•
•
•
High-Speed 8-Bit Parallel Pipeline Register
Serial Shadow Register With Right-Shift Only
’ALS29818 Performs Parallel-to-Serial and
Serial-to-Parallel Conversion
Designed Specifically for Use in Applications
Such As:
Write Control Store (’ALS29818)
Serial Shadow-Register Diagnostics
’ALS819 Provides Even-Parity Output
Low Power Dissipation . . . 215 mW Typical
’ALS29818 is Functionally Equivalent to AMD
AM29818
Package Options include Plastic Small Outline
Packages, Standard Plastic DIPs, and Plastic
Chip Carriers
SN74ALS819 . . . DW OR JT PACKAGE
(TOP VIEW)
PE
SRCLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDI
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
MODE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDO
ORCLK
SN74ALS819 . . . FN PACKAGE
(TOP VIEW)
DQ0
SRCLK
PE
NC
VCC
MODE
Y0
•
•
•
DQ1
DQ2
DQ3
NC
DQ4
DQ5
DQ6
description
Y1
Y2
Y3
NC
Y4
Y5
Y6
DQ7
SDI
GND
NC
ORCLK
SD0
Y7
The SN74ALS819 and SN74ALS29818 are 8-bit
pipeline registers each with an on-chip shadow
register. They are for use in applications such as
write control store and shadow register diagnostics.
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
The output registers of the ’ALS819 and
’ALS29818 are loaded in parallel from either the
I/O port (DQ0ā −ā DQ7) or the shadow register. The
shadow register of the ’ALS2981A 8 can be
loaded serially or from either the I/O port (Y0ā −ā Y7)
or the pipeline register. The ’ALS819 shadow
register can be loaded serially or from the I/O port
(DQ0ā −ā DQ7). In addition, the ’ALS819 provides a
Parity-Even (PE) output, which monitors parity of
the output register. Operation of these devices is
controlled by the Mode and SDI inputs as shown
in the function table.
SN74ALS29818 . . . DW OR NT PACKAGE
(TOP VIEW)
OEY
SRCLK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDI
GND
The SN74ALS819 and SN74ALS29818 are
characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
MODE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDO
ORCLK
DQ0
SRCLK
OEY
NC
VCC
MODE
Y0
SN74ALS29818 . . . FN PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 1718
Y1
Y2
Y3
NC
Y4
Y5
Y6
DQ7
SDI
GND
NC
ORCLK
SD0
Y7
DQ1
DQ2
DQ3
NC
DQ4
DQ5
DQ6
NC − No internal connection
Copyright 1986, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
•
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•
1
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
logic symbols†
ORCLK
13
2
SRCLK
23
MODE
11
SDI
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
3
4
5
6
7
8
9
10
SN74ALS819
SN74ALS29818
[PIPELINE REGISTER]
[PIPELINE REGISTER]
C6
SRG8
1 /C2
M1/4EN5
Z3/G4
MUX
3
7
1
1
14
SDO
1
OEY 13
ORCLK
EN8
C7
2
SRCLK
23
MODE
11
SDI
SRG8
MUX
1 /C3
M1/5,3D,EN6 3 1
27 1
M2/Z4/G5
1,2D [SHADOW REGISTER]
1,2D/Z10
5
1,2D/Z11
5
DQ0
DQ1
1,2D/Z17
5
10,6D
17,6D
2K
[EVEN PARITY
FOR Y OUTPUTS]
DQ2
DQ3
DQ4
DQ5
DQ6
Z7
22
Y0
21
Y1
20
Y2
19
Y3
18
17 Y4
Y5
16
Y6
15
Y7
1
DQ7
3
4
5
6
7
8
9
10
37,1,2,3D
Z17
6
MUX
10,1
20,1
Z27
7D
8
Z30
PE
MUX
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for DW and NT packages.
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•
SDO
1,3D [SHADOW REGISTER]
30,1,2,3D
Z20
Z10
6
31,1,2,3D
Z21
Z11
6
17,1
27,1
2
14
7D
8
Z37
22
21
20
19
18
17
16
15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
logic diagrams (positive logic)
SN74ALS819
13
ORCLK
Shadow
Register
MODE
SRCLK
M1
1 /C2
11
G1
1
1
1,2D [0]
1,2D
1,2D [1]
[2]
[3]
[4]
[5]
[6]
[7]
SD1
10 −3
MUX
SRG8
23
2
8
SD0
Pipeline
Register
3-State
Buffers
EN
C1
8X
8
8
8X
1D
8
15 −22
Y7−Y0
8
8
SR7
8
14
8
2k
1
8
PE
DQ7−DQ0
SN74ALS29818
1
OEY
13
ORCLK
SRCLK
2
Shadow
Register
MODE
SD1
SRG8
23
1D
M1
1 /C3
M2
11
MUX
G1
1
1
C1
1,3D [0]
1,2,3D
1,2,3D [1]
[2]
[3]
[4]
[5]
[6]
[7]
Pipeline
Register
3-State
Buffer
EN
G1
8 8 X MUX
1
1
8
8X
8
14
8
3-State
Buffer
EN
C1
8
8X
1D
SDO
15 −22
8X
8
Y7−Y0
8
8
8
SR7
10 −3
DQ7−DQ0
8
8
Pin numbers shown are for DW and NT packages.
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•
3
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
SN74ALS819 gate-level logic diagram (positive logic)
ORCLK
SRCLK
SDI
MODE
13
2
11
23
D
D
C1
DQ0
C1
D
C1
C1
4
21
20
6
DQ3 7
DQ4
8
DQ5
9
DQ6
19
18
17
5 Identical Sections
Not Shown
16
15
D
C1
10
C1
Y2
Y3
Y4
Y5
Pin numbers shown are for DW and NT packages.
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•
Y7
QY7
QY7
14
4
To Next
Sheet
Y6
QY2
QY2
QY3
QY3
QY4 To Next
QY4 Sheet
QY5
QY5
QY6
QY6
D
DQ7
To Next
Sheet
Y1
QY1
QY1
5
DQ2
Y0
QY0
QY0
3
D
DQ1
22
To Next
Sheet
SDO
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
SN74ALS819 gate-level logic diagram (positive logic) (continued)
QY0
QY1
QY2
QY3
QY0
QY1
QY2
QY3
From Previous
Sheet
1
PE
QY4
QY5
QY6
QY7
QY4
QY5
QY6
QY7
Pin numbers shown are for DW and NT packages.
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5
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
SN74ALS29818 gate-level logic diagram (positive logic)
1
OEY
13
ORCLK
2
SRCLK
11
SDI
MODE
C1
1D
23
C1
1D
C1
22
Y0
1D
DQ0
3
C1
1D
C1
21
Y1
1D
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
4
5
6
7
8
9
20
19
18
17
16
5 Identical Sections
Not Shown
Y2
Y3
Y4
Y5
Y6
C1
1D
C1
15
1D
DQ7
10
14
Pin numbers shown are for DW and NT packages.
6
Y7
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SD0
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
Function Tables
SN74ALS819
INPUTS
OUTPUT AND I/O
OPERATION OR FUNCTION
MODE
SDI
SRCLK
ORCLK
SDO
Y0 −Y7
PE
DQ0 −DQ7
L
X
↑
X
SR7
OUTPUT
HI-Z
OUTPUT
INPUT
Parallel load shadow register from
DQ0 −DQ7
Serial input, shift right
H
L
↑
X
SDI
(L)
H
L
↑
↑
SDI
(L)
OUTPUT
INPUT
Parallel load shadow register and pipeline
register from DQ0 −DQ7
L
X
X
L
X
X
↑
↑
SR7
−
OUTPUT
INPUT
Load pipeline register from DQ0 −DQ7
L
X
↑
↑
SR7
OUTPUT
INPUT
Load pipeline register from DQ0 −DQ7 while
shifting shadow register
H
H
No↑
↑
SDI
(H)
OUTPUT
OUTPUT
Load pipeline register from shadow register
H
X
X
X
SDI
OUTPUT
−
H
H
X
X
SDI
(H)
OUTPUT
OUTPUT
HOLD
L
X
X
L
X
X
X
X
SR7
−
OUTPUT
HI-Z
Serial data in to serial data out
Hold shadow register, enable DQ0 −DQ7,
transitions on SRCLK ignored
Disable DQ0 −DQ7 outputs
SN74ALS29818
INPUTS
OUTPUT AND I/O
OPERATION OR FUNCTION
MODE
OEY
SDI
SRCLK
ORCLK
SDO
Y0 −Y7
DQ0 −DQ7
L
X
X
↑
X
SR7
−
HI-Z
Serial input, shift right, disable DQ0 −DQ7
INPUT
HI-Z
Parallel load shadow register from Y0 −Y7,
disable DQ0 −DQ7
Parallel load shadow register from pipeline
register, disable DQ0 −DQ7
H
H
L
↑
X
SDI
(L)
H
L
L
↑
No ↑
SDI
(L)
OUTPUT
HI-Z
L
X
X
X
↑
SR7
−
INPUT†
Load pipeline register from DQ0 −DQ7
L
X
X
↑
↑
SR7
−
INPUT†
Load pipeline register from DQ0 −DQ7 while
shifting shadow register
H
X
X
No ↑
↑
SDI
−
−
Load pipeline register from shadow register
H
X
X
X
X
SDI
−
−
Serial data in to serial data out
H
L
L
↑
↑
SDI
(L)
OUTPUT
HI-Z
H
X
H
X
X
SDI
(H)
−
−
H
X
H
↑
X
SDI
(H)
−
OUTPUT
Exchange data between registers,
DQ0 −DQ7 disabled
Hold shadow register, transitions on SRCLK
do not effect shadow register
Enable DQ0 −DQ7 for parallel shadow
register output
† The DQ0 −DQ7 outputs must be disabled before applying data to DQ0 −DQ7.
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7
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
absolute maximum ratings over operating free-air temperature range
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, any input or I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
recommended operating conditions
VCC
VIH
Supply voltage
VIL
Low-level input voltage
High-level input voltage
IOH
High-level output current
IOL
Low-level output current
tw
Pulse duration
tsu
th
th
Setup time before SRCLK↑
Setup time before ORCLK↑
Hold time after RCLK↑
Hold time after ORCLK↑
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
0.8
Y0 −Y7, PE
−3
All others
−1
Y0 −Y7, PE
24
All others
8
SRCLK high or low
25
ORCLK high or low
15
Y0 −Y7 (’ALS29818)†
tsu
MIN
V
mA
mA
ns
5
MODE
12
SDI
10
ORCLK (’ALS29818)†
40
DQ0 −DQ7
MODE (’ALS29818)†
SRCLK‡
15
Y0 −Y7 (’ALS29818)†
5
MODE
2
SDI
0
DQ0 −DQ7
2
MODE (’ALS29818) †
0
ns
8
ns
5
ns
ns
SDI (’ALS819)
TA
Operating free-air temperature
† This setup time ensures that the shadow register will see stable data from the output register.
‡ This setup time ensures that the output register will see stable data from the shadow register.
8
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•
0
70
°C
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
electrical characteristics over recommended operating temperature range (unless otherwise
noted)
PARAMETER
VIK
Y0 −Y7, PE
VOH
All others
Y0 −Y7, PE
VOL
All others
II
IIH‡
IIL‡
TEST CONDITIONS
VCC = 4.75 V,
VCC = 4.75 V,
II = −18 mA
IOH = −3mA
VCC = 4.75 V,
VCC = 4.75 V,
IOH = −1 mA
IOL = 24 mA
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 8 mA
VI = 5.5 V
VCC = 5.25 V,
VI = 2.4 V
MIN
TYP†
2.4
3.2
2.4
3.2
IOS§
’ALS29818
−1.2
V
V
0.5
0.35
0.5
V
0.1
mA
20
µA
− 0.2
VCC = 5.25 V,
VI = 0.5 V
VCC = 5.25 V,
VO = 0
− 0.1
−75
’ALS819
ICC
UNIT
0.35
MODE, SDI
All others
MAX
VCC = 5.25 V,
See Note 1
−250
65
100
85
120
mA
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state current.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 1: ICC is measured with all 3-state outputs in the high-impedance state.
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9
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
SN74ALS819 switching characteristics (see Figure 1)
VCC = 5 V,
CL = 50 pF,
TA = 25°C
MIN
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
MODE
SDO
RL = 2 kΩ
tPLH
tPHL
SDI
SDO
RL = 2 kΩ
tPLH
tPHL
ORCLK
Y0 −Y7
RL = 2 kΩ
tPLH
tPHL
ORCLK
PE
RL = 2 kΩ
tPLH
tPHL
SRCLK
SDO
RL = 2 kΩ
DQ0 −DQ7
R1 = 5 kΩ,
R2 = 2 kΩ
DQ0 −DQ7
R1 = 5 kΩ,
R2 = 2 kΩ
tPZH
tPZL
MODE
tPHZ
tPLZ
MODE
or SDI
or SDI
TEST
CONDITIONS
VCC = 4.75 V to 5.25 V,
CL = 50 pF,
TA = 0°C to 70°C
MIN
MAX
10
14
4
16
8
11
4
13
13
17
7
20
10
14
5
16
10
14
4
16
9
12
4
14
25
32
10
45
16
20
8
25
14
18
7
22
9
12
5
15
11
15
5
17
14
19
8
20
48
75
23
80
21
29
12
35
UNIT
ns
ns
ns
ns
ns
ns
ns
SN74ALS29818 switching characteristics (see Figure 1)
VCC = 5 V,
CL = 50 pF,
TA = 25°C
MIN
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
MODE
SDO
RL = 2 kΩ
tPLH
tPHL
SDI
SDO
RL = 2 kΩ
tPLH
tPHL
ORCLK
Y0 −Y7
RL = 2 kΩ
tPLH
tPHL
SRCLK
SDO
RL = 2 kΩ
tPZH
tPZL
SRCLK
DQ0 −DQ7
R1 = 5 kΩ,
R2 = 2 kΩ
tPHZ
tPLZ
SRCLK
DQ0 −ā
−DQ7
DQ0ā
DQ7
R1 = 5 kΩ,
R2 = 2 kΩ
tPHZ
tPLZ
OEY
Y0 −Y7
R1 = 5 kΩ,
R2 = 2 kΩ
tPZH
tPZL
OEY
Y0 −Y7
R1 = 5 kΩ,
R2 = 2 kΩ
10
TEST
CONDITIONS
•
10
14
16
10
14
16
10
14
16
10
14
16
10
12
13
10
12
13
12
18
25
9
14
20
13
20
25
16
25
30
52
80
85
21
33
45
12
19
25
8
12
15
7
12
15
11
15
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•
VCC = 4.75 V to 5.25 V,
CL = 50 pF,
TA = 0°C to 70°C
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
SDAS105A − JANUARY 1986 − REVISED OCTOBER 1986
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
Test Point
S1
R2
From Output
Under Test
RL
From Output
Under Test
CL
(see Note A)
SWITCH POSITION TABLE
TEST
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
All Diodes
1N916 of 1N3064
R1
CL
(see Note A)
S2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
S2
Closed
Closed
Closed
Open
Closed
Closed
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3V
High-Level
Input
3V
Timing
Input
1.5 V
1.5 V
tw
th
tsu
3V
3V
1.5 V
1.5 V
0V
0V
Data
Input
S1
Closed
Closed
Open
Closed
Closed
Closed
Low-Level
Input
1.5 V
0V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
tPZL
VOH
In-Phase
Output
1.5 V
1.5 V
0V
tPHL
tPLH
1.5 V
tPLZ
1.5 V
4.5 V
VOL
Out-of-Phase
Output
Waveform 1
(see Note B)
tPLH
tPHL
1.5 V
1.5 V
tPHZ
VOL
0.5 V
VOH
1.5 V
1.5 V
VOL
tPZH
VOH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2
(see Note B)
1.5 V
≈ 1.5 V
0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 2.5 ns, tf ≤ 2.5 ns.
Figure 1
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11
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74ALS29818DW
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
SN74ALS29818DWR
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
SN74ALS29818DWR
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
SN74ALS29818NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
SN74ALS29818NT
OBSOLETE
PDIP
NT
24
TBD
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(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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