Actel Libero 2.2 Integrated Design Environment Release Notes Contents About this Release . . . . . . . . . Supported Platforms . . . . . . . . Minimum System Requirements . . Included Software . . . . . . . . . New Features . . . . . . . . . . . Known Limitations and Solutions . Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 .1 .2 .3 .4 .6 .9 About this Release Thank you for upgrading to the Actel Libero v2.2 integrated FPGA design environment. These release notes outline new features and benefits, new device support, known limitations, and other information about the Libero 2.2 release. Updates are posted on our website, http://www.actel.com. Supported Platforms Libero is available for the PC only. Supported platforms include: • • • • 5139121-4 WinNT 4.0 SP5 & SP6 Win2000 SP1 and SP2 Win98, 2nd Edition (except APA750 and APA1000) WinXP 1 15 July, 2002 Minimum System Requirements • • • • • • • • • • 15 July, 2002 300-MHz Pentium processor or greater 128 MB RAM FAT32 or NTF (NTFS file system STRONGLY recommended) 600 MB available hard disk space minimum, 1 GB for full install of Libero and all libraries 100 MB free space in C: drive for installation file swapping is recommended 5 MB available hard disk space for each VITAL/VHDL device family simulation library 5 MB available hard disk space for each Verilog device family simulation library CD-ROM drive HTML browser 800x600 video resolution 2 5139121-4 Minimum RAM Requirements The table below contains the minimum and Actel recommended RAM requirements your computer needs to program these Actel devices. Device Minimum RAM Required Actel Recommended RAM for Optimal Performance APA750a 500 MB 750 MB APA1000b 750 MB 1 GB AX2000 512 MB 750 MB AX1000 256 MB 384 MB AX500 128 MB 256 MB a. APA750 devices are not supported on the Windows 98 platform. This is due to memory management limitation with Windows 98AX b. APA1000 devices are not supported on the Windows 98 platform. This is due to memory management limitation with Windows 98AX Included Software Actel Software • • • Libero v2.2 Designer R1-2002 Silicon Explorer 4.1 OEM Software • • • • 5139121-4 ViewDraw for Actel 7.7 Synplicity - Synplify v7.1A SynaptiCAD - WaveFormer Lite 8.3f MentorGraphics - ModelSim for Actel 5.5e 3 15 July, 2002 New Features New Device Support Libero Platinum now supports the following devices: • • • • • • • • APA075 APA150 APA300 APA450 APA600 AX500 AX1000 AX2000 Note: AX125 is not supported in Libero v2.2; support is planned in a future release. Design Flow Schematic Flow This new schematic flow uses an HDL structural netlist as the main back-end netlist format. If all of the HDL modules instantiated in a schematic design are gate level HDL netlists, you can import the top level netlist into Designer directly without performing synthesis. Pure Schematic and Structural HDL Flow Pure schematic and structural HDL designs can be imported directly into Designer without synthesis. You have the option, however, to optimize your design or automatically insert I/O pads by running the design through Synplify. Generate EDIF The Generate EDIF command is no longer necessary for schematic design flows and it has been removed from the standard flow. This command is still available from the Options command menu, should you need to generate EDIF files directly from the schematic. 15 July, 2002 4 5139121-4 Creating ACTgen Symbols To generate ACTgen macros, click ACTgen in Libero’s Process window. Create and save your macros. When saving your macro, the Netlist/CAE Format selected must be the same format used in your Libero project, either VHDL or Verilog. ACTgen macros are added to the Libero project and appear in the Design Hierarchy window. To create an ACTgen symbol, right-click the ACTgen macro in the Design Hierarchy window and select Create Symbol. Creating Test Benches with the HDL Editor Test benches can now be created with WaveFormer Lite or the HDL Editor. To create a stimulus file with the HDL Editor, from the File menu, select New. In the New File dialog box, select Stimulus HDL File, type a name, and click OK. The HDL Editor opens. Create your test bench and save it. Multiple Test Bench Support Libero supports multiple test benches for top-level and sub-modules. You must specify the test bench to use during simulation. To select the test bench, rightclick the root module in the Design Hierarchy window and click Select a Stimulus File from the right-click menu. Select the test bench and click OK. Flexible Simulation Options Each Libero project can now include simulation preferences, such as simulation run time and resolution. To set your simulation options, from the Tools menu, click Options. In the Options dialog box, click the Simulation tab. Schematic Connectivity Checker The new Schematic Connectivity Checker checks for unconnected nets. Rightclick the schematic file in the File Manager and select Check Schematic from the right-click menu. HDL Syntax Check You can now run an HDL syntax check on your HDL files. Right-click the HDL file in the File Manager and select Check HDL File from the right-click menu. ACTgen ACTgen supports all Actel families. 5139121-4 5 15 July, 2002 Designer For features related to Designer R1-2002 please refer to the Designer release notes at http://www.actel.com/docs/R1-2002/release.pdf OEM Tools ViewDraw 7.7 Bus rippers are supported in this release. For example: a 4-bit bus ripper will have input I, outputs A, B, C and D. If the input bus is named Data[3:0], A will be Data[3]; if the input bus is named Data[0:3], A will be Data[0]. WaveFormer Lite 8.3f WaveFormer Lite provides a new default stimulus file format *.btim. The *.btim file is an optimized *.tim file. The *.tim file is still supported by WaveFormer Lite. Libero supports the use of either file format. Convert Clocks Any signal can be converted to a clock. Highlight the clock row, right-click the clock and select Signal(s) <-> Clock(s) from the right-click menu. Libero Online Help Libero online help is now available from the Help menu. Internet Explorer 4.0 or later is required. Known Limitations and Solutions There are several known issues with the Libero 2.2 release. In order to help you through some of these limitations, please read the following sections carefully. Design Flows Input, Output, and Bi-directional connectors In your schematic design, the built-in library connectors IN and OUT ARE REQUIRED. Make sure to use these connectors in mixed flow schematic top levels and all the sub-modules of both pure schematic and mixed flow designs. The schematic will not convert to HDL (synthesis will fail), if these symbols are not included. 15 July, 2002 6 5139121-4 Note: Both BIBUF and BI connectors are needed for any bi-directional external signals in both pure schematic and mixed flow designs. ModelSim 5.5e If your Libero project contains a VHDL package file, you must set your simulation options to recompile the package on the next simulation. From the Tools menu, click Options and then the Simulation tab. Check Re-Compile VHDL Package Files on Next Simulation and click OK. File Manager Function Block Declaration Function block declaration is supported in package files. Currently, the Libero HDL hierarchy parser does not support function block declaration in the top level HDL file. This will be fixed in a future Libero service pack. ifdef…else Compiler Directive ifdef…else construct is supported in sub module .v files. Using this compiler directive in Top module .v file could cause incorrect results in the Design Hierarchy window. Solution: Put the ifdef…else construct into corresponding sub-module .v files. Design Hierarchy After using the Save+Check command in ViewDraw for Actel, duplicated modules might appear in the Design Hierarchy window. From the Libero Edit menu, click Refresh to update the Design Hierarchy window. OEM Tools Synplify 7.1A Fanout Limit: To improve design performance for Axcelerator devices, change the fanout limit between 10 to 16. 5139121-4 7 15 July, 2002 Cannot Find Reference Clock: During syntheses of mixed flow designs, you might get errors similar to the one below: tacstrt.c:1887 Error: Cannot find reference clock \$1I1284.q2_inferred_clock Solution: Return to ViewDraw for Actel and modify the schematic by renaming the instance name.The new name cannot contain “$” in the name. For example, $1I1284 could be renamed INST1 or TOTO1. From ViewDraw’s File menu, click Save+Check to save the schematic and then click Exit. Using Synplify, run synthesis again. ViewDraw 7.7 Uninstalling Libero does not remove all the ViewDraw directories. <Libero_installation>/ <ViewDraw> cannot be removed completely because vnsd.exe is still running and all of its parent directories cannot be removed at this time. Solution: Reboot the machine after Libero uninstallation, then manually remove the <Libero_installation> folder. WaveFormer Lite 8.3f Output signals: Output signals are not grayed out in the WaveFormer Lite window. If any wave is added to any output, the output signal turns blue in color. This does not affect the test bench generation. ModelSim 5.5e Simulation cannot proceed if clock_stop_time= xe+00x ns. If the test bench clock_stop_time is in expression as xe+00x ns, i.e. 2e+008ns, the simulation cannot process more than one clock cycle. Solution: Change test bench clock_stop_time to 2e8 ns or 200000000 ns. Note: This workaround applies to clock_offset as well. To implement 200ms clock offset, please change the expression of test bench clock_offset to 2e8 ns or 200000000 ns. 15 July, 2002 8 5139121-4 Miscellaneous Language Support Libero currently supports Verilog 95 and VHDL 93. Design Flow When starting Synplify from Libero, a dialog window stating "Project not found…" might appear. Safely ignore this message and click Close to dismiss this dialog box. Documentation Libero includes printed and online manuals. The manuals are available from Libero’s Start Menu and on the CD-ROM. From the Start menu choose: • Programs > Libero 2.2 > Libero 2.2 Documentation From the CD, insert your CD-ROM and click Documentation from the main screen, or look on the CD-ROM in the “/doc” directory. These manuals are also installed onto your system when you install the Libero software. To view the online manuals, you must install Adobe® Acrobat Reader® from the CDROM. Libero comes with online help. Online help specific to each Actel software tool is available for Designer, ChipEdit, PinEdit, and Libero’s integrated tool suiteViewDraw, ModelSim, Synplify, and WaveFormer Lite. Libero’s online help is available from the Start menu and Libero’s Help menu. From the Start menu: • Programs > Libero 2.2 > Libero Help From Libero: • Help > Libero Topics Actel Corporation, Sunnyvale, CA 94086 © 2002 Actel Corporation. All rights reserved. All names mentioned herein are trademarks or registered trademarks of their respective companies. 5139121-4 9 15 July, 2002