HD74HC74 Dual D-type Flip-Flops (with Preset and Clear) REJ03D0549-0200 (Previous ADE-205-421) Rev.2.00 Oct 06, 2005 Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Features • • • • • • High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Ordering Information Part Name Package Type HD74HC74P DILP-14 pin HD74HC74FPEL SOP-14 pin (JEITA) HD74HC74TELL TSSOP-14 pin Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DF-B (FP-14DAV) PTSP0014JA-B (TTP-14DV) Package Abbreviation Taping Abbreviation (Quantity) P — FP EL (2,000 pcs/reel) T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Outputs Preset Clear Clock Data Q Q L H X X H L H L X X L H L L X X H H H H H L H L L H H H H L X No change H H H X No change X No change H H *1 *1 H H: High level L: Low level X: Irrelevant Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go High simultaneously. Rev.2.00, Oct 06, 2005 page 1 of 7 HD74HC74 Pin Arrangement 14 VCC 1CLR 1 CK 1D 2 D PR 1CK 3 13 2CLR CLR Q 12 2D Q 1PR 4 11 2CK 1Q 5 D CLR 1Q 6 10 2PR CK PR 9 2Q Q Q GND 7 8 2Q (Top view) Logic Diagram (1/2) PR Q CLR # CK CK Q D # CK CK CK CK # CK # CK CK # CK CK Absolute Maximum Ratings Item Supply voltage range Symbol VCC Ratings –0.5 to 7.0 Unit V Input / Output voltage Input / Output diode current Vin, Vout IIK, IOK –0.5 to VCC +0.5 ±20 V mA Output current VCC, GND current IO ICC or IGND ±25 ±50 mA mA PT Tstg 500 –65 to +150 mW °C Power dissipation Storage temperature Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00, Oct 06, 2005 page 2 of 7 HD74HC74 Recommended Operating Conditions Symbol Ratings Unit Supply voltage Input / Output voltage Item VCC VIN, VOUT 2 to 6 0 to VCC V V Operating temperature Ta –40 to 85 0 to 1000 °C 0 to 500 0 to 400 ns Input rise / fall time Note: *1 tr , tf Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Ta = 25°C Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Ta = –40 to+85°C 2.0 Min 1.5 Typ — Max — Min 1.5 Max — 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 — — — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 — 0.1 0.26 — — 0.1 0.33 Unit Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA Input current Iin 6.0 6.0 — — — — 0.26 ±0.1 — — 0.33 ±1.0 IOL = 5.2 mA µA Vin = VCC or GND Quiescent supply current ICC 6.0 — — 2.0 — 20 µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Setup time Symbol VCC (V) fmax tPLH, tPHL tsu Min Ta = 25°C Ta = –40 to +85°C Unit Typ Max Min Max 2.0 4.5 — — — 35 5 25 — — 4 20 6.0 2.0 — — — — 29 160 — — 24 200 4.5 6.0 — — 14 — 32 27 — — 40 34 2.0 4.5 — — — 13 160 32 — — 200 40 6.0 2.0 — 100 — — 27 — — 125 34 — 4.5 6.0 20 17 1 — — — 25 21 — — Rev.2.00, Oct 06, 2005 page 3 of 7 Test Conditions MHz ns Clock to Q or Q ns Preset or Clear to Q or Q ns Data to Clock HD74HC74 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Hold time Removal time Pulse width Output rise/fall time Input capacitance Symbol VCC (V) th trem tw tTLH, tTHL Cin Ta = –40 to +85°C 2.0 Min 5 Typ — Max — Min 5 Max — 4.5 6.0 5 5 0 –5 — — 5 5 — — 2.0 4.5 25 5 — — — — 31 6 — — 6.0 2.0 4 80 — — — — 5 100 — — 4.5 6.0 16 14 8 — — — 20 17 — — 2.0 4.5 — — — 5 75 15 — — 95 19 6.0 — — — — 5 13 10 — — 16 10 Unit Test Conditions ns Clock to Data ns Preset, Clear to Clock ns Clock, Preset, Clear ns pF Test Circuit VCC VCC Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω See Function Table Output Input Clock Q CL = 50 pF PR Output D Clear Q Note: C L includes the probe and jig capacitance. Rev.2.00, Oct 06, 2005 page 4 of 7 CL = 50 pF HD74HC74 Waveforms • Waveform − 1 tr tf VCC 90 % Clock 50 % 50 % 50 % 10 % 10 % tw(H) 0V tw(L) VCC D 0V t TLH t THL Q VOH 90 % 50 % 90 % 50 % 10 % 10 % t PLH t PHL t PHL t PLH 90 % 90 % Q 50 % 10 % 50 % 10 % VOL VOH VOL t TLH t THL • Waveform − 2 tf Clear tr VCC 90 % 50 % 10 % 90 % 50 % 10 % tf tw Preset tr 50 % 10 % tw t PHL 90 % 50 % 10 % 0V VCC 0V t PLH VOH Q 50 % 50 % VOL t PLH t PHL VOH Q 50 % 50 % VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct 06, 2005 page 5 of 7 HD74HC74 Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 L θ A1 0.51 bp 0.40 e1 0.48 c 0.19 θ 0° JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.56 e 2.29 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 7.4 0.25 Z ( Ni/Pd/Au plating ) 20.32 1.30 b3 c Max 5.06 A bp e Dimension in Millimeters Min 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 1.27 e x 0.12 y 0.15 Z 1.42 0.50 L L Rev.2.00, Oct 06, 2005 page 6 of 7 8° 1 0.70 1.15 0.90 HD74HC74 JEITA Package Code P-TSSOP14-4.4x5-0.65 RENESAS Code PTSP0014JA-B *1 Previous Code TTP-14DV D MASS[Typ.] 0.05g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 8 HE c *2 E bp Reference Symbol Index mark Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 5.00 5.30 E 4.40 A2 7 1 *3 Z bp A1 x 0.03 0.07 0.10 0.15 0.20 0.25 0.10 0.15 0.20 6.40 6.60 1.10 A M L1 bp e b1 c A c A1 θ L y Detail F 1 θ 0° HE 6.20 0.65 e x 0.13 y 0.10 Z 0.83 0.4 L L Rev.2.00, Oct 06, 2005 page 7 of 7 8° 1 0.5 1.0 0.6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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