fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 Advance Information Sheet for the fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 ® IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 Copyright 2012 by Innovasic, Inc. Published by Innovasic, Inc. 5635 Jefferson St. NE, Suite A, Albuquerque, NM 87109 fido® and fido2100® are trademarks of Innovasic, Inc. IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 TABLE OF CONTENTS List of Figures ..................................................................................................................................4 List of Tables ...................................................................................................................................5 1. Overview.................................................................................................................................6 1.1 Introduction to Device Level Ring Protocol .................................................................6 1.2 Introduction to IEEE-1588 ............................................................................................6 2. Features ...................................................................................................................................9 3. Packaging, Pin Descriptions, and Physical Dimensions .......................................................10 3.1 LQFP Package .............................................................................................................11 3.1.1 LQFP Pinout ...................................................................................................11 3.1.2 LQFP Physical Dimensions ............................................................................16 3.2 BGA 10- by 10-mm Package ......................................................................................17 3.2.1 BGA 10- by 10-mm Pinout.............................................................................17 3.2.2 BGA 10- by 10-mm Physical Package Dimensions .......................................23 4. Electrical Characteristics ......................................................................................................24 5. Application Example ............................................................................................................25 6. For Additional Information...................................................................................................26 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 26 http://www.Innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 LIST OF FIGURES Figure 1- Block Diagram of the fido2100........................................................................................8 Figure 2. LQFP Package Diagram ................................................................................................11 Figure 3. LQFP Physical Package Dimensions ............................................................................16 Figure 4. BGA 10- by 10-mm Package Diagram .........................................................................18 Figure 5. BGA 10- by 10-mm Physical Package Dimensions ......................................................23 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 26 http://www.Innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. LQFP Pin Listing ............................................................................................................12 BGA 10- by 10-mm Package Pin Listing .......................................................................19 Absolute Maximum Ratings ...........................................................................................24 Recommended Operating Conditions .............................................................................24 DC Characteristics of I/O Cells ......................................................................................24 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 26 http://www.Innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 1. Advance Information Sheet May 30, 2012 Overview The fido2100 is part of Innovasic’s fido® family of real-time communication products. The fido2100 is a managed, 3-port Industrial Ethernet switch with support for IEEE-1588 and Device Level Ring (DLR) protocol. The fido2100 enhances the capabilities of Innovasic’s line of Industrial Ethernet product by providing an infrastructure element with low latency, time synchronization and redundancy for embedded Industrial Ethernet solutions. Figure 1 illustrates the top-level blocks of the fido2100 architecture. 1.1 Introduction to Device Level Ring Protocol There are a variety of Industrial applications in which Ethernet ring topologies are preferable to the star topologies common in enterprise networks. Ring networks provide inherent single-point fault tolerance and reduced connectivity costs. Device Level Ring (DLR) protocol provides a means for detecting, managing and recovering from faults in a ring-based network. DLR supports three classes of devices: • • • Ring Supervisor – Ring Supervisors are required to send and process DLR beacon frames at the default beacon interval. Ring Node, Beacon-based – These devices are required to process beacon frames. Ring Node, Announce-based – These devices are not required to process DLR beacon frames, but must be capable of processing announce frames. A DLR network consists of a Ring Supervisor and any number of Ring Nodes. Ring nodes incorporate embedded switch technology with at least two external ports. The Ring Supervisor is responsible for generating a “beacon” at regular intervals. These beacons traverse the ring in each direction. The ring supervisor must be capable of blocking DLR frames to avoid infinite propagation of beacons. Faults are detected when beacon traffic is interrupted. There are obviously a number of failure mechanisms and associated recovery strategies. For a detailed explanation of DLR refer to Volume II: EtherNet/IP Adaptation of CIP, chapter 9, section 9-5. For definition of the DLR EtherNet/IP object, refer to Volume II: EtherNet/IP Adaptation of CIP, chapter 5, section 5-5. 1.2 Introduction to IEEE-1588 The IEEE 1588 standard, also known as Precision Time Protocol (PTP), provides a means to synchronize participants in a network to a common time source. Each network participant has its own precision time source or “ordinary clock”. A PTP system consists of some number of ordinary clocks connected to a network. A grandmaster is elected based upon the quality of available time sources and all other participants synchronize directly to it. PTP systems can be IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 expanded through the use of “boundary clocks”. The boundary clock provides a means to bridge synchronization from one network segment to another. A synchronization master is can then be elected for each network segments. The root timing reference is remains the grandmaster. PTP is a master-slave protocol. The master and network participants exchange synchronization messages. However, these messages will be delayed as they traverse the network due to the inherent latency of the network infrastructure. To compensate for this latency, PTP includes the concept of a transparent clock. The transparent clock automatically compensates for latency by modifying the timestamps in synchronization messages as they pass through a given device. The fido2100 provides hardware support for both transparent and ordinary clocks. IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Advance Information Sheet May 30, 2012 Figure 1- Block Diagram of the fido2100 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 2. Advance Information Sheet May 30, 2012 Features • IEEE 802.3 o 10/100Mbps, Half / Full Duplex o Full Duplex Flow Control o Half Duplex Back Pressure Flow Control o Broadcast / Multicast Storm Prevention • IEEE 1588 V2 o Hardware Assist for Ordinary Clock o End-to-end Transparent Clock • DLR Beacons o Capability to processes beacons from 100 ms down to 100 µs o Provides auto-generation of beacon frames for supervisor functions • Cut through forwarding o Cut through forwarding minimizes latency for High Performance Control Applications such as CIP Motion • IP Differentiated Services Code Point (DSCP) based Quality of Service (QoS) o 4 Prioritized Queues per Port • Incoming Filtering on Unicast / Multicast Traffic o 256-entry Dynamic Unicast MAC Learning and Filtering for 2 External Ports o 128 buffers of 128 bytes for each port • Statistics Counters for 2 External Ports • Supported Network topologies: o Hierarchical Star with either one of the external ports o Daisy Chain / Hybrid Daisy Chain Hierarchical Star o DLR Media Redundancy with Hardware Support for a Single Fault Tolerant Ring Protocol • Software for Switch & DLR Protocol Management • Full Industrial Temperature Range -40 to +85C • Packages: o 128 pin, Plastic Low Profile QFP (LQFP), RoHS Compliant o 128 Ball Grid Array (BGA), RoHS Compliant IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 3. Advance Information Sheet May 30, 2012 Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the fido2100 switch LQFP and BGA 10- by 10-mm package is provided individually. Refer to sections, figures, and tables for information on the device of interest. IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 3.1 LQFP Package 3.1.1 LQFP Pinout Advance Information Sheet May 30, 2012 The pinout for the fido2100 Industrial Ethernet Switch LQFP package is as shown in Figure 2. The corresponding pinout is provided in Table 1. Figure 2. LQFP Package Diagram IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 Advance Information Sheet May 30, 2012 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Table 1. LQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Signal Name sw_event_irq_n ts_event_irq_n pps_sig event_1_sig event_2_sig p1_txc vcck gndk gndio vcc3io p1_txen p1_txer p1_txd[0] p1_txd[1] p1_txd[2] p1_txd[3] p1_rxc p1_rxdv p1_rxer p1_rxd[0] p1_rxd[1] p1_rxd[2] vcc3io gndio gndk vcck p1_rxd[3] p1_col p1_crs p1_lnk_stts p1_led_grn p1_led_ylw p2_txc p2_txen p2_txer p2_txd[0] p2_txd[1] p2_txd[2] Type output output output input input input power ground ground power output output output output output output input input input input input input power ground ground power input input input input output output input output output output output output LQFP Pin Descriptions switch event IRQ, must be connected to a high priority IRQ pin on cpu time sync event IRQ. Optional for non-1588 devices. pulse per second signal for 1588 compliance external event 1 snapshot trigger from CPU/others external event 2 snapshot trigger from CPU/others port 1 mii, transmit clock from PHY 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage port 1 mii, transmit enable to PHY port 1 mii, transmit error to PHY port 1 mii, transmit data bit 0 to PHY port 1 mii, transmit data bit 1 to PHY port 1 mii, transmit data bit 2 to PHY port 1 mii, transmit data bit 3 to PHY port 1 mii, receive clock from PHY port 1 mii, receive data valid from PHY port 1 mii, receive data error from PHY port 1 mii, receive data bit 0 from PHY port 1 mii, receive data bit 1 from PHY port 1 mii, receive data bit 2 from PHY 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage port 1 mii, receive data bit 3 from PHY port 1 mii, collision from PHY port 1 mii, carrier sense from PHY port 1 mii, link status from PHY (1:link pass, 0:link fail) port 1 mii,, green led port 1 mii,, yellow led port 2 mii, transmit clock from PHY port 2 mii, transmit enable to PHY port 2 mii, transmit error to PHY port 2 mii, transmit data bit 0 to PHY port 2 mii, transmit data bit 1 to PHY port 2 mii, transmit data bit 2 to PHY IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Signal Name vcck gndk gndio vcc3io p2_txd[3] p2_rxc p2_rxdv p2_rxer gndo vdd3o p2_rxd[0] p2_rxd[1] p2_rxd[2] p2_rxd[3] p2_col p2_crs vcc3io gndio gndk vcck p2_lnk_stts p2_led_grn p2_led_ylw reset_n sys_clk test0 cpu_txen vcc18a_pll gnda_pll cpu_txer cpu_txc cpu_txd[0] vcck gndk gndio vcc3io cpu_txd[1] cpu_txd[2] cpu_txd[3] cpu_rxc Type power ground ground power output input input input ground power input input input input input input power ground ground power input output output input input input input power ground input output input power ground ground power input input input output Advance Information Sheet May 30, 2012 LQFP Pin Descriptions 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage port 2 mii, transmit data bit 3 to PHY port 2 mii, receive clock from PHY port 2 mii, receive data valid from PHY port 2 mii, receive data error from PHY i/o ground 3.3 V i/o supply voltage port 2 mii, receive data bit 0 from PHY port 2 mii, receive data bit 1 from PHY port 2 mii, receive data bit 2 from PHY port 2 mii, receive data, bit 3 from PHY port 2 mii, collision from PHY port 2 mii, carrier sense from PHY 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage port 2 mii, link status from PHY (1:link pass, 0:link fail) port 2 mii,, green led port 2 mii,, yellow led chip reset, active low (internal pull-up) 25 MHz system clock test, active high (internal pull-down) cpu mii, transmit enable from CPU 1.8 V analog supply voltage analog ground cpu mii, transmit error from CPU cpu mii, 25 MHz transmit clock to CPU cpu mii, transmit data bit 0 from CPU 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage cpu mii, transmit data bit 1 from CPU cpu mii, transmit data bit 2 from CPU cpu mii, transmit data bit 3 from CPU cpu mii, 25 MHz receive clock to CPU IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Signal Name cpu_rxdv vcc3o cpu_rxer cpu_crs cpu_col cpu_rxd[0] cpu_rxd[1] cpu_rxd[2] vcc3io gndio gndk vcck cpu_rxd[3] cpu_adrs[1] cpu_adrs[2] cpu_adrs[3] cpu_adrs[4] cpu_adrs[5] cpu_adrs[6] cpu_adrs[7] cpu_adrs[8] cpu_data[0] cpu_data[1] cpu_data[2] vcck gndk gndio vcc3io cpu_data[3] cpu_data[4] cpu_data[5] cpu_data[6] cpu_data[7] gndo vdd3o cpu_data[8] cpu_data[9] cpu_data[10] cpu_data[11] cpu_data[12] Type output power output output output output output output power ground ground power output input input input input input input input input bidir bidir bidir power ground ground power bidir bidir bidir bidir bidir ground power bidir bidir bidir bidir bidir Advance Information Sheet May 30, 2012 LQFP Pin Descriptions cpu_mii, receive data valid to CPU 3.3 V i/o supply voltage cpu mii, receive error cpu mii, cpu mii, collision cpu mii, receive data bit 0 to CPU cpu mii, receive data bit 1 to CPU cpu mii, receive data bit 2 to CPU 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage cpu mii, receive data bit 3 to CPU cpu host interface, address bit 1 cpu host interface, address bit 2 cpu host interface, address bit 3 cpu host interface, address bit 4 cpu host interface, address bit 5 cpu host interface, address bit 6 cpu host interface, address bit 7 cpu host interface, address bit 8 cpu host interface, data bit 0 cpu host interface, data bit 1 cpu host interface, data bit 2 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage cpu host interface, data bit 3 cpu host interface, data bit 4 cpu host interface, data bit 5 cpu host interface, data bit 6 cpu host interface, data bit 7 i/o ground 3.3 V i/o supply voltage cpu host interface, data bit 8 cpu host interface, data bit 0 cpu host interface, data bit 10 cpu host interface, data bit 11 cpu host interface, data bit 12 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin 119 120 121 122 123 124 125 126 127 128 Signal Name vcc3io gndio gndk vcck cpu_data[13] cpu_data[14] cpu_data[15] cpu_cs_n cpu_rd_n cpu_wr_n Type power ground ground power bidir bidir bidir input input input Advance Information Sheet May 30, 2012 LQFP Pin Descriptions 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage cpu host interface, data bit 13 cpu host interface, data bit 14 cpu host interface, data bit 15 cpu host interface, chip select, active low (internal pull-up) cpu host interface, read enable, active low (internal pull-up) cpu host interface, write enable, active low (internal pull-up) IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 3.1.2 Advance Information Sheet May 30, 2012 LQFP Physical Dimensions The physical dimensions for the 128-pin LQFP package are as shown in Figure 3. Figure 3. LQFP Physical Package Dimensions IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 3.2 BGA 10- by 10-mm Package 3.2.1 BGA 10- by 10-mm Pinout Advance Information Sheet May 30, 2012 The pinout for the fido2100 Industrial Ethernet Switch BGA 10- by 10-mm package is as shown in Figure 4. The corresponding pinout is provided in Table 2. IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 Advance Information Sheet May 30, 2012 3-Port Industrial Ethernet DLR Switch with IEEE 1588 M p1_lnk_stts p2_txc p2_txd[0] p2_txd[2] p2_rxc p2_rxdv p2_rxd[0] p2_rxd[2] p2_col p2_lnk_stts p2_led_grn reset_n L p1_col p1_led_grn p2_txen p2_txd[1] p2_txd[3] p2_rxer p2_rxd[1] p2_rxd[3] p2_crs p2_led_ylw sys_clk cpu_txen K p1_rxd[2] p1_crs p1_led_ylw p2_txer vcck vcc3io vcc3io vcc3io vcck test cpu_txer cpu_txd[0] J p1_rxd[1] p1_rxd[3] vcck vcck gndio vss18a_pll cpu_txc cpu_txd[2] H p1_rxer p1_rxd[0] vdd3io gndio gndk gndk gndio gnda_pll cpu_txd[1] cpu_txd[3] G p1_rxc p1_rxdv vcc3io gndio gndk gndk gndio vcck cpu_rxc cpu_rxdv F p1_txd[3] p1_txd[2] vcc3io gndio gndk gndk gndio vcc3io cpu_rxer cpu_crs E p1_txd[1] p1_txd[0] vcck gndio gndk gndk gndio vcc3io cpu_rxd[0] cpu_col D p1_txer p1_txc vcck gndio vcck vcc3io cpu_rxd[2] cpu_rxd[1] C p1_txen event_1_sig sw_event_irq_n cpu_cs_n vcc3io cpu_data[9] cpu_data[5] vcc3io cpu_adrs[8] cpu_adrs[5] cpu_adrs[2] cpu_rxd[3] B event_2_sig ts_event_irq_n cpu_rd_n cpu_data[14] cpu_data[12] cpu_data[10] cpu_data[6] cpu_data[3] cpu_data[1] cpu_adrs[7] cpu_adrs[4] cpu_adrs[1] A pps_sig cpu_wr_n cpu_data[15] cpu_data[13] cpu_data[11] cpu_data[8] cpu_data[4] cpu_data[2] cpu_data[0] cpu_adrs[6] cpu_adrs[3] 1 2 3 4 5 6 8 9 10 11 12 cpu_data[7] 7 Figure 4. BGA 10- by 10-mm Package Diagram IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 Advance Information Sheet May 30, 2012 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Table 2. BGA 10- by 10-mm Package Pin Listing Pin C3 B2 A1 C2 B1 D2 E3 E6 F5 F3 C1 D1 E2 E1 F2 F1 G1 G2 H1 H2 J1 K1 G3 G5 F6 J3 J2 L1 K2 M1 L2 K3 M2 L3 K4 M3 L4 M4 Signal Name sw_event_irq_n ts_event_irq_n pps_sig event_1_sig event_2_sig p1_txc vcck gndk gndio vcc3io p1_txen p1_txer p1_txd[0] p1_txd[1] p1_txd[2] p1_txd[3] p1_rxc p1_rxdv p1_rxer p1_rxd[0] p1_rxd[1] p1_rxd[2] vcc3io gndio gndk vcck p1_rxd[3] p1_col p1_crs p1_lnk_stts p1_led_grn p1_led_ylw p2_txc p2_txen p2_txer p2_txd[0] p2_txd[1] p2_txd[2] Type output output output input input input power ground ground power output output output output output output input input input input input input power ground ground power input input input input output output input output output output output output BGA Pin Descriptions switch event IRQ, must be connected to a high priority IRQ pin on cpu time sync event IRQ. Optional for non-1588 devices. pulse per second signal for 1588 compliance external event 1 snapshot trigger from CPU/others external event 2 snapshot trigger from CPU/others port 1 mii, transmit clock from PHY 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage port 1 mii, transmit enable to PHY port 1 mii, transmit error to PHY port 1 mii, transmit data bit 0 to PHY port 1 mii, transmit data bit 1 to PHY port 1 mii, transmit data bit 2 to PHY port 1 mii, transmit data bit 3 to PHY port 1 mii, receive clock from PHY port 1 mii, receive data valid from PHY port 1 mii, receive data error from PHY port 1 mii, receive data bit 0 from PHY port 1 mii, receive data bit 1 from PHY port 1 mii, receive data bit 2 from PHY 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage port 1 mii, receive data bit 3 from PHY port 1 mii, collision from PHY port 1 mii, carrier sense from PHY port 1 mii, link status from PHY (1:link pass, 0:link fail) port 1 mii,, green led port 1 mii,, yellow led port 2 mii, transmit clock from PHY port 2 mii, transmit enable to PHY port 2 mii, transmit error to PHY port 2 mii, transmit data bit 0 to PHY port 2 mii, transmit data bit 1 to PHY port 2 mii, transmit data bit 2 to PHY IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin J4 G6 H5 H3 L5 M5 M6 L6 J9 K6 M7 L7 M8 L8 M9 L9 K7 H8 H6 K5 M10 M11 L10 M12 L11 K10 L12 J10 H10 K11 J11 K12 K9 H7 G8 K8 H11 J12 H12 G11 Signal Name vcck gndk gndio vcc3io p2_txd[3] p2_rxc p2_rxdv p2_rxer gndio vcc3io p2_rxd[0] p2_rxd[1] p2_rxd[2] p2_rxd[3] p2_col p2_crs vcc3io gndio gndk vcck p2_lnk_stts p2_led_grn p2_led_ylw reset_n sys_clk test cpu_txen vcc18a_pll gnda_pll cpu_txer cpu_txc cpu_txd[0] vcck gndk gndio vcc3io cpu_txd[1] cpu_txd[2] cpu_txd[3] cpu_rxc Type power ground ground power output input input input ground power input input input input input input power ground ground power input output output input input input input power ground input output input power ground ground power input input input output Advance Information Sheet May 30, 2012 BGA Pin Descriptions 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage port 2 mii, transmit data bit 3 to PHY port 2 mii, receive clock from PHY port 2 mii, receive data valid from PHY port 2 mii, receive data error from PHY i/o ground 3.3 V i/o supply voltage port 2 mii, receive data bit 0 from PHY port 2 mii, receive data bit 1 from PHY port 2 mii, receive data bit 2 from PHY port 2 mii, receive data, bit 3 from PHY port 2 mii, collision from PHY port 2 mii, carrier sense from PHY 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage port 2 mii, link status from PHY (1:link pass, 0:link fail) port 2 mii,, green led port 2 mii,, yellow led chip reset, active low (internal pull-up) 25 MHz system clock test, active high (internal pull-down) cpu mii, transmit enable from CPU 1.8 V analog supply voltage analog ground cpu mii, transmit error from CPU cpu mii, 25 MHz transmit clock to CPU cpu mii, transmit data bit 0 from CPU 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage cpu mii, transmit data bit 1 from CPU cpu mii, transmit data bit 2 from CPU cpu mii, transmit data bit 3 from CPU cpu mii, 25 MHz receive clock to CPU IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin G12 F10 F11 F12 E12 E11 D12 D11 E10 F8 G7 G10 C12 B12 C11 A12 B11 C10 A11 B10 C9 A10 B9 A9 D9 F7 E8 D10 B8 A8 C7 B7 A7 E5 C8 A6 C6 B6 A5 B5 Signal Name cpu_rxdv vcc3io cpu_rxer cpu_crs cpu_col cpu_rxd[0] cpu_rxd[1] cpu_rxd[2] vcc3io gndio gndk vcck cpu_rxd[3] cpu_adrs[1] cpu_adrs[2] cpu_adrs[3] cpu_adrs[4] cpu_adrs[5] cpu_adrs[6] cpu_adrs[7] cpu_adrs[8] cpu_data[0] cpu_data[1] cpu_data[2] vcck gndk gndio vcc3io cpu_data[3] cpu_data[4] cpu_data[5] cpu_data[6] cpu_data[7] gndio vdd3io cpu_data[8] cpu_data[9] cpu_data[10] cpu_data[11] cpu_data[12] Type output power output output output output output output power ground ground power output input input input input input input input input bidir bidir bidir power ground ground power bidir bidir bidir bidir bidir ground power bidir bidir bidir bidir bidir Advance Information Sheet May 30, 2012 BGA Pin Descriptions cpu_mii, receive data valid to CPU 3.3 V i/o supply voltage cpu mii, receive error cpu mii, cpu mii, collision cpu mii, receive data bit 0 to CPU cpu mii, receive data bit 1 to CPU cpu mii, receive data bit 2 to CPU 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage cpu mii, receive data bit 3 to CPU cpu host interface, address bit 1 cpu host interface, address bit 2 cpu host interface, address bit 3 cpu host interface, address bit 4 cpu host interface, address bit 5 cpu host interface, address bit 6 cpu host interface, address bit 7 cpu host interface, address bit 8 cpu host interface, data bit 0 cpu host interface, data bit 1 cpu host interface, data bit 2 1.8 V digital core supply voltage digital core ground i/o ground 3.3 V i/o supply voltage cpu host interface, data bit 3 cpu host interface, data bit 4 cpu host interface, data bit 5 cpu host interface, data bit 6 cpu host interface, data bit 7 i/o ground 3.3 V i/o supply voltage cpu host interface, data bit 8 cpu host interface, data bit 0 cpu host interface, data bit 10 cpu host interface, data bit 11 cpu host interface, data bit 12 IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 Pin C5 D4 E7 D3 A4 B4 A3 C4 B3 A2 Signal Name vcc3io gndio gndk vcck cpu_data[13] cpu_data[14] cpu_data[15] cpu_cs_n cpu_rd_n cpu_wr_n Type power ground ground power bidir bidir bidir input input input Advance Information Sheet May 30, 2012 BGA Pin Descriptions 3.3 V i/o supply voltage i/o ground digital core ground 1.8 V digital core supply voltage cpu host interface, data bit 13 cpu host interface, data bit 14 cpu host interface, data bit 15 cpu host interface, chip select, active low (internal pull-up) cpu host interface, read enable, active low (internal pull-up) cpu host interface, write enable, active low (internal pull-up) IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 3.2.2 Advance Information Sheet May 30, 2012 BGA 10- by 10-mm Physical Package Dimensions The physical dimensions for the BGA 10- by 10-mm package are as shown in Figure 5. Figure 5. BGA 10- by 10-mm Physical Package Dimensions IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 23 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 Advance Information Sheet May 30, 2012 3-Port Industrial Ethernet DLR Switch with IEEE 1588 4. Electrical Characteristics Tables 3, 4, and 5 show the absolute maximum ratings, recommended operating conditions and DC characteristics, respectively. Table 3. Absolute Maximum Ratings Symbol vcck vcc18a_pll vcc3io vcc3o TSTG Parameter Name digital core supply voltage pll analog supply voltage digital i/o supply voltage digital i/o supply voltage Storage Temperature Conditions Min -0.5 -0.5 -0.5 -0.5 -65 Typ - Max 2.5 2.5 4.6 4.6 150 Units V V V V o C Conditions Min 1.62 1.62 3.0 3.0 -40 - Typ 1.8 1.8 3.3 3.3 25 Max 1.98 1.98 3.6 3.6 85 - Units V V V V o C MHz Conditions Min 2.0 2.4 40 40 Typ 75 75 2.4 Max 0.8 0.4 190 190 Units V V V V kΩ kΩ pF Table 4. Recommended Operating Conditions Symbol vcck vcc18a_pll vcc3io vcc3o TA sys_clk Parameter Name digital core supply voltage pll analog supply voltage digital i/o supply voltage digital i/o supply voltage Ambient Temperature system clock Table 5. DC Characteristics of I/O Cells Symbol VIH VIL VOH VOL RPU RPD CIN Parameter Name input high voltage input low voltage output high voltage output low voltage Input pull-up resistance Input pull-down resistance Input Capacitance IOH = -12 mA IOL = 12 mA IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 24 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 5. Advance Information Sheet May 30, 2012 Application Example Processor and MII Interface IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 25 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184 fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588 6. Advance Information Sheet May 30, 2012 For Additional Information This Advance Information Sheet for the fido2100 Industrial Ethernet Switch provides preliminary information regarding the product and is subject to change before the design is completed. Additional information will be provided in the complete data sheet that will be available with the release of the prototypes in Q3 2012. The Innovasic Support Team is continually planning and creating tools for your use. Visit http://www.innovasic.com for up-to-date documentation and software. Our goal is to provide timely, complete, accurate, useful, and easy-to-understand information. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team 5635 Jefferson St. NE, Suite A Albuquerque, NM 87109 Phone: +1-505-883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 US E-mail: [email protected] Website: http://www.Innovasic.com IA211111101-00 UNCONTROLLED WHEN PRINTED OR COPIED Page 26 of 26 http://www.innovasic.com Customer Support: 1-888-824-4184