abmjb-903

High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
Moisture Sensitivity Level: MSL=1
FEATURES:
• Low power and miniature package programmable jitter attenuator
• Input frequency up to 200MHz
• Output frequency up to 840MHz
• Jitter attenuation 20dB at 3 MHz spur frequency
• Additive phase jitter or phase jitter floor:
- 55fs for 1.875MHz to 20MHz
- 251fs for 12MHz to 20MHz
• Single ended CMOS input
• One differential or two single ended outputs. Output logic types
supported are LVPECL, LVDS, HCSL and LVCMOS (single ended or differential).
• Operating temperature range from -40°C to +85°C
• 24-pin QFN RoHS-complaint package
• Related devices:
- ABMJB-902: LVCMOS, period jitter cleaning.
4.0 x 4.0 x 0.85 mm 24-Pin QFN
APPLICATIONS:
• 1/10/40/100 Gigabiy Ethernet (GbE)
• SONET/SDH
• PCI-Express
• CPRI/OBSAI wireless base stations
• Fibre Channel
• SAS/SATA
• DIMM
STANDARD SPECIFICATIONS:
Absolute Maximum Ratings (1)
Parameters
Min.
Typ.
Max.
Units
+4.6
V
VDD +0.5
V
Lead Temperature
+ 260
ºC
Case Temperature
+ 115
ºC
+150
ºC
Max.
Units
+3.465
50
+85
V
ºC/W
ºC
Typ.
Max.
Units
100
+3.465
120
V
mA
80
100
mA
70
90
mA
Supply Voltage (VDD, VDDO)
Input Voltage (VIN)
-0.5
Storage Temperature (TS)
-65
Notes
Soldering, 20s
Operation Ratings (2)
Parameters
Supply Voltage (VDD, VDDO)
Junction Thermal Resistance (
Ambient Temperature (TA)
Min.
Typ.
+2.375
(3)
JA)
-40
Notes
Still-Air
DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C
Parameters
Power Supply Voltage (VDD)
Min.
+2.375
Total Supply Current, VDD + VDDO
(IDD)
Notes
LVPECL, 321.5MHz, Outputs open
HCSL (PCIe), 100MHz,
Outputs terminated with 50 to VSS
2 x LVCMOS, 125MHz, Outputs open
LVCMOS Inputs (OE, REFIN) DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C
Parameters
Input High Voltage (VIH)
Input Low Voltage (VIN)
Input High Current (IIH)
Input Low Current (IIL)
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Min.
Typ.
Max.
Units
70% VDD
VDD+0.3
VSS-0.3
30% VDD
V
V
µA
µA
150
-150
LLC
Notes
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
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High Performance MEMS Jitter Attenuator
ABMJB-903
Pb RoHS/RoHS II Compliant
ESD Sensitive
4.0 x 4.0 x 0.85 mm 24-Pin QFN
LVDS Output DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C; RL = 100Ω across Q and /Q
Parameters
Min.
Typ.
Max.
Units
Differential Output Voltage (VOD)
VOD Magnitude Change (ΔVOD )
275
350
475
40
mV
mV
Offset Voltage (VOS)
VOD Magnitude Change (ΔVOS )
1.15
1.25
1.5
50
V
mV
Notes
See page 10
HCSL Output DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C; RL = 50Ω to VSS
Parameters
Min.
Typ.
Max.
Units
Notes
Output High Voltage (VOH)
Output Low Voltage (VOL)
660
-150
700
0
850
27
mV
mV
See page 8 & 10
See page 8 & 10
Output Voltage Swing (VSWING)
630
700
1000
mV
See page 8 & 10
LVPECL Output DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5%; T A = -40°C to +85°C; RL = 50Ω to VDD - 2V
Parameters
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Voltage Swing (VSWING)
Min.
Typ.
Max.
Units
Notes
VDD-1.145
VDD-1.945
VDD-0.97
VDD-1.77
VDD-0.845
VDD-1.645
V
V
See page 8 & 9
0.6
0.8
1.0
V
See page 8 & 9
See page 8 & 9
LVCMOS Output DC Electrical Characteristics (4)
VDD = VDDO = 3.3V±5% or 2.5V±5%; T A = -40°C to +85°C; RL = 50Ω to VDD/2
Parameters
Output High Voltage (VOH)
Output Low Voltage (VOL)
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Min.
Typ.
Max.
Units
0.6
V
V
VDD-0.7
LLC
Notes
See page 8 & 10
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
Pb RoHS/RoHS II Compliant
ESD Sensitive
4.0 x 4.0 x 0.85 mm 24-Pin QFN
LVPECL AC Electrical Characteristics (4, 5, 6, 10)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C, unless otherwise noted
Parameters
Output Frequency (FOUT)
LVPECL Output Rise/Fall Time
(TR/TF)
Output Duty Cycle (ODC)
Min.
Typ.
12
Max.
Units
840
MHz
ps
80
175
350
48
50
52
45
50
55
20
PLL Lock Time (TLOCK)
%
20% - 80%
FOUT < 350MHz
FOUT ≥ 350MHz
ms
251
55
RMS Phase Jitter @ 156.25MHz
with Clean Input Signal (Tjit(Ø))
Notes
fs
fs
Integration range (12kHz to 20MHz)
Integration range (1.875MHz to 20MHz)
LVDS AC Electrical Characteristics (4, 5, 6, 7)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C, unless otherwise noted
Parameters
Output Frequency (FOUT)
LVDS Output Rise/Fall Time
(TR/TF)
Output Duty Cycle (ODC)
Min.
Typ.
12
Max.
Units
840
MHz
ps
20% - 80%
%
< 350MHz
≥350MHz
100
160
400
48
45
50
50
52
55
20
PLL Lock Time (TLOCK)
RMS Phase Jitter @ 156.25MHz
(Tjit(Ø))
Notes
ms
60
fs
Integration range (1.875MHz to 20MHz)
HCSL AC Electrical Characteristics (4, 5, 6, 8)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C, unless otherwise noted
Parameters
Output Frequency (FOUT)
LVDS Output Rise/Fall Time
(TR/TF)
Output Duty Cycle (ODC)
PLL Lock Time (TLOCK)
RMS Phase Jitter @ 100MHz
(Tjit(Ø))
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Min.
Typ.
12
Max.
Units
840
MHz
ps
20% - 80%
%
< 350MHz
≥350MHz
150
300
450
48
45
50
50
52
55
20
250
ms
fs
LLC
Notes
Integration range (12kHz to 20MHz)
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
Pb RoHS/RoHS II Compliant
ESD Sensitive
4.0 x 4.0 x 0.85 mm 24-Pin QFN
LVCMOS AC Electrical Characteristics (4, 5, 6, 9)
VDD = VDDO = 3.3V±5% or 2.5V±5% ; T A = -40°C to +85°C, unless otherwise noted
Parameters
Max.
Units
12
12
250
200
REFIN Amplitude (VREF)
Output Rise/Fall Time (TR/TF)
40% VDD
VDD + 0.6
100
500
MHz
MHz
VPP
ps
Output Duty Cycle (ODC)
PLL Lock Time (TLOCK)
RMS Phase Jitter @ 125MHz
(Tjit(Ø))
45
55
20
ms
Output Frequency (FOUT)
REFIN Frequency (FREF)
Min.
Typ.
50
55
fs
Notes
20% - 80%
Integration range (1.875MHz to 20MHz)
Notes:
1.
2.
3.
Exceeding the absolute maximum ratings may damage the device.
The device is not guaranteed to function outside tis operating ratings.
Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on
the PCB.
4. The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables after thermal
equilibrium has been established.
5. See Section 7.1.7 through 7.1.10 for load test circuit examples.
6. All phase noise measurements were taken with an Agilent 5052B phase noise system.
7. Outputs terminated 100Ω between Q and /Q. All unused outputs must be terminated.
8. Output load is 50Ω to VSS.
9. Output load is 50Ω to VDD/2.
10. Output load is 50Ω to VDD-2V.
OPTIONS AND PART IDENTIFICATION:
Please refer to the ABMJB-903 Part Number and Configuration Guide for available part
numbers and configurations.
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ISO9001:2008
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
OUTLINE DIMENSION:
Pin No.
22
23
3
12
1, 20
17, 24
2, 8, 13, 14,
15, 21
4, 5, 7, 9,
11, 16, 18
6, 10, 19
ePad
Configuration
Q
/Q
REFIN
OE
VDD
VDDO
VSS
DNC
DNC
Exposed Pad
Notes:
1. Max package warpage is 0.05mm.
2. Max allowable burr is 0.076mm in all directions.
3. Pin 1is on top and will be laser marked.
4. Red circles in land pattern indicate thermal vias. Size should be 0.30 – 0.35M in
diameter and should be connected to GND for max thermal performance.
5. Green rectangles (shaded area) indicate solder stencil opening on exposed pad
area. Size should be 1.00 x 1.00 mm in size, 1.20mm pitch.
Dimension: mm
ABRACON IS
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
Pb RoHS/RoHS II Compliant
ESD Sensitive
4.0 x 4.0 x 0.85 mm 24-Pin QFN
PIN DESCRIPTION:
24-Pin QFN package
Pin No.
Pin Name
Pin Type
Pin Level
22
Q
23
/Q
3
O
Various
REFIN
I, (SE)
Various
12
OE
I
LVCMOS
1, 20
VDD
PWR
Core power supply
17, 24
2, 8, 13, 14,
15, 21
4, 5, 7, 9,
11, 16, 18
VDDO
PWR
Output buffer power supply
VSS
PWR
Power supply ground
6, 10, 19
DNC
ePad
Exposed Pad
Notes:
1.
DNC
GND
Function
Clock output
Can be programmed to one of the following logic types: (1)
LVPECL, LVDS, HCSL or LVCMOS
Reference clock input
Can be programmed to either LVCMOS levels or smaller
amplitude signals from other logic types
Output enable control input with pull-up (45k )
Used for production test
Do not connect anything to these pins
Not internally connected. No need to connect anything to
these pins.
The center pad must be connected to the ground plane both
for electrical ground and thermal relief.
In case of LVCMOS, the output pair can provide two single-ended LVCMOS outputs.
BLOCK DIAGRAM:
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
FUNCTIONAL DESCRIPTION
ABMJB-903 series is a very flexible, advanced programmable jitter filter design for high performance, small form-factor
applications. The ABMJB-903 accepts a reference clock input between 12MHz and 200MHz and is capable of producing
one differential output up to 840MHz or two single ended outputs up to 250MHz. The most common configuration will
be with the same input and output frequency but this flexible design also allows frequency translation from one
frequency to another frequency, as long as both frequencies are within the specified ranges for input and output.
Jitter Attenuation
Typically the jitter attenuation settings will be optimized for one particular input and output frequency. Customization of
attenuation properties is possible.
The lowest possible output phase jitter, or phase jitter floor, is 251fs for the 12kHz to 20MHz integration range and 55fs
for the Gigabit Ethernet integration range of 1.875MHz to 20MHz. The ABMLB-903 excels at attenuating deterministic
jitter that presents itself as spurs in the phase noise plot above 1MHz.
Clock Output
The output pins Q and /Q make a differential output that can be programmed to several different logic types: LVPECL,
LVDS, HCSL or LVCMOS. In the case of LVCMOS, there are three possible configurations:
1. One single-ended output with the complementary pin disabled to a high impedance.
2. Two single-ended, in-phase outputs.
3. A differential output with opposite phases at the two output pins
Output Frequency
The most common configuration is where the output frequency is the same as the input frequency. However, frequency
translations are possible. The input frequency upper limit is 200MHz, but the output can go up to 840MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin
incorporates a 45kΩ pull-up resistor giving a default condition of logic “1” that enables the output(s).
Reference (Noisy) Clock Input (REFIN)
The input requires a single-ended CMOS signal. The frequency range for the input is 12MHz to 200MHz.
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
APPLICATION INFORMATION
Power Supply Filtering Recommendations
Preferred filter, using Micrel’s MIC94300 or MIC94310 Ripple Blocker™:
Alternative, traditional filter, using a ferrite bead:
Power Supply Decoupling
Place the smallest value decoupling capacitor (4.7nF above) between the VDD and VSS pins, as close as possible to
those pins and at the same side of the PCB as the IC. The shorter the physical path from VDD to capacitor and back from
capacitor to VSS, the more effective the decoupling. Use one 4.7nF capacitor for each VDD pin on the ABMJB-903.
The impedance value of the ferrite bead (FB) needs to be between 240 and 600 with a saturation current ≥150mA.
VDDO pins connect directly to the VDD plane. All VDD pins on the ABMJB-903 connect to VDD after the power
supply filter.
Output Traces
Design the traces for the output signals according to the output logic requirements. If LVCMOS is unterminated, add a
30 resistor in series with the output, as close as possible to the output pin, and start a 50 trace on the other side of the
resistor.
For differential traces, you can either use a differential design or two separate 50 traces. For EMI reasons, it is better to
use a differential design.
LVDS can be AC-coupled or DC-coupled to its termination.
Duty Cycle Timing
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
APPLICATION INFORMATION
All Outputs Rise/Fall Time
RMS Phase Noise Jitter
LVPECL Output Load and Test Circuit
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
APPLICATION INFORMATION
HCSL Output Load and Test Circuit
LVDS Output Load and Test Circuit
LVCMOS Output Load and Test Circuit
ABRACON IS
ISO9001:2008
CE RTIFIED
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
Pb RoHS/RoHS II Compliant
ESD Sensitive
4.0 x 4.0 x 0.85 mm 24-Pin QFN
JITTER ATTENUATION PERFORMANCE
The jitter attenuating frequency response was measured at 156.25MHz.
10
Jitte r Atte nuatio n (dB)
0
-10
-20
-30
-40
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Jitter / Modulation Frequency (Hz)
The jitter attenuation works like a low-pass filter for frequency modulated signals or noise. The bandwidth for this low
pass filter is 500kHz with a 12dB/octave slope above 500kHz. At about 6MHz the noise floor of this measurement is
reached but in reality, the attenuation continues with the 12dB/octave slope.
Phase noise performance with a clean input clock:
156.25MHz with 55fsRMS for phase jitter for 1.875MHz to 20MHz integration range
156.25MHz with 251fsRMS for phase jitter for 12kHz to 20MHz integration range
ABRACON IS
ISO9001:2008
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
JITTER ATTENUATION PERFORMANCE
Example: 156.25MHz input test clock with bad phase jitter caused by a 3MHz spur – 1.1psRMS of phase jitter for
1.875MHz to 20MHz integration range
Output Clock from ABMJB-903: The 3MHz spur is attenuated by 20dB, resulting in a phase jitter reduction from 1.1ps
to 0.10ps for 1.875MHz to 20MHz integration range
ABRACON IS
ISO9001:2008
CE RTIFIED
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale
High Performance MEMS Jitter Attenuator
ABMJB-903
ESD Sensitive
Pb RoHS/RoHS II Compliant
4.0 x 4.0 x 0.85 mm 24-Pin QFN
REFLOW PROFILE:
Parameters
Average Ramp-up Rate
Pre-Heat Temp 150 – 200°C
Temp > 217°C
Time @ Peak Temperature
Peak Temperature
Ramp-down Rate
Time 25°C to Peak Temp.
Specifications
3°C /second max.
60 – 180 second
60 – 150 second
20 – 40 second
260°C + 0°C / -5°C
-6°C / second max.
8 minutes max.
TAPE & REEL:
Packaging:
T: 1000pcs/reel
T5: 500pcs/reel
Dimensions: mm
ATTENTION: Abracon Corporation’s products are COTS – Commercial-Off-The-Shelf products; suitable for Commercial, Industrial and, where designated, Automotive Applications. Abracon’s products are not specifically designed for Military, Aviation, Aerospace, Life-dependant Medical applications or any application requiring high reliability where
component failure could result in loss of life and/or property. For applications requiring high reliability and/or presenting an extreme operating environment, written consent and
authorization from Abracon Corporation is required. Please contact Abracon Corporation for more information.
ABRACON IS
ISO9001:2008
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LLC
2 Faraday, Suite# B | Irvine | CA 92618 Revised: 03.26.15
Ph. 949.546.8000 | Fax. 949.546.8001
Visit www.abracon.com for Terms and Conditions of Sale