IN16C554A

IN16C554A
Quadruple UART
February 2009
REV 1.01
1. Description
IN16C554A is an enhanced quadruple version of the 16C550UART (Universal
Asynchronous Receiver Transmitter). IN16C554A is in part an upgrade version of
IN16C554, as it is designed for 3.3V only and has AUTO-CTS, AUTO-RTS functions.
In IN16C554A, Each channel can be put into FIFO mode to relieve the CPU of excessive
software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of
error data per byte can be stored in both receive and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a
peripheral device or a MODEM, and parallel-to-serial conversion on data characters
received from the CPU. The CPU can read the complete status of the UART at any time
during the functional operation. The Status information includes the type and condition of
the transfer operations being performed by the UART, as well as any error conditions
such as parity, overrun, framing, and break interrupt.
IN16C554A includes a programmable baud rate generator which is capable of dividing the
timing reference clock input by divisors of 1 to 216-1, and producing a 16x clock for driving
the internal transmitter logic. Provisions are also included to use this clock to drive the
receiver logic.IN16C554A has complete MODEM-control capability and an interrupt
system that can be programmed to the user’s requirements, minimizing the computing
required to handle the communication links. Moreover IN16C554A can select hardware
flow control. Hardware flow control significantly reduces software overhead and increases
system efficiency.
2. Features
■
In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte
FIFO to reduce the number of interrupts to CPU.
■
Adds or deletes standard asynchronous communication bits (start, stop, parity) to or
from the serial data.
■
Holding Register and Shift Register eliminate need for precise synchronization
between the CPU and serial data.
■
Independently controlled transmit, receive, line status and data interrupts.
■
Programmable Baud Rate Generators which allow division of any input reference
clock by 1 to 216-1 and generate an internal 16X clock.
■
Independent receiver clock input
Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
■
Fully programmable serial interface characteristics.
- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only
one stop bit, no matter how many they are)
1
IN16C554A
QUAD UART
JULY 2008
REV 0.99
■
False start bit detection
■
Generates or Detects Line Break
■
Internal diagnostic capabilities : Loopback controls for communications link fault
isolation.
■ Full prioritized interrupt system controls
■ Hardware (RTS#/CTS#) Flow Control
3. Ordering Information
Table 1:
Ordering Information
Part Number
Package
Operating Temperature Range
Device Status
IN16C554A-TQ80
80-Pin TQFP
-20 ℃ to +85 ℃
Active
IN16C554A-PL68
68-Pin PLCC
-20 ℃ to +85 ℃
Active
IN16C554A-TQ64
64-Pin TQFP
-20 ℃ to +85 ℃
Active
2
IN16C554A
Quadruple UART
February 2009
REV 1.01
4. Block Diagram
SB16C554A
D[7:0]
IOR#/IOW#
RESET
A[2:0]
CS#[3:0]
TRANSMIT
FIFO
REGISTER
DATA AND
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXD0
RECEIVE
SHIFT
REGISTER
RXD0
HARDWARE
FLOW
CONTROL
LOGIC
REGISTER
CONTROL
LOGIC
RECEIVE
FIFO
REGISTER
HARDWARE
FLOW
CONTROL
LOGIC
MODEM
SIGNAL
CONTROL
LOGIC
RTS0#/DTR0#
CTS0#/DSR0#/DCD0#/RI0#
INTERRUPT
CONTROL
LOGIC
INT[3:0]
TXRDY#/RXRDY #
UART 0
TXD1
RXD1
RTS1#/DTR1#
CTS1#/DSR1#/DCD1#/RI1#
UART 1
TXD2
RXD2
RTS2#/DTR2#
CTS2#/DSR2#/DCD2#/RI2#
UART 2
TXD3
RXD3
RTS3#/DTR3#
CTS3#/DSR3#/DCD3#/RI3#
UART 3
CLOCK AND
BAUD RATE
GENERATOR
XTAL1
Figure 1:
XTAL2
Block Diagram
3
IN16C554A
QUAD UART
JULY 2008
REV 0.99
5. Pin Configuration
NC
nDCD1
nRI1
RXD1
VCC
A1
A2
NC
A0
XTAL1
NC
NC
nDSR2
62
39
nDSR1
nCTS2
63
38
nCTS1
nDTR2
64
37
nDTR1
VCC
65
36
GND
nRTS2
66
35
nRTS1
INT2
67
34
INT1
nCS2
68
33
nCS1
TXD2
69
32
TXD1
nIOR
70
31
nIOW
NC
71
30
NC
SB16C554A-TQ80
TXD3
72
29
TXD0
nCS3
73
28
nCS0
INT3
74
27
INT0
nRTS3
75
26
nRTS0
GND
76
25
VCC
nDTR3
77
24
nDTR0
80-Pin TQFP Pin Configuration
NC
nDCD0
nRI0
GND
RXD0
D7
D6
D5
D4
D3
D2
NC
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
D0
D1
80
VCC
nDSR0
NC
nINTN
nCTS0
RXD3
23
22
nRI3
78
79
nDCD3
nCTS3
nDSR3
NC
4
XTAL2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
NC - No internal connection
Figure 2:
NC
nRXRDY
RESET
nTXRDY
GND
nRI2
RXD2
nDCD2
NC
5.1 Pin Configuration for 80-Pin TQFP Package
NC
IN16C554A
Quadruple UART
February 2009
REV 1.01
nDCD3
nRI3
RXD3
VCC
nINTN
D1
D0
D3
D2
D4
D6
D5
D7
GND
RXD0
nDSR0
10
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
nDSR3
nCTS0
11
59
nCTS3
nDTR0
12
58
nDTR3
VCC
13
57
GND
nRTS0
14
56
nRTS3
INT0
15
55
INT3
nCS0
16
54
nCS3
TXD0
17
53
TXD3
nIOW
18
52
nIOR
TXD1
19
51
TXD2
nCS1
20
50
nCS2
SB16C554A-PL68
nDSR1
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
nDSR2
nDCD2
nCTS2
nRI2
45
GND
25
RXD2
nCTS1
nTXRDY
nDTR2
RESET
46
nRXRDY
24
XTAL2
VCC
nDTR1
XTAL1
47
A1
A0
23
A2
nRTS2
GND
NC
INT2
48
VCC
49
22
RXD1
21
nRI1
INT1
nRTS1
nDCD1
Figure 3:
nRI0
nDCD0
5.2 Pin Configuration for 68-Pin PLCC Package
68-Pin PLCC Pin Configuration
5
IN16C554A
QUAD UART
JULY 2008
REV 0.99
6
nDCD3
nRI3
nINTN
RXD3
D0
D1
D2
D3
D4
D5
D6
D7
GND
nRI0
nDSR0
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
nDSR3
nCTS0
2
47
nCTS3
nDTR0
3
46
nDTR3
VCC
4
45
GND
nRTS0
5
44
nRTS3
INT0
6
43
INT3
nCS0
7
42
nCS3
TXD0
8
nIOW
9
SB16C554A-TQ64
41
TXD3
40
nIOR
nDTR2
nCTS1
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nCTS2
64-Pin TQFP Pin Configuration
nDSR2
34
nDCD2
15
nRI2
VCC
nDTR1
RXD2
35
GND
14
RESET
nRTS2
GND
XTAL2
INT2
36
XTAL1
37
A0
12
13
A1
INT1
nRTS1
A2
nCS2
VCC
TXD2
38
RXD1
39
11
nRI1
10
nDCD1
TXD1
nCS1
nDSR1
Figure 4:
RXD0
nDCD0
5.2 Pin Configuration for 64-pin-TQFP Package
IN16C554A
Quadruple UART
February 2009
REV 1.01
5.3 Pin Description
Table 2:
Pin Description
Data Bus Interface
Name
Pin
Type
Description
TQFP80
PLCC68
TQFP64
A0
A1
A2
48
47
46
34
33
32
24
23
22
I
I
I
Address Bus Lines [2:0]. These 3 address lines
select one of the internal registers in UART channel
0-3 during a data bus transaction.
D0
D1
D2
D3
D4
D5
D6
D7
7
8
9
11
12
13
14
15
66
67
68
1
2
3
4
5
53
54
55
56
57
58
59
60
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Bus Lines [7:0]. These pins are tri-state data
bus for data transfer to or from the controlling CPU.
IOR#
70
52
40
I
Read Data (active low strobe). A valid low level on
IOR# will load the data of an internal register defined
by address lines A [2:0] onto the UART data bus for
access by an external CPU.
IOW#
31
18
9
I
Write Data (active low strobe). A valid low level on
IOW# will transfer the data from external CPU to an
internal register that is defined by address lines A
[2:0].
CS0#
CS1#
CS2#
CS3#
28
33
68
73
16
20
50
54
7
11
38
42
I
I
I
I
Chip Select 0, 1, 2, and 3 (active low). These pins
enable data transfers between the external CPU and
the UART for the respective channel.
INT0/GINT
INT1
INT2
INT3
27
34
67
74
15
21
49
55
6
12
37
43
O
O
O
O
External interrupt output. When activated, INTx
output informs CPU that
UART has an interrupt to be serviced.
INTSEL
6
65
52
I
Interrupt Select. When INTSEL is left open or low
state, the tri-state interrupts available on INT0-3 are
enabled by MCR[3]. But, when INTSEL is in high
state, INT0-3 are always enabled.
TXRDY#
55
39
O
Transmitter Ready (active low). This is asserted by
TX FIFO/THR status for transmit channels 0-3.
RXRDY#
54
38
O
Receiver Ready (active low). This is asserted by RX
FIFO/RHR status for receive channels 0-3.
7
IN16C554A
QUAD UART
JULY 2008
Table 2:
REV 0.99
Pin Description…continued
Modem and Serial I/O Interface
Name
Pin
Type
Description
TQFP80
PLCC68
TQFP64
TXD0
TXD1
TXD2
TXD3
29
32
69
72
17
19
51
53
8
10
39
41
O
O
O
O
Transmit Data. These pins are individual transmit
data output. During the local loop-back mode, the
TXD output pin is disabled and TXD data is
internally connected to the RXD input.
RXD0
RXD1
RXD2
RXD3
17
44
57
4
7
29
41
63
62
20
29
51
I
I
I
I
Receive Data. These pins are individual receive data
input. During the local loop-back mode, the RXD
input pin is disabled and RXD data is internally
connected to the TXD output.
RTS0#
RTS1#
RTS2#
RTS3#
26
35
66
75
14
22
48
56
5
13
36
44
O
O
O
O
Request to Send (active low). These pins indicate
that the UART is ready to send data to the modem,
and affect transmit and receive operations only
when Auto-RTS function is enabled.
CTS0#
CTS1#
CTS2#
CTS3#
23
38
63
78
11
25
45
59
2
16
33
47
I
I
I
I
Clear to Send (active low). These pins indicate the
modem is ready to accept transmitted data from the
UART, and affect transmit and receive operations
only when Auto-CTS function is enabled.
DTR0#
DTR1#
DTR2#
DTR3#
24
37
64
77
12
24
46
58
3
15
34
46
O
O
O
O
Data Terminal Ready (active low). These pins
indicate UART is ready to transmit or receive data.
DSR0#
DSR1#
DSR2#
DSR3#
22
39
62
79
10
26
44
60
1
17
32
48
I
I
I
I
Data Set Ready (active low). These pins indicate
modem is powered-on and is ready for data
exchange with UART.
DCD0#
DCD1#
DCD2#
DCD3#
19
42
59
2
9
27
43
61
64
18
31
49
I
I
I
I
Carrier Detect (active low). These pins indicate that
a carrier has been detected by modem.
RI0#
RI1#
RI2#
RI3#
18
43
58
3
8
28
42
62
63
19
30
50
I
I
I
I
Ring Indicator (active low). These pins indicate the
modem has received a ringing signal from telephone
line. A low to high transition on these input pins
generates a modem status interrupt, if enabled.
Other Interfaces
Name
Pin
TQFP80
Type
PLCC68
Description
TQFP64
XTAL1
50
35
25
I
Crystal or External Clock Input.
XTAL2
51
36
26
O
Crystal or Buffered Clock Output.
8
IN16C554A
Quadruple UART
February 2009
Table 2:
REV 1.01
Pin Description…continued
Other Interfaces
Name
Pin
Type
Description
TQFP80
PLCC68
TQFP64
RESET
53
37
27
I
Reset (active high). This pin will reset the internal
registers and all the outputs.
VCC
5
25
45
65
13
30
47
64
4
21
35
I
Power Supply Input. 3.3V (2.7V ~ 3.6V)
GND
16
36
56
76
6,
23
40
57
14
28
45
61
I
Signal and Power Ground.
NC
1
10
20
21
30
40
41
49
52
60
61
71
80
31
-
No Internal Connection.
9
IN16C554A
QUAD UART
JULY 2008
REV 0.99
6. Functional Description
The IN16C554A UART is pin-to-pin compatible with the TL16C554A and SB16C554
UARTs. The IN16C554A has same function with IN16C554 except for flow control and
voltage that are used in operations.
IN16C554A can select hardware flow control. Hardware flow control significantly reduces
software overhead and increases system efficiency by automatically controlling serial
data flow using the RTS# output and CTS# input signals.
6.1 Hardware Flow Control
Hardware flow control is executed by Auto-RTS and Auto-CTS. Auto-RTS and Auto-CTS
can be enabled/disabled by programming MCR [5]. If Auto-RTS is enabled, it reports that
it cannot receive more data by asserting RTS# when RX FIFO has no space. Then after
the data stored in RX FIFO is read by CPU, it reports that it can receive new data by
deasseting RTS# when the amount of existing data in RX FIFO is less than trigger level.
When Auto-CTS is enabled and CTS# is cleared to ‘0’, transmitting data to TX FIFO has
to be suspended because external device has reported that it cannot accept more data.
When data transmission has been suspended and CTS# is set to ‘1’, data in TX FIFO is
retransmitted because external device has reported that it can accept more data. These
operations prevent overrun during communication and if hardware flow control is disabled
and transmit data rate exceeds RX FIFO service latency, overrun error occurs.
6.1.1 Auto-RTS
To enable Auto-RTS, MSR [5], [1] should be set to ‘1’. Once enabled, RTS# outputs ‘0’. If
the number of received data in RX FIFO reaches a trigger level, RTS# will be changed to
‘1’ and if not, holds ‘0’. This state indicates that RX FIFO can accept more data. After
RTS# changed to ‘1’ and reported to the CPU that it cannot accept more data, the CPU
reads the data in RX FIFO and then the amount of data in RX FIFO reduces. When the
amount of data in RX FIFO has a space to store data, RTS# changes to ‘0’ and reports
that it can accept more data. That is, if RTS# is ‘0’ now, RTS# is not changed to ‘1’ until
the amount in RX FIFO reaches to trigger level. But if RTS# is ‘1’ now, RTS# is not
changed to ‘0’ until the RX FIFO has at least one available byte space.
While Auto-RTS is enabled, you can verify if RTS# is ‘0’ or ‘1’ by FSR[5]. If FSR[5] is ‘0’,
RTS# is ‘0’ and if ‘1’, RTS# is ‘1’, too. When IER[6] is set to ‘1’ and RTS# is changed from
‘0’ to ‘1’ by Auto-RTS function, interrupt occurs and it is displayed on ISR[5:0]. Interrupts
by Auto-RTS function are removed if MSR is read. RTS# is changed from ‘0’ to ‘1’ after
the first STOP bit is received. Figure 5 shows the RTS# timing chart while Auto-RTS is
enabled.
In Figure 5, Data Byte n-1 is received and RTS# is deasserted when the amount of data
in RX FIFO is larger than the value written in FUR. UART completes transmitting new
data (DATA BYTE n) which has started being transmitted even though external UART
recognizes RTS# has been deasserted. After that, the device stops transmitting more
data.
10
IN16C554A
Quadruple UART
February 2009
RXD
START
DATA BYTE n-1
STOP
START
DATA BYTE n
STOP
REV 1.01
START
RTS#
DATA BYTE 1
DATA BYTE 2
DATA BYTE n
IOR#
Figure 5:
RTS# Functional Timing
6.1.2 Auto-CTS
Setting MSR [5] to ‘1’ enables Auto-RTS. If enabled, data in TX FIFO are determined to
be transmitted or suspended by the value of CTS#. If ‘0’, it means external UART can
receive new data and data in TX FIFO are transmitted through TXD pin. If ‘1’, it means
external UART can not accept more data and data in TX FIFO are not transmitted. But
data being transmitted by then complete transmission. These procedures are performed
irrespective of FIFO modes. While Auto-CTS is enabled, you can verify the input value of
CTS# by FSR[1]. If ‘0’, CTS# is ‘0’ and it means external UART can accept new data,
If ’1’, CTS# is ‘1’ and it means external UART can not accept more data and data in TX
FIFO are not being transmitted. If IER[7] is set to ‘1’, interrupt is generated by Auto-CTS
when the input of CTS# is changed from ‘0’ to ‘1’, and it is shown on ISR[5:0]. Interrupts
generated by Auto-CTS are removed if MSR is read.
6.2 Programmable Baud Rate Generator
The IN16C554A has a programmable baud rate generator. The baud rate generator
divides this clock frequency by a programmable divisor (DLL and DLM) between 1 and
(216 – 1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate
clock is used by transmitter for data bit shifting and receiver for data sampling.
The divisor of the baud rate generator is:
Divisor =
(
XTAL1 Crystal Input Frequency
)
(Desired Baud Rate x 16)
PROGAMMABLE
DIVISOR
XTAL1
XTAL2
INTERNAL
OSCILLATOR
LOGIC
BAUD RATE
GENERATOR
LOGIC
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
Figure 6: Baud Rate Generator Block Diagram
11
IN16C554A
QUAD UART
JULY 2008
REV 0.99
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are
both zero, the IN16C554A is effectively disabled, as no baud clock will be generated.
Table 3 shows the baud rate and divisor value as well as crystal with frequency
1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.7456MHz, respectively.
Figure 7 shows the crystal clock circuit reference.
Table 3:
Baud Rates
Desired Baud Rate
16X Digit Divisor
1.8432MHz
12
3.6864MHz
7.3728MHz
14.7456MHz
50
0900h
1200h
2400h
4800h
75
0600h
0C00h
1800h
3000h
150
0300h
0600h
0C00h
1800h
300
0180h
0300h
0600h
0C00h
600
00C0h
0180h
0300h
0600h
1200
0060h
00C0h
0180h
0300h
1800
0040h
0080h
0100h
0200h
2000
003Ah
0074h
00E8h
01D0h
2400
0030h
0060h
00C0h
0180h
3600
0020h
0040h
0080h
0100h
4800
0018h
0030h
0060h
00C0h
7200
0010h
0020h
0040h
0080h
9600
000Ch
0018h
0030h
0060h
19.2K
0006h
000Ch
0018h
0030h
38.4K
0003h
0006h
000Ch
0018h
57.6K
0002h
0004h
0008h
0010h
115.2K
0001h
0002h
0004h
0008h
230.4K
―
0001h
0002h
0004h
460.8K
―
―
0001h
0002h
921.6K
―
―
―
0001h
IN16C554A
Quadruple UART
February 2009
REV 1.01
XTAL1
External
Clock
XTAL1
R1
SB16C554A
CRYSTAL
SB16C554A
R2
XTAL2
Optional
Clock
Output
XTAL2
C1
C2
Figure 7: Baud Rate Generator Block Diagram
Table 4:
Component Values
Frequency Range (MHz)
C1 (pF)
C2 (pF)
R1 (Ω)
R2(Ω)
1.8~8
22
68
220K
470 ~ 1.5K
8~16
33~68
33 ~ 68
220K ~ 2.2M
470 ~ 1.5K
6.3 Break and Time-out Conditions
Break Condition:
Break Condition is occurred when TXD signal outputs ‘0’ and sustains for more than one
character.
It is occurred if LCR[6] is set to ‘1’ and deleted if ‘0’. If break condition is occurred when
normal data are transmitted on TXD, break signal is transmitted and internal serial data
are also transmitted, but they are not outputted to external TXD pin. When Break
condition is deleted, then they are transmitted to TXD pin.
Figure 7 below shows the Break Condition Block Diagram.
Time-out Condition:
When serial data is received from external UART, characters are stored in RX FIFO.
When the number of characters in RX FIFO reaches the trigger level, interrupt is
generated for the CPU to treat characters in RX FIFO. But when the number of characters
in RX FIFO does not reach the trigger level and no more data arrives from external
device, interrupt is not generated and therefore CPU cannot recognize it. IN16C554A
offers time-out function for this situation. Time-out function generates an interrupt and
reports to CPU when the number of RX FIFO is less than trigger level and no more data
receives for four character time.
Time-out interrupt is enabled when IER[2] is set to ‘1’ and can be verified by ISR.
13
IN16C554A
QUAD UART
JULY 2008
REV 0.99
7. Register Descriptions
LCR[7] = 0
LCR[7] = 1
Address
LCR[7:0]
≠ BFh
A[2:0]
0h
THR/RBR
DLL
1h
IER
DLM
2h
FCR/ISR
3h
LCR
4h
MCR
5h
LSR
6h
MSR
7h
SPR
Table 5:
Address
Internal Registers Map…continued
Register
Read/Write
Comments
A[2:0]
Registers
0h
1h
2h
THR : Transmit Holding Register
Write-only
RBR : Receive Buffer Register
Read-only
LCR[7] = 0
IER : Interrupt Enable Register
Read/Write
LCR[7] = 0
FCR : FIFO Control Register
Write-only
LCR[7] = 0
ISR : Interrupt Status Register
Read-only
LCR[7] = 1, LCR
3h
LCR : Line Control Register
Read/Write
4h
MCR : Modem Control Register
Read/Write
≠ BFh
—
LCR[7] = 0
LCR[7] = 1, LCR
≠ BFh,
LCR[7] = 0
5h
LSR : Line Status Register
Read-only
LCR[7] = 0
LCR[7] = 1, LCR
6h
MSR : Modem Status Register
Read-only
7h
SPR : Scratch Pad Register
Read/Write
LCR[7] = 0
LCR[7] = 1, LCR
14
≠ BFh
≠ BFh
LCR[7] = 0
LCR[7] = 1, LCR
≠ BFh
0h
DLL : Divisor Latch LSB
Read/Write
LCR[7] = 1, LCR
≠ BFh
1h
DLM : Divisor Latch MSB
Read/Write
LCR[7] = 1, LCR
≠ BFh
IN16C554A
Quadruple UART
February 2009
Table 6:
Addr.
A[2:0]
REV 1.01
Internal Registers Description
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 2
Bit 2
Receive
Line
Status
Interrupt
Enable
Interrupt
Priority
Bit 2
TX FIFO
Reset
Bit 1
Bit 1
THR
Empty
Interrupt
Enable
Bit 0
Bit 0
Receive
Data
Available
Interrupt
Enable
Interrupt
Priority
Bit 0
FIFO
Enable
Page 0 Registers
0h
0h
1h
THR
RBR
IER
Bit 7
Bit 7
0
Bit 6
Bit 6
0
Bit 5
Bit 5
0
Bit 4
Bit 4
0
Bit 3
Bit 3
Modem
Status
Interrupt
Enable
2h
ISR
FIFOs
Enabled
FIFOs
Enabled
0
0
2h
FCR
Reserved
LCR
RX
Trigger
Level
(LSB)
Set
TX Brake
Reserved
3h
RX
Trigger
Level
(MSB)
Divisor
Enable
Interrupt
Priority
Bit 3
DMA
Mode
Select
Set
Parity
4h
MCR
0
0
5h
LSR
MSR
SCR
THR &
TSR
Empty
RI#
Bit 6
Receive
Break
6h
7h
RX FIFO
Data
Error
DCD#
Bit 7
Autoflow
Control
enable
THR
Empty
Parity
Type
Select
0/Loop
Back
DSR#
Bit 5
0h
1h
DLL
DLM
Bit 7
Bit 15
Bit 6
Bit 14
Bit 5
Bit 13
Interrupt
Priority
Bit 1
RX
FIFO
Reset
reserved
Word
Length
Bit 1
RTS#
Word
Length
Bit 0
DTR#
Parity
Error
Overrun
Error
∆DCD#
∆RI#
∆DSR#
Bit 3
Bit 2
Bit 1
Receive
Data
Ready
∆CTS#
Bit 0
Bit 3
Bit 11
Bit 2
Bit 10
Bit 1
Bit 9
Bit 0
Bit 8
Parity
Enable
Stop
Bits
OUT/
INTx
Enable
Framing
Error
CTS#
Bit 4
Bit 4
Bit 12
7.1 Interrupt Enable Register (IER)
IER enables each of the four types of Interrupt, namely receive data ready, transmit
empty, line status, modem status. All interrupts are disabled if bit[7:0] are cleared.
Interrupt is enabled by setting appropriate bits. Table 9 shows IER bit settings.
15
IN16C554A
QUAD UART
JULY 2008
REV 0.99
Table 7:
Interrupt Enable Register Description
Bit
Symbol
Description
7:4
IER[7:4]
These four bits of the IER are cleared
3
IER[3]
Modem Status Interrupt Enable
0 : Disable the modem status register interrupt (default).
1: Enable the modem status register interrupt.
2
IER[2]
Receive Line Status Interrupt Enable
0 : Disable the receive line status interrupt (default).
1: Enable the receive line status interrupt.
1
IER[1]
Transmit Holding Register Interrupt Enable
0 : Disable the THR interrupt (default).
1 : Enable the THR interrupt.
0
IER[0]
Receive Buffer Register Interrupt Enable
0 : Disable the RBR interrupt (default).
1 : Enable the RBR interrupt.
7.2 Interrupt Status Register (ISR)
The UART provides multiple levels of prioritized interrupts to minimize software work load.
ISR provides the source of interrupt in a prioritized manner.
Table 10 shows ISR[7:0] bit settings.
Table 8:
Interrupt Status Register Description
Bit
Symbol
Description
7:6
ISR[7:6]
ISR[7:6] are set when FCR[0]=1
Mirror the content of FCR[0].
Table 8:
Interrupt Status Register Description…continued
Bit
Interrupt Priority List and Reset Functions
5:0
Priority
Interrupt Type
Interrupt Source
Interrupt Reset Control
00_0001
―
None
None
―
00_0110
1
Receiver Line Status
OE, PE, FE, BI
Reading the LSR.
00_0100
2
Receive Data Available
Receiver data available, reaches
Reading the RBR or FIFO
trigger level.
falls below trigger level.
Character Timeout Indi-
At least one data is in RX FIFO and
Reading the RBR.
cation
there are no more data in FIFO during
00_1100
2
four character time.
00_0010
3
00_0000
4
16
Transmit Holding
When THR is empty or TX FIFO passes
Reading the ISR or write
Register Empty
above trigger level (FIFO enable).
data on THR.
Modem Status
CTS#, DSR#, DCD#, RI#
Reading the MSR.
IN16C554A
Quadruple UART
February 2009
REV 1.01
7.3 FIFO Control Register (FCR)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO
trigger level, and selecting the DMA modes. Table 11 shows FCR bit settings.
Table 9:
FIFO Control Register Description
Bit
Symbol
Description
7:6
FCR[7:6]
RX FIFO Trigger Level Select
00 : 1 characters (default)
01 : 4 characters
10 : 8 characters
11 : 14 characters
5:4
FCR[5:4]
FCR[5:4] are reserved
3
FCR[3]
DMA Mode Select
0 : Set DMA mode 0 (default)
1 : Set DMA mode 1
2
FCR[2]
TX FIFO Reset
0 : No TX FIFO reset (default)
1 : Reset TX FIFO pointers and TX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
1
FCR[1]
RX FIFO Reset
0 : No RX FIFO reset (default)
1 : Reset RX FIFO pointers and RX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
0
FCR[0]
FIFO enable
0 : Disable the TX and RX FIFO (default).
1 : Enable the TX and RX FIFO
7.4 Line Control Register (LCR)
LCR controls the asynchronous data communication format. The word length, the number
of stop bits, and the parity type are selected by writing the appropriate bits to the LCR.
Table 12 shows LCR bit settings.
Table 10:
Line Control Register Description
Bit
Symbol
Description
7
LCR[7]
Divisor Latch Enable.
0 : Disable the divisor latch (default).
1 : Enable the divisor latch.
6
LCR[6]
Break Enable.
0 : No TX break condition output (default).
1 : Forces TXD output to ‘0’, for alerting the communication
terminal to a line break condition.
5
LCR[5]
Set Stick Parity.
17
IN16C554A
QUAD UART
JULY 2008
REV 0.99
LCR[5:3] = xx0 : No parity is selected.
LCR[5:3] = 0x1 : Stick parity disabled. (default)
LCR[5:3] = 101 : Stick parity is forced to ‘1’.
LCR[5:3] = 111 : Stick parity is forced to ‘0’.
4
LCR[4]
Parity Type Select.
LCR[5:3] =001 : Odd parity is selected.
LCR[5:3] =011 : Even parity is selected.
3
LCR[3]
Parity Enabled.
0 : No parity (default).
1 : A parity bit is generated during the transmission and
the receiver checks for receive parity.
2
LCR[2]
Number of Stop Bits.
LCR[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8).
LCR[2:0] = 100 : 1.5 stop bits (word length = 5).
LCR[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8).
1:0
LCR[1:0]
Word Length Bits.
00 : 5 bits (default).
01 : 6 bits.
10 : 7 bits.
11 : 8 bits.
7.5 Modem Control Register (MCR)
MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem. Table 13 shows MCR bit settings.
Table 11:
Modem Control Register Description
Bit
Symbol
Description
7:6
MCR [7:6]
These two bits are always cleared
5
MCR[5]
Autoflow control enable.
0 : Auto-RTS and auto-CTS disabled
1 : If MCR[1]=1, Auto-RTS and auto-CTS enabled (autoflow
control enabled)
If MCR[1]=1, Auto-CTS only enabled.
4
MCR[4]
Internal Loop Back Enable.
0 : Disable loop back mode (default).
1 : Enable internal loop back mode. In this mode the MCR[3:0]
signals are looped back into MSR[7:4] and TXD output is
looped back to RXD input internally.
3
MCR[3]
OUT/Interrupt Output Enable.
0 : INTx outputs disabled (default). During loop back mode,
OUT2 output ‘0’ and it controls MSR[7] to ‘1’.
1 : INTx outputs enabled. During loop back mode, OUT2 output
18
IN16C554A
Quadruple UART
February 2009
REV 1.01
‘1’ and it controls MSR[7] to ‘0’.
OUT is not available as an output pin on the IN16C554A.
2
MCR[2]
1
MCR[1]
It has no effect on operation.
RTS# Output.
0 : Force RTS# output to ‘1’. During loop back mode, controls
MSR[4] to ‘1’.
1 : Force RTS# output to ‘0’. During loop back mode, controls
MSR[4] to ‘0’.
0
MCR[0]
DTR# Output.
0 : Force DTR# output to ‘1’. During loop back mode, controls
MSR[5] to ‘1’.
1 : Force DTR# output to ‘0’. During loop back mode, controls
MSR[5] to ‘0’.
7.6 Line Status Register (LSR)
LSR provides the status of data transfers between the UART and the CPU. When LSR is
read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX
FIFO. The errors in a character are identified by reading LSR and then reading RBR.
Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RBR. Table 14 shows LSR bit settings.
Table 12:
Line Status Register Description
Bit
Symbol
Description
7
LSR[7]
RX FIFO data error Indicator.
0 : No RX FIFO error (default).
1 : At least one parity error, framing error, or break indication is in the
RX FIFO. This bit is cleared when there is no more error in any of
characters in the RX FIFO.
6
LSR[6]
THR and TSR Empty Indicator.
0 : THR or TSR is not empty.
1 : THR and TSR are empty.
5
LSR[5]
THR Empty Indicator.
0 : THR is not empty.
1 : THR is empty. It indicates that the UART is ready to accept a new
character for transmission. In addition, it uses the UART to generate an interrupt to the CPU when the THR empty interrupt enable
is set to ‘1’.
4
LSR[4]
Break Interrupt Indicator.
0 : No break condition (default).
1 : The receiver received a break signal (RXD was ‘0’ for at least one
character frame time). In FIFO mode, only one character is loaded
19
IN16C554A
QUAD UART
JULY 2008
REV 0.99
into the RX FIFO.
3
LSR[3]
Framing Error Indicator.
0 : No framing error (default).
1 : Framing error. It indicates that the received character did not have a
valid stop bit.
2
LSR[2]
Parity Error Indicator.
0 : No parity error (default).
1 : Parity error. It indicates that the receive character did not have the
correct even or odd parity, as selected by the LCR[4]
1
LSR[1]
Overrun Error Indicator.
0 : No overrun error (default).
1 : Overrun error. It indicates that the character in the RBR or RX FIFO
was not read by the CPU, thereby ignored the receiving character.
0
LSR[0]
Receive Data Ready Indicator.
0 : No character in the RBR or RX FIFO.
1 : At least one character in the RBR or RX FIFO.
7.7 Modem Status Register (MSR)
MSR provides the current status of control signals from modem or auxiliary devices.
MSR[3:0] are set to ‘1’ when input from modem changes and cleared to ‘0’ as soon as
CPU reads MSR. Table 15 shows MSR bit settings.
Table 13:
Modem Status Register Description
Bit
Symbol
Description
7
MSR[7]
DCD Input Status.
Complement of Data Carrier Detect (DCD#) input.
In loop back mode this bit is equivalent to OUT2 in the MCR.
6
MSR[6]
RI Input Status.
Complement of Ring Indicator (RI#) input.
In loop back mode this bit is equivalent to OUT1 in the MCR.
5
MSR[5]
DSR Input Status.
Complement of Data Set Ready (DSR#) input.
In loop back mode this bit is equivalent to DTR in the MCR.
4
MSR[4]
CTS Input Status.
Complement of Clear To Send (CTS#) input.
In loop back mode this bit is equivalent to RTS in the MCR.
3
MSR[3]
∆DCD Input Status.
0 : No change on CD# input (default).
1 : Indicates that the DCD# input has changed state.
20
IN16C554A
Quadruple UART
February 2009
2
MSR[2]
REV 1.01
∆RI Input Status.
0 : No change on RI# input (default).
1 : Indicates that the RI# input has changed state from ‘0’ to ‘1’.
1
MSR[1]
∆DSR Input Status.
0 : No change on DSR# input (deault).
1 : Indicates that the DSR# input has changed state.
0
MSR[0]
∆CTS Input Status.
0 : No change on CTS# input (deault).
1 : Indicates that the CTS# input has changed state.
7.8 Scratch Pad Register (SPR)
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a
scratch pad register to be used by the programmer to hold data temporarily.
7.9 Divisor Latches (DLL, DLH)
Two 8-bit registers which store the 16-bit divisor for generation of the clock in baud rate
generator. DLH stores the most significant part of the divisor, and DLL stores the least
significant part of the divisor. Divisor of zero is not recommended.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e., before
IER[4] is set. Chapter 6.2 describes the details of divisor latches.
Table 14:
IN16C554A Reset Conditions
Registers
Reset State
RBR
[7:0] = ‘XXXX_XXXX’
IER
[7:0] = ‘0000_0000’
FCR
[7:0] = ‘0000_0000’
ISR
[7:0] = ‘0000_0001’
LCR
[7:0] = ‘0000_0000’
MCR
[7:0] = ‘0000_0000’
LSR
[7:0] = ‘0110_0000’
MSR
[7:4] = ‘0000’
[3:0] = Logic levels of the inputs inverted
SPR
[7:0] = ‘0000_0000’
DLL
[7:0] = ‘1111_1111’
DLM
[7:0] = ‘1111_1111’
Output Signals
Reset State
TXD, RTS#, DTR#
Logic 1
TXRDY#
Logic 0
RXRDY#
Logic 1
INT
Tri-State Condition = INTSEL is open or low state
Logic 0 = INTSEL is high state
21
IN16C554A
QUAD UART
JULY 2008
REV 0.99
8. Programmer’s Guide
The base set of registers that is used during high-speed data transfer has a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.
Table 15:
Register Programming Guide
Command
Set Baud Rate to VALUE1, VALUE2
Action
Read LCR, save in temp
Set LCR to 80h
Set DLL to VALUE1
Set DLM to VALUE2
Set LCR to temp
Read Flow Control Status
Read LCR, save in temp1
Read MCR, save in temp2
Set LCR to (‘0111_1111’ AND temp1)
Set MCR to (‘0100_0000’ OR temp2)
Read FSR, save in temp3
Pass temp3 back to host
Set MCR to temp2
Set LCR to temp1
Read TX FIFO / RX FIFO Count Value
Read LCR, save in temp1
Read MCR, save in temp2
Set LCR to (‘0111_1111’ AND temp1)
Set MCR to (‘0100_0000’ OR temp2)
Read TCR, save in temp3
Read RCR, save in temp4
Pass temp3 back to host
Pass temp4 back to host
Set MCR to temp2
Set LCR to temp1
22
IN16C554A
Quadruple UART
February 2009
REV 1.01
9. Electrical Characteristics
Absolute Maximum Ratings
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
Supply voltage
—
3.6
V
VI
Input voltage
—0.5
5.5
V
VO
Output voltage
GND + 0.1
VCC – 0.1
V
Tamb
Operating ambient temperature
—20
+85
℃
Tstg
Storage temperature
—60
+150
℃
In free-air
DC Electrical Characteristics
Symbol
Parameter
Conditions
3.3V
Unit
Min
Nom
Max
VCC
Supply voltage
2.7
3.3
3.6
V
VI
Input voltage
0
—
VCC
V
VCC ⅹ 0.7
—
5.5
V
0
—
VCC ⅹ 0.3
V
0
—
VCC
V
IOH = —8mA
2.4
—
—
V
IOL = 8mA
—
—
0.4
V
Input capacitance
—
—
9
pF
Oscillator/Clock speed
—
—
85
MHz
Clock duty cycle
—
50
—
%
VIH
VIL
VO
VOH
VOL
CI
High-level input
voltage
Low-level input
voltage
Output voltage
High-level output
voltage
Low-level output
voltage
ICC
Supply current
f=14.7456MHz
—
—
37.8
mA
ICCsleep
Sleep current
f=14.7456MHz
—
—
2.5
mA
23
IN16C554A
QUAD UART
JULY 2008
REV 0.99
Symbol
Parameter
Min
trd
Pulse duration, IOR# low
24
ns
tcsr
Set up time, CSx# valid before IOR# low †
10
ns
tar
Set up time, A2~A0 valid before IOR# low †
10
ns
tra
Hold time, A2~A0 valid after IOR# high †
2
ns
trcs
Hold time, CSx# valid after IOR# high †
0
ns
tfrc
Delay time, tar+trd+trc ‡
54
ns
trc
Delay time, IOR# high to IOR# or IOW# low
20
ns
twr
Pulse duration, IOW#↓
24
ns
tcsw
Setup time, CSx# valid before IOW#↓
10
ns
taw
Setup time, A2~A0 valid before IOW#↓
10
ns
tds
Setup time, D7~D0 valid before IOW#↑
15
ns
twa
Hold time, A2~A0 valid after IOW#↑
2
ns
twcs
Hold time, CSx# valid after IOW#↑
2
ns
tdh
Hold time, D7~D0 valid after IOW#↑
5
ns
tfwc
Delay time, taw+twr+twc
54
ns
twc
Delay time, IOW#↑ to IOW# or IOR#↓
20
ns
trvd
Enable time, IOR#↓ to D7~D0 valid
thz
Disable time, IOR# to D7~D0 released
4
tirs
Delay time, INTx↓ to TXDx↓ at start
8
24
RCLK
tsti
Delay time, TXDx↓ at start to INTx↑
8
8
RCLK
tsi
Delay time, IOW# high or low (WR THR) to INTx↑
16
32
RCLK
tsxa
Delay time, TXDx↓ at start to TXRDY#↓
8
RCLK
thr
Propagation delay time, IOW#(WR THR)↓ to INTx↓
12
ns
tir
Propagation delay time, IOR#(RD IIR)↑ to INTx↓
12
ns
twxi
Propagation delay time, IOW#(WR THR) ↓ to TXRDY#↑
10
ns
tsint
Delay time, stop bit to INTx↑ or stop bit to RXRDY# or read RBR to set interrupt
trint
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
12
ns
trint
Propagation delay time, IOR# RCLK↓ to RXRDY#↑
12
ns
tmdo
Propagation delay time, IOW#(WR MCR)↑ to RTSx#, DTRx#↑
12
ns
tsim
Propagation delay time, modem input CTSx#, DSRx#, and DCDx#↓↑ to INTx↑
12
ns
trim
Propagation delay time, IOR#(RD MSR)↑ to interrupt↓
3
ns
tsim
Propagation delay time, Rix#↑ to INTx#↓
12
ns
† The internal address strobe is always in active state.
‡ In the FIFO mode, td1= xxns (min) between reads of the FIFO and the status register.
24
Max
24
Unit
ns
ns
RCLK
1
IN16C554A
Quadruple UART
February 2009
A[2:0]
REV 1.01
VALID ADDRESS
t ra
CSx#
t csr
t rcs
t frc
t ar
IOR#
ACTIVE
t rc
t rd
IOW#
t rvd
t hz
D[7:0]
Figure 8:
VALID DATA
Read Cycle Timing
A[2:0]
VALID ADDRESS
t wa
CSx#
t csw
t wcs
t fwc
t aw
IOR#
t wr
t wc
IOW#
ACTIVE
t ds
D[7:0]
Figure 9:
t dh
VALID DATA
Write Cycle Timing
25
IN16C554A
QUAD UART
JULY 2008
REV 0.99
TXDx
START
DATA(5-8)
PARITY
STOP(1-2)
START
t irs
t sti
INTx
t hr
t si
t hr
IOW#
(WR THR)
t ir
IOR#
(RD IIR)
Figure 10:
Transmitter Timing
IOW#
(WR THR)
TXDx
BY TE #1
DATA
PARITY
STOP
START
TXRDY#
t sxa
t w xi
Figure 11:
Transmitter Ready Mode 0 Timing
IOW#
(WR THR)
TXDx
BY TE #16
DATA
PARITY
TXRDY#
26
START
FIFO FULL
t w xi
Figure 12:
STOP
Transmitter Ready Mode 1 Timing
t sxa
IN16C554A
Quadruple UART
February 2009
RXDx
START
DATA(5-8)
PARITY
REV 1.01
STOP
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
INTx(TRIGGER
LEVEL INTERRUPT
(FCR6, 7 = 0, 0)
t sint
t rint
(FIFO BELOW
TRIGGER LEVEL)
LSI INTERRUPT
IOR#
(RD LSR)
t rint
IOR#
(RD RBR)
Figure 13:
Receiver FIFO First Byte (Sets RBR) Timing
RXDx
STOP
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
TIMEOUT OR
TRIGGER LEVEL
INTERRUPT
t sint
LSI INTERRUPT
t rint
(FIFO BELOW
TRIGGER LEVEL)
TOP BYTE OF FIFO
IOR#
(RD LSR)
t sint
t rint
IOR#
(RD RBR)
PREVIOUS BYTE
READ FROM FIFO
Figure 14:
Receiver FIFO After First Byte (After RBR Set) Timing
27
IN16C554A
QUAD UART
JULY 2008
REV 0.99
IOR#
(RD RBR)
RXDx
(FIRST BYTE)
STOP
Sample
Clock
RXRDY#
t sint
Figure 15:
t rint
Receiver Ready Mode 0 Timing
IOR#
(RD RBR)
RXDx
(FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL)
STOP
Sample
Clock
RXRDY#
t sint
Figure 16:
t rint
Receiver Ready Mode 1 Timing
IOW#
(WR MCR)
t mdo
t mdo
RTSx#, DTRx#
CTSx#, DSRx#, DCDx#
INTx
t sim
IOR#
(RD MSR)
RIx#
Figure 17:
28
Modem Control Timing
t rim
t sim
t rim
t sim
IN16C554A
Quadruple UART
February 2009
REV 1.01
10. Package Outline
80-Pin TQFP: Thin Plastic Quad Flat Package; Body 12 ⅹ 12 ⅹ 1.0 mm
0,27
0,17
9,50
12,00
14,00
1,05
0,95
1,20 MAX
0,10
0,50
0,75
0,45
0-7
1.00
Note :
1. All dimensions are in millimeters.
2. Falls within ANSI Y14.5-1982
29
IN16C554A
QUAD UART
JULY 2008
REV 0.99
68-Pin PLCC: Plastic Leaded Chip Carrier
1. All dimensions are in inches (millimeters).
2. Falls within ANSI Y14.5-1982
30
0.469 (11,913)
0.441 (11,201)
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
Note :
0.18 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.02 (0,51) MIN
0.469 (11,913)
0.441 (11,201)
0.956 (24,282)
0.950 (24,130)
0.995 (25,273)
0.985 (25,019)
0.956 (24,282)
0.950 (24,130)
0.032 (0.081)
0.026 (0,66)
0.995 (25,273)
0.985 (25,019)
IN16C554A
Quadruple UART
February 2009
REV 1.01
64-Pin TQFP: Thin Plastic Quad Flat Package; Body 10 ⅹ 10 ⅹ 1.0 mm
0.27
0.17
1.05 MAX
1.20 MAX
0.10
0.5
7.5
10
12
0.75
0.45
0-7
1.00
Note :
1. All dimensions are in inches (millimeters).
2. Falls within ANSI Y14.5-1982
31