EXAR XR16C2550

XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
FEBRUARY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR16C2550 (2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16C2550 is an improved version of the PC16550
UART with higher operating speed and faster access
times. The 2550 provides enhanced UART functions
with 16 byte FIFO’s, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates from 50 bps to
4 Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
2550 is available in a 44-pin PLCC and 48-pin TQFP
packages. The 2550 is fabricated in an advanced
CMOS process capable of operating from 2.97 volt to
5.5 volt power supply.
FEATURES
• 2.97 Volt to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s ST16C2450,
XR16L2550 and XR16L2750
• Pin-to-pin compatible to TI’s TL16C752B on the 48TQFP package
• Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
• 2 independent UART channels
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APPLICATIONS
■
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
■
Up to 4 Mbps with external clock of 64 MHz
Up to 1.5 Mbps data rate with a 24 MHz crystal
frequency
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
• Crystal oscillator or external clock input
• 48-TQFP and 44-PLCC packages
FIGURE 1. XR16C2550 BLOCK DIAGRAM
A2:A0
D7:D0
*All inputs are 5V tolerant
IOR#
IOW#
UART Channel A
GND
UART
Regs
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
Reset
2.97 V to 5.5V
8- bit Data
Bus
Interface
BRG
16 Byte TX FIFO
TX & RX
TXA , RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
16 Byte RX FIFO
UART Channel B
( same as Channel A )
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
Crystal Osc / Buffer
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
A0
CSA#
10
27
A1
CSB#
11
26
A2
NC
12
25
NC
CTSA#
28
40
9
DSRA#
INTB
OP2B#
CDA#
INTA
29
41
30
8
RIA#
7
TXB
42
TXA
VCC
RXRDYA#
43
31
D5
7
39
RESET
D6
8
38
DTRB#
D7
9
37
DTRA#
RXB
10
36
RTSA#
RXA
11
35
OP2A#
XR16C2550
44-pin PLCC
TXRDYB#
12
34
RXRDYA#
TXA
13
33
INTA
INTB
25
26
27
28
RIB#
RTSB#
CTSB#
24
IOR#
29 A2
DSRB#
17
23
CSB#
RXRDYB#
30 A1
22
16
GND
CSA#
21
31 A0
CDB#
32
15
20
14
IOW#
TXB
OP2B#
XTAL2
19
20
21
22
23
24
IOR#
RIB#
RTSB#
CTSB#
NC
18
RXRDYB#
DSRB#
16
17
IOW#
GND
15
XTAL2
CDB#
13
14
XTAL1
XR16C2550
48-pin TQFP
44
6
TXRDYA#
OP2A#
TXRDYB#
D0
32
1
5
D1
RTSA#
RXA
2
33
D2
4
3
DTRA#
RXB
D3
34
4
3
5
DTRB#
D7
D4
RESET
35
6
36
2
19
37
1
D6
18
CTSA#
NC
38
D5
XTAL1
CDA#
DSRA#
RIA#
41
39
VCC
42
40
D0
TXRDYA#
43
D1
45
44
D3
D2
46
D4
48
47
FIGURE 2. PIN OUT ASSIGNMENT
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING
TEMPERATURE RANGE
DEVICE STATUS
XR16C2550IJ
44-Lead PLCC
-40°C to +85°C
Active
XR16C2550IM
48-Lead TQFP
-40°C to +85°C
Active
2
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
PIN DESCRIPTIONS
Pin Description
NAME
40-PDIP 44-PLCC 48-TQFP
TYPE
PIN #
PIN #
PIN #
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
26
27
28
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO
IOR#
21
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on the
rising edge.
IOW#
18
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
14
16
10
I
UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
CSB#
15
17
11
I
UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
INTA
30
33
30
O
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
INTB
29
32
29
O
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
TXRDYA#
-
1
43
O
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2.
If it is not used, leave it unconnected.
RXRDYA#
-
34
31
O
UART channel A Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel A. See Table 2. If it is
not used, leave it unconnected.
TXRDYB#
-
12
6
O
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See Table 2.
If it is not used, leave it unconnected.
Data bus lines [7:0] (bidirectional).
3
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
Pin Description
NAME
RXRDYB#
40-PDIP 44-PLCC 48-TQFP
TYPE
PIN #
PIN #
PIN #
-
23
DESCRIPTION
18
O
UART channel B Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel B. See Table 2. If it is
not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
11
13
7
O
UART channel A Transmit Data. If it is not used, leave it unconnected.
RXA
10
11
5
I
UART channel A Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
RTSA#
32
36
33
O
UART channel A Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
CTSA#
36
40
38
I
UART channel A Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
DTRA#
33
37
34
O
UART channel A Data-Terminal-Ready (active low) or general purpose output. If it is not used, leave it unconnected.
DSRA#
37
41
39
I
UART channel A Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
CDA#
38
42
40
I
UART channel A Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
RIA#
39
43
41
I
UART channel A Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
OP2A#
31
35
32
O
Output Port 2 Channel A - The output state is defined by the user
and through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic
1. INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTA output functionality. If it is not used at all, leave it unconnected.
TXB
12
14
8
O
UART channel B Transmit Data. If it is not used, leave it unconnected.
RXB
9
10
4
I
UART channel B Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
RTSB#
24
27
22
O
UART channel B Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
CTSB#
25
28
23
I
UART channel B Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
DTRB#
34
38
35
O
UART channel B Data-Terminal-Ready (active low) or general purpose output. If it is not used, leave it unconnected.
4
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
Pin Description
NAME
40-PDIP 44-PLCC 48-TQFP
TYPE
PIN #
PIN #
PIN #
DESCRIPTION
DSRB#
22
25
20
I
UART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
CDB#
19
21
16
I
UART channel B Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
RIB#
23
26
21
I
UART channel B Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
OP2B#
13
15
9
O
Output Port 2 Channel B - The output state is defined by the user
and through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTB is set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTB output functionality. If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
16
18
13
I
Crystal or external clock input.
XTAL2
17
19
14
O
Crystal or buffered clock output.
RESET
35
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter
output will be held at logic 1, the receiver input will be ignored and
outputs are reset during reset period (see External Reset Conditions).
VCC
40
44
42
Pwr 2.97V to 5.5V power supply. All inputs are 5V tolerant.
GND
20
22
17
Pwr Power supply common, ground.
N.C.
-
-
12, 24,
25, 37
No Connection.
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
1.0 PRODUCT DESCRIPTION
The XR16C2550 (2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The 2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-toparallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The 2550 represents such an integration with greatly enhanced features. The 2550 is fabricated with an
advanced CMOS process.
The 2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The 2550 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased performance is realized in the
2550 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the 2550, the data buffer will not require unloading/loading for 1.53 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely
provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The 2550 is capable of operation up to 4 Mbps with a 64 MHz external clock. With a crystal or external clock
input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature set of the 2550 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the 2550 is software compatible with the previous generation, ST16C2450.
6
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2550 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3.
XR16C2550 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
VCC
D0
D1
D2
D3
D4
D5
D6
D7
UART
Channel A
A0
A0
A1
A2
DTRA#
RTSA#
CTSA#
IOR#
CDA#
RIA#
OP2A#
IOR#
IOW#
UART_CSB#
CSA#
CSB#
UART_INTA
INTA
UART_INTB
INTB
UART_CSA#
TXRDYA#
TXRDYA#
RXRDYA#
RXRDYA#
TXRDYB#
TXRDYB#
RXRDYB#
RXRDYB#
UART_RESET
Serial Interface of
RS-232, RS-485
DSRA#
A1
A2
IOW#
VCC
TXA
RXA
TXB
RXB
UART
Channel B
DTRB#
RTSB#
CTSB#
DSRB#
Serial Interface of RS232, RS-485
CDB#
RIB#
OP2B#
RESET
GND
2750int
.
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 11). An active high pulse of at least 40 ns duration will be required to activate the reset
function in the device.
2.3
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1.
TABLE 1: CHANNEL A AND B SELECT
CSA#
CSB#
FUNCTION
1
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
0
Channel A and B selected
7
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.4
REV. 1.0.2
Channel A and B Internal Registers
Each UART channel in the 2550 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.5
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 2550 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see Figures 17 through 22.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.6
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Tables 3and 4summarize the operating behavior for the transmitter and receiver. Also see Figures 17
through 22.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
INTA/B Pin
0 = a byte in THR
1 = THR empty
FCR BIT-0 = 1
(FIFO ENABLED)
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
INTA/B Pin
0 = no data
1 = 1 byte
FCR BIT-0 = 1
(FIFO ENABLED)
0 = FIFO below trigger level
1 = FIFO above trigger level
8
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
2.7
Crystal Oscillator or External Clock Input
The 2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. SEE”PROGRAMMABLE BAUD
RATE GENERATOR” ON PAGE 9.
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
(Optional)
R2
500 Κ Ω − 1 Μ Ω
Y1
C1
C2
22-47 pF
22-47 pF
1.8432 MHz
to
24 MHz
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.8
Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
9
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
External Clock
vcc
XTAL1
gnd
VCC
R1
2K
XTAL2
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
FIGURE 6. OPERATING FREQUENCY VERSUS POWER SUPPLY CHART.
XTAL1 External Clock Frequency in MHz.
Requires a 2K ohms pull-up resistor on XTAL2 pin to increase operating speed
Operating frequency for XR16C2550
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
80
-40oC
25oC
85oC
70
60
50
40
30
3.0 3.5 4.0 4.5 5.0 5.5
Suppy Voltage
10
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
The 2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
153.6k
6
06
00
06
0
230.4k
4
04
00
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0
460.8k
2
02
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921.6k
1
01
00
01
0
2.9
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
16X Clock
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE
Transm it FIFO
Data Byte
THR
THR Interrupt (ISR bit-1) when TX
FIFO becom es em pty. FIFO is
enabled by FCR bit-0=1.
16X Clock
Transm it Data Shift Register
(TSR)
T XFIF O 1
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
12
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
2.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Error
Tags in
LSR bits
4:2
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Data Bit
Validation
Receive Data Characters
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
16 bytes by 11-bit
Error Tags
(16-sets)
wide FIFO
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
RX FIFO
Receive Data
Byte and Errors
Error Tags in
LSR bits 4:2
FIFO is Enabled by FCR bit-0=1
RHR
RXFIFO1
13
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.11
REV. 1.0.2
Internal Loopback
The 2550 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
RXA/RXB
VCC
RTSA#/RTSB#
RTS#
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
MCR bit-4=1
CTS#
CTSA#/CTSB
VCC
DTRA#/DTRB#
DTR#
DSR#
DSRA#/DSRB#
OP1#
RI#
RIA#/RIB#
VCC
OP2A#/OP2B#
OP2#
CD#
CDA#/CDB#
14
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the 2550 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete
register set is shown on Table 6 and Table 7.
TABLE 6: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0 0
DLL - Div Latch Low Byte
Read/Write
LCR[7] = 1
0
0 1
DLM - Div Latch High Byte
Read/Write
LCR[7] = 1
0
0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0
1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
1 1
LCR - Line Control Register
Read/Write
1
0 0
MCR - Modem Control Register
Read/Write
1
0 1
LSR - Line Status Register
Reserved
Read-only
Write-only
1
1 0
MSR - Modem Status Register
Reserved
Read-only
Write-only
1
1 1
SPR - Scratch Pad Register
Read/Write
15
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
.
TABLE 7: INTERNAL REGISTERS DESCRIPTION
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
000
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
000
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
IER
RD/WR
0
0
0
0
Modem RX Line
TX
RX
Stat.
Stat.
Empty
Data
Int.
Int.
Int
Int.
Enable Enable Enable Enable
010
ISR
RD
FIFOs
FIFOs
Enabled Enabled
0
0
INT
INT
INT
INT
Source Source Source Source
Bit-3
Bit-2
Bit-1
Bit-0
010
FCR
WR
RX FIFO RX FIFO
Trigger Trigger
0
0
DMA
Mode
Enable
TX
FIFO
Reset
011
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set Parity
Even
Parity
Parity
Enable
Stop
Bits
100
MCR
RD/WR
0
0
0
Internal
Loopback
Enable
101
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX
Parity
Error
RX
Overrun
Error
RX
Data
Ready
110
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
111
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
RX
FIFO
Reset
LCR[7] = 0
FIFOs
Enable
Word
Word
Length Length
Bit-1
Bit-0
OP2#/ Rsrvd RTS# DTR#
INT
(OP1#) Output Output
Output
Control Control
Enable
Baud Rate Generator Divisor
000
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 1
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 12.
4.2
Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 11.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
16
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C2550 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates Transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
17
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
4.4
REV. 1.0.2
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
]
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
ISR REGISTER STATUS BITS
PRIORITY LEVEL
SOURCE OF INTERRUPT
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
1
0
LSR (Receiver Line Status Register)
2
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
MSR (Modem Status Register)
-
0
0
0
1
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 8).
ISR[5:4]: Reserved
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
18
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
• Logic 0 = Normal Operation (default).
• Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION
4.6
FCR
BIT-7
FCR
BIT-6
RECEIVE
TRIGGER
LEVEL
0
0
1
1
0
1
0
1
1 (default)
4
8
14
COMPATIBILITY
16C550, 16C2552,
16C554, 16C580 compatible.
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
19
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
BIT-2
WORD
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
20
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 10: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2550. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
21
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
MCR[7:5]: Reserved
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error. An interrupt will be generated
immediately if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1. If the LSR interrupt is enabled (IER bit-2), an interrupt will
be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
22
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is
equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when
the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
23
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 9.
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
RESET STATE
DLM
Bits 7-0 = 0xXX
DLL
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
I/O SIGNALS
RESET STATE
TX
Logic 1
OP2#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RXRDY#
Logic 1
TXRDY#
Logic 0
INT
Three-State Condition
24
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
7 Volts
Voltage at Any Pin
GND-0.3 V to VCC+0.3 V
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Package Dissipation
500 mW
PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP)
theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (44-PLCC)
theta-ja = 50oC/W, theta-jc = 21oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC = 2.97V TO 5.5V
SYMBOL
PARAMETER
3.3V
LIMITS
MIN
MAX
5.0V
LIMITS
MIN
MAX
UNITS
CONDITIONS
VILCK
Clock Input Low Level
-0.3
0.6
-0.5
0.6
V
VIHCK
Clock Input High Level
2.4
5.5
3.0
5.5
V
VIL
Input Low Voltage
-0.3
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
5.5
2.2
5.5
V
VOL
Output Low Voltage
0.4
V
V
IOL = 6 mA
V
V
IOL = 4 mA
0.4
VOH
Output High Voltage
2.4
2.0
IIL
Input Low Leakage Current
±10
±10
uA
IOH = -6 mA
IIH
Input High Leakage Current
±10
±10
uA
IOH = -1 mA
CIN
Input Pin Capacitance
5
5
pF
ICC
Power Supply Current
1.3
3
mA
25
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS
TA=-40O TO +85OC, VCC = 2.97V TO 5.5V, 70 PF LOAD WHERE APPLICABLE
PARAMETER
SYMBOL
-
3.3
LIMITS
MIN
MAX
Crystal Frequency
5.0
LIMITS
MIN
MAX
20
17
24
8
UNIT
ns
CLK
Clock Pulse Duration
OSC
External Clock Frequency
TAS
Address Setup Time
5
0
ns
TAH
Address Hold Time
10
5
ns
TCS
Chip Select Width
70*
40
ns
TRD
IOR# Strobe Width
70*
40
ns
TDY
Read or Write Cycle Delay
70*
40
ns
TRDV
Data Access Time
TDD
Data Disable Time
0
TWR
IOW# Strobe Width
40
25
ns
TDS
Data Setup Time
20
15
ns
TDH
Data Hold Time
5
5
ns
30
25
ns
64
35
0
MHz
25
ns
15
ns
TWDO
Delay From IOW# To Output
50
40
ns
TMOD
Delay To Set Interrupt From MODEM
Input
40
35
ns
TRSI
Delay To Reset Interrupt From IOR#
40
35
ns
TSSI
Delay From Stop To Set Interrupt
1
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
40
ns
TSI
Delay From Start To Interrupt
45
40
ns
TINT
Delay From Initial INT Reset To Transmit
Start
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
45
40
ns
TSSR
Delay From Stop To Set RXRDY#
1
1
Bclk
TRR
Delay From IOR# To Reset RXRDY#
45
40
ns
TWT
Delay From IOW# To Set TXRDY#
45
40
ns
TSRT
Delay From Center of Start To Reset
TXRDY#
8
8
Bclk
TRST
Reset Pulse Width
40
N
Baud Rate Divisor
1
Bclk
8
Baud Clock
24
8
40
216-1
1
16X of data rate
26
COMMENTS
ns
216-1
Hz
* 55ns if VCC =
3.3V +10%/-5%
and
TA = 0 to 70oC
(See Figure 12)
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
a
FIGURE 12. AC TIMING VALUES
80
70
70
TCS, TRD, TDY: 3.3V ± 10%
63
60
TCS, TRD, TDY: 3.3V +10%/- 5%
53
48
50
Time (ns)
55
40
40
TWR: 3.3V ± 10%
34
TCS, TRD, TDY: 5V ± 10%
30
27
25
22
26
20
TWR: 5V ± 10%
16
10
0
-40
25
Temperature (deg C)
FIGURE 13. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
27
70
85
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW #
Active
T W DO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
T MOD
T MO D
INT
Active
Active
Active
T RSI
IOR#
Active
Active
Active
T M OD
Change of state
RI#
FIGURE 15. DATA BUS READ TIMING
A0-A2
Valid Address
TAS
TCS
Valid Address
TAS
TAH
TAH
TCS
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TRDV
D0-D7
Valid Data
TDD
TRDV
Valid Data
RDTm
28
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 16. DATA BUS WRITE TIMING
A0-A2
Valid Address
Valid Address
TAS
TAS
TAH
TCS
TAH
TCS
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDH
TDS
TDS
Valid Data
D0-D7
TDH
Valid Data
16Write
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
INT
RXRDY#
Start
Bit
D0:D7
Stop
Bit
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
in RHR
1 Byte
in RHR
1 Byte
in RHR
TSSR
TSSR
Active
Data
Ready
Active
Data
Ready
TRR
TRR
TSSR
Active
Data
Ready
TRR
IOR#
(Reading data
out of RHR)
RXNFM
29
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
Start
Bit
(Unloading)
IER[1]
enabled
Stop
Bit
D0:D7
D0:D7
ISR is read
D0:D7
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S D0:D7
S D0:D7 T
Stop
Bit
D0:D7
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops
below RX
Trigger Level
TSSI
INT
FIFO
Empties
TSSR
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
30
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start
Bit
RX
Stop
Bit
S D0:D7
S D0:D7 T
D0:D7
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops
below RX
Trigger Level
TSSI
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
FIFO
Empties
TSSR
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
Stop
Bit
Start
Bit
S D0:D7 T
(Unloading)
IER[1]
enabled
Last Data Byte
Transmitted
S D0:D7 T S D0:D7 T
T S D0:D7 T S D0:D7 T
S D0:D7 T
TSRT
ISR is read
TX FIFO no
longer empty
INT*
TSI
TWRI
TXRDY#
TX FIFO
Empty
Data in
TX FIFO
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
31
TXDMA#
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
Stop
Bit
Start
Bit
S D0:D7 T
(Unloading)
IER[1]
enabled
Last Data Byte
Transmitted
T S D0:D7 T S D0:D7 T
S D0:D7 T S D0:D7 T
ISR is read
S D0:D7 T
TSRT
TX FIFO no
longer empty
TSI
INT*
TWRI
TX FIFO
Empty
TXRDY#
At least 1
empty location
in FIFO
TX FIFO
Full
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
32
TXDMA
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D1
36
25
24
37
D1
13
48
1
2
1
B
e
A2
C
A
α
Seating
Plane
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.039
0.047
1.00
1.20
A1
0.002
0.006
0.05
0.15
A2
0.037
0.041
0.95
1.05
B
0.007
0.011
0.17
0.27
C
0.004
0.008
0.09
0.20
D
0.346
0.362
8.80
9.20
D1
0.272
0.280
6.90
7.10
e
0.020 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
33
D
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
PACKAGE DIMENSIONS (44 PIN PLCC)
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
Seating Plane
D1
2 1
45° x H2
45° x H1
A2
44
B1
D
D1
B
D3
e
R
D3
A1
A
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.165
0.180
4.19
4.57
A1
0.090
0.120
2.29
3.05
A2
0.020
---
0.51
---
B
0.013
0.021
0.33
0.53
B1
0.026
0.032
0.66
0.81
C
0.008
0.013
0.19
0.32
D
0.685
0.695
17.40
17.65
D1
0.650
0.656
16.51
16.66
D2
0.590
0.630
14.99
16.00
D3
0.500 typ.
12.70 typ.
e
0.050 BSC
1.27 BSC
H1
0.042
0.056
1.07
1.42
H2
0.042
0.048
1.07
1.22
R
0.025
0.045
0.64
1.14
34
D2
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
REVISION HISTORY
Date
Revision
Description
December 2004
1.0.0
Initial Datasheet. This datasheet applies to devices with top mark date code of "B2
YYWW" and newer.
January 2005
1.0.1
Clarified AC Electrical Characteristics.
February 2007
1.0.2
40-pin PDIP package is no longer offered and has been removed from the ordering
information.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet February 2007.
Send your UART technical inquiry with technical details to hotline: [email protected].
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
35
xr
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
5.0 TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16C2550 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................7
2.1 CPU INTERFACE .............................................................................................................................................. 7
FIGURE 3.
XR16C2550 DATA BUS INTERCONNECTIONS ................................................................................................................. 7
2.2 DEVICE RESET ................................................................................................................................................ 7
2.3 CHANNEL A AND B SELECTION .................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 7
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.5 DMA MODE ....................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ............................................................................................. 8
2.6 INTA AND INTB OUTPUTS .............................................................................................................................. 8
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 8
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 8
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS ................................................................................................................................. 9
2.8 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 10
FIGURE 6. OPERATING FREQUENCY VERSUS POWER SUPPLY CHART. ............................................................................................. 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.9 TRANSMITTER ............................................................................................................................................... 11
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ......................................................................................... 11
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE ...................................................................................................................... 12
2.10 RECEIVER .................................................................................................................................................... 12
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 13
FIGURE 10. RECEIVER OPERATION IN FIFO MODE.......................................................................................................................... 13
2.11 INTERNAL LOOPBACK ............................................................................................................................... 14
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 14
3.0 UART INTERNAL REGISTERS ...........................................................................................................15
TABLE 6:
TABLE 7:
UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 15
INTERNAL REGISTERS DESCRIPTION ................................................................................................................... 16
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................16
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 16
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 16
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 16
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 17
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 17
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 18
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 18
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 18
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 18
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 19
TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................................................................................... 19
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 19
TABLE 10: PARITY SELECTION ........................................................................................................................................................ 21
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ...........................................................................................
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE ..............................................
I
21
22
23
24
24
xr
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.0.2
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 24
ABSOLUTE MAXIMUM RATINGS .................................................................................. 25
PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)................ 25
ELECTRICAL CHARACTERISTICS................................................................................ 25
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 25
AC ELECTRICAL CHARACTERISTICS .............................................................................................................. 26
TA=-40o to +85oC, Vcc = 2.97V to 5.5V, 70 pF load where applicable .................................................................... 26
FIGURE 12.
FIGURE 13.
FIGURE 14.
FIGURE 15.
FIGURE 16.
FIGURE 17.
FIGURE 18.
FIGURE 19.
FIGURE 20.
FIGURE 21.
FIGURE 22.
AC TIMING VALUES ..................................................................................................................................................... 27
CLOCK TIMING............................................................................................................................................................. 27
MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 28
DATA BUS READ TIMING .............................................................................................................................................. 28
DATA BUS WRITE TIMING ............................................................................................................................................ 29
RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 29
TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 30
RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 30
RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 31
TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 31
TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 32
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................ 33
PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 34
REVISION HISTORY ............................................................................................................................ 35
5.0 TABLE OF CONTENTS .......................................................................................................................... I
II