Intel® Platform Controller Hub MP30 Datasheet

Intel® Platform Controller Hub MP30
Datasheet
May 2011
Revision 001
Document Number: 325565-001US
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Platform Controller Hub MP30 component may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed
by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
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Intel, Intel® Atom™ Processor Z6xx Series, Intel® Platform Controller Hub MP30, Next-Generation Intel® Atom™ Processorbased Platform, Intel® Smart Sound Technology (Intel® SST), Intel® Smart & Secure Technology (Intel® S&ST), and the Intel
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*Other names and brands may be claimed as the property of others.
Copyright © 2011, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Read
1.1
1.2
1.3
1.4
2
Introduction ............................................................................................................ 11
2.1
Chapter Contents .............................................................................................. 11
2.2
Intel® Platform Controller Hub MP30 Acronyms and Terminology ............................ 11
2.3
Architectural Overview ....................................................................................... 13
2.4
Intel® Platform Controller Hub MP30 Feature Set .................................................. 15
3
Signal Descriptions .................................................................................................. 17
3.1
Chapter Contents .............................................................................................. 17
3.2
Buffer Types and Descriptions ............................................................................. 18
3.3
Intel® Platform Controller Hub MP30 Signal and Pin Descriptions............................. 18
3.3.1 cDMI Interface ....................................................................................... 20
3.3.2 cDVO Interface ...................................................................................... 21
3.3.3 Host Power Management and Clock Interface ............................................. 21
3.3.4 HDMI Interface ...................................................................................... 22
3.3.5 I2C Interface ......................................................................................... 22
3.3.6 MIPI CSI-2 Interface............................................................................... 23
3.3.7 BT.601/BT.656 Interface ......................................................................... 23
3.3.8 Camera Sideband Interface ..................................................................... 24
3.3.9 USB Interface ........................................................................................ 25
3.3.10 SDIO Port 2 Interface ............................................................................. 25
3.3.11 SD/eMMC* Port 0 Interface ..................................................................... 26
3.3.12 SD Port 1 Interface................................................................................. 27
3.3.13 Discrete NAND Flash Interface ................................................................. 27
3.3.14 I2S Interface ......................................................................................... 28
3.3.15 Analog Clock Interface ............................................................................ 28
3.3.16 JTAG Interface ....................................................................................... 29
3.3.17 Reset Out Interface ................................................................................ 29
3.3.18 PMIC Interface ....................................................................................... 30
3.3.19 SPI Port 0 Interface ................................................................................ 31
3.3.20 SPI Port 1 Interface ................................................................................ 31
3.3.21 Scan Matrix Keypad Interface .................................................................. 32
3.3.22 Miscellaneous GPIO Interface ................................................................... 32
3.4
Intel® Platform Controller Hub MP30 Discrete NAND Controller Multiplexing .............. 33
3.4.1 SD Port 1 and Flash Channel 1 Pin Multiplexing .......................................... 33
3.5
Intel® Platform Controller Hub MP30 SPI Slave Pin Exchange.................................. 33
3.5.1 I2S0 Pin Exchange for SPI Slave Functionality ............................................ 33
3.6
Power Rails ...................................................................................................... 34
3.6.1 Power Rail Type ..................................................................................... 34
3.6.2 Power Rail Descriptions ........................................................................... 34
3.7
Serial I/O and GPIO ........................................................................................... 35
4
Electrical Specifications ........................................................................................... 39
4.1
Chapter Contents .............................................................................................. 39
4.2
Intel® Platform Controller Hub MP30 Power Net Characteristics............................... 39
Datasheet
Me First ............................................................................................................ 9
Abstract ............................................................................................................. 9
About the Intel® Platform Controller Hub MP30 Datasheet........................................ 9
Organization of the Intel® Platform Controller Hub MP30 Datasheet........................... 9
Reference Documents .......................................................................................... 9
3
4.3
4.4
Intel®
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
Intel®
Platform Controller Hub MP30 DC Characteristics .........................................41
cDMI/cDVO ............................................................................................41
HDMI ....................................................................................................41
MMC/eMMC* ..........................................................................................42
SD/SDIO ...............................................................................................44
BT.601 and BT.656 .................................................................................46
I2C .......................................................................................................46
I2S .......................................................................................................47
MIPI CSI-2.............................................................................................48
ONFI 1.0 NAND (Flash)............................................................................48
SPI .......................................................................................................50
USB ......................................................................................................51
USB-OTG VBUS Characteristics .................................................................52
Platform Controller Hub MP30 Power Sequencing Timing ...............................52
5
Absolute Maximums and Operating Conditions.........................................................53
5.1
Chapter Contents...............................................................................................53
5.2
Intel® Platform Controller Hub MP30 DC
Absolute Maximum Operating Conditions ..............................................................53
5.3
Thermal Management Acronyms ..........................................................................54
5.4
Intel® Platform Controller Hub MP30
Absolute Maximum Temperature Conditions ..........................................................54
5.5
Intel® Platform Controller Hub MP30 Thermal Characteristics ..................................55
5.6
Intel® Platform Controller Hub MP30 Power Specifications ......................................56
6
Intel® Platform Controller Hub MP30 Pin States ......................................................57
6.1
Chapter Contents...............................................................................................57
6.2
Integrated Pull-Ups and Pull-Downs......................................................................57
7
Mechanical and Package Specifications ....................................................................59
7.1
Chapter Contents...............................................................................................59
7.2
Intel® Platform Controller Hub MP30
Mechanical and Package Acronyms.......................................................................59
7.3
Intel® Platform Controller Hub MP30
Ballout Pin Information .......................................................................................59
7.4
Intel® Platform Controller Hub MP30
Package Specifications........................................................................................70
7.5
Intel® Platform Controller Hub MP30
Package Diagrams .............................................................................................71
7.6
Intel® Platform Controller Hub MP30
Ballout Definition and Signal Locations..................................................................76
4
Datasheet
Figures
2-1
3-1
4-1
4-2
7-1
7-2
7-3
7-4
7-5
7-6
Next-Generation Intel® Atom™ Processor-Based Platform Block Diagram........................ 14
Intel® Platform Controller Hub MP30 Signal Diagram.................................................... 19
eMMC* Bus Signal Levels .......................................................................................... 43
Timing Diagram Data Input/Output Referenced to Clock (Default) .................................. 45
Intel® Platform Controller Hub MP30 (Top View) .......................................................... 71
Intel® Platform Controller Hub MP30 (Bottom View) ..................................................... 72
Intel® Platform Controller Hub MP30 (Side View, Unmounted) ....................................... 73
Intel® Platform Controller Hub MP30 Package (Solder Ball Detail) .................................. 74
Intel® Platform Controller Hub MP30 Package (Underfill Detail)...................................... 74
Intel® Platform Controller Hub MP30 Package (Solder Resist Opening)............................ 75
Tables
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
Intel® Platform Controller Hub MP30 Reference Documents............................................ 9
Acronyms and Terminology ...................................................................................... 11
Intel® Platform Controller Hub MP30 I/O Buffer Characteristics..................................... 18
cDMI Interface Signals............................................................................................. 20
cDVO Interface Signals ............................................................................................ 21
Host Power Management and Clock Interface Signals................................................... 21
HDMI Interface Signals ............................................................................................ 22
I2C Interface Signals ............................................................................................... 22
MIPI CSI-2 Interface Signals .................................................................................... 23
BT.601/BT.656 Interface Signals............................................................................... 23
Camera Side Band Signals ....................................................................................... 24
USB Interface Signals .............................................................................................. 25
SDIO Port 2 Interface Signals ................................................................................... 25
SD/eMMC* Port 0 Interface Signals ........................................................................... 26
Discrete NAND Flash Interface Signals ....................................................................... 27
I2S Interface Signals ............................................................................................... 28
Analog Clock Interface Signals .................................................................................. 28
JTAG Interface Signals............................................................................................. 29
Reset Out Interface Signals ...................................................................................... 29
PMIC Interface Signals............................................................................................. 30
SPI Port 0 Interface Signals...................................................................................... 31
SPI Port 1 Interface Signals...................................................................................... 31
Scan Matrix Keypad Interface Signals ........................................................................ 32
Miscellaneous GPIO Interface Signals......................................................................... 32
SD Port 1 and Flash Channel 1 Pin Multiplexing ........................................................... 33
I2S0 Pin Exchange for SPI Slave Functionality ............................................................ 33
Power Rail Types .................................................................................................... 34
Core and I/O Power Signals...................................................................................... 34
PLL/Bandgap Power and Ground Signals .................................................................... 35
GPIO Alternate Function Mapping .............................................................................. 36
Power Net Characteristics ........................................................................................ 39
cDMI/cDVO DC Characteristics.................................................................................. 41
HDMI DC Characteristics .......................................................................................... 41
MMC Power Supply—High Voltage MultiMediaCard ....................................................... 42
MMC Power Supply—Dual Voltage MultiMediaCard ....................................................... 42
eMMC* Power Supply—High Voltage MultiMediaCard.................................................... 42
eMMC* Capacitance ................................................................................................ 42
eMMC* Push-Pull Mode Bus Signal Level—High Voltage MultiMediaCard .......................... 43
eMMC* Push-Pull Mode Bus Signal Level—Dual Voltage MultiMediaCard .......................... 43
SD/SDIO Threshold Level for High Voltage Range and General Parameters ..................... 44
SD/SDIO Bus Signal Line Load.................................................................................. 45
BT.656 Minimum, Nominal, and Maximum Voltage Parameters...................................... 46
Datasheet
5
4-13 I2C—SDA and SCL I/O Stages for F/S-Mode Devices.....................................................46
4-14 I2S_0 Minimum, Nominal, and Maximum Voltage Parameters ........................................47
4-15 I2S_1 Minimum, Nominal, and Maximum Voltage Parameters ........................................47
4-16 MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage Parameters ...............48
4-17 Recommended Discrete NAND Operating Conditions .....................................................48
4-18 Discrete NAND Interface CMOS DC Parameters ............................................................49
4-19 SPI Master Minimum, Nominal, and Maximum Voltage Parameters .................................50
4-20 SPI Slave Minimum, Nominal, and Maximum Voltage Parameters ...................................50
4-21 USB Low/Full Speed DC Input Characteristics ..............................................................51
4-22 USB High Speed DC Input Characteristics ...................................................................51
4-23 USB Minimum, Nominal, and Maximum Voltage Parameters ..........................................52
5-1 Intel® Platform Controller Hub MP30 Absolute Maximum DC Ratings ..............................53
5-2 Thermal Management Acronyms ................................................................................54
5-3 Intel® Platform Controller Hub MP30 Absolute Maximum Temperature Storage Ratings ....55
5-4 Thermal Characteristics ............................................................................................55
5-5 Thermal Design Power..............................................................................................56
6-1 Default Integrated Pull-Up and Pull-Down Signals ........................................................57
7-1 Mechanical and Package Acronyms ............................................................................59
7-2 Intel® Platform Controller Hub MP30 Ballout
(Sort by Pin Name)...................................................................................................60
7-3 Intel® Platform Controller Hub MP30 Ballout
(Sort by Pin Number) ................................................................................................65
7-4 Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (1–6) ...........................76
7-5 Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (7-13)..........................77
7-6 Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (14–20) .......................78
7-7 Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (21–27) .......................79
6
Datasheet
Revision History
Document
Number
Revision
Number
325565
001
Description
Initial release
Revision Date
May 2011
§§
Datasheet
7
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8
Datasheet
Read Me First
1
Read Me First
1.1
Abstract
The Intel® Platform Controller Hub MP30 Datasheet describes the architecture,
features, buffers, signal descriptions, power management, pin states, operating
parameters, electrical, mechanical, and thermal specifications for the Intel® Platform
Controller Hub MP30.
1.2
About the Intel® Platform Controller Hub MP30
Datasheet
The Intel® Platform Controller Hub MP30 Datasheet is intended for use by hardware
developers that are designing and manufacturing products using the Intel® Platform
Controller Hub MP30.
1.3
Organization of the Intel® Platform Controller
Hub MP30 Datasheet
The Intel® Platform Controller Hub MP30 Datasheet is composed of seven chapters and
is organized as follows:
• Chapter 1—“Read Me First”
• Chapter 2—“Introduction”
• Chapter 3—“Signal Descriptions”
• Chapter 4—“Electrical Specifications”
• Chapter 5—“Absolute Maximums and Operating Conditions”
• Chapter 6—“Intel® Platform Controller Hub MP30 Pin States”
• Chapter 7—“Mechanical and Package Specifications”
Each chapter begins with a chapter contents description. This is high level information
about the subject matter contained within chapter.
Some chapters contain a list of important acronyms and a description of the acronyms
used in the chapter.
1.4
Reference Documents
Table 1-1.
Intel® Platform Controller Hub MP30 Reference Documents (Sheet 1 of 2)
Document
Datasheet
Document Number/Location
Universal Host Controller Interface, Revision 1.1
(UHCI)
http://download.intel.com/technology/
usb/UHCI11D.pdf
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/technology/
usb/ehcispec.htm
Universal Serial Bus Specification (USB), Revision
2.0
http://www.usb.org/developers/docs
9
Read Me First
Table 1-1.
Intel® Platform Controller Hub MP30 Reference Documents (Sheet 2 of 2)
Document
Document Number/Location
On-The-Go Supplement to the USB 2.0 Specification
Rev 1.3
http://www.usb.org/developers/onthego/
SDIO Specification
http://www.sdcard.org/developers/tech/
sdio/sdio_spec/
SD Host Controller Specification
http://www.sdcard.org/developers/tech/
host_controller/simple_spec/
MIPI CSI-2 Specification
http://www.mipi.org/
I2C Bus Specification
http://www.nxp.com/
acrobat_download2/various/I2CBUS.pdf
I2S Bus Specification
http://en-origin.nxp.com/
acrobat_download2/various/I2SBUS.pdf
Intel® Atom™ Processor Z6xx Series Datasheet
325567-0011,2
NOTES:
1.
Contact your Intel representative for the latest revision and document number for this
document.
2.
The Intel® Atom™ processor Z6xx series is also known as Lincroft.
§
10
Datasheet
Introduction
2
Introduction
2.1
Chapter Contents
This chapter contains information about:
• “Intel® Platform Controller Hub MP30 Acronyms and Terminology”
• “Architectural Overview”
• “Intel® Platform Controller Hub MP30 Feature Set”
2.2
Intel® Platform Controller Hub MP30 Acronyms
and Terminology
Table 2-1.
Acronyms and Terminology (Sheet 1 of 2)
Acronym
Datasheet
Description
AMBA
Advanced Microcontroller Bus Architecture
AOAC
Always On, Always Connected
BGA
Ball Grid Array
Bluetooth*, BT
Bluetooth* is a local connectivity wireless protocol. Bluetooth* supports the
transport of unencoded voice signals (that is, wireless headsets). Bluetooth*
basebands typically have a PCM audio interface for the unencoded voice
data and a UART or USB for control, data, and compressed audio (using subband coding).
BT.601/BT.656
ITU-R Recommendation BT.601/BT.656
cDMI
CMOS Direct Media Interface
cDVO
CMOS Display Video Output
CI/CSI
Camera Interface/Camera Sideband Interface
CSB
Camera Side Band signals
eMMC*
Embedded MultiMediaCard
ESSP
Enhanced Synchronous Serial Port
FIPS
Federal Information Processing Standards
GPIO
General Purpose Input Output
GPS
Global Positioning Satellite
HDMI
High Definition Multimedia Interface
Host
This term is used synonymously with the processor.
I2 S
The Inter-IC Sound (I2S) bus is a variant of a general PCM interface in which
the SYNC signal is asserted/deasserted for an entire data word. The signal
toggles high and low to distinguish between left and right signals. I2S is an
industry standard for supporting stereo DACs and comes in many flavors
(differences in clock/data alignment, receive data signal, and so on).
JTAG
Joint Test Action Group
LAN
Local Area Network
TRM
Intel® Platform Controller Hub MP30 Technical Reference Manual
LCD
Liquid Crystal Display
MIPI
Mobile Industry Processor Interface
11
Introduction
Table 2-1.
Acronyms and Terminology (Sheet 2 of 2)
Acronym
12
Description
MIPI CSI-2
Mobile Industry Processor Interface organizations Camera Serial Interface 2
specification
MLC
Multiple Layer Cell
MMC
MultiMediaCard
MSI
Message Signaled Interrupt—MSI is a transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same
path that normally carries read and write commands.
Multi-drop
Indicates that a line goes to several devices on a board. Multi-drop buses
make use of multi-drop lines to provide a data transport between multiple
devices. Output drivers of devices on a multi-drop line often tri-state to
avoid bus contention.
OCP
Open Core Protocol
OCP-IP
Open Core Protocol-International Partnership
OTG
On-The-Go
PCH
Platform Controller Hub
PCM Interface
Basic serial interface providing connectivity processors and audio sources/
sinks. Data format commonly used is PCM though compounded variants are
also used. The simplest PCM interface has lines for CLK, SYNC, TxDATA, and
RxDATA though 6-wire PCM interfaces with rate-independent transmit and
receive subsections are also used. Many variations in PCM interfaces exist
(rising-edge clock versus falling-edge clock, positive polarity SYNC versus
negative polarity SYNC, bit-length SYNC versus word-length SYNC.
PMIC SPI
Power Management Integrated Controller Serial Peripheral Interface
Pulse Code
Modulation (PCM)
Standard technique of representing an audio stream using x-bits sampled
uniformly y times a second. Each sample captures the amplitude of the
signal at that point in time. PCM samples are sent over serial buses between
processors and audio codecs.
RO
Reset Out
SCU
System Controller Unit
SD
Secure Digital Memory Device
SDIO
Secure Digital I/O
SLC
Single Layer Cell
SMK
Scan Matrix Keypad
SoC
System on Chip
SPI
Serial Peripheral Interface
SSP
Synchronous Serial Port
Tri-state
An output is tri-stated when it is not actively driven either high or low.
Output drivers on a serial bus are often tri-stated to allow other devices to
communicate on the same line. The electrical state of such line is
determined by either the output of another driver on the same line (if being
actively driven), by a pull-up/pull-down resistor, or by a weak Keeper.
USB
Universal Serial Bus
UTMI
USB Transceiver Macrocell Interface
Voice codec
A voice codec typically contains one (or more ADCs) and one DAC tailored
for voice-band operation (8 KHz, 16 KHz, and 26 KHz). The voice codec is a
key device during a voice call.
WLAN
Wireless Local Area Network
Datasheet
Introduction
2.3
Architectural Overview
The Next-Generation Intel® Atom™ processor-based platform consists of 3 chips:
• Intel® Atom™ processor Z6xx series with Integrated Graphics and Memory
Controller
• Intel® Platform Controller Hub MP30
• Power Management Integrated Circuit (PMIC)
— The PMIC has power delivery and audio codec features incorporated into its
integrated circuit.
Figure 2-1 is a block diagram that describes the Next-Generation Intel® Atom™
processor-based platform architecture.
The Intel® Platform Controller Hub MP30 is built around the AMBA protocol, an OCP
industry standard for interfaces and interconnects. The Intel® Platform Controller Hub
MP30 is designed to leverage proven functional blocks from the System-on-Chip (SoC)
ecosystem; thus, improving software stability and reducing Time-To-Market (TTM).
To protect personal data and play protected multimedia content, the Intel® Platform
Controller Hub MP30 integrates a cryptographic engine. This engine performs high
speed decryption of protected content and provides storage and management of
cryptographic secret keys. The cryptographic engine also validates software—enabling
secure boot in run-time environments through signed firmware and software modules.
To provide low-cost camera functionality, the Intel® Platform Controller Hub MP30
integrates an image processing array. This array interfaces uses low-cost imaging
sensors to perform image enhancement, color correction, color space, and image size
conversion.
The Intel® Platform Controller Hub MP30 introduces several USB power saving
features. For USB devices inside the box, it supports the USB L1 link state and
deferring. These power saving features provide a low power link state that quiets the
link and the host controller when there are no activities on the USB bus. The Intel®
Platform Controller Hub MP30 also allows the end device to reactivate the link when it
needs attention. This significantly reduces platform power by eliminating USB polling in
an otherwise idle system.
Along with the integrated System Controller Unit (SCU), the Intel® Platform Controller
Hub MP30 introduces the new power state, “Always On, Always Connected” (AOAC).
This new, very low power standby state, uses the System Controller Unit to quickly
awaken the system to respond to system or user events. This provides the perception
to the user that the device is never off and never loses network connectivity—even
while most of the system is in the standby state. This feature allows Next-Generation
Intel® Atom™ processor-based Tablets and Smartphones to have battery standby
times of several days while instantly responding to user requests.
To reduce component count and board space the Intel® Platform Controller Hub MP30
integrates the system clock generation functions for the platform. The Intel® Platform
Controller Hub MP30 also provides voltage control by means of the PMIC to optimize
battery life.
Datasheet
13
Introduction
Figure 2-1.
Next-Generation Intel® Atom™ Processor-Based Platform Block Diagram
Intel® Atom(TM) Processor Z6xx Series
MIPI DSI
Display
IA-32 Core
LVDS
Display
Display
North
Cluster
2D/3D
DDR2/
LLPDDR1Mem
Ctrl
Memory
Power Mgt
HD Video
Decode
DC-DC/LDO
Supplies
Integrated
USB 2.0
Peripherals
USB 2.0
Mini A/B
Connector
USB OTG
Backlight Ctrl
Audio
Engine
Headphone/
Speakers
Li-ion/ Li-poly
Battery
GPIO
I2S X 2
RTC Battery
Buzzer
Audio I2S x2
Codec
cDVO
cDMI
cDVO
HDMI
Image
Sensor
Processor
SRAM
Touchscreen
Battery Chrgr
cDMI
3G
Subsystem
GPIO
PCM
SPI X 3
I2C X 2
SPI
Display
BT.656
MIPI-CSI or
BT.656
Camera
Sensor
NAND Ctrl
ONFI 1.0
MIPI CSI
Interconnect Fabric
LCD
Backlight
Video Encode
System
Controller
GPIO
Clock Gen
KBD
virtRTC
SD/SDIO/MMC
Security
Sensor
Lens Control
Flash Control
Intel® Platform Controller Hub MP30
SPI
PMIC
14
Datasheet
Introduction
2.4
Intel® Platform Controller Hub MP30 Feature Set
The major features of the Intel® Platform Controller Hub MP30 are:
• CMOS Direct Media Interface (cDMI)—Primary link between the Intel® Atom™
Processor Z6xx Series and the Intel® Platform Controller Hub MP30
• CMOS Display Video Output (cDVO)—Secondary video link from the Intel® Atom™
Processor Z6xx Series to the Intel® Platform Controller Hub MP30
• High Definition Multimedia Interface (HDMI)—Primary display/multimedia output
• Discrete NAND Controller—Primary boot device and storage
• Universal Serial Bus (USB) High Speed (HS)—USB HS device interface
• USB On-The-Go (USB-OTG) 2.0—USB host and peripheral file transfer and
synchronization
• Secure Digital Memory Device (SD) and Embedded MultiMediaCard
(eMMC*)—secondary storage
• Secure Digital I/O (SDIO)—Supports wireless communication solutions
• Intel® Smart Sound Technology (Intel® SST)
• Mobile Industry Processor Interface (MIPI) CSI-2 and BT.601/BT.656—Still camera
and video interface
• Serial Interface and General Purpose I/O (GPIO)
— GPIO—Flexible I/O voltage (1.8V, 2.5V, and 3.3V)
— Integrated key pad interface—Supports matrix key pad and Direct Key/
thumbwheel
— I2C—Camera control and sensor interface
— Serial Peripheral Interface (SPI)—Wireless communication and PMIC interface
— Pulse Code Modulation (PCM)—Transfer encoded voice from PMIC to Intel®
Platform Controller Hub MP30 and communication components
— I2S/PCM—Support for audio playback and voice communication
• Integrated Clock Generator—To enhance power management control and reduce
BOM
• Intel® Smart & Secure Technology (Intel® S&ST)—To improve wireless
networking, personal data and platform security
• System Controller Unit (SCU)—Provides platform power management by use of
PMIC and management system standby states
• Comprehensive power management
• SRAM—A 256KB block of SRAM used for system boot code and other functions
when system DRAM (connected to the Intel® Atom™ Processor Z6xx Series) is
unavailable.
— This allows the processor to extend standby time and enhances battery life.
• Integrated Clocking
— BCLK—100 MHz differential
— MIPI CSI-2 Side band clock: 25 MHz
• DFx—Design for Test/Debug
— Boundary Scan
— JTAG access to System Controller Unit (SCU) to support power management
and boot debug
§
Datasheet
15
Introduction
(This page intentionally left blank)
16
Datasheet
Signal Descriptions
3
Signal Descriptions
3.1
Chapter Contents
This chapter contains detailed information about:
• “Buffer Types and Descriptions”
• “Intel® Platform Controller Hub MP30 Signal and Pin Descriptions”
• “Intel® Platform Controller Hub MP30 Discrete NAND Controller Multiplexing”
• “Intel® Platform Controller Hub MP30 SPI Slave Pin Exchange”
• “Power Rails”
• “Serial I/O and GPIO”
Datasheet
17
Signal Descriptions
3.2
Buffer Types and Descriptions
Table 3-1 describes various buffers used on the Intel® Platform Controller Hub MP30.
CMOS18, CMOS25, and CMOS33 buffers are based on the same CMOSXX buffer. The
COMSXX buffer is able to support 1.8V, 2.5V, and 3.3V operation. CMOS18, CMOS25,
and CMOS33 represent the default configuration of the buffer set by the SCU Firmware.
Table 3-1.
Intel® Platform Controller Hub MP30 I/O Buffer Characteristics
Type
CMOS105
1.05V CMOS buffers
CMOS18
CMOS buffers configured for 1.8V operation
CMOS25
CMOS buffers configured for 2.5V operation
CMOS33
CMOS buffers configured for 3.3V operation
CMOSXX
CMOS buffers that can be configured for 3.3V, 2.5V, or 1.8V operation
HDMI
Buffer compatible with differential High Definition Multimedia Interface
MIPI
Buffer compatible with differential Mobile Industry Processor Interface
USB-OTG
USB-HS
A
3.3
Description
USB-On The Go buffer type
USB Hi-speed buffer type
Analog reference or output—May be used as a threshold voltage or for buffer
compensation.
Intel® Platform Controller Hub MP30 Signal and
Pin Descriptions
The Intel® Platform Controller Hub MP30 signal and pin descriptions are arranged in
functional groups according to their associated interface as shown in Table 3-2.
Each signal description table has the following headings:
• Signal/Pin: The name of the signal/pin that supports the interface.
• Dir., Type: The buffer direction and type. Buffer direction can be either Input (I),
Output (O), or I/O (bi-directional). See Table 3-1 for additional definitions of the
different buffer types.
• Power Rail: The power plane used to supply power to that signal. See Table 3-26.
• Reset State: The state of the pin upon exiting Reset.
• Description: A brief explanation of the signal function.
The signals are arranged in functional groups according to their associated interface
(see Figure 3-1).
18
Datasheet
Signal Descriptions
Intel® Platform Controller Hub MP30 Signal Diagram
MIPI_CSI_CLKP
MIPI_CSI_CLKN
MIPI_CSI_DQP[1:0]
MIPI_CSI_DQN[1:0]
MIPI_CSI_RCOMP
BT_CSI_CLK
BT_CSI_HSYNC
BT_CSI_VSYNC
BT_CSI_DATA[9:0]
BT.656
SCLK25
FLASH_TRG
PRE_FLASH_TRG
SNSR_STB
SNSR1_STDBY
SNSR2_STDBY
SNSR_RESET#
SNSR_SS_TRG
Camera
Sideband
I2S_0_CLK
I2S_0_FS
I2S_0_TXD
I2S_0_RXD
I2S_1_CLK
I2S_1_FS
I2S_1_TXD
I2S_1_RXD
I2S Audio
Interface
SPI_0_SS[3:0]
SPI_0_SDO
SPI_0_SDI
SPI_0_CLK
SPI_1_SS[3:0]
SPI_1_SDO
SPI_1_SDI
SPI_1_CLK
USB_DP[2:0]
USB_DN[2:0]
OTG_DP
OTG_DN
OTG_ID
OTG_VBUS
USB_RCOMP
SD0_DATA[7:0]
SD0_CMD
SD0_CLK
SD0_WP
SD0_CD#
SDIO2_DATA[3:0]
SDIO2_CMD
SDIO2_CLK
FLSH_RB[3:0]#
FLSH_CE[3:0]#
FLSH_0_RE#
FLSH_0_CLE
FLSH_0_ALE
FLSH_0_WE#
FLSH_0_WP#
FLSH_0_IO[7:0]
FLSH_1_RE#
FLSH_1_CLE
FLSH_1_ALE
FLSH_1_WE#
FLSH_1_WP#
FLSH_1_IO[7:0]
Datasheet
cDMI
CDMI_TXD[7:0]
CDMI_TXSTB_EVEN#
CDMI_TXSTB_ODD#
CDMI_TXCHAR#
CDMI_TXDPWR#
CDMI_RXD[7:0]
CDMI_RXSTB_EVEN#
CDMI_RXSTB_ODD#
CDMI_RXCHAR#
CDMI_RXDPWR#
CDMI_RCOMP
CDMI_CVREF
CDMI_GVREF
cDVO
CDVO_RXD[5:0]
CDVO_RXSP
CDVO_RXSN
CDVO_VBLNK
CDVO_RXPWR_N
CDVO_STALL_N
CDVO_CVREF
CDVO_GVREF
HDMI
HDMI_DATA[2:0]P
HDMI_DATA[2:0]N
HDMI_CLKP
HDMI_CLKN
HDMI_COMP
HDMI_HPD
MIPI CSI-2
SPI
USB
Intel® Platform Controller Hub
MP30
Figure 3-1.
I2C
Keypad
I2C_2_SCL
I2C_2_SDA
I2C_1_SCL
I2C_1_SDA
I2C_0_SCL
I2C_0_SDA
KP_DKIN[3:0]
KP_MKIN[7:0]
KP_MKOUT[7:0]
PMIC
PWRGOOD
RESET#
PMIC_INTR
VR_COMP
EXIT_STDBY
SPI_2_SS[1:0]
SPI_2_SDO
SPI_2_SDI
SPI_2_CLK
SRFWEN#
HV_RCOMP
PM / Clock /
GPIO
PWRMODE[2:0]
BSEL1
BCLKP
BCLKN
OSC_IN
OSC_OUT
RESET_OUT#
GPIO59
GPIO60
GPIO61
SD Port 0
SDIO Port 2
Discrete
NAND
Flash
JTAG
TEST
TDO
TDI
TMS
TCK
TRST#
19
Signal Descriptions
3.3.1
cDMI Interface
Table 3-2.
cDMI Interface Signals
Signal/Pin
CDMI_TXD[7:0]
CDMI_TXSTB_EVEN#
CDMI_TXSTB_ODD#
CDMI_TXCHAR#
CDMI_TXDPWR#
CDMI_RCOMP
CDMI_CVREF
CDMI_GVREF
CDMI_RXD[7:0]
CDMI_RXSTB_EVEN#
CDMI_RXSTB_ODD#
CDMI_RXCHAR#
CDMI_RXDPWR#
20
Dir.,
Type
I
CMOS105
I
CMOS105
I
CMOS105
I
CMOS105
I
CMOS105
I
A
I
A
I
A
O
CMOS105
O
CMOS105
O
CMOS105
O
CMOS105
O
CMOS105
Power Rail
Description
PWR_DMIDVO
CMOS DMI Receive Data in from the North
Complex
PWR_DMIDVO
CMOS DMI Receive Data Strobe Positive in
from the North Complex
PWR_DMIDVO
CMOS DMI Receive Data Strobe Negative in
from the North Complex
PWR_DMIDVO
CMOS DMI Receive Control for command or
data
PWR_DMIDVO
CMOS DMI Receive Power Management
PWR_DMIDVO
CMOS Resistor Compensation: Connect a
precision ±1% resistor to PWR_DMIDVO input
source. Refer to the Next-Generation Intel®
Atom™ Processor-based Board Design Guide for
specific recommendation.
PWR_DMIDVO
VREF for CDMI Receivers: Connect to
1/2*PWR_DMIDVO resistor divider when CDMI
I/O mode is fused to CMOS mode.
PWR_DMIDVO
VREF for CDMI strobe signals: Connect to
1/2*PWR_DMIDVO resistor divider when CDMI
I/O mode is fused to CMOS mode.
PWR_DMIDVO
CMOS DMI Transmit Data out to North
Complex
PWR_DMIDVO
CMOS DMI Transmit Data Strobe EVEN for
CDMI_RXD[7:0]
PWR_DMIDVO
CMOS DMI Transmit Data Strobe ODD for
CDMI_RXD[7:0]
PWR_DMIDVO
CMOS DMI Control to indicate either command
or data transmits on CDMI_RXD[7:0]
PWR_DMIDVO
CMOS DMI Receive Buffer Power
Management control
Datasheet
Signal Descriptions
3.3.2
cDVO Interface
Table 3-3.
cDVO Interface Signals
Signal/Pin
CDVO_RXD[5:0]
Dir.,
Type
I
CMOS105
I
CDVO_RXSP
CMOS105
I
CDVO_RXSN
CMOS105
O
CDVO_VBLNK
CMOS105
CDVO_RXPWR_N
CDVO_STALL_N
I
CMOS105
O
CMOS105
Power
Rail
Description
PWR_DMIDVO
CMOS Display Link Receive Data
PWR_DMIDVO
CMOS Display Link Data Strobe, Positive
PWR_DMIDVO
CMOS Display Link Data Strobe, Negative
PWR_DMIDVO
CMOS Display Link Vertical Blank
PWR_DMIDVO
CMOS Display Link Receive Power
Management: This active low signal is used to
gate-off Intel® Platform Controller Hub MP30
input sense amps to save power when asserted.
PWR_DMIDVO
External Display Pipe Stall: Indicates the
South Complex can no longer receive display
data from the North Complex.
CDVO_CVREF
A
PWR_DMIDVO
VREF for cDVO Receivers
CDVO_GVREF
A
PWR_DMIDVO
VREF for cDVO strobe signals
3.3.3
Host Power Management and Clock Interface
Table 3-4.
Host Power Management and Clock Interface Signals
Signal/Pin
PWRMODE[2:0]
BSEL1
BCLKP
BCLKN
Datasheet
Dir.,
Type
O
CMOS105
I
CMOS105
O
CMOS105
O
CMOS105
Power Rail
Description
PWR_CPU
CPU PM: Grey-code output to allow processor to
transition properly on power-up.
CPU Clock Select: Host clock frequency select.
PWR_CPU
0 = 100 MHz
1 = Reserved
VCC_HCLK
Positive Host Ref Clock: Based on value of
BSEL1
-0.5% SSC at spread modulation of 32 KHz
VCC_HCLK
Negative Host Ref Clock: Based on value of
BSEL1
-0.5% SSC at spread modulation of 32 KHz
21
Signal Descriptions
3.3.4
HDMI Interface
Table 3-5.
HDMI Interface Signals
Signal/Pin
HDMI_DATA[2:0]P
HDMI_DATA[2:0]N
Dir.,
Type
Power
Rail
O
HDMI
O
HDMI
O
HDMI_CLKP
HDMI
O
HDMI_CLKN
HDMI
HDMIVCC33
Positive TMDS Data: Differential signals for
HDMI
HDMIVCC33
Negative TMDS Data: Differential signals for
HDMI
HDMIVCC33
Positive TMDS Clock: Differential clock output
HDMIVCC33
Negative TMDS Clock: Differential clock output
I
HDMI_COMP
HDMI_RCOMP: Tied to external resistor for
output buffer compensation.
A
I
HDMI_HPD
Description
HDMI Hot Plug Detect: 5V-tolerant hot plug
detect.
CMOSXX
3.3.5
I2C Interface
Table 3-6.
I2C Interface Signals
Dir.,
Type
Power Rail
I2C_0_SCL
I/O
CMOSXX
PWR_KBDMISC
I2C Clock: I2C Serial Clock
I2C_0_SDA
I/O
CMOSXX
PWR_KBDMISC
I2C Data: I2C Serial Data
I2C_1_SCL
I/O
CMOSXX
PWR_CSB
I2C 1 SDATA: This signal defaults to a GPIO. It
can be programmed to be an I2C port to support
imaging/video sensors.
I2C_1_SDA
I/O
CMOSXX
PWR_CSB
I2C 1 SCLK: This signal defaults to a GPIO. It
can be programmed to be an I2C port to support
imaging/video sensors.
I2C_2_SCL
I/O
CMOSXX
PWR_KBDMISC
I2C_2_SDA
I/O
CMOSXX
PWR_KBDMISC
Signal/Pin
22
Description
I2C Clock: I2C Serial Clock
Dedicated for use with the HDMI Interface
I2C Data: I2C Serial Data
Dedicated for use with the HDMI Interface
Datasheet
Signal Descriptions
3.3.6
MIPI CSI-2 Interface
Table 3-7.
MIPI CSI-2 Interface Signals
Signal/Pin
MIPI_CSI_CLKP
MIPI_CSI_CLKN
MIPI_CSI_DQP
Dir.,
Type
I
MIPI
I
MIPI
I
[1:0]
MIPI
MIPI_CSI_DQN
[1:0]
I
MIPI
MIPI_CSI_RCOMP
I
A
Power Rail
Description
VCC12
MIPI Clock: Common to Lanes 0 and 1
VCC12
MIPI Clock: Common to Lanes 0 and 1
VCC12
MIPI Positive Data for Lanes 0 and 1
VCC12
MIPI Negative Data for Lanes 0 and 1
VCC12
MIPI Compensation: Compensation analog pin
for MIPI interface; tie on board to a precision
±1% resistor to VCC12. Refer to the NextGeneration Intel® Atom™ Processor-based
Platform Board Design Guide for specific
recommendations.
3.3.7
BT.601/BT.656 Interface
Table 3-8.
BT.601/BT.656 Interface Signals
Signal/Pin
BT_CSI_CLK
BT_CSI_HSYNC
BT_CSI_VSYNC
BT_CSI_DATA[9:0]
Datasheet
Dir.,
Type
I
CMOSXX
I
CMOSXX
I
CMOSXX
I
CMOSXX
System Rail
Name
Description
PWR_BT
Camera I/F BT.656 Clock Input
PWR_BT
Camera BT.656 Horizontal Synchronization
PWR_BT
Camera BT.656 Vertical Synchronization
PWR_BT
Camera 10b Data Input
23
Signal Descriptions
3.3.8
Camera Sideband Interface
Table 3-9.
Camera Side Band Signals
Signal
SCLK25
Dir.,
Type
O
CMOSXX
Power Rail
PWR_CSB
Description
SCLK25 is a 25 MHz clock supply to camera
Sensor 1 and Sensor 2. The same clock signal
can be shared between the two sensors. The
PLL on the camera sensor uses the SCK25 to
generate the target pixel clock.
Flash Trigger: This signal is asserted by the
Camera Interface in the Intel® Platform
Controller Hub MP30 indicating that a full frame
is about to be captured. The Flash fires when it
detects an assertion of this signal. The signal
deasserts to revert the flash into charge buildup
mode.
FLASH_TRG
O
CMOSXX
PWR_CSB
This signal can be used to control White LEDs.
The assertion of the signal causes the LEDs to
light up, and deassertion of this signal turns the
LEDs off.
The Camera Interface will adjust the pulse width
and timing depending on whether the signal is
driving a Flash or an LED.
For details, refer to the ISP_FLASH register in
the camera chapter of the Intel® Platform
Controller Hub MP30 Technical Reference
Manual.
PRE_FLASH_TRG
SNSR_STB
O
CMOSXX
I
CMOSXX
PWR_CSB
PWR_CSB
Pre Flash Trigger: The Camera Interface
asserts this signal to light up a pilot lamp prior
to firing the flash to support prevent red-eye
reduction.
Sensor Strobe: The Sensor asserts this signal
to indicate the start of a full frame, when it is
configured in the single shot mode, or to
indicate a flash exposed frame for flash
synchronization.
Some sensors may not support this signal, this
signal can be a N/C.
Single shot mode might be supported by the
sensor, but CI will have to synchronize to
BT_CSI_Vsync.
SNSR1_STDBY
O
CMOSXX
PWR_CSB
Sensor Standby 1: This signal is used to
control Sensor 1 Standby power states.
SNSR2_STDBY
O
CMOSXX
PWR_CSB
Sensor Standby 2: This signal is used to
control Sensor 2 Standby power states.
SNSR_RESET#
O
CMOSXX
PWR_CSB
Sensor Reset: This signal is active low and
shared by both sensors.
PWR_CSB
Sensor Single Shot Trigger: This signal is
used to request of the sensor, when configured
in single shot mode, that the next frame (or a
programmable delay later, if provided) be
captured as a full frame.
SNSR_SS_TRG
24
O
CMOSXX
Datasheet
Signal Descriptions
3.3.9
USB Interface
Table 3-10. USB Interface Signals
Signal/Pin
USB_DP[2:0]
USB_DN[2:0]
OTG_DP
OTG_DN
Power Rail
Description
USB 2.0 Data Positive Data (D+): In USB 2.0
mode this is the positive differential data signal.
I/O
VCCA_USB33
USB-HS
VCCA_USB25
I/O
VCCA_USB33
USB-HS
VCCA_USB25
I/O
VCCA_USB33
USB-OTG
VCCA_USB25
I/O
VCCA_USB33
USB-OTG
VCCA_USB25
I
OTG_ID
CMOSXX
I
OTG_VBUS
A
I
USB_RCOMP
3.3.10
Dir.,
Type
A
VCCA_USB33
USB 2.0 Data Negative (D-): In USB 2.0
mode, this is the negative differential data
signal.
OTG Data Positive (D+): OTG port Data
Positive.
OTG Data Negative (D-): OTG port Data
Negative.
ID: Determine the initial port status (master or
slave) to determine the port that owns the
initialization.
n/a
VBUS: Connect to GND.
n/a
Resistor Compensation: Connect to a
precision ±1% resistor to GND. Refer to the
Next-Generation Intel® Atom™ Platform-based
Board Design Guide for specific
recommendation.
SDIO Port 2 Interface
Table 3-11. SDIO Port 2 Interface Signals
Signal/Pin
SDIO2_DATA[3:0]
SDIO2_CMD
SDIO2_CLK
Datasheet
Dir.,
Type
I/O
CMOSXX
I/O
CMOSXX
O
CMOSXX
Power Rail
Description
PWR_SDIO2
SDIO Data: Four bi-directional data signals.
PWR_SDIO2
SDIO CMD: Bi-directional command response
signal.
PWR_SDIO2
SDIO CLK: Active high clock that is CMOS level
and interfaces to internal communication ports.
25
Signal Descriptions
3.3.11
SD/eMMC* Port 0 Interface
Table 3-12. SD/eMMC* Port 0 Interface Signals
Signal/Pin
Dir.,
Type
Power Rail
Description
SD Port Data: By default, after power-up, only
SDIO_DATA[0] is used for data transfer. A wider
data bus can be configured for data transfer.
SD0_DATA[7:0]
I/O
CMOSXX
PWR_SD0
MMC Port Data: These signals operate in pushpull mode. The MMC card includes internal pullups for all data lines. By default, after power-up,
only MMC_DATA[0] is used for data transfer. A
wider data bus can be configured for data
transfer.
SD Port Command: This signal is used for card
initialization and transfer of commands.
SD0_CMD
SD0_CLK
SD0_WP
SD0_CD#
26
I/O
CMOSXX
O
CMOSXX
I
CMOSXX
I
CMOSXX
PWR_SD0
PWR_SD0
PWR_SD0
PWR_SD0
MMC Port Command: This signal is used for
card initialization and transfer of commands. It
has two modes—open-drain for initialization and
push-pull for fast command transfer.
SD Port Clock: With each cycle of this signal a
one-bit transfer on the command and each data
line occurs. It is generated by the Intel®
Platform Controller Hub MP30, at a maximum
frequency of 25 MHz.
MMC Port Clock: With each cycle of this signal
a one-bit transfer on the command and each
data line occurs. It is generated by the Intel®
Platform Controller Hub MP30, at a maximum
frequency of 52 MHz.
SD Port Write Protect: Active high when a
card does not want to accept writes.
MMC Port Write Protect: Active high when a
card is not accepting writes.
SD Port Card Detect: Active low when a card is
present. Floating (pulled high) when a card is
not present. This signal is attached to the SDIO
connector.
MMC Port Card Detect: Active low when a card
is present. Floating (pulled high) when a card is
not present. This signal is attached to the MMC
connector.
Datasheet
Signal Descriptions
3.3.12
SD Port 1 Interface
SD Port 1 is multiplexed with discrete NAND controller port 1. See section Section 3.4.
3.3.13
Discrete NAND Flash Interface
Table 3-13. Discrete NAND Flash Interface Signals
Signal/Pin
FLSH_RB[3:0]#
FLSH_[1:0]_RE#
FLSH_[3:0]_CE#
FLSH_[1:0]_CLE
FLSH_[1:0]_ALE
FLSH_[1:0]_WE#
FLSH_[1:0]_WP#
FLSH_1_IO[7:0]
FLSH_0_IO[7:0]
Datasheet
Dir.,
Type
I
CMOSXX
Power Rail
PWR_FLASH0
O
PWR_FLASH1
CMOSXX
PWR_FLASH0
O
CMOSXX
PWR_FLASH0
O
PWR_FLASH1
CMOSXX
PWR_FLASH0
O
PWR_FLASH1
CMOSXX
PWR_FLASH0
O
PWR_FLASH1
CMOSXX
PWR_FLASH0
O
PWR_FLASH1
CMOSXX
PWR_FLASH0
I/O
CMOSXX
I/O
CMOSXX
Description
NAND FLASH Port Run/Busy#: The Ready/
Busy signal indicates the target status. When
low, the signal indicates that one or more LUN
operations are in progress.
NAND FLASH Port Read Enable: Valid for
Standard Flash ONFI interface. Active low read
enable signal.
NAND FLASH Port Chip Enable: Active low
chip enable signal used to select a target.
NAND FLASH Port Command Latch Enable:
When asserted, the command on FLSH_IO is
latched on the rising edge of FLSH_WE#.
NAND FLASH Port Address Latch Enable:
Address Latch Enable is used to load address
into target. When asserted, the address is
loaded on the rising edge of FLSH_WE#.
NAND FLASH Port Write Enable: Valid only
for Standard Flash ONFI interface. These are
active low write enable signals.
NAND FLASH Port Write Protect: Write
Protect disables the Flash array program and
erase operations.
PWR_FLASH1
NAND FLASH Port Address/Data:
Eight (8)-bit wide bi-directional bus for
transferring address, command, and data to and
from the device. These signals transfer the
upper byte when instantiated in a two x8
configuration at the platform level.
PWR_FLASH0
NAND FLASH Port Address/Data:
Eight (8)-bit wide bi-directional bus for
transferring address, command, and data to and
from the device. These signals transfer the lower
byte when instantiated in a two x8 configuration
at the platform level.
27
Signal Descriptions
3.3.14
I2S Interface
The I2S0 is dedicated for voice call interface and the I2S1 is dedicated for audio/music
playback.
Table 3-14. I2S Interface Signals
Signal/Pin
I2S_0_CLK
I2S_0_FS
I2S_0_TXD
I2S_0_RXD
I2S_1_CLK
I2S_1_FS
I2S_1_TXD
I2S_1_RXD
3.3.15
Dir.,
Type
I/O
CMOSXX
I/O
CMOSXX
O
CMOSXX
I
CMOSXX
I/O
CMOS18
I/O
CMOS18
O
CMOS18
I
CMOS18
Power Rail
Description
PWR_I2S
I2S 0 Clock: This signal can be configured
either as an input or an output. It is configured
as an input to support voice PCM payload.
PWR_I2S
I2S 0 Frame Sync: This signal can be
configured either as an input or an output.
PWR_I2S
I2S 0 Transmit Data: Output data line is
actively driven or tri-state.
PWR_I2S
I2S 0 Receive Data: Input data line
PWR_PMIC
I2S 1 Clock: This signal can be configured
either as an input or an output. it is configured
as an input to support audio PCM payload.
PWR_PMIC
I2S 1 Frame Sync: This signal can be
configured either as an input or an output.
PWR_PMIC
I2S 1 Transmit Data: Output data line is
actively driven or tri-stated.
PWR_PMIC
I2S 1 Receive Data: Input data line
Analog Clock Interface
Table 3-15. Analog Clock Interface Signals
Signal/Pin
OSC_IN
OSC_OUT
28
Dir.,
Type
I
CMOS105
O
CMOS105
Power Rail
Description
VCCAHPLL
Oscillator Input: This signal provides input to
Pierce oscillator from 25-MHz crystal.
VCCAHPLL
Oscillator Output: This is the output of Pierce
oscillator and should be connected to the
crystal.
Datasheet
Signal Descriptions
3.3.16
JTAG Interface
Table 3-16. JTAG Interface Signals
Dir.,
Type
Signal
I
TEST
CMOS105
O
TDO
CMOS105
I
TDI
CMOS105
I
TMS
CMOS105
I
TCK
CMOS105
I
TRST#
3.3.17
CMOS105
Power Rail
Description
PWR_CPU
TEST: When asserted, the component is put into
TEST modes in specific combinations. Keeping
an active high termination is not required.
PWR_CPU
JTAG Test Data Output: This serial output is
for test instruction and data from the test logic.
PWR_CPU
JTAG Test Data Input: This signal receives
serial test instruction and data of test logic.
PWR_CPU
JTAG Test Mode Select: This signal is decoded
by the TAP controller to control test operations.
PWR_CPU
JTAG Test Clock: Clock for the test logic.
PWR_CPU
JTAG Test Reset: Asynchronous initialization of
the TAP controller.
Reset Out Interface
Table 3-17. Reset Out Interface Signals
Signal/Pin
RESET_OUT#
Datasheet
Dir.,
Type
O
CMOS18
Power Rail
Description
PWR_PMIC
RESET_OUT: A programmable delayed reset for
platform components.
29
Signal Descriptions
3.3.18
PMIC Interface
Table 3-18. PMIC Interface Signals
Signal/Pin
PWRGOOD
RESET#
PMIC_INTR
VR_COMP
EXIT_STDBY
SPI_2_SS[1:0]
SPI_2_SDO
SPI_2_SDI
SPI_2_CLK
SRFWEN#
HV_RCOMP
30
Dir.,
Type
I
CMOS18
I
CMOS18
I
CMOS18
I
CMOS18
O
CMOS18
I/O
CMOS18
I/O
CMOS18
I/O
CMOS18
I/O
CMOS18
O
CMOS18
I
A
Power Rail
Description
POWER GOOD: PMIC asserts this signal to
indicate that all initial power rails to the Intel®
Platform Controller Hub MP30 are valid.
PWR_PMIC
Assertion of PWRGOOD also means that
VCCA_OSC has been valid for at least 30 µs. The
Intel® Platform Controller Hub MP30 will remain
off until this signal is asserted.
PWR_PMIC
Active Low Hard Reset for Intel® Platform
Controller Hub MP30: This signal is driven by
the PMIC.
PWR_PMIC
PMIC Interrupt: Active high—Attach this to
PMIC IRQ9.
PWR_PMIC
Voltage Regulator Complete: Active high
indication from the PMIC that the requested
voltage regulation request over SPI has been
completed.
PWR_PMIC
EXIT Standby: When asserted, the PMIC
should exit the AOAC Standby settings for
regulating the platform supplies.
PWR_PMIC
SPI 2 Slave Select(s): The second slave select
is reserved for additional PMIC load.
PWR_PMIC
SPI Port 2 Serial Data Out: Defaults to output
PWR_PMIC
SPI Port 2 Serial Data In: Defaults to input
PWR_PMIC
SPI Port 2 Clock: Defaults to output
PWR_PMIC
Memory Self-Refresh: The Intel® Platform
Controller Hub MP30 asserts this SRFWEN# after
the Intel® Atom™ processor Z6xx series sends
the ACK_S0i3 to force DDR into self-refresh.
n/a
HVIO Buffer RCOMP: Tie to a precision ±1%
resistor to ground—Please refer to the NextGeneration Intel® Atom™ Processor-based
Board Design Guide for specific
recommendations.
Datasheet
Signal Descriptions
3.3.19
SPI Port 0 Interface
Table 3-19. SPI Port 0 Interface Signals
Signal
SPI_0_SS[3:0]
SPI_0_SDO
SPI_0_SDI
SPI_0_CLK
3.3.20
Dir.,
Type
O
CMOSXX
O
CMOSXX
I
CMOSXX
O
CMOSXX
Power Rail
PWR_SPI
Description
SPI 0 Slave Select(s): active low; output from
master
A total of 4 slaves are supported on this SPI
port.
PWR_SPI
SPI Port 0 Serial Data Out: Connects to MOSI
PWR_SPI
SPI Port 0 Serial Data In: Connects to MISO
PWR_SPI
SPI Port 0 Clock: Serial Clock (output from
master)
SPI Port 1 Interface
Table 3-20. SPI Port 1 Interface Signals
Signal
SPI_1_SS[3:0]
SPI_1_SDO
SPI_1_SDI
SPI_1_CLK
Note:
Datasheet
Dir.,
Type
O
CMOSXX
O
CMOSXX
I
CMOSXX
O
CMOSXX
Power Rail
PWR_SPI
Description
SPI_1_Slave Select(s): active low; output
from master
A total of 4 slaves are supported by this SPI
port.
PWR_SPI
SPI Port 1 Serial Data Out: Connects to MOSI
PWR_SPI
SPI Port 1 Serial Data In: Connects to MISO
PWR_SPI
SPI Port 1 Clock: Serial Clock (output from
master)
The SDI/SDO convention requires that the master SDO be connected to the slave SDI,
and the slave SDO be connected to the master SDI.
31
Signal Descriptions
3.3.21
Scan Matrix Keypad Interface
Table 3-21. Scan Matrix Keypad Interface Signals
Dir.,
Type
Signal
I
KP_DKIN[3:0]
CMOSXX
I
KP_MKIN[7:0]
CMOSXX
KP_MKOUT[7:0]
O
CMOSXX
Power Rail
Description
PWR_KBDMISC
Direct Key Inputs:
PWR_KBDMISC
Matrix Key Returns:
PWR_KBDMISC
Matrix Key Output:
NOTE: Some of these pins may also serve as straps for Intel® Reference Board ID. Use with
caution when leveraging Intel designs.
3.3.22
Miscellaneous GPIO Interface
Table 3-22. Miscellaneous GPIO Interface Signals
Signal
GPIO59
Dir.,
Type
I/O
CMOSXX
GPIO60 /
I/O
SPI_IRQ#
CMOSXX
GPIO61
32
I/O
CMOSXX
Power Rail
Description
PWR_KBDMISC
Spare GPIOs: Defaults to GPIO. This pin
shares the power plane with I2C_0.
PWR_KBDMISC
GPIOs: This GPIO is used as SPI_IRQ# for the
communication devices. This pin shares the
power plane with I2C_0.
PWR_KBDMISC
Spare GPIOs: Defaults to GPIO. This pin
shares the power plane with I2C_0.
Datasheet
Signal Descriptions
3.4
Intel® Platform Controller Hub MP30 Discrete
NAND Controller Multiplexing
3.4.1
SD Port 1 and Flash Channel 1 Pin Multiplexing
Table 3-23. SD Port 1 and Flash Channel 1 Pin Multiplexing
SDIO Signal
NAND Flash Signal
Power Well
Pin Count
SD_1_DATA[7:0]
FLSH_1_IO[7:0]
PWR_FLSH1
8
SD_1_CMD
FLSH_1_ALE
PWR_FLSH1
1
SD_1_CLK
FLSH_1_CLE
PWR_FLSH1
1
SD_1_WP
FLSH_1_WP#
PWR_FLSH1
1
SD_1_CD#
FLSH_1_WE#
PWR_FLSH1
1
3.5
Intel® Platform Controller Hub MP30 SPI Slave
Pin Exchange
3.5.1
I2S0 Pin Exchange for SPI Slave Functionality
Table 3-24. I2S0 Pin Exchange for SPI Slave Functionality
Datasheet
I2S0 Signal
SPI Slave Signal
Power Well
Pin Count
I2S_0_CLK
SPI_3_CLK
PWR_I2S
1
I2S_0_SYNC
SPI_3_SS
PWR_I2S
1
I2S_0_TXD
SPI_3_SDI (MISO)
PWR_I2S
1
I2S_0_RXD
SPI_3_SDO (MOSI)
PWR_I2S
1
33
Signal Descriptions
3.6
Power Rails
3.6.1
Power Rail Type
This section defines the power state and power level options.
Table 3-25. Power Rail Types
Rail Type
Description
F
Fixed: Voltage level is fixed—based on I/O family.
AON
Always ON: The voltage level must always be on for the component to
operate safely and reliably.
S
Selectable: Voltage can be selected at the platform level, that is, low-speed
I/O support for 1.8-, 2.5-, and 3.3-Volt levels.
V
Variable: Variable supplies are negotiable supply levels; that is, with SDIO the
specification supports dynamic voltage management and the Intel® Platform
Controller Hub MP30 will support negotiated from 3.3V to 1.8V.
SbF
Selectable but Fixed: I/O family or segment supports multi-termination
levels; however, the current POR platform will only use one “fixed” level. This
reduces electrical validation required at component and platform level.
VbF
Variable but Fixed: I/O family or segment supports variable, multi-term
level; however, the current POR platform will only use one “fixed” level. This
reduces the logic and electrical validation required at component and platform
level.
3.6.2
Power Rail Descriptions
3.6.2.1
Core and I/O Power
This section describes the power signals and power states of each power signal.
Table 3-26. Core and I/O Power Signals (Sheet 1 of 2)
Signal
VCC12
Signal
Group
Description
F, AON
Core/MIPI
1.2V Core and MIPI Supply: Always on, required
for the Intel® Platform Controller Hub MP30 poweron.
Host PM/
PWR_CPU
F
VCC_HCLK
F
Host BCLK
Supply for Host Clock Driver.
VCC_HCLK33
F
Host BCLK
3.3V Supply for Host Clock PLL
PWR_DMIDVO
F
CDMI
1.05V Supply: For cDMI Output Drivers
F, AON
CDMI,
CDVO
1.8V Supply: For cDMI Receive buffer
VCCHDMI
F
HDMI
1.2V HDMI Supply
VCCHDMIBG
F
HDMI
3.3V HDMI Display Bandgap Supply
VCCA_USB33
F
USB OTG
3.3V USB Supply
VCCA_USB25
F
USB
2.5V USB Supply
PWR_ADMIDVO
34
Type
JTAG
1.05V Supply for Host PM and JTAG Signals
Datasheet
Signal Descriptions
Table 3-26. Core and I/O Power Signals (Sheet 2 of 2)
Type
Signal
Group
V
SD/eMMC
Port 0
PWR_SDIO2
VbF
SDIO_2
PWR_FLSH0
S
NAND
PWR_FLSH1
S
NAND,
Storage
Port1
NAND and SDIO/MMC Port 1 Supply: Typically
3.3V or 1.8V.
PWR_BT
SbF
BT.656
BT.656 Camera Interface Supply: Targeted for
2.5V, but 1.8V-operation possible.
PWR_PMIC
SbF
PMIC
PMIC and SPI2 Interface Supply: Powers SPI
interface to PMIC. Required for the Intel® Platform
Controller Hub MP30 power-on.
PWR_I2S
S
I2S_0
I2S_0 (Voice) Interface Supply: Typically 3.3V
or 1.8V
PWR_CSB
S
CSB
PWR_SPI
S
PWR_KBDMISC
S
Signal
PWR_SD0
3.6.2.2
Description
SDIO/MMC Port 0 Supply: Dynamically
negotiated from 3.3V to 1.8V based on the device.
SDIO Supply: Typically 3.3V
NAND Supply: Typically 3.3V or 1.8V.
Camera Sideband Interface Supply: Typically
1.8V.
SPI0, SPI1 SPI Port 0 and Port 1 Supply
KBD,
MISC
Keypad and Miscellaneous GPIO Supply:
Typically 3.3V or 1.8V.
PLL/Bandgap Power and Ground
Table 3-27. PLL/Bandgap Power and Ground Signals
Signal
Type
Signal
Group
Description
Host PM,
3.7
VCCAHPLL
F, AON
VCCADPLL
F, AON
Analog
CLK
Display
PLL
1.2V analog supply for oscillator and host PLL
1.2V dedicated analog supply for display PLL
Serial I/O and GPIO
The Intel® Platform Controller Hub MP30 provides 62 highly-multiplexed General
Purpose I/O (GPIO) pins for use in generating and capturing application-specific input
and output signals. Each pin can be programmed as an output, an input, or as a
bi-directional for certain alternate functions. Refer to Table 3-28 for the default GPIO
usage.
Note:
Datasheet
Refer to the Intel® Platform Controller Hub Technical Reference Manual for the GPIO
pin multiplexing.
35
Signal Descriptions
Table 3-28. GPIO Alternate Function Mapping (Sheet 1 of 2)
GPI
Pin
0
1
2
3
4
Alternate
Function 1 (In)
Alternate
Function 1 (Out)
GPIO[0]
PWRGOOD
GPIO[1]/RESET#
GPIO[2]
PMIC_INTR
GPIO[3]
VR_COMP
GPIO[4]
EXIT_STANDBY
5
GPIO[5]
SPI_2_SS[0]
6
GPIO[6]
SPI_2_SS[1]
7
GPIO[7]
8
GPIO[8]
9
36
Pin Name
SPI_2_SDO
SPI_2_SDI
GPIO[9]
SPI_2_CLK
10
GPIO[10]
SPI_1_SS[0]
11
GPIO[11]
SPI_1_SS[1]
12
GPIO[12]
SPI_1_SS[2]
13
GPIO[13]
SPI_1_SS[3]
14
GPIO[14]
SPI_1_SDO
15
GPIO[15]
16
GPIO[16]
SPI_1_CLK
17
GPIO[17]
SPI_0_SS[0]
18
GPIO[18]
SPI_0_SS[1]
19
GPIO[19]
SPI_0_SS[2]
20
GPIO[20]
SPI_0_SS[3]
21
GPIO[21]
22
GPIO[22]
SPI_1_SDI
SPI_0_SDO
SPI_0_SDI
23
GPIO[23]
24
GPIO[24]
KP_MKIN[0]
SPI_0_CLK
25
GPIO[25]
KP_MKIN[1]
26
GPIO[26]
KP_MKIN[2]
27
GPIO[27]
KP_MKIN[3]
28
GPIO[28]
KP_MKIN[4]
29
GPIO[29]
KP_MKIN[5]
30
GPIO[30]
KP_MKIN[6]
31
GPIO[31]
KP_MKIN[7]
32
GPIO[32]
KP_MKOUT[0]
33
GPIO[33]
KP_MKOUT[1]
34
GPIO[34]
KP_MKOUT[2]
Datasheet
Signal Descriptions
Table 3-28. GPIO Alternate Function Mapping (Sheet 2 of 2)
GPI
Pin
Pin Name
Alternate
Function 1 (In)
Alternate
Function 1 (Out)
35
GPIO[35]
36
GPIO[36]
KP_MKOUT[4]
37
GPIO[37]
KP_MKOUT[5]
38
GPIO[38]
KP_MKOUT[6]
39
GPIO[39]
KP_MKOUT[7]
40
GPIO[40]
KP_DKIN[0]
41
GPIO[41]
KP_DKIN[1]
42
GPIO[42]
KP_DKIN[2]
43
GPIO[43]
KP_DKIN[3]
44
GPIO[44]
SCLK25
45
GPIO[45]
FLASH_TRG
46
GPIO[46]
47
GPIO[47]
48
49
50
51
KP_MKOUT[3]
PRE_LIGHT_TRG
SNSR_STB
GPIO[48]
SNSR_STDBY_1
GPIO[49]
SNSR_STDBY_2
GPIO[50]
SNSR_RESET#
GPIO[51]
SNSR_SS_TRG
52
GPIO[52]
I2C_2_SDA
I2C_2_SDA
53
GPIO[53]
I2C_2_SCL
I2C_2_SCL
54
GPIO[54]
I2C_1_SDA
I2C_1_SDA
55
GPIO[55]
I2C_1_SCL
I2C_1_SCL
56
GPIO[56]
I2C_0_SDA
I2C_0_SDA
57
GPIO[57]
I2C_0_SCL
I2C_0_SCL
58
GPIO[58]
SRFWEN#
59
GPIO[59]
60
GPIO[60]
61
GPIO[61]
§
Datasheet
37
Signal Descriptions
(This page is intentionally left blank)
§§
38
Datasheet
Electrical Specifications
4
Electrical Specifications
4.1
Chapter Contents
This chapter contains information about:
• “Intel® Platform Controller Hub MP30 Power Net Characteristics”
• “Intel® Platform Controller Hub MP30 DC Characteristics”
• “Intel® Platform Controller Hub MP30 Power Sequencing Timing”
4.2
Intel® Platform Controller Hub MP30 Power Net
Characteristics
Table 4-1.
Power Net Characteristics (Sheet 1 of 2)
Power Rail
Parameters
Input
(V)
Tolerance
(%)
Peak
Idle
Sustained
Current
Current
(µA)
(ma)
S0
S0i1
S0i3
VCC12
1.2V Core and MIPI
Supply: Always on,
required for Intel®
Platform Controller
Hub MP30 power-on.
1.2
+5/-5
210
—
ON
ON
ON
PWR_CPU
1.05V Supply for Host
PM and JTAG Signals
1.05
+5/-5
1
0.01
ON
ON
OFF
VCC_HCLK
Supply for Host Clock
Driver.
1.05
+5/-5
4.1
—
ON
ON
OFF
VCC_HCLK33
3.3V Supply for Host
Clock PLL
3.3
+5/-5
1.2
—
ON
ON
ON
PWR_DMIDVO
1.05V Supply for cDMI
Output Drivers
1.05
+5/-5
174
14.7
ON
ON
OFF
PWR_ADMIDVO
1.8V Supply for cDMI
Receivers
1.8
+5/-5
5
0
ON
ON
ON
1.2V Supply DMI
Supply
1.2
+5/-5
13.8
5
ON
ON
ON
VCCHDMI
HDMIVCC3
3.3V HDMI Supply
3.3
+5/-5
—
—
ON
ON
ON
VCCHDMIBG
3.3V HDMI Bandgap
Supply
3.3
+5/-5
3.62
0
ON
ON
ON
VCCA_USB33
3.3V USB Supply
3.3
+5/-5
6
11
ON
ON
ON
VCCA_USB25
2.5V USB Supply
2.5
+5/-5
120
1.72
ON
ON
ON
SDIO/MMC Port 0
Supply: dynamically
negotiated from 3.3V
to 1.8V based on
device type.
1.8
+5/-5
—
—
ON
ON
ON
3.3
+5/-5
7.5
0.03
ON
ON
ON
PWR_SD0
Datasheet
39
Electrical Specifications
Table 4-1.
Power Net Characteristics (Sheet 2 of 2)
Power Rail
Parameters
PWR_SDIO2
SDIO Supply: Typically
3.3V
1.8
PWR_FLSH0
Idle
Peak
Sustained Current
Tolerance
(µA)
Current
(%)
(Contin
(ma)
+5/-5
—
—
3.3
+5/-5
5
0.03
NAND Supply:
Typically 3.3V or 1.8V
1.8
+5/-5
3.3
+5/-5
40
NAND and SDIO/MMC
Port 1 Supply:
Typically 3.3V or 1.8V
1.8
+5/-5
PWR_FLSH1
3.3
PWR_BT
BT.656 Camera
Interface Supply:
Targeted for 2.5V, but
1.8V operation is
possible
PWR_PMIC
PMIC and SPI2
Interface Supply:
Powers SPI interface
to PMIC. Required for
Intel® Platform
Controller Hub MP30
power-on
S0
S0i1
S0i3
ON
ON
ON
ON
ON
ON
ON
ON
ON
0.08
ON
ON
ON
—
—
ON
ON
ON
+5/-5
33
0.08
ON
ON
ON
2.5
+5/-5
—
—
ON
ON
ON
1.8
+5/-5
1
0.01
ON
ON
ON
PWR_I2S
I2S_0 (Voice)
Interface Supply
1.8
+5/-5
—
—
ON
ON
ON
3.3
+5/-5
1
0.02
ON
ON
ON
Camera Sideband
Interface Supply:
Typically 1.8V
1.8
+5/-5
—
—
ON
ON
ON
PWR_CSB
3.3
+5/-5
1
0.01
ON
ON
ON
PWR_SPI
SPI Port 0, Port 1
Supply
1.8
+5/-5
—
—
ON
ON
ON
3.3
+5/-5
5
0.03
ON
ON
ON
1.8
+5/-5
—
—
ON
ON
ON
3.3
+5/-5
1
10
ON
ON
ON
Keyboard and
Miscellaneous GPIO
PWR_KBDMISC
Supply: Typically 3.3V
or 1.8V.
40
Input
(V)
VCCAHPLL
Dedicated analog
supply for oscillator
and host PLL
1.2
+5/-5
10
0.01
ON
ON
ON
VCCADPLL
Dedicated analog
supply for display PLL
1.2
+5/-5
20
0.01
ON
ON
ON
Datasheet
Electrical Specifications
4.3
Intel® Platform Controller Hub MP30 DC
Characteristics
This section documents the DC characteristics of the following Intel® Platform
Controller Hub MP30 signal groups and interfaces.
4.3.1
cDMI/cDVO
Table 4-2.
cDMI/cDVO DC Characteristics
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
CMOS cDMI
VOH
Output High Voltage
0.9*PWR_DMIDVO
PWRDMIDVO
1.1*PWR_DMIDVO
V
VOL
Output Low Voltage
0
0
0.1*PWR_DMIDVO
V
VIH
Input High Voltage
1/2*PWR_DMIDVO+0.1
PWRDMIDVO
PWR_DMIDVO+0.1
V
VIL
Input Low Voltage
-0.1
0
1/2*PWR_DMIDVO -0.1
V
Input Leakage Current
—
—
10
µA
Input Capacitance
—
1.5
—
pF
ILEAK
CIN
4.3.2
HDMI
Table 4-3.
HDMI DC Characteristics
Symbol
Datasheet
Parameter
Minimum
Nominal
Maximum
Unit
AVCC
Nominal High-level
Signal Voltage
—
3.3
—
V
VH
Single-ended Highlevel Output
AVCC – 10mV
—
AVCC + 10mV
V
VL
Single-ended Lowlevel Output
AVCC − 600mV
—
AVCC − 400mV
V
mV
VSWING
Single-ended Output
Swing Voltage
400
—
600
VOFF
Single-ended Standby
(Off) Output Voltage
AVCC − 1V
—
AVCC + 10mV
41
Electrical Specifications
4.3.3
MMC/eMMC*
Table 4-4.
MMC Power Supply—High Voltage MultiMediaCard
Symbol
Table 4-5.
Maximum
Unit
Supply voltage
2.7
3.6
V
VSS
Supply voltage
-0.5
0.5
V
Notes
MMC Power Supply—Dual Voltage MultiMediaCard
Parameter
Minimum
Maximum
Unit
Notes
1.95–2.7V
is not
supported
VDDL
Supply voltage (low voltage range)
1.7
1.95
V
VDDH
Supply voltage (high voltage range)
2.7
3.6
V
Supply voltage
-0.5
0.5
V
VSS
eMMC* Power Supply—High Voltage MultiMediaCard
Symbol
VCC
VCCQ
4.3.3.1
Minimum
VDD
Symbol
Table 4-6.
Parameter
Parameter
Minimum
Maximum
Unit
2.7
3.6
V
Supply voltage (NAND)
Supply voltage (I/O)
1.7
1.95
V
-0.5
0.5
V
1.7
1.95
V
Notes
eMMC* Bus Signal Line Load
The total capacitance CL of each line of the MultiMediaCard bus is the sum of the bus
master capacitance CHOST, the bus capacitance CBUS itself, and the capacitance CCARD
of the card connected to this line,
CL = CHOST+CBUS+CCARD
and requiring the sum of the host and bus capacitances not to exceed 20 pF.
Table 4-7.
eMMC* Capacitance
Symbol
Parameter
Typ.
Max.
Unit
Notes
RCMD
Pull-up resistance for CMD
4.7
—
100
KΩ
to prevent bus
floating
RDAT
Pull-up resistance for DAT
50
—
100
KΩ
to prevent bus
floating
RINT
Internal pull-up resistance
DAT1–DAT7
50
—
150
KΩ
to prevent
unconnected
lines floating
CL
Bus signal line capacitance
—
—
30
pF
Single card
1.7
—
1.95
For MMCmicro
pF
For MMCmobile
and MMCplus
CMICRO
CMOBILE
Single card capacitance
CBGA
Maximum signal line
capacitance
42
Min.
—
—
30
—
7
12
—
—
16
For BGA
nH
fpp
≤ 52 MHz
Datasheet
Electrical Specifications
4.3.3.2
eMMC* Bus Signal Levels
To meet the requirements of the JEDEC specification JESD8-1A, the card input and
output voltages shall be within the following specified ranges for any VDD of the allowed
voltage range.
Table 4-8.
eMMC* Push-Pull Mode Bus Signal Level—High Voltage MultiMediaCard
Symbol
Parameter
Minimum
Maximum
Units
Notes
VOH
Output High Voltage
0.75*VDD
—
V
IOH=–100 µA VDD
minimum
VOL
Output Low Voltage
—
0.125*VDD
V
IOL = 100 µA VDD
minimum
VIH
Input High Voltage
0.625*VDD
VDD+0.3
V
VIL
Input Low Voltage
VSS–0.3
0.25*VDD
V
The definition of the I/O signal levels for the Dual voltage MultiMediaCard changes as a
function of VDD.
• 2.7–3.6V: Identical to the High Voltage MultiMediaCard
• 1.95–2.7V: Undefined. The card is not operating at this voltage range
• 1.70–1.95V: Compatible with EIA/JEDEC Standard “EIA/JESD8-7 Wide Range” as
defined in Table 4-9.
Table 4-9.
eMMC* Push-Pull Mode Bus Signal Level—Dual Voltage MultiMediaCard
Symbol
Parameter
Minimum
Maximum
Units
Notes
VOH
Output High Voltage
VDD–0.2
—
V
IOH = –100 µA
VDD minimum
VOL
Output Low Voltage
—
0.2
V
IOL = 100 µA VDD
minimum
VIH
Input High Voltage
0.7*VDD
VDD+0.3
V
VIL
Input Low Voltage
VSS–0.3
0.3*VDD
V
As the bus can be supplied with a variable supply voltage, all signal levels are related to
the supply voltage.
Figure 4-1.
Datasheet
eMMC* Bus Signal Levels
43
Electrical Specifications
4.3.4
SD/SDIO
Table 4-10. SD/SDIO Threshold Level for High Voltage Range and General Parameters
Symbol
VDD
Parameter
Supply Voltage
Maximum
—
—
2.7
3.6
Units
Notes
V
3.3V input
VOH
Output High Voltage
0.75*VDD
—
V
IOH=–100 µA VDD
minimum
VOL
Output Low Voltage
—
0.125*VDD
V
IOL=100 µA VDD
minimum
VIH
Input High Voltage
0.625*VDD
VDD+0.3
V
VIL
Input Low Voltage
VSS–0.3
0.25*VDD
V
—
250
ms
Peak voltage on all lines
-0.3
VDD + 0.3
V
Input Leakage Current
-10
10
uA
Output Leakage Current
-10
10
uA
Power Up Time
4.3.4.1
Minimum
From 0V to VDD
minimum
SD/SDIO/eMMC* Current Consumption
Current consumption is measured by averaging over one second.
• Before first command: Maximum current is 15 mA
• During initialization: Maximum current is 100 mA
• Operation in Default Mode: Maximum current is 100 mA
• Operation in High Speed Mode: Maximum current is 200 mA
• Operation with other functions: Maximum current is 500 mA.
44
Datasheet
Electrical Specifications
4.3.4.2
SD/SDIO Bus Signal Line Load
The total capacitance of the SD Memory Card bus is the sum of the bus master
capacitance CHOST, the bus capacitance CBUS, and the capacitance CCARD of each
card connected to this line:
Total bus capacitance = CHOST + CBUS + N CCARD
Note:
Where N is the number of connected cards.
Table 4-11. SD/SDIO Bus Signal Line Load
Symbol
RCMD
RDAT
Parameter
Minimum
Maximum
Units
Notes
10
100
KΩ
To prevent bus
floating
Pull-up resistance
One card
CL
Total bus
capacitance for each
signal line
—
40
pF
CCARD
Capacitance of the
card for each signal
pin
—
10
pF
Maximum signal line
inductance
—
16
nH
fPP ≤ 20 MHz
Pull-up resistance
inside card (pin1)
10
90
KΩ
May be used for
card detection
RDAT3
Figure
CHOST+CBUS
shall not exceed
30 pF
4.3.4.3
SD/SDIO Bus Signal Levels
Figure 4-2.
Timing Diagram Data Input/Output Referenced to Clock (Default)
To meet the requirements of JEDEC specifications JESD8-1A and JESD8-7, the card
input and output voltages must be within the specified ranges shown in Table 4-12 for
any VDD of the allowed voltage range.
Datasheet
45
Electrical Specifications
4.3.5
BT.601 and BT.656
Table 4-12. BT.656 Minimum, Nominal, and Maximum Voltage Parameters
Symbol
4.3.6
Parameter
VIH
Input high voltage
Minimum
Nominal
Maximum
Unit
1.26
—
—
V
VIL
Input low voltage
—
—
0.54
V
VOH
Output high voltage
1.62
—
—
V
VOL
Output low voltage
—
—
0.18
V
CIN
Input capacitance
—
—
10
pF
Notes
I2C
Table 4-13. I2C—SDA and SCL I/O Stages for F/S-Mode Devices
Symbol
VIL
VIH
Vhys
Parameter
Standard-Mode
Fast-Mode
Unit
Notes
V
2
−
V
2, 3
0.05 VDD
—
V
0.1 VDD
—
V
Min.
Max.
Min.
- 0.5
0.3 VDD
- 0.5
0.7 VDD
—
0.7 VDD
VDD > 2V
n/a
n/a
VDD < 2V
n/a
n/a
LOW level input voltage:
VDD-related input levels
HIGH level input voltage:
VDD-related input levels
Max.
0.3*
VDD
Hysteresis of Schmidt
trigger inputs:
LOW level output voltage
(open drain or open
collector) at 3 mA sink
current:
46
2
VOL
VDD > 2V
0
0.4
0
0.4
V
VOL3
VDD < 2V
n/a
n/a
0
0.2VDD
V
tof
Output fall time from
VIHmin to VILmax with a
bus capacitance from
10–400 pF
—
250
250
ns
tSP
Pulse width of spikes
which must be
suppressed by the input
filter
n/a
n/a
0
50
ns
Ii
Input current each I/O
pin with an input voltage
between
0.1 VDD and 0.9
VDDmax
-10
10
-10
10
µA
Ci
Capacitance for each I/O
pin
−
10
−
10
pF
20 +
0.1Cb
4, 5
6
Datasheet
Electrical Specifications
NOTES:
1.
VDD refers both to PWR_CSB at 1.8V and to PWR_KBDMISC at either 1.8V or 3.3V.
2.
Devices that use non-standard supply voltages which do not conform to the intended
I2C-bus system levels must relate their input levels to the VDD voltage to which the
pull-up resistors Rp are connected.
3.
Maximum VIH = VDDmax + 0.5V.
4.
Cb = capacitance of one bus line in pF.
5.
The maximum tf for the SDA and SCL bus lines quoted in Table 4-13 (300 ns) is longer
than the specified maximum tof for the output stages (250 ns). This allows series
protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus
lines as shown in Table 4-13 without exceeding the maximum specified tf.
6.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched
off.
4.3.7
I2S
4.3.7.1
I2S_0 (Voice Interface)
Table 4-14. I2S_0 Minimum, Nominal, and Maximum Voltage Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
Notes
I2S_0
VIL
Input Low Voltage
−
−
0.3 *
PWR_I2S
V
1, 4
VIH
Input High Voltage
0.7*PWR_I2S
−
PWR_I2S
V
1, 4
VOL
Output Low Voltage
−
−
0.1
V
2, 4
VOH
Output High Voltage
PWR_I2S–0.1
−
−
V
3, 4
NOTES:
1.
I2S_0 VIL can undershoot -1.0V for periods of <2 ns and I2S_0 VIH can overshoot to a
maximum of 2.8V for periods <2 ns.
2.
IOL = +100 µA
3.
IOH = -100 µA
4.
PWR_I2S = 1.8V, 2.5V, or 3.3V
4.3.7.2
I2S_1 (Audio Interface)
Table 4-15. I2S_1 Minimum, Nominal, and Maximum Voltage Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
Note
I2S_1
VIL
Input Low Voltage
−
1.8
0.3 *
PWR_PMIC
V
1, 4
VIH
Input High Voltage
0.7*PWR_PMIC
−
PWR_PMIC
V
1, 4
VOL
Output Low Voltage
−
−
0.1
V
2, 4
−
−
V
3, 4
VOH
Datasheet
Output High Voltage
PWR_PMIC
–0.1
47
Electrical Specifications
NOTES:
1.
I2S_1 VIL can undershoot -1.0V for periods of <2 ns and I2S_1 VIH can overshoot to a
maximum of 2.8V for periods <2 ns.
2.
IOL = +100 µA
3.
IOH = -100 µA
4.
PWR_PMIC = 1.8V
4.3.8
MIPI CSI-2
Table 4-16. MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage
Parameters
Symbol
Parameter
Min.
Nom.
Max.
Unit
Common-mode voltage HS receive
mode
70
—
330
mV
VIDTH
Differential input high threshold
—
—
70
mV
Notes
MIPI HS-RX
VCMRX(DC)
VIDTL
Differential input low threshold
-70
−
—
mV
VIHHS
Single-ended input high voltage
—
—
460
mV
VILHS
Single-ended input low voltage
-40
−
—
mV
VTERM-EN
Single-ended threshold for HS
termination enable
—
—
450
mV
Differential input impedance
80
100
125
ohm
ZID
MIPI LP-RX
VIH
Logic 1 input voltage
880
−
−
mV
VIL
Logic 0 input voltage, not in ULP state
−
−
550
mV
Logic 0 input voltage, ULP state
−
−
300
mV
Input hysteresis
25
−
−
mV
VIL-ULPS
VHYST
4.3.9
ONFI 1.0 NAND (Flash)
Table 4-17. Recommended Discrete NAND Operating Conditions
Symbol
Minimum
Nominal
Maximum
Unit
VCC33
Supply voltage for 3.3V
devices
2.7
3.3
3.6
V
VCC18
Supply voltage for 1.8V
devices
1.7
1.8
1.95
V
0
0
0
V
VSS
48
Parameter
Supply voltage
Notes
Datasheet
Electrical Specifications
Table 4-18. Discrete NAND Interface CMOS DC Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
Notes
Discrete NAND CMOS3.31
ICC1
Operating current Read
Page with serial access
—
—
50
mA
ICC2
Operating current
Program
—
—
50
mA
ICC3
Operating current Erase
—
v
50
mA
ISB1
Standby current
—
—
1
mA
ISB2
Standby current
—
—
50
µA
ILI
Input Leakage Current
—
—
±10
µA
ILO
Output Leakage Current
—
—
±10
µA
VIH
Input High Voltage
VCC33*0.8
VCC33
VCC33+0.3
V
VIL
Input Low Voltage
-0.3
—
VCC33*0.2
V
VOH
Output High Voltage
VCC33*0.67
—
VOL
Output Low Voltage
—
—
0.1
V
IOL
Output Low Current
8
10
—
mA
—
—
10 per LUN
mA
(R/B#)
IST
(R/B#)
Staggered power-up
current
V
Discrete NAND CMOS1.81
ICC1
Operating current Read
Page with serial access
—
—
50
mA
ICC2
Operating current
Program
—
—
50
mA
ICC3
Operating current Erase
—
—
50
mA
ISB1
Standby current
—
—
1
mA
ISB2
Standby current
—
—
50
µA
ILI
Input Leakage Current
—
—
±10
µA
ILO
Output Leakage Current
—
—
±10
µA
VIH
Input High Voltage
VCC18*0.8
−
VCC18+0.3
V
VIL
Input Low Voltage
-0.3
−
VCC18*0.2
V
VOH
Output High Voltage
VCC18*0.67
—
VOL
Output Low Voltage
—
—
0.1
V
IOL
Output Low Current
3
4
—
mA
—
—
10 per LUN
mA
(R/B#)
IST
(R/B#)
Staggered power-up
current
V
NOTE: 1Flash port 0 operates at 3.3V. Flash port 1/SD port 1 can operate at 3.3V or 1.8V.
Datasheet
49
Electrical Specifications
4.3.10
SPI
Table 4-19. SPI Master Minimum, Nominal, and Maximum Voltage Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
1.57
1.8
1.98
V
2.92
3.3
3.63
Notes
SPI
PWR_SPI
Supply Voltage
VIL
Input Low Voltage
—
—
PWR_SPI*0.30
V
VIH
Input High Voltage
PWR_SPI*0.70
—
—
V
0.1
VOL
Output Low Voltage
—
—
VOH
Output High Voltage
PWR_SPI-0.1
—
IOL
Output Low Current
—
—
3.5
mA
Input Leakage
Current
—
—
1.4
µA
2.0
—
3.4
pF
ILEAK
CIN
Input Capacitance
V
V
Table 4-20. SPI Slave Minimum, Nominal, and Maximum Voltage Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
1.57
1.8
1.98
V
Notes
SPI
VDD
Supply Voltage
VIL
Input Low Voltage
—
—
0.54
V
VIH
Input High Voltage
1.26
—
—
V
VOL
Output Low Voltage
—
—
0.1
V
VOH
Output High Voltage
1.7
—
—
V
IOL
Output Low Current
—
—
3.5
mA
Input Leakage Current
—
—
1.4
µA
2.0
—
3.4
pF
ILEAK
CIN
50
Input Capacitance
Datasheet
Electrical Specifications
4.3.11
USB
Table 4-21. USB Low/Full Speed DC Input Characteristics
Symbol
Parameter
Min.
Max.
Unit
Notes
Input
VDI
Differential Input Sensitivity
0.2
—
V
1, 3, 4
VCM
Differential Common Mode Range
0.8
2.5
V
2, 3, 4
VSE
Single-Ended Receiver Threshold
0.8
2.0
V
3, 4
Output
Vol
Low
0
0.3v
V
VOH
High (Driven)
2.8
3.6
V
VOSE1
SE1
0.8
—
V
VCRS
Output Signal Crossover Voltage
1.3
2.0
V
NOTES:
1.
VDI = |D+ – D-|
2.
Includes VDI range
3.
Applies to Low-Speed/High-Speed USB
4.
Applies OTG_D{P/N} signals that support High/Full/Low and Full Speed modes.
Table 4-22. USB High Speed DC Input Characteristics
Symbol
Parameter
Min.
Max.
Unit
Notes
Input
VHSSQ
HS Squelch Detection Threshold
100
150
mV
Note 1,2
VHSDSC
HS Disconnect Detection Threshold
525
625
mV
Note 1,2
VHSCM
HS Data Signaling Common Mode Voltage
Range
–50
500
mV
Note 1,2
VHSOI
High-speed idle level
-10
10
mV
VHSOH
High-speed data signaling high
260
440
mV
VHSOL
High-speed data signaling low
-10
10
mV
VCHIRPJ
Chirp J level (differential voltage)
700
1100
mV
VCHIRPK
Chirp K level (differential voltage)
-900
-500
mV
Output
NOTES:
1.
Applies to USB_D{P/N}[2:0] that support USB High Speed only.
2.
Applies OTG_D{P/N} signals that support High/Full/Low and Full Speed modes.
Datasheet
51
Electrical Specifications
4.3.12
USB-OTG VBUS Characteristics
The VBus is driven by the PMIC. Refer to the respective PMIC specification for the VBus
characteristics.
Refer to the On-the-Go Supplement to the USB 2.0 Specification Revision 1.3 for
details, refer to:
http://www.usb.org/developers/docs/USB_OTG_1-3.pdf
Table 4-23. USB Minimum, Nominal, and Maximum Voltage Parameters
Symbol
Parameter
Minimum
Nominal
Maximum
Unit
Notes
USB High Speed
Refer to the Universal Serial Bus (USB) Base Specification, Rev. 2.0. Only High-speed signaling
is supported on the USB 2.0 ports. Full-speed and low-speed signaling are not supported on USB
2.0 ports. High speed and full-speed signaling are supported on the USB-OTG ports.
USB-OTG
Refer to the Universal Serial Bus (USB) On the Go Specification, Revision 1.3. Only High-Speed
and Full Speed signaling is supported on the USB-OTG port. Low-speed signaling is not
supported on USB-OTG ports.
4.4
Intel® Platform Controller Hub MP30 Power
Sequencing Timing
Refer to the Briertown Power Management Integrated Circuit (PMIC) Specification for
power-on sequencing timing.
§
52
Datasheet
Absolute Maximums and Operating Conditions
5
Absolute Maximums and
Operating Conditions
5.1
Chapter Contents
This chapter contains information about:
• “Intel® Platform Controller Hub MP30 DC Absolute Maximum Operating Conditions”
• “Intel® Platform Controller Hub MP30 Absolute Maximum Temperature Conditions”
• “Thermal Management Acronyms”
• “Intel® Platform Controller Hub MP30 Thermal Characteristics”
• “Intel® Platform Controller Hub MP30 Power Specifications”
5.2
Intel® Platform Controller Hub MP30 DC
Absolute Maximum Operating Conditions
The maximum DC ratings for the Intel® Platform Controller Hub MP30 are described in
Table 5-1.
Table 5-1.
Datasheet
Intel® Platform Controller Hub MP30 Absolute Maximum DC Ratings
Symbol
Absolute
Minimum
(V)
Absolute
Maximum
(V)
VCC12
-0.3
1.32
PWR_CPU
-0.3
1.15
VCC_HCLK
-0.3
1.15
VCC_HCLK33
-0.3
3.63
PWR_DMIDVO
-0.3
1.15
PWR_ADMIDVO
-0.3
1.98
VCCHDMI
-0.3
1.32
HDMIVCC3
-0.3
3.63
VCCHDMIBG
-0.3
3.63
VCCA_USB33
-0.3
3.63
VCCA_USB25
-0.3
2.75
VCCA_USB12
-0.3
1.32
PWR_SD0
-0.3
3.63
PWR_SDIO2
-0.3
3.63
PWR_FLSH0
-0.3
3.63
PWR_FLSH1
-0.3
3.63
PWR_BT
-0.3
3.63
PWR_PMIC
-0.3
1.98
53
Absolute Maximums and Operating Conditions
Table 5-1.
Intel® Platform Controller Hub MP30 Absolute Maximum DC Ratings
Symbol
Absolute
Minimum
(V)
Absolute
Maximum
(V)
PWR_I2S
-0.3
3.63
PWR_CSB
-0.3
3.63
PWR_SPI0
-0.3
3.63
PWR_SPI1
-0.3
3.63
PWR_KBDMISC
-0.3
3.63
VCCAHPLL
-0.3
1.32
VCCADPLL
-0.3
1.32
5.3
Thermal Management Acronyms
Table 5-2.
Thermal Management Acronyms
Acronym
5.4
Description
Ψjt
Characterization—Juntion-to-top
Θja
Thermal Resistance—Junction-to-ambient
Tdie
Die Junction Operating Temperature
Intel® Platform Controller Hub MP30
Absolute Maximum Temperature Conditions
Table 5-3 lists the Intel® Platform Controller Hub MP30 maximum environmental stress
ratings. Functional operating parameters at the absolute maximum and minimum is
neither implied nor ensured.
The voltage on a specific pin shall be denoted as “V” followed by the subscripted name
of that pin.
Caution:
54
At conditions outside functional operation limits, but within absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected. If a
device is returned to conditions within functional operation limits after having been
subjected to conditions outside these limits, but within the absolute maximum and
minimum ratings, the device may be functional, but with its lifetime degraded
depending on exposure to conditions exceeding the functional operation condition
limits. If the component is exposed to conditions exceeding absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected.
Moreover, if a device is subjected to these conditions for any length of time then, when
returned to conditions within the functional operating condition limits, it will either not
function, or its reliability will be severely degraded. Although the device contains
protective circuitry to resist damage from electro-static discharge, precautions should
always be taken to avoid high static voltages or electric fields.
Datasheet
Absolute Maximums and Operating Conditions
5.5
Intel® Platform Controller Hub MP30 Thermal
Characteristics
Table 5-3.
Intel® Platform Controller Hub MP30 Absolute Maximum Temperature
Storage Ratings
Parameter
Description/
Signal Names
Minimum
Maximum
Tstorage (mounted)
Storage Temperature
-40
85
Tstorage (un-mounted)
Storage Temperature
-25
85
Unit
ºC
The thermal resistance of the package is provided in Table 5-4. Package thermal
resistance is the measure of the package heat dissipation capability from the die active
surface (junction) to a specified reference point (for example; case, board, ambient,
and so forth).
Table 5-4.
Thermal Characteristics
Symbol
Ψjt
Parameter
Characterization
Junction-to-top
Θja
Thermal Resistance
Junction-to-ambient
Tdie
Die Junction Operating
Temperature
Minimum
Nominal
Maximum
Units
Notes
—
3.0
—
ºC/
Watt
1
—
32
—
ºC/
Watt
1
-25
—
90
ºC
2, 3
NOTES:
1.
Functionality is not ensured for parts that exceed Tdie temperature above 90º C. Tdie is
measured at the top center of the package. Full performance may be affected if the on-die
thermal sensor is enabled.
2.
Possible damage to the system controller hub may occur if the Intel® Platform Controller
Hub MP30 storage temperature exceeds Tstorage (mounted) or Tstorage (un-mounted). Intel
does not ensure functionality for parts that have exceeded storage temperatures due to
specification violation.
3.
Storage temperature is applicable to storage conditions only. In this scenario, the device
must not receive a clock, and no pins can be connected to a voltage bias. Storage within
these limits will not effect the long-term reliability of the device. This rating applies to the
silicon and does not include any tray or packaging.
4.
In addition to this storage temperature specification, compliance to the latest
IPC/JEDEC J-STD-033B.1 joint industry standard is required for all Surface Mount Devices
(SMDs). This document governs handling, packing, shipping and use of moisture/reflow
sensitive SMDs.
Datasheet
55
Absolute Maximums and Operating Conditions
5.6
Intel® Platform Controller Hub MP30 Power
Specifications
Table 5-5.
Thermal Design Power
Symbol
TDP
Parameter
Thermal Design Power
(under nominal voltages)
Value
Units
0.7
W
Notes
§
56
Datasheet
Intel® Platform Controller Hub MP30 Pin States
6
Intel® Platform Controller Hub
MP30 Pin States
6.1
Chapter Contents
This chapter describes the default integrated pull-ups and pull-downs in the Intel®
Platform Controller Hub MP30.
6.2
Integrated Pull-Ups and Pull-Downs
Table 6-1.
Default Integrated Pull-Up and Pull-Down Signals (Sheet 1 of 2)
Signal/Pin
Resistor
Nominal
Tolerance
SDIO2_CMD
Pull-up
75 KΩ
±30%
SDIO2_DATA[3:0]
Pull-up
75 KΩ
±30%
SDIO2_CLK
disable
n/a
SDIO Port 2
SD Port 0
SD0_CMD
Pull-up
75 KΩ
±30%
SD0_WP
Pull-up
75 KΩ
±30%
SD0_CD#
Pull-up
75 KΩ
±30%
SD0_DATA[7:0]
Pull-up
75 KΩ
±30%
SD0_CLK
disable
n/a
Discrete NAND Flash Interface
FLSH_RB[3:0]#
Pull-up
75 KΩ
±30%
FLSH_[1:0]_RE#
Pull-up
75 KΩ
±30%
FLSH_[3:0]_CE#
Pull-up
75 KΩ
±30%
FLSH_[1:0]_CLE
Pull-down
75 KΩ
±30%
FLSH_[1:0]_ALE
Pull-down
75 KΩ
±30%
FLSH_[1:0]_WE#
Pull-up
75 KΩ
±30%
FLSH_[1:0]_WP#
Pull-up
75 KΩ
±30%
FLSH_[1:0]_IO[7:0]
disable
n/a
SPI1
SPI_1_SS[3:0]
Pull-up
75 KΩ
±30%
SPI_1_SDO
Pull-down
75 KΩ
±30%
SPI_1_SDI
Pull-down
75 KΩ
±30%
SPI_1_CLK
Pull-down
75 KΩ
±30%
SPI0
SPI_0_SS[3:0]
Datasheet
Pull-up
75 KΩ
±30%
SPI_0_SDO
Pull-down
75 KΩ
±30%
SPI_0_SDI
Pull-down
75 KΩ
±30%
SPI_0_CLK
Pull-down
75 KΩ
±30%
57
Intel® Platform Controller Hub MP30 Pin States
Table 6-1.
Default Integrated Pull-Up and Pull-Down Signals (Sheet 2 of 2)
Signal/Pin
Resistor
Nominal
Tolerance
Pull-down
2 KΩ
±30%
KP_MKOUT[7:0]
disable
n/a
KP_DKIN[3:0]
disable
n/a
Pull-down
20 KΩ
±30%
Keypad
KP_MKIN[7:0]
Camera Sideband/I
SCLK25
2C
FLASH_TRG
Pull-down
20 KΩ
±30%
PRE_FLASH_TRG
Pull-down
20 KΩ
±30%
disable
n/a
SNSR1_STDBY
Pull-down
20 KΩ
±30%
SNSR2_STDBY
Pull-down
20 KΩ
±30%
SNSR_RESET#
Pull-up
20 KΩ
±30%
SNSR_SS_TRG
Pull-up
20 KΩ
±30%
I2C_2_SDA
Pull-up
20 KΩ
±30%
I2C_2_SCL
Pull-up
20 KΩ
±30%
I2C_1_SDA
Pull-up
20 KΩ
±30%
I2C_1_SCL
Pull-up
20 KΩ
±30%
I2C_0_SDA
Pull-up
20 KΩ
±30%
I2C_0_SCL
Pull-up
20 KΩ
±30%
Pull-up
20 KΩ
±30%
SNSR_STB
Spare GPIOs
GPIO[61:59]
Parallel Camera Interface
BT_CSI_CLK
disable
n/a
BT_CSI_HSYNC
disable
n/a
BT_CSI_VSYNC
disable
n/a
BT_CSI_DATA_0
disable
n/a
I2S_1_TXD
Pull-down
75 KΩ
I2S_1_RXD
disable
n/a
I2S_1_SYNC
disable
n/a
I2 S
Note:
I2S_1_CLK
disable
n/a
I2S_0_TXD
Pull-down
75 KΩ
I2S_0_RXD
disable
n/a
I2S_0_SYNC
disable
n/a
I2S_0_CLK
disable
n/a
±30%
±30%
The default Intel® Plaform Controller Hub MP30 integrated pull-up and pull-down
signals are based on Intel® Platform Controller Hub MP30 I/O configuration registers,
as set by the SCU Firmware. For more information about these registers, refer to the
Intel® Platform Controller Hub MP30 Technical Reference Manual, Chapter 5—General
Purpose I/O.
§
58
Datasheet
Mechanical and Package Specifications
7
Mechanical and Package
Specifications
7.1
Chapter Contents
This chapter contains information about:
• “Intel® Platform Controller Hub MP30 Mechanical and Package Acronyms”
• “Intel® Platform Controller Hub MP30 Ballout Pin Information”
• “Intel® Platform Controller Hub MP30 Package Specifications”
• “Intel® Platform Controller Hub MP30 Package Diagrams”
• “Intel® Platform Controller Hub MP30 Ballout Definition and Signal Locations”
7.2
Intel® Platform Controller Hub MP30
Mechanical and Package Acronyms
Table 7-1. Mechanical and Package Acronyms
Acronym
7.3
Description
BGA
Ball Grid Array
BO
Ball Out
DO
Die Outline
PL
Pin List
Intel® Platform Controller Hub MP30
Ballout Pin Information
Table 7-2 lists the Intel® Platform Controller Hub MP30 ballout information arranged
alphabetically by signal name. Table 7-3 lists the ballout arranged numerically by pin
number. Figure 7-4 through Figure 7-7 show the ballout map as viewed from the top of
the package.
Datasheet
59
Mechanical and Package Specifications
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 1 of 14)
Pin Name
BCLKN
60
Pin #
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 2 of 14)
Pin Name
Pin #
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 3 of 14)
Pin Name
Pin #
E7
CDMI_TXD6
E10
FLSH_1_IO1
H20
BCLKP
E6
CDMI_TXD7
A10
FLSH_1_IO2
H21
BSEL1
E21
CDMI_TXDPWR#
B11
FLSH_1_IO3
H22
BT_CSI_CLK
AB19
CDMI_TXSTB_EVEN#
A6
FLSH_1_IO4
G22
BT_CSI_DATA 0
AA16
CDMI_TXSTB_ODD#
E8
FLSH_1_IO5
G23
BT_CSI_DATA 1
Y16
CDVO_CVEF
G18
FLSH_1_IO6
F24
BT_CSI_DATA 2
AB17
CDVO_GVREF
H16
FLSH_1_IO7
D25
BT_CSI_DATA 3
AC17
CDVO_TXD0
D17
FLSH_1_RE#
K22
BT_CSI_DATA 4
AC18
CDVO_TXD1
G16
FLSH_1_WE#
F23
BT_CSI_DATA 5
AF19
CDVO_TXD2
E18
FLSH_1_WP#
G20
BT_CSI_DATA 6
AC20
CDVO_TXD3
B19
FLSH_2_CE#
K25
BT_CSI_DATA 7
AG20
CDVO_TXD4
A18
FLSH_3_CE#
J26
BT_CSI_DATA 8
AE20
CDVO_TXD5
F18
FLSH_RB0#
E26
BT_CSI_DATA 9
AF22
CDVO_TXSN
B17
FLSH_RB1#
F25
BT_CSI_HSYNC
AB18
CDVO_TXSP
E16
FLSH_RB2#
F27
BT_CSI_VSYNC
G26
AA18
CDVO_TXPWR_N
D19
FLSH_RB3#
CDMI_CVREF
G10
CDVO_STALL_N
H15
GPIO59
T3
CDMI_GVREF
H12
CDVO_VBLNK
D15
GPIO60
T1
CDMI_RCOMP
F10
EXIT_STDBY
M1
GPIO61
P1
CDMI_RXCHAR#
A16
FLASH_TRG
AD5
HDMI_CLK_DN
AG12
CDMI_RXD0
D11
FLSH_0_ALE
M21
HDMI_CLK_DP
AE12
CDMI_RXD1
A12
FLSH_0_CE#
H27
HDMI_HOTPLUG
AC16
CDMI_RXD2
F14
FLSH_0_CLE
K27
HDMICOMP
AB12
CDMI_RXD3
E12
FLSH_0_IO0
M25
HDMIDATA0_DN
AA12
CDMI_RXD4
B13
FLSH_0_IO1
L26
HDMIDATA0_DP
Y12
CDMI_RXD5
G14
FLSH_0_IO2
M27
HDMIDATA1_DN
AB14
CDMI_RXD6
A14
FLSH_0_IO3
N26
HDMIDATA1_DP
AB13
CDMI_RXD7
D13
FLSH_0_IO4
P20
HDMIDATA2_DN
AC14
CDMI_RXDPWR#
F16
FLSH_0_IO5
P21
HDMIDATA2_DP
AC13
CDMI_RXSTB_EVEN#
E14
FLSH_0_IO6
P22
HDMIVCC3
Y10
CDMI_RXSTB_ODD#
B15
FLSH_0_IO7
R20
HDMIVCC3
AA10
CDMI_TXCHAR#
H13
FLSH_0_RE#
H25
HV_RCOMP
K3
CDMI_TXD0
F12
FLSH_0_WE#
M22
I2C_0_SCL
T6
CDMI_TXD1
B7
FLSH_0_WP#
M23
I2C_0_SDA
T5
CDMI_TXD2
D9
FLSH_1_ALE
D23
I2C_1_SCL
AC5
CDMI_TXD3
A8
FLSH_1_CE#
K23
I2C_1_SDA
AB5
CDMI_TXD4
B9
FLSH_1_CLE
D24
I2C_2_SCL
P3
CDMI_TXD5
G12
FLSH_1_IO0
C24
I2C_2_SDA
P5
Datasheet
Mechanical and Package Specifications
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 4 of 14)
Pin Name
Pin Name
Pin #
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 6 of 14)
Pin Name
Pin #
I2S_0_CLK
Y21
OTG_DP
AA26
RESERVED1
AG4
I2S_0_RXD
AF23
OTG_ID
Y22
RESERVED10
AF9
I2S_0_SYNC
AB22
OTG_VBUS
Y25
RESERVED11
AG10
I2S_0_TXD
AA20
PMIC_INTR
P8
RESERVED12
AG8
I2S_1_CLK
AC22
PRE_FLASH_TRG
AA8
RESERVED13
AF7
I2S_1_RXD
AG22
PWR_ADMIDVO
K10
RESERVED14
AC10
I2S_1_SYNC
AE22
PWR_BT
V17
RESERVED15
AG6
I2S_1_TXD
AB20
PWR_CPU
K18
RESERVED16
AF5
KP_DKIN0
AB4
PWR_CSB
V10
RESERVED17
AE8
KP_DKIN1
AC4
PWR_DMIDVO
J11
RESERVED18
AE10
KP_DKIN2
AC2
PWR_DMIDVO
J2
RESERVED2
AG2
KP_DKIN3
Y7
PWR_DMIDVO
J4
RESERVED3
D1
KP_MKIN0
V8
PWR_DMIDVO
K12
RESERVED32
AA14
KP_MKIN1
AB3
PWR_DMIDVO
K15
RESERVED33
AB10
KP_MKIN2
AB1
PWR_DMIDVO
K16
RESERVED34
AA10
KP_MKIN3
Y6
PWR_FLSH0
M20
RESERVED35
Y10
KP_MKIN4
AA2
PWR_FLSH0
N17
RESERVED4
B1
KP_MKIN5
Y5
PWR_FLSH0
N19
RESERVED5
B5
KP_MKIN6
Y3
PWR_FLSH1
K20
RESERVED6
D4
KP_MKIN7
V7
PWR_FLSH1
K21
RESERVED7
AA23
KP_MKOUT0
V6
PWR_FLSH1
L17
RESERVED8_NCTF
A27
KP_MKOUT1
Y1
PWR_FLSH1
L19
RESERVED9_NCTF
AG1
KP_MKOUT2
V3
PWR_I2S
V20
RESET_OUT#
L2
KP_MKOUT3
V5
PWR_KBDMISC
R10
RESET#
P7
KP_MKOUT4
T8
PWR_KBDMISC
U10
SCLK25
AC7
KP_MKOUT5
V1
PWR_PMIC
N9
SD0_CD#
Y23
KP_MKOUT6
U2
PWR_SD0
R17
SD0_CLK
W24
KP_MKOUT7
T7
PWR_SD0
R18
SD0_CMD
W26
MIPI_CSI_CLKN
AE16
PWR_SD0
T20
SD0_DATA0
T23
MIPI_CSI_CLKP
AG16
PWR_SD0
T21
SD0_DATA1
T22
MIPI_CSI_DQN0
AG14
PWR_SDIO2
P18
SD0_DATA2
V27
MIPI_CSI_DQN1
AG18
PWR_SPI0
L9
SD0_DATA3
U26
MIPI_CSI_DQP0
AE14
PWR_SPI1
L10
SD0_DATA4
V25
MIPI_CSI_DQP1
AE18
PWRGOOD
P6
SD0_DATA5
V24
MIPI_CSI_RCOMP
AB16
PWRMODE0
E22
SD0_DATA6
Y27
G8
PWRMODE1
A22
SD0_DATA7
V23
F7
PWRMODE2
B23
SD0_WP
V22
PWR_DMIDVO
J14
SDIO2_CLK
T25
OSC_IN
OSC_OUT
OTG_DN
Datasheet
Pin #
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 5 of 14)
AB27
61
Mechanical and Package Specifications
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 7 of 14)
Pin Name
Pin #
Pin Name
SDIO2_CMD
R26
USB_DN2
SDIO2_DAT0
P25
SDIO2_DAT1
P23
SDIO2_DAT2
P27
SDIO2_DAT3
T27
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 9 of 14)
Pin #
Pin Name
Pin #
AD24
VSS
AB21
USB_DP0
AC26
VSS
AB7
USB_DP1
AD25
VSS
AC19
USB_DP2
AE24
VSS
AC21
USB_RCOMP
AB24
VSS
AC23
SNSR_RESET#
Y8
VCC_HCLK
D3
VSS
AC9
SNSR_SS_TRG
AD4
VCC_HCLK33
D5
VSS_NCTF
AD1
SNSR_STB
AE4
VCC12
P14
VSS
AD11
SNSR1_STDBY
AB6
VCC12
R12
VSS
AD13
SNSR2_STDBY
AC6
VCC12
R15
VSS
AD15
F1
VCC12
V13
VSS
AD17
SPI_0_SDI
K7
VCC12
V15
VSS
AD19
SPI_0_SDO
H5
VCC12
Y18
VSS
AD21
SPI_0_SS0
H3
VCC25
L12
VSS
AD23
SPI_0_SS1
H1
VCCA_USB25
U18
VSS_NCTF
AD27
SPI_0_SS2
K5
VCCA_USB25
U20
VSS
AD3
SPI_0_SS3
K6
VCCA_USB33
Y20
VSS
AD7
SPI_1_CLK
F5
VCCADPLL
AE6
VSS
AD9
SPI_1_SDI
H7
VCCAHPLL
H8
VSS_NCTF
AF1
SPI_1_SDO
F4
VCCHDMI
Y14
SPI_1_SS0
E2
VCCHDMIBG
SPI_1_SS1
H6
VR_COMP
SPI_1_SS2
F2
VSS
SPI_1_SS3
K8
VSS_NCTF
SPI_2_CLK
M7
SPI_2_SDI
M8
SPI_2_SDO
M6
SPI_2_SS0
M3
SPI_2_SS1
M5
K1
SPI_0_CLK
SRFWEN#
VSS_NCTF
AF2
AB11
VSS
L20
N2
VSS
L21
L11
VSS
L22
AG27
VSS
L23
VSS_NCTF
A2
VSS
L24
VSS_NCTF
A24
VSS
L4
VSS_NCTF
A26
VSS
L5
VSS_NCTF
A4
VSS
L6
VSS
AA11
VSS
L7
VSS
AA13
VSS
L8
N10
TCK
H18
VSS
AA17
VSS
TDI
D21
VSS
AA19
VSS
N11
TDO
H19
VSS
AA22
VSS
N12
TEST
B21
VSS
AA24
VSS
N13
TMS
A20
VSS
AA4
VSS
N14
E20
VSS
AA5
VSS
N15
N16
N18
TRST#
62
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 8 of 14)
USB_DN0
AB25
VSS
AA6
VSS
USB_DN1
AC24
VSS
AA9
VSS
Datasheet
Mechanical and Package Specifications
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 10 of 14)
Pin Name
Pin #
Pin Name
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 12 of 14)
Pin #
Pin Name
Pin #
VSS
N20
VSS
E15
VSS
V11
VSS
N21
VSS
E17
VSS
V12
VSS
N22
VSS
E19
VSS
V14
VSS
N24
VSS
E23
VSS
V16
VSS
N4
VSS
E24
VSS
V18
VSS
N5
VSS
E4
VSS
V19
VSS
N6
VSS
E5
VSS
V21
VSS
N7
VSS
E9
VSS
W2
VSS
N8
VSS
F11
VSS
W20
VSS
P11
VSS
F13
VSS
W21
VSS
P12
VSS
F15
VSS
W22
VSS
P16
VSS
F17
VSS
W23
VSS
R13
VSS
F19
VSS
W4
VSS
R2
VSS
F20
VSS
W5
VSS
R21
VSS
F21
VSS
W6
VSS
R22
VSS
R4
VSS
AA15
VSS
R24
VSS
R5
VSS
AB15
VSS_NCTF
AF26
VSS
R6
VSS
AC12
VSS_NCTF
AF27
VSS
R7
VSS
AC15
VSS_NCTF
AG25
VSS
R8
VSS
AC8
VSS_NCTF
AG26
VSS
T11
VSS
AF11
VSS_NCTF
B2
VSS
T13
VSS
AF13
VSS_NCTF
B26
VSS
T15
VSS
AF15
VSS_NCTF
B27
VSS
T17
VSS
AF17
VSS
C10
VSS
T19
VSS
F22
VSS
C12
VSS
U12
VSS
F8
VSS
C14
VSS
U14
VSS
F9
VSS
C16
VSS
U16
VSS
G11
VSS
C18
VSS
U21
VSS
G13
VSS
C20
VSS
U22
VSS
G15
VSS
C22
VSS
U23
VSS
G17
VSS
C4
VSS
U24
VSS
G19
VSS
C6
VSS
U25
VSS
G2
VSS
C8
VSS
U4
VSS
G24
VSS_NCTF
Datasheet
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 11 of 14)
D27
VSS
U5
VSS
G4
VSS
D7
VSS
U6
VSS
G5
VSS
E11
VSS
U7
VSS
G6
VSS
E13
VSS
U8
VSS
G9
63
Mechanical and Package Specifications
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 13 of 14)
Pin Name
64
Pin #
Table 7-2. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Name)
(Sheet 14 of 14)
Pin Name
Pin #
VSS
H11
VSSHDMI
VSS
H14
VSSADPLL
AB8
VSS
H17
VSSAHPLL
H10
VSS
H23
VSS
H9
VSS
J12
VSS
J16
VSS
J17
VSS
J20
VSS
J21
VSS
J22
VSS
J23
VSS
J24
VSS
J5
VSS
J6
VSS
J7
VSS
J8
VSS
K13
VSS
L13
VSS
L14
VSS
L15
VSS
L16
VSS
L18
VSS
W7
VSS
W8
VSS
Y11
VSS
Y13
VSS
Y15
VSS
Y17
VSS
Y19
VSS
Y9
VSS
AB23
VSS
AB9
VSS
F6
VSS
N23
VSS
R23
AC11
Datasheet
Mechanical and Package Specifications
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 1 of 13)
Pin #
Pin #
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 3 of 13)
Pin #
Pin Name
A10
CDMI_TXD7
AB12
HDMICOMP
AC26
USB_DP0
A12
CDMI_RXD1
AB13
HDMIDATA1_DP
AC4
KP_DKIN1
A14
CDMI_RXD6
AB14
HDMIDATA1_DN
AC5
I2C_1_SCL
A16
CDMI_RXCHAR#
AB15
VSS
AC6
SNSR2_STDBY
CDVO_TXD4
AB16
MIPI_CSI_RCOMP
AC7
SCLK25
VSS_NCTF
AB17
BT_CSI_DATA 2
AC8
VSS
A20
TMS
AB18
BT_CSI_HSYNC
AC9
VSS
A22
PWRMODE1
AB19
BT_CSI_CLK
AD1
VSS_NCTF
A24
VSS_NCTF
AB20
I2S_1_TXD
AD11
VSS
A26
VSS_NCTF
AB21
VSS
AD13
VSS
A18
A2
RESERVED8_NCTF
AB22
I2S_0_SYNC
AD15
VSS
A4
VSS_NCTF
AB23
VSS
AD17
VSS
A6
CDMI_TXSTB_EVEN#
AB24
USB_RCOMP
AD19
VSS
A8
CDMI_TXD3
AB25
USB_DN0
AD21
VSS
AA10
HDMIVCC3
AB27
OTG_DN
AD23
VSS
AA11
VSS
AB3
KP_MKIN1
AD24
USB_DN2
AA12
HDMIDATA0_DN
AB4
KP_DKIN0
AD25
USB_DP1
AA13
VSS
AB5
I2C_1_SDA
AD27
VSS_NCTF
AA14
RESERVED32
AB6
SNSR1_STDBY
AD3
VSS
AA15
VSS
AB7
VSS
AD4
SNSR_SS_TRG
AA16
BT_CSI_DATA 0
AB8
VSSADPLL
AD5
FLASH_TRG
AA17
VSS
AB9
VSS
AD7
VSS
A27
Datasheet
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 2 of 13)
AA18
BT_CSI_VSYNC
AC10
RESERVED14
AD9
VSS
AA19
VSS
AC11
VSSHDMI
AE10
RESERVED18
AA2
KP_MKIN4
AC12
VSS
AE12
HDMI_CLK_DP
AA20
I2S_0_TXD
AC13
HDMIDATA2_DP
AE14
MIPI_CSI_DQP0
AA22
VSS
AC14
HDMIDATA2_DN
AE16
MIPI_CSI_CLKN
AA23
RESERVED7
AC15
VSS
AE18
MIPI_CSI_DQP1
AA24
VSS
AC16
HDMI_HOTPLUG
AE20
BT_CSI_DATA 8
AA26
OTG_DP
AC17
BT_CSI_DATA 3
AE22
I2S_1_SYNC
AA4
VSS
AC18
BT_CSI_DATA 4
AE24
USB_DP2
AA5
VSS
AC19
VSS
AE4
SNSR_STB
AA6
VSS
KP_DKIN2
AE6
VCCADPLL
AA8
PRE_FLASH_TRG
AC20
BT_CSI_DATA 6
AE8
RESERVED17
AA9
VSS
AC21
VSS
AF1
VSS_NCTF
AB1
KP_MKIN2
AC22
I2S_1_CLK
AF11
VSS
AB10
RESERVED33
AC23
VSS
AF13
VSS
AB11
VCCHDMIBG
AC24
USB_DN1
AF15
VSS
AC2
65
Mechanical and Package Specifications
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 4 of 13)
Pin #
AF17
AF19
VSS
Pin #
B9
Pin Name
CDMI_TXD4
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 6 of 13)
Pin #
E2
Pin Name
SPI_1_SS0
BT_CSI_DATA 5
C10
VSS
E20
TRST#
VSS_NCTF
C12
VSS
E21
BSEL1
AF22
BT_CSI_DATA 9
C14
VSS
E22
PWRMODE0
AF23
I2S_0_RXD
C16
VSS
E23
VSS
AF26
VSS_NCTF
C18
VSS
E24
VSS
AF27
VSS_NCTF
C20
VSS
E26
FLSH_RB0#
AF5
RESERVED16
C22
VSS
E4
VSS
AF7
RESERVED13
C24
FLSH_1_IO0
E5
VSS
AF9
RESERVED10
C4
VSS
E6
BCLKP
AG1
RESERVED9_NCTF
C6
VSS
E7
BCLKN
AF2
AG10
RESERVED11
C8
VSS
E8
CDMI_TXSTB_ODD#
AG12
HDMI_CLK_DN
D1
RESERVED3
E9
VSS
AG14
MIPI_CSI_DQN0
D11
CDMI_RXD0
F1
AG16
MIPI_CSI_CLKP
D13
CDMI_RXD7
F10
AG18
SPI_0_CLK
CDMI_RCOMP
MIPI_CSI_DQN1
D15
CDVO_VBLNK
F11
VSS
RESERVED2
D17
CDVO_TXD0
F12
CDMI_TXD0
AG20
BT_CSI_DATA 7
D19
CDVO_TXPWR_N
F13
VSS
AG22
I2S_1_RXD
D21
TDI
F14
CDMI_RXD2
AG25
VSS_NCTF
D23
FLSH_1_ALE
F15
VSS
AG26
VSS_NCTF
D24
FLSH_1_CLE
F16
CDMI_RXDPWR#
AG2
AG27
VSS_NCTF
D25
FLSH_1_IO7
F17
VSS
AG4
RESERVED1
D27
VSS_NCTF
F18
CDVO_TXD5
AG6
RESERVED15
D3
VCC_HCLK
F19
VSS
AG8
RESERVED12
D4
RESERVED6
B1
F2
SPI_1_SS2
RESERVED4
D5
VCC_HCLK33
F20
VSS
B11
CDMI_TXDPWR#
D7
VSS
F21
VSS
B13
CDMI_RXD4
D9
CDMI_TXD2
F22
VSS
B15
CDMI_RXSTB_ODD#
E10
CDMI_TXD6
F23
FLSH_1_WE#
B17
CDVO_TXSN
E11
VSS
F24
FLSH_1_IO6
B19
CDVO_TXD3
E12
CDMI_RXD3
F25
FLSH_RB1#
B2
VSS_NCTF
E13
VSS
F27
FLSH_RB2#
TEST
E14
CDMI_RXSTB_EVEN#
F4
SPI_1_SDO
B23
PWRMODE2
E15
VSS
F5
SPI_1_CLK
B26
VSS_NCTF
E16
CDVO_TXSP
F6
VSS
B21
B27
66
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 5 of 13)
VSS_NCTF
E17
VSS
F7
OSC_OUT
B5
RESERVED5
E18
CDVO_TXD2
F8
VSS
B7
CDMI_TXD1
E19
VSS
F9
VSS
Datasheet
Mechanical and Package Specifications
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 7 of 13)
Pin #
Pin #
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 9 of 13)
Pin #
Pin Name
G10
CDMI_CVREF
H3
SPI_0_SS0
K6
SPI_0_SS3
G11
VSS
H5
SPI_0_SDO
K7
SPI_0_SDI
G12
CDMI_TXD5
H6
SPI_1_SS1
K8
SPI_1_SS3
G13
VSS
H7
SPI_1_SDI
L10
PWR_SPI1
G14
CDMI_RXD5
H8
VCCAHPLL
L11
VSS
G15
VSS
H9
VSS
L12
VCC25
G16
CDVO_TXD1
J11
PWR_DMIDVO
L13
VSS
G17
VSS
J12
VSS
L14
VSS
G18
CDVO_CVREF
J14
PWR_DMIDVO
L15
VSS
G19
VSS
J16
VSS
L16
VSS
VSS
J17
VSS
L17
PWR_FLSH1
PWR_DMIDVO
L18
VSS
PWR_FLSH1
G2
Datasheet
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 8 of 13)
G20
FLSH_1_WP#
J2
G22
FLSH_1_IO4
J20
VSS
L19
G23
FLSH_1_IO5
J21
VSS
L2
G24
VSS
J22
VSS
L20
VSS
G26
FLSH_RB3#
J23
VSS
L21
VSS
G4
VSS
J24
VSS
L22
VSS
G5
VSS
J26
FLSH_3_CE#
L23
VSS
G6
VSS
J4
PWR_DMIDVO
L24
VSS
G8
OSC_IN
J5
VSS
L26
FLSH_0_IO1
G9
VSS
J6
VSS
L4
VSS
H1
SPI_0_SS1
J7
VSS
L5
VSS
H10
VSSAHPLL
J8
VSS
L6
VSS
H11
VSS
K1
SRFWEN#
L7
VSS
H12
CDMI_GVREF
K10
PWR_ADMIDVO
L8
VSS
H13
CDMI_TXCHAR#
K12
PWR_DMIDVO
L9
PWR_SPI0
H14
VSS
K13
VSS
M1
EXIT_STDBY
H15
CDVO_STALL_N
K15
PWR_DMIDVO
M20
PWR_FLSH0
H16
CDVO_GVREF
K16
PWR_DMIDVO
M21
FLSH_0_ALE
H17
VSS
K18
PWR_CPU
M22
FLSH_0_WE#
H18
TCK
K20
PWR_FLSH1
M23
FLSH_0_WP#
H19
TDO
K21
PWR_FLSH1
M25
FLSH_0_IO0
H20
FLSH_1_IO1
K22
FLSH_1_RE#
M27
FLSH_0_IO2
H21
FLSH_1_IO2
K23
FLSH_1_CE#
M3
H22
FLSH_1_IO3
K25
FLSH_2_CE#
M5
SPI_2_SS1
H23
VSS
K27
FLSH_0_CLE
M6
SPI_2_SDO
RESET_OUT#
SPI_2_SS0
H25
FLSH_0_RE#
K3
HV_RCOMP
M7
SPI_2_CLK
H27
FLSH_0_CE#
K5
SPI_0_SS2
M8
SPI_2_SDI
67
Mechanical and Package Specifications
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 10 of 13)
Pin #
N10
VSS
N11
N12
Pin #
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 12 of 13)
Pin #
Pin Name
P7
RESET#
U12
VSS
VSS
P8
PMIC_INTR
U14
VSS
VSS
R10
PWR_KBDMISC
U16
VSS
N13
VSS
R12
VCC12
U18
VCCA_USB25
N14
VSS
R13
VSS
U2
KP_MKOUT6
N15
VSS
R15
VCC12
U20
VCCA_USB25
N16
VSS
R17
PWR_SD0
U21
VSS
N17
PWR_FLSH0
R18
N18
VSS
N19
R2
PWR_SD0
U22
VSS
VSS
U23
VSS
PWR_FLSH0
R20
FLSH_0_IO7
U24
VSS
VR_COMP
R21
VSS
U25
VSS
N20
VSS
R22
VSS
U26
N21
VSS
R23
VSS
U4
VSS
N22
VSS
R24
VSS
U5
VSS
N23
VSS
R26
SDIO2_CMD
U6
VSS
N24
VSS
R4
VSS
U7
VSS
N26
FLSH_0_IO3
R5
VSS
U8
VSS
N4
VSS
R6
VSS
V1
N5
VSS
R7
VSS
V10
PWR_CSB
N6
VSS
R8
VSS
V11
VSS
N7
VSS
T1
GPIO60
V12
VSS
N8
VSS
T11
VSS
V13
VCC12
N9
PWR_PMIC
T13
VSS
V14
VSS
N2
P1
SD0_DATA3
KP_MKOUT5
GPIO61
T15
VSS
V15
VCC12
VSS
T17
VSS
V16
VSS
P12
VSS
T19
VSS
V17
PWR_BT
P14
VCC12
T20
PWR_SD0
V18
VSS
P16
VSS
T21
PWR_SD0
V19
VSS
P18
PWR_SDIO2
T22
SD0_DATA1
V20
PWR_I2S
P20
FLSH_0_IO4
T23
SD0_DATA0
V21
VSS
P21
FLSH_0_IO5
T25
SDIO2_CLK
V22
SD0_WP
P22
FLSH_0_IO6
T27
P23
SDIO2_DAT1
T3
P25
SDIO2_DAT0
P27
SDIO2_DAT2
P3
P5
P6
PWRGOOD
U10
P11
68
Pin Name
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 11 of 13)
SDIO2_DAT3
V23
SD0_DATA7
GPIO59
V24
SD0_DATA5
T5
I2C_0_SDA
V25
SD0_DATA4
T6
I2C_0_SCL
V27
SD0_DATA2
I2C_2_SCL
T7
KP_MKOUT7
V3
KP_MKOUT2
I2C_2_SDA
T8
KP_MKOUT4
V5
KP_MKOUT3
PWR_KBDMISC
V6
KP_MKOUT0
Datasheet
Mechanical and Package Specifications
Table 7-3. Intel®
Platform Controller Hub
MP30 Ballout
(Sort by Pin Number)
(Sheet 13 of 13)
Pin #
V7
KP_MKIN7
V8
KP_MKIN0
W2
VSS
W20
VSS
W21
VSS
W22
VSS
W23
VSS
W24
SD0_CLK
W26
SD0_CMD
W4
VSS
W5
VSS
W6
VSS
W7
VSS
W8
VSS
Y1
Y10
KP_MKOUT1
HDMIVCC3
Y11
VSS
Y12
HDMIDATA0_DP
Y13
VSS
Y14
VCCHDMI
Y15
VSS
Y16
BT_CSI_DATA 1
Y17
VSS
Y18
VCC12
Y19
VSS
Y20
VCCA_USB33
Y21
I2S_0_CLK
Y22
OTG_ID
Y23
SD0_CD#
Y25
OTG_VBUS
Y27
Datasheet
Pin Name
SD0_DATA6
Y3
KP_MKIN6
Y5
KP_MKIN5
Y6
KP_MKIN3
Y7
KP_DKIN3
Y8
SNSR_RESET#
Y9
VSS
69
Mechanical and Package Specifications
7.4
Intel® Platform Controller Hub MP30
Package Specifications
The Intel® Platform Controller Hub MP30 comes in a Flip-Chip Ball Grid Array (FCBGA)
package and consists of a silicon die mounted face down on an organic substrate
populated with 493 solder balls on the bottom side. Capacitors may be placed in the
area surrounding the die. Because the die-side capacitors are electrically conductive,
and only slightly shorter than the die height, care should be taken to avoid contacting
the capacitors with electrically conductive materials. Doing so may short the capacitors
and possibly damage the device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out zone,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.
Unless otherwise specified, interpret the dimensions and tolerances in accordance with
ASME Y14.5-1994. The dimensions are in millimeters. Key package attributes are listed
below:
Dimensions:
• Package parameters: 14 mm x 14 mm
• Height 1.3 mm (maximum)
• Ball Count: 493
• Land metal diameter: See following Diagrams
• Solder resist opening: See following Diagrams
70
Datasheet
Mechanical and Package Specifications
7.5
Intel® Platform Controller Hub MP30
Package Diagrams
Figure 7-1.
Intel® Platform Controller Hub MP30 (Top View)
Datasheet
71
Mechanical and Package Specifications
Figure 7-2.
72
Intel® Platform Controller Hub MP30 (Bottom View)
Datasheet
Mechanical and Package Specifications
Figure 7-3.
Intel® Platform Controller Hub MP30 (Side View, Unmounted)
NOTE:The maximum outgoing package coplanarity cannot exceed 8 mils.
Datasheet
73
Mechanical and Package Specifications
Figure 7-4.
Intel® Platform Controller Hub MP30 Package (Solder Ball Detail)
Figure 7-5.
Intel® Platform Controller Hub MP30 Package (Underfill Detail)
74
Datasheet
Mechanical and Package Specifications
Figure 7-6.
Datasheet
Intel® Platform Controller Hub MP30 Package (Solder Resist Opening)
75
Mechanical and Package Specifications
7.6
Intel® Platform Controller Hub MP30
Ballout Definition and Signal Locations
Table 7-4. Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (1–6)
6
AG
RESERVED15
AF
AE
5
4
RESERVED1
RESERVED16
VCCADPLL
AD
2
1
RESERVED2
RESERVED9_N
CTF
VSS_NCTF
VSS_NCTF
SNSR_STB
FLASH_TRG
SNSR_SS_TRG
AC
SNSR2_STDBY
I2C_1_SCL
KP_DKIN1
AB
SNSR1_STDBY
I2C_1_SDA
KP_DKIN0
AA
VSS
VSS
VSS
Y
KP_MKIN3
KP_MKIN5
W
VSS
VSS
V
KP_MKOUT0
KP_MKOUT3
U
VSS
VSS
T
I2C_0_SCL
I2C_0_SDA
R
VSS
VSS
VSS
VSS_NCTF
KP_DKIN2
KP_MKIN1
KP_MKIN2
KP_MKIN6
VSS
KP_MKOUT1
KP_MKOUT2
VSS
KP_MKOUT5
GPIO59
GPIO60
I2C_2_SDA
VSS
M
SPI_2_SDO
SPI_2_SS1
L
VSS
VSS
K
SPI_0_SS3
SPI_0_SS2
J
VSS
VSS
H
SPI_1_SS1
SPI_0_SDO
G
VSS
VSS
VSS
VSS
F
VSS
SPI_1_CLK
SPI_1_SDO
SPI_1_SS2
E
BCLKP
VSS
VSS
SPI_1_SS0
VCC_HCLK33
RESERVED6
B
A
I2C_2_SCL
VSS
P
N
EXIT_STDBY
RESET_OUT#
HV_RCOMP
PWR_DMIDVO
SRFWEN#
K
PWR_DMIDVO
SPI_0_SS0
J
SPI_0_SS1
VCC_HCLK
G
SPI_0_CLK
F
E
RESERVED3
VSS_NCTF
VSS_NCTF
4
H
D
C
RESERVED5
5
M
L
VSS
CDMI_TXSTBP
6
T
GPIO61
SPI_2_SS0
V
R
VR_COMP
VSS
Y
U
VSS
VSS
AB
W
KP_MKOUT6
VSS
AD
AA
VSS
PWRGOOD
VSS
AF
AC
KP_MKIN4
P
C
AG
AE
N
D
76
3
RESERVED4
VSS_NCTF
3
2
B
A
1
Datasheet
Mechanical and Package Specifications
Table 7-5. Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (7-13)
13
12
11
HDMI_CLK_D
N
AG
AF
VSS
9
RESERVED11
VSS
HDMI_CLK_D
P
AE
10
RESERVED10
RESERVED18
VSS
AC
HDMIDATA2_
DP
VSS
HDMIVSS
RESERVED14
VSS
AB
HDMIDATA1_
DP
HDMICOMP
VCCHDMIBG
RESERVED33
AA
VSS
HDMIDATA0_
DN
VSS
Y
VSS
HDMIDATA0_
DP
VCC12
VSS
R
VSS
P
N
VSS
AD
VSS
SCLK25
AC
VSS
VSSADPLL
VSS
AB
HDMIVCC3
VSS
PRE_FLASH_T
RG
VSS
HDMIVCC3
VSS
SNSR_RESET#
VSS
PWR_CSB
PWR_KBDMISC
VSS
VCC12
PWR_KBDMISC
VSS
VSS
VSS
VSS
VSS
PWR_PMIC
M
L
VSS
VCC25
K
VSS
PWR_DMIDVO
J
H
VSS
CDMI_TXCHA
CDMI_GVREF
R#
G
VSS
AE
VSS
VSS
VSS
RESERVED13 AF
VSS
W
T
AG
RESERVED17
VSS
U
7
RESERVED12
AD
V
8
VSS
PWR_SPI1
PWR_SPI0
PWR_ADMIDVO
PWR_DMIDVO
AA
KP_DKIN3
Y
VSS
VSS
W
KP_MKIN0
KP_MKIN7
V
VSS
VSS
U
KP_MKOUT4
KP_MKOUT7
T
VSS
VSS
R
PMIC_INTR
RESET#
P
VSS
VSS
N
SPI_2_SDI
SPI_2_CLK
M
VSS
VSS
L
SPI_1_SS3
SPI_0_SDI
K
VSS
VSS
J
SPI_1_SDI
H
VSS
VSSAHPLL
VSS
VCCAHPLL
CDMI_TXD5
VSS
CDMI_CVREF
VSS
OSC_IN
G
F
VSS
CDMI_TXD0
VSS
CDMI_RCOMP
VSS
VSS
OSC_OUT
F
E
VSS
CDMI_RXD3
VSS
CDMI_TXD6
VSS
CDMI_TXSTBN
BCLKN
E
D
CDMI_RXD7
VSS
D
C
B
CDMI_RXD0
VSS
CDMI_TXDPW
R#
CDMI_RXD4
A
CDMI_RXD1
13
Datasheet
CDMI_TXD2
VSS
12
VSS
CDMI_TXD4
CDMI_TXD7
11
10
C
CDMI_TXD1
CDMI_TXD3
9
8
B
A
7
77
Mechanical and Package Specifications
Table 7-6. Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (14–20)
20
19
17
MIPI_CSI_DQ
N1
AG BT_CSI_DATA7
AF
18
BT_CSI_DATA5
AD
VSS
AC BT_CSI_DATA6
VSS
15
MIPI_CSI_CLK
P
VSS
MIPI_CSI_DQP
1
AE BT_CSI_DATA8
16
14
MIPI_CSI_DQ
N0
VSS
MIPI_CSI_CLK
N
VSS
AF
MIPI_CSI_DQP
AE
0
VSS
AD
HDMI_HOTPLU
G
VSS
HDMIDATA2_D
AC
N
MIPI_CSI_RCO
BT_CSI_HSYN
BT_CSI_DATA2
MP
C
VSS
HDMIDATA1_D
AB
N
BT_CSI_DATA4 BT_CSI_DATA3
AB
I2S_1_TXD
BT_CSI_CLK
AA
I2S_0_TXD
VSS
BT_CSI_VSYN
C
VSS
BT_CSI_DATA0
VSS
RESERVED32
Y
VCCA_USB33
VSS
VCC12
VSS
BT_CSI_DATA1
VSS
VCCHDMI
W
VSS
V
PWR_I2S
U
VCCA_USB25
T
PWR_SD0
R
FLSH_0_IO7
VSS
VSS
PWR_SD0
FLSH_0_IO4
VSS
M
PWR_FLSH0
L
VSS
K
PWR_FLSH1
J
VSS
H
FLSH_1_IO1
TDO
G
FLSH_1_WP#
VSS
PWR_BT
VSS
VSS
V
VSS
U
VSS
VSS
T
VCC12
R
VCC12
P
PWR_FLSH0
PWR_SDIO2
VSS
PWR_FLSH0
VSS
VSS
VSS
VSS
N
PWR_FLSH1
VSS
PWR_FLSH1
VSS
VSS
VSS
M
PWR_CPU
PWR_DMIDVO PWR_DMIDVO
VSS
VSS
TCK
VSS
CDVO_GVREF
CDVO_CVREF
VSS
CDVO_STALL_
N
VSS
H
CDVO_TXD1
VSS
CDMI_RXD5
G
VSS
CDMI_RXD2
F
VSS
CDMI_RXSTBP
E
CDVO_TXD5
VSS
E
TRST#
VSS
CDVO_TXD2
VSS
CDVO_TXSP
VSS
CDVO_TXD0
VSS
CDVO_TXD3
TMS
19
CDVO_VBLNK
VSS
CDVO_TXSN
18
17
D
VSS
CDMI_RXSTBN
CDMI_RXCHAR
#
CDVO_TXD4
K
J
VSS
CDVO_TXPWR
_N
L
PWR_DMIDVO
VSS
20
Y
PWR_SD0
F
A
VCC12
VSS
CDMI_RXDPW
R#
C
78
VSS
VCCA_USB25
P
B
AA
W
N
D
AG
16
CDMI_RXD6
15
C
B
14
Datasheet
A
Mechanical and Package Specifications
Table 7-7. Intel® Platform Controller Hub MP30 Ball Map—Signal Locations (21–27)
AG
AF
27
26
25
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
AE
AD
VSS_NCTF
AB
OTG_DN
SD0_DATA6
SD0_DATA2
SDIO2_DAT3
SDIO2_DAT2
AF
I2S_1_SYNC
AE
AD
AC
USB_RCOMP
VSS
I2S_0_SYN
VSS
VSS
RESERVED7
VSS
SD0_CD#
OTG_ID
I2S_0_CLK
Y
VSS
VSS
VSS
W
SDO_DATA5
SD0_DATA7
SD0_WP
VSS
V
VSS
VSS
VSS
VSS
U
SD0_DATA0
SD0_DATA1
PWR_SD0
T
VSS
VSS
VSS
R
SDIO2_DAT1
FLSH_0_IO6
FLSH_0_IO5
P
VSS
VSS
VSS
N
FLSH_0_WP# FLSH_0_WE#
FLSH_2_CE#
FLSH_0_CE#
FLSH_RB2#
FLSH_RB1#
FLSH_RB0#
VSS_NCTF
FLSH_1_IO7
C
FLSH_0_ALE
M
VSS
VSS
VSS
L
FLSH_1_CE#
FLSH_1_RE#
PWR_FLSH1
K
VSS
VSS
VSS
VSS
J
VSS
FLSH_1_IO3
FLSH_1_IO2
H
VSS
FLSH_1_IO5
FLSH_1_IO4
FLSH_1_IO6
FLSH_1_WE#
VSS
VSS
F
VSS
VSS
PWRMODE0
BSEL1
E
FLSH_1_CLE
FLSH_1_ALE
TDI
D
FLSH_0_RE#
FLSH_RB3#
FLSH_1_IO0
B
VSS_NCTF
VSS_NCTF
A
RESERVED8_
NCTF
VSS_NCTF
27
26
VSS_NCTF
24
G
VSS
PWRMODE2
25
AB
AA
SD0_CLK
VSS
FLSH_3_CE#
E
VSS
VSS
FLSH_0_IO0
FLSH_0_CLE
G
D
I2S_0_RXD
I2S_1_CLK
VSS
FLSH_0_IO1
J
F
AG
VSS
SDIO2_DAT0
FLSH_0_IO2
L
H
I2S_1_RXD
BT_CSI_DATA
9
VSS
VSS
FLSH_0_IO3
21
USB_DN2
SDIO2_CLK
SDIO2_CMD
N
K
SD0_DATA4
SD0_DATA3
R
M
22
USB_DN1
OTG_VBUS
SD0_CMD
U
P
USB_DN0
OTG_DP
W
T
USB_DP1
USB_DP0
AA
V
23
USB_DP2
AC
Y
24
C
TEST
B
PWRMODE1
23
22
A
21
§
Datasheet
79
Mechanical and Package Specifications
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§
80
Datasheet