19-0576; Rev 0; 8/07
ৰۇ
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,96°D*ᆨࣞपᆍă
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``````````````````````````````````` ።
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``````````````````````````````` ࢾ৪ቧᇦ
ጓ።
၀ดᎥಘᇹᄻ
PART
PIN-PACKAGE
LANGUAGE
PKG
CODE
MAX7456EUI+
28 TSSOP-EP*
English/
Japanese
U28E-5
ሿॅಢ࢟ᔇ
*FQ! >! ൡă
,ܭာᇄॖᓤă
ᓖǖকୈᔫ᎖.51°Dᒗ,96°Dᆨࣞपᆍă
୭ᒙᏴၫᓾ೯ࡼᔢઁ߲ă
TQJဵNpupspmb-! Jod/ࡼܪă
`````````````````````````````````````````````````````````````````````` ଼છถౖᅄ
AVDD
VIN
CLKIN
XFB
AGND
DGND
DVDD
PVDD
PGND
CLAMP
XTAL
OSCILLATOR
SYSTEM
CLOCK
OSD
MUX
SYNC
SEPARATOR
VIDEO
DRIVER
VOUT
DAC
CLKOUT
HSYNC
VIDEO
TIMING
GENERATOR
VSYNC
LOS
SAG
NETWORK
MAX7456
SAG
SYNC
DISPLAY
ADDRESS
CS
SCLK
SDIN
SERIAL
INTERFACE
DISPLAY
MEMORY
(SRAMS)
CHARACTER
ADDRESS
CHARACTER
MEMORY
(NVM)
PIXEL
CODE
OSD
GENERATOR
PIXEL
CONTROL
SDOUT
RESET
POR
________________________________________________________________ Maxim Integrated Products
1
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NBY8567
``````````````````````````````````` গၤ
NBY8567
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ᄰࡸĂྻႲືመာ
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V
DVDD to DGND ........................................................-0.3V to +6V
PVDD to PGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to PGND .....................................................-0.3V to +0.3V
DGND to PGND.....................................................-0.3V to +0.3V
VIN, VOUT, SAG to AGND......................-0.3V to (VAVDD + 0.3V)
HSYNC, VSYNC, LOS to AGND ...............................-0.3V to +6V
RESET to AGND .....................................-0.3V to (VAVDD + 0.3V)
CLKIN, CLKOUT, XFB to DGND ............-0.3V to (VDVDD + 0.3V)
SDIN, SCLK, CS, SDOUT to DGND........-0.3V to (VDVDD + 0.3V)
Maximum Continuous Current into VOUT ........................±100mA
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 27mW/°C above +70°C) .......2162mW*
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*As per JEDEC51 Standard (Multilayer Board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Analog Supply Voltage
VAVDD
4.75
5
5.25
V
Digital Supply Voltage
VDVDD
4.75
5
5.25
V
Driver Supply Voltage
VPVDD
4.75
5
5.25
V
Analog Supply Current
IAVDD
VIN = 1VP-P (100% white flat field signal),
VOUT load, RL = 150Ω
24
35
mA
Digital Supply Current
IDVDD
VIN = 1VP-P (100% white flat field signal),
VOUT load, RL = 150Ω
25
30
mA
Driver Supply Current
IPVDD
VIN = 1VP-P (100% white flat field signal),
VOUT load, RL = 150Ω
58
80
mA
NONVOLATILE MEMORY
Data Retention
TA = +25°C
100
Years
Endurance
TA = +25°C
100,000
Stores
DIGITAL INPUTS (CS, SDIN, RESET, SCLK)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
V
0.8
VHYS
Input Leakage Current
Input Capacitance
2.0
50
VIN = 0 or VDVDD
mV
±10
CIN
V
5
μA
pF
DIGITAL OUTPUTS (SDOUT, CLKOUT, VSYNC, HSYNC, LOS)
Output High Voltage
VOH
ISOURCE = 4mA (SDOUT, CLKOUT)
Output Low Voltage
VOL
ISINK = 4mA
0.45
V
SDOUT, CS = VDVDD
±10
μA
Tri-State Leakage Current
2
2.4
_______________________________________________________________________________________
V
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (CLKIN)
Clock Frequency
27
Clock-Pulse High
Clock-Pulse Low
Input High Voltage
ns
14
ns
0.7 x
VDVDD
V
Input Low Voltage
Input Leakage Current
MHz
14
VIN = 0V or VDVDD
0.3 x
VDVDD
V
±50
μA
CLOCK OUTPUT (CLKOUT)
Duty Cycle
5pF and 10kΩ to DGND
Rise Time
5pF and 10kΩ to DGND
40
50
3
60
ns
%
Fall Time
5pF and 10kΩ to DGND
3
ns
DC Power-Supply Rejection
VAVDD = VDVDD = VPVDD = 5V;
VIN = 1VP-P, measured at VOUT
40
dB
AC Power-Supply Rejection
VAVDD = VDVDD = VPVDD = 5V;
VIN = 1VP-P, measured at VOUT;
f = 5MHz; power-supply ripple = 0.2VP-P
30
dB
VIDEO CHARACTERISTICS
Short-Circuit Current
VOUT to PGND
230
mA
Line-Time Distortion
LTD
Figures 1a, 1b
0.5
%
Output Impedance
ZOUT
Figures 1a, 1b
Gain
Figures 1a, 1b
Black Level
1.89
2.0
At VOUT, Figures 1a, 1b
Input-Voltage Operating Range
Ω
0.2
2.11
V/V
AGND
+ 1.5
V
VIN
Figures 1a, 3 (Note 2)
0.5
1.2
VP-P
Input-Voltage Sync Detection
Range
VINSD
Figures 1a, 3 (Note 3)
0.5
2.0
VP-P
Maximum Output-Voltage Swing
VOUT
Figures 1a, 1b
2.4
Output-Voltage Sync Tip Level
Large Signal Bandwidth (0.2dB)
BW
VOUT = 2VP-P, Figures 1a, 1b
VIN to VOUT Delay
VP-P
0.7
V
6
MHz
30
ns
Differential Gain
DG
0.5
%
Differential Phase
DP
0.5
Degrees
OSD White Level
VOUT 100% white level with respect to
black level
Horizontal Pixel Jitter
Between consecutive horizontal lines
Video Clamp Settling Time
1.25
1.33
1.45
V
24
ns
32
Lines
_______________________________________________________________________________________
3
NBY8567
ELECTRICAL CHARACTERISTICS (continued)
NBY8567
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ᄰࡸĂྻႲືመာ
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OSD CHARACTERISTICS
OSD Rise Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60
ns
OSD Fall Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60
ns
OSD Insertion Mux Switch Time
OSD insertion mux register
OSDM[2,1,0] = 011b
75
ns
TIMING CHARACTERISTICS
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
SCLK Period
tCP
100
ns
SCLK Pulse-Width High
tCH
40
ns
ns
SCLK Pulse-Width Low
tCL
40
CS Fall to SCLK Rise Setup
tCSS0
30
ns
CS Fall After SCLK Rise Hold
tCSH0
0
ns
CS Rise to SCLK Setup
tCSS1
30
ns
CS Rise After SCLK Hold
tCSH1
0
ns
CS Pulse-Width High
tCSW
100
ns
SDIN to SCLK Setup
tDS
30
ns
0
ns
SDIN to SCLK Hold
tDH
SDOUT Valid Before SCLK
tDO1
20pF to ground
25
ns
SDOUT Valid After SCLK
tDO2
20pF to ground
0
ns
CS High to SDOUT High
Impedance
tDO3
20pF to ground
300
ns
CS Low to SDOUT Logic Level
tDO4
20pF to ground
20
ns
tDOV
20pF to ground
30
NTSC external sync mode, Figure 4
375
PAL external sync mode, Figure 6
400
HSYNC, VSYNC, AND LOS TIMING
LOS, VSYNC, and HSYNC Valid
before CLKOUT Rising Edge
VOUT Sync to VSYNC Falling
Edge Delay
4
tVOUT-VSF
_______________________________________________________________________________________
ns
ns
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ᄰࡸĂྻႲືመာ
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
VOUT Sync to VSYNC Rising
Edge Delay
tVOUT-VSR
VSYNC Falling Edge to VOUT
Sync Delay
tVSF-VOUT
VSYNC Rising Edge to VOUT
Sync Delay
tVSR-VOUT
VOUT Sync to HSYNC Falling
Edge Delay
CONDITIONS
MIN
TYP
NTSC external sync mode, Figure 4
400
PAL external sync mode, Figure 6
425
NTSC internal sync mode, Figure 5
40
PAL internal sync mode, Figure 7
45
MAX
UNITS
ns
ns
NTSC internal sync mode, Figure 5
32
PAL internal sync mode, Figure 7
30
tVOUT-HSF
NTSC and PAL external sync mode,
Figure 8
310
ns
VOUT Sync to HSYNC Rising
Edge Delay
tVOUT-HSR
NTSC and PAL external sync mode,
Figure 8
325
ns
HSYNC Falling Edge to VOUT
Sync Delay
tHSF-VOUT
NTSC and PAL internal sync mode,
Figure 9
115
ns
HSYNC Rising Edge to VOUT
Sync Delay
tHSR-VOUT
NTSC and PAL internal sync mode,
Figure 9
115
ns
All Supplies High to CS Low
tPUD
NVM Write Busy
tNVW
Power-up delay
ns
50
ms
12
ms
Note 1: See the standard test circuits of Figure 1. RL = 75Ω, unless otherwise specified. All digital input signals are timed from a
voltage level of (VIH + VIL) / 2. All parameters are tested at TA = +85°C and values through temperature range are guaranteed by design.
Note 2: The input-voltage operating range is the input range over which the output signal parameters are guaranteed (Figure 3).
Note 3: The input-voltage sync detection range is the input composite video range over which an input sync signal is properly
detected and the OSD signal appears at VOUT. However, the output voltage specifications are not guaranteed for input signals exceeding the maximum specified in the input operating voltage range (Figure 3).
CIN
0.1μF
SIGNAL
GEN
VOUT
VIN
RIN
75Ω
MAX7456
a) INPUT TEST CIRCUIT
MAX7456
SAG
CL
22pF
RL
150Ω
b) ONE STANDARD VIDEO LOAD, DC-COUPLED
ᅄ2/! ܪᓰހ၂࢟വ
_______________________________________________________________________________________
5
NBY8567
TIMING CHARACTERISTICS (continued)
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
````````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ
(VAVDD = +5V, VDVDD = +5V, VPVDD = +5V, TA = +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
IMAGE WITH ON-SCREEN GRAPHICS
100% COLOR BARS RESPONSE
6
MAX7456 toc04
MAX7456 toc03
CVBS OUT
(200mV/div)
10μs/div
60% MULTIBURST RESPONSE
75% COLOR BARS VECTOR DIAGRAM
MAX7456 toc02
MAX7456 toc01
CVBS OUT
(200mV/div)
CVBS OUT
10μs/div
_______________________________________________________________________________________
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DIFFERENTIAL PHASE
100% SWEEP RESPONSE
MAX7456 toc05
CVBS OUT
(200mV/div)
DIFFERENTIAL PHASE (deg)
MAX7456 toc06
0.20
0.15
0.10
CVBS OUT
0.05
0
-0.05
1st
10μs/div
2nd
3rd
4th
5th
6th
STEP
DIFFERENTIAL GAIN
2T RESPONSE
0.15
DIFFERENTIAL GAIN (%)
MAX7456 toc08
MAX7456 toc07
0.20
CVBS IN
(200mV/div)
0.10
CVBS OUT
0.05
CVBS OUT
(200mV/div)
0
-0.05
1st
2nd
3rd
4th
5th
6th
400ns/div
STEP
12.5T RESPONSE
OSD OUTPUT 100% WHITE PIXEL
MAX7456 toc09
MAX7456 toc10
CVBS IN
(200mV/div)
CVBS OUT
(200mV/div)
CVBS OUT
(200mV/div)
400ns/div
200ns/div
_______________________________________________________________________________________
7
NBY8567
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VAVDD = +5V, VDVDD = +5V, VPVDD = +5V, TA = +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
NBY8567
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ᄰࡸĂྻႲືመာ
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VAVDD = +5V, VDVDD = +5V, VPVDD = +5V, TA = +25°C, unless otherwise noted. See the Typical Operating Circuit of Figure 2, if applicable.)
H TIMING (EXTERNAL-SYNC MODE)
LINE-TIME DISTORTION
MAX7456 toc12
MAX7456 toc11
CVBS OUT
(200mV/div)
CVBS OUT
(200mV/div)
2μs/div
10μs/div
LOSS-OF-SYNC (LOW TO HIGH)
H TIMING (INTERNAL-SYNC MODE)
MAX7456 toc14
MAX7456 toc13
CVBS OUT
(200mV/div)
CVBS OUT
(200mV/div)
LOS
(1V/div)
500μs/div
2μs/div
LOSS-OF-SYNC (HIGH TO LOW)
MAX7456 toc15
CVBS OUT
(200mV/div)
LOS
(1V/div)
500μs/div
8
_______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
୭
߂
1, 2, 13–16,
27, 28
N.C.
ถ
ೌݙăดݝᆚೌă
3
DVDD
ၫᔊ࢟ᏎၒྜྷLjጙৈ1/2μG࢟ྏവᒗEHOEă
4
DGND
ၫᔊă
5
CLKIN
ᄏೌ2ăᏴDMLJOਜ਼YGCᒄମೌጙৈ݀ೊቕᑩĂຫෝါᄏ৩߅ᄏᑩLjဧ38NI{ᇹᄻ
ݬఠဟᒩᒇདࣅDMLJOă
6
XFB
7
CLKOUT
ᄏೌ3ăᏴDMLJOਜ਼YGCᒄମೌጙৈ݀ೊቕᑩĂຫෝါᄏ৩߅ᄏᑩLjྙਫဧ38NI{
ᇹᄻݬఠဟᒩདࣅDMLJOLjYGCኞహă
ဟᒩၒ߲ă38NI{൝࢟ຳၒ߲ࡼᇹᄻဟᒩă
8
CS
9
SDIN
ࠈቲၫၒྜྷăၫᏴTDMLဍዘጤྜྷă
10
SCLK
ࠈቲဟᒩၒྜྷăᆐၫၒྜྷࡵTEJOਜ਼࠭TEPVUၒ߲ᄋဟᒩLjᐴహܘ܈ኍᏴ51&ᒗ71&ᒄମă
11
SDOUT
12
LOS
ᄴࣀݛပၒ߲)ఎധ*ăࡩWJOᄴݛ൴ߡࣀပ43ৈೌኚᒲ໐ဟLjMPTܤᆐ࢟ຳăࡩ၃ࡵ43ৈೌኚᎌ
ᄴݛ൴ߡဟLjMPTܤᆐࢅ࢟ຳăᄰਭ2lΩ౯࢟ᔜೌᒗEWEEጙৈ९၃ୈࡼ࢟Ꮞᑵă
17
VSYNC
ޝᄴݛၒ߲)ఎധ*ă၁ຫၒྜྷޝᄴݛ໐ମLjVSYNCܤᆐࢅ࢟ຳăVSYNCభጲ࠭WJOૂআLjጐభጲᏴด
ᄴݛෝါሆดޘݝညăᄰਭ2lΩ౯࢟ᔜೌᒗEWEEᑗጙৈ९၃ୈࡼ࢟Ꮞᑵă
18
HSYNC
ቲᄴݛၒ߲)ఎധ*ă၁ຫၒྜྷቲᄴݛ໐ମLjHSYNCܤᆐࢅ࢟ຳăHSYNCభጲ࠭WJOૂআLjጐభጲᏴด
ᄴݛෝါሆดޘݝညăᄰਭ2lΩ౯࢟ᔜೌᒗEWEEጙৈ९၃ୈࡼ࢟Ꮞᑵă
19
RESET
ᇹᄻআᆡၒྜྷăᔢቃRESET൴ߡࣞᆐ61ntăRESETဍዘ211μtઁLjჅᎌTQJࡀۻআᆡᒗ෦ཱྀᒋă
Ᏼࠥ໐ମLjݙถ࣪ࡀቲࣗቖषᆰăRESETဍዘ31μtઁLjመာࡀჅᎌᆡᒙ࣒ۻআᆡᒗ
෦ཱྀᒋ11Iă
20
AGND
ෝผă
21
AVDD
ෝผ࢟ᏎၒྜྷLjጙৈ1/2μG࢟ྏവᒗBHOEă
22
VIN
23
PGND
དࣅLjᏴጙৈ࢛ೌᒗBHOEă
24
PVDD
དࣅ࢟ᏎၒྜྷLjጙৈ1/2μG࢟ྏവᒗQHOEă
25
SAG
26
VOUT
—
EP
ࢅ࢟ຳᎌຢኡၒྜྷăࡩCSᆐ࢟ຳဟLjTEPVUܤᆐᔜఝă
ࠈቲၫၒ߲ăၫᏴTDMLሆଢ଼ዘၒ߲ăࡩCSᆐ࢟ຳဟLjܤᆐᔜఝă
QBMᑗOUTD! DWCT၁ຫၒྜྷă
࢟ኹၱିኀᑵၒྜྷLjྙਫݙဧኍೌᒗWPVULjݬఠᅄ2că
၁ຫၒ߲ă
ൡăดೌݝᒗBHOEăFQೌᒗBHOEށጲᄋྲེቶถăݙገFQᔫᆎጙࡼೌă
_______________________________________________________________________________________
9
NBY8567
```````````````````````````````````````````````````````````````````````````` ୭ႁී
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
+5V
MAX7456
+5V
0.1μF
27MHz
1
N.C.
2
N.C.
N.C. 28
N.C. 27
3 DVDD
VOUT 26
4
DGND
SAG 25
5
CLKIN
PVDD 24
COUT
75Ω
CVBS OUT
CSAG
0.1μF
6
XFB
CLKOUT
7
CLKOUT
CS
8
CS
AVDD 21
SDIN
9
SDIN
AGND 20
SCLK
10 SCLK
RESET 19
SDOUT
11 SDOUT
HSYNC 18
12 LOS
VSYNC 17
13 N.C.
N.C. 16
14 N.C.
N.C. 15
PGND 23
0.1μF
CVBS IN
VIN 22
0.1μF
75Ω
+5V
1kΩ
1kΩ
1kΩ
HS
VS
LOS
ᅄ3/! ࢜ቯᔫ࢟വ
``````````````````````````````` ሮᇼႁී
NBY8567ᄰࡸྻႲືመာ)PTE*खညૹ߅೫ޘည
ઓࢾፃࡼ PTE ݀ଝᏲࡵၒ߲ቧჅኊࡼཝݝถă
NBY8567ถ৫၃OUTDᑗQBMআ၁ຫቧăୈ۞
౪ၒྜྷ༃ᆡĂᄴݛॊಭĂ၁ຫဟኔखညĂPTEྜྷރআ
Ăऻጵပᔊ९ࡀĂመာࡀĂPTEखညĂ
ᄏᑩጲૺࣗ0ቖPTEၫࡼTQJରྏాਜ਼၁ຫདࣅ
ࢀ)༿ݬఠ଼છถౖᅄ*ăࠥᅪLjNBY8567થᆐᇹᄻᄴݛ
ᄋޝᄴ)ݛVSYNC*Ăቲᄴ)ݛHSYNC*ਜ਼ᄴࣀݛပ)MPT*
ၒ߲ቧăဟᒩၒ߲ቧ)DMLPVU*ᑽߒࣶৈୈࡼቯ
ă
༿ݬఠ NBY8567ࡀႁීݝॊLj೫ஊ۾ၫᓾ೯ᒦဧ
ࡼࡀ९ă
10
367ৈઓࢾፃ23 y 29ሷႤᔊ९ᔝᎌᎾᓤྜྷLj݀Ꭷၒྜྷ
၁ຫഗআLjޘညࡒᎌ PTE ၁ຫၒ߲ࡼ DWCT ቧăᏴ
OWNᒦLjᔢࣶభጲᒮ367ৈ23 y 29ሷႤᔊ९ăᏴOUTDᒜ
ါᒦLjመာ24ቲ y 41ৈᔊ९ăᏴQBMᒜါᒦLjመာ27ቲ y
41ৈᔊ९ăᎌၒྜྷ၁ຫቧဟLjဧNBY8567ࡼดݝ
၁ຫဟኔखညLj྆భጲመာPTEᅄስă
၁ຫၒྜྷ
NBY8567ࡼWJOభ၃ܪᓰOUTDᑗQBM DWCTቧăܘ
ኍጙৈ1/2μG࢟ྏ࣪၁ຫቧၒྜྷቲୣഗẮLj݀Ᏼ
ดݝ༃ᆡăኊገ1/2μGၒྜྷẮ࢟ྏཀྵۣਖࢾࡼሣဟମပ
ᑞ)MUE*ਜ਼၁ຫ༃ᆡᆮࢾဟମă၁ຫ༃ᆡᆮࢾဟମႲၒྜྷ
Ắ࢟ྏᄴ܈ಿܤછLjऎMUEႲ࢟ྏन܈ಿܤછă
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
MAXIMUM VIDEO SWING
WHITE LEVEL
INPUT VOLTAGE
VIN
COLOR BURST
BLACK LEVEL
SYNC TIP
LEVEL
MINIMUM VIDEO SWING
ᅄ4/! ၣᎫࢾፃ
ၒྜྷ༃ᆡ
ᄴݛॊಭ
NBY8567ࡼ༃ᆡဵᒇഗᒮ࢟വLjᏴᓆቲLjဧ
ၒྜྷẮ࢟ྏቅᑵၒྜྷቧࡼᒇഗມጤLjWJOࡼᄴݛᄿ
༃ᆡᏴᏖ661nWăᏴWJO࣡ೂࡼᒇഗ࢟ຳభ᎖ຢดᄴ
ݛଶހਜ਼၁ຫࠀಯถăক࢟വથሿ߹೫ࢅຫᐅဉLjಿ
ྙ71I{Ꮽፒଝྜྷࡼࢅຫᐅဉă
ᄴݛॊಭଶހ၁ຫၒྜྷࡼআᄴݛ൴ߡLjᄋན߲ဟኔ
ቧᇦLjޘညHSYNCਜ਼VSYNCቧǗથ᎖ดݝPTEᄴ
ݛਜ਼ᄴࣀݛပ)MPT*ଶހăྙਫᏴWJO43ᄟೌኚቲᒲ໐
ᎌყࡵހᄴݛቧLjMPTܤᆐ࢟ຳLjྙਫყࡵހ43ৈ
ೌኚቲᄴݛቧLjᐌܤᆐࢅ࢟ຳăᏴMPTᓨზ໐ମLjࡩ
WN1\6^! >! 1! )၁ຫෝါ1ࡀLj6ᆡ*ဟLjᒑᎌPTE߲ሚ
ᏴWPVUăࠥဟLjၒྜྷᅄስᏴWPVUۻᒙᆐᎅWN2\7;5^
ཀྵࢾࡼાࣞăܭ2߲೫Ⴥᎌᄴݛෝါă
ܭ2/! ၁ຫᄴݛෝါ
VIDEO MODE
VIN
VSYNC
HSYNC
Auto Sync Select Mode
VM0[5, 4] = 0x
Video
Active
No input
Active
Video
External Sync Select
VM0[5, 4] = 10
Internal Sync Select
VM0[5, 4] = 11
LOS
VOUT
Active
Low
VIN + OSD
Active
High
OSD only
Active
Active
Low
VIN + OSD
No input
Inactive (high)
Inactive (high)
High
DC
Video
Active
Active
High
OSD only
No input
Active
Active
High
OSD only
Y! >! ᇄਈă
______________________________________________________________________________________
11
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
၁ຫဟኔखည
መာࡀ)TSBN*
၁ຫဟኔखညဵၫᔊ࢟വLjޘညჅᎌࡼดݝਜ਼ᅪݝ
)VSYNCਜ਼HSYNC*ဟኔቧăVSYNCਜ਼HSYNCభጲਜ਼
WJOᄴݛLjᏴดݝᄴݛෝါሆࣖೂ᎖ၒྜྷᏥቲă၁ຫဟ
ኔखညถ৫ဧᄴጙৈ38NI{ᄏޘညOUTDᑗQBM
ဟኔ)༿ݬఠᅄ5ᒗᅄ:*ă
መာࡀࡀ೫591ৈᔊ९ᒍLjᑚቋᒍᒎሶࡀᏴ
OWNᔊ९ࡀᒦࡼᔊ९ăઓభጲᄰਭTQJରྏࠈా
ᒙመာࡀࡼดྏăመာࡀᒍ࣪።᎖ପ၁ࡼ
ৼࢾᆡᒙ)ݬఠᅄ21*ăᏴޝሿ໐ମቖྜྷመာࡀLjభ
ऴᒏPTEᅄስࡼၾဟڗܤăభVSYNCᔫᆐᓍ૦ࠀಯ
ᒦࣥLjࣅቖྜྷመာࡀݷᔫLjጲဣሚၤถă
ᄏᑩ
ดݝᄏᑩޘည၁ຫဟኔखညဧࡼᇹᄻဟᒩăᑩ
ဧጙৈ38NI{ᄏLjጐభጲᎅDMLJO࣡ᅪݝ38NI{
UUMဟᒩདࣅăᅪݝဟᒩෝါሆLjᏴDMLJO࣡ೌጙৈ
38NI{ UUMၒྜྷဟᒩLjYGC࣡ኞహă
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
VOUT
(ODD FIELD)
50%
VOUT
(EVEN FIELD)
50%
VSYNC
50%
1/2H
50%
50%
tVOUT-VSF
tVOUT-VSR
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
ᅄ5/! WPVUĂVSYNCਜ਼HSYNCဟኔ)OUTDLjᅪᄴݛෝါ*
12
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
VOUT
(ODD FIELD)
50%
VOUT
(EVEN FIELD)
50%
VSYNC
NBY8567
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
1/2H
50%
50%
50%
50%
tVSF-VOUT
tVSR-VOUT
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
ᅄ6/! WPVUĂVSYNCਜ਼HSYNCဟኔ)OUTDLjดᄴݛෝါ*
______________________________________________________________________________________
13
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
1/2H
VOUT
(ODD FIELD)
50%
50%
VOUT
(EVEN FIELD)
50%
50%
VSYNC
50%
50%
tVOUT-VSF
tVOUT-VSR
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
ᅄ7/! WPVUĂVSYNCਜ਼HSYNCဟኔ)QBMLjᅪᄴݛෝါ*
14
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
VOUT
(ODD FIELD)
50%
50%
VOUT
(EVEN FIELD)
50%
50%
VSYNC
50%
NBY8567
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
1/2H
50%
tVSF-VOUT
tVSR-VOUT
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
ᅄ8/! WPVUĂVSYNCਜ਼HSYNCဟኔ)QBMLjดᄴݛෝါ*
______________________________________________________________________________________
15
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
VOUT
50%
50%
tVOUT-HSF
tVOUT-HSR
HSYNC
ᅄ9/! WPVUਜ਼HSYNCቲᄴݛဟኔ)OUTDਜ਼QBMLjᅪᄴݛෝါ*
VOUT
50%
50%
tHSF-VOUT
tHSR-VOUT
HSYNC
ᅄ:/! WPVUਜ਼HSYNCቲᄴݛဟኔ)OUTDਜ਼QBMLjดᄴݛෝါ*
16
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ᔊ९ࡀဵ367ቲ y 75ᔊஂऻጵပࡀ)OWN*Ljࡀ
ᔊ९ᑗᅄተLjᏴޣᒦᎾᓤྜྷ೫ᅄ 23 Ⴥာࡼᔊ९ă
ઓభᄰਭTQJରྏࠈాᒙᔊ९ࡀᒦࡼดྏăඛጙ
ቲ࣒۞ጙৈPTEᔊ९ࡼහၤăඛጙᔊ९ᎅ23ৈቲ y! 29
ሷႤᔝ߅LjඛৈሷႤ࢛ᎅᎌྯᒬᓨზࡼ3ᆡၫܭာLj
ྯᒬᓨზᆐǖྻڹĂ੨ྻᑗᅀීăፐࠥLjඛৈᔊ९ኊ
ገ65ᔊஂࡼሷႤၫ)ᅄ22*ă
DISPLAY MEMORY ADDRESS
(DMAH, DMAL)
OWNኊገጙࠨࣗቖჅᎌᔊ९)75ᔊஂ*Ljᄰਭ߂ۻᆐስ
SBNࡼࡀቲဣሚă75ᔊஂဟስSBN۞ᎌჅኡ
ᔊ९)DNBI\8;1^*ࡼჅᎌሷႤၫLjᔫOWNࣗቖݷᔫࡼ
દߡ)ᅄ24*ăᔐဵᄰਭስSBNषᆰOWNLjჅጲኊገೝ
ৈݷᔫݛᒾăሶOWNቖྜྷᔊ९ဟLjઓ၅ሌಽ65ৈ9ᆡ
TQJቖݷᔫቖྜྷስSBNLjઁᒊቲጙᄟስSBNቖෘഎă
ಢ႒ࡼLjࣗནጙৈᔊ९ࡼሷႤဟLjሌᔊ९ࡼሷႤၫ
ࣗྜྷስSBNLjᏳ࠭ስSBNჅኊࡼሷႤၫࣗᒗTQJ
࣡ాă
NBY8567
ᔊ९ࡀ)OWN*
DISPLAY MEMORY ADDRESS
(DMAH, DMAL)
CHARACTER
ADDRESS (CA)
0
29
30
59
DISPLAY AREA
0
ADDRESS (8 BIT)
29
ADDRESS (8 BIT)
(16 ROWS x 30 CHARACTERS)
CHARACTER
ATTRIBUTE
L B I
B L N X X X X X
C K V
CHARACTER DATA
ARRANGEMENT IN
DISPLAY MEMORY
(SRAM) 480 ROWS
x 2 BYTES SRAM
L B I
B L N X X X X X
C K V
CHARACTER ATTRIBUTE BIT DEFINITIONS:
LBC = LOCAL BACKGROUND CONTROL
BLK = BLINK CONTROL
INV = INVERT CONTROL
X = DON'T CARE
DISPLAY MEMORY
(TWO, 256 x 16-BIT SRAMs)
450
479
479
ADDRESS (8 BIT)
CHARACTER MEMORY
ADDRESS LOW (CMAL)
CHARACTER MEMORY
ADDRESS HIGH (CMAH)
0
12 PIXELS
0
0
1
L B I
B L N X X X X X
C K V
1
2
51
52
53
54
53
54
63
18 PIXELS
61
62
63
0
61
62
63
255
2
CHARACTER
DATA USAGE
(12 x 18 PIXELS)
CHARACTER
DATA
UNUSED
MEMORY
4 PIXEL VALUES
(1 BYTE)
51
52
53
(SEE FIGURE 11 FOR PIXEL MAP)
2-BIT PIXEL DEFINITIONS:
00 = BLACK, OPAQUE
10 = WHITE, OPAQUE
X1 = TRANSPARENT (EXTERNAL SYNC MODE)
OR GRAY (INTERNAL SYNC MODE)
0
1
2
51
52
53
54
PIXEL DATA ARRANGEMENT IN CHARACTER MEMORY (NVM)
256 ROWS x 64 BYTES EEPROM
ᅄ21/! ᒬݬၫࢾፃ
______________________________________________________________________________________
17
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
PIXEL ROW NUMBER
PIXEL COLUMN NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
CHARACTER MEMORY
ADDRESS LOW
CMAL[5:0]
0
CDMI
[7, 6]
CDMI
[5, 4]
CDMI
[3, 2]
CDMI
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
0, 1, 2
1
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
3, 4, 5
2
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
6, 7, 8
3
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
9, 10, 11
4
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
12, 13, 14
5
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
15, 16, 17
6
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
18, 19, 20
7
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
21, 22, 23
8
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
24, 25, 26
9
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
27, 28, 29
10
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
30, 31, 32
11
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
33, 34, 35
12
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
36, 37, 38
13
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
39, 40, 41
14
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
42, 43, 44
15
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
45, 46, 47
16
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
48, 49, 50
17
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
[7, 6]
[5, 4]
[3, 2]
[1, 0]
51, 52, 53
2-BIT PIXEL DEFINITION:
[x, y]
00 = BLACK
[x, y]
10 = WHITE
[x, y]
X1 = TRANSPARENT (EXTERNAL SYNC MODE)
OR GRAY (INTERNAL SYNC MODE)
X = DON'T CARE
ᅄ22/! ᔊ९ၫဧ)ሷႤ፯*
18
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
CA[7:4], CMAH[7:4]
CA[3:0], CMAH[3:0]
ᅄ23/! ᔊ९ᒍ፯)෦ཱྀᔊ९ૹ*
______________________________________________________________________________________
19
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
0. . . . . . . . . . . . . . . . . . . . . . . 63
CMAH [7:0]
ADDRESS
DECODER
0
..
..
..
..
.
..
NVM ARRAY
(256 ROWS x 64 BYTES)
ܘኍᔗ৫ࢅᒗถᄰਭޝᄴݛମ)QBMቃ᎖36I{LjOUTDቃ
᎖41I{*Ljጲܜ༷ޝቓăࠅᄻLjᒏ࢛ቃ᎖6I{LjẮ
࢟ྏܘኍऻࡍޟLj࢜ቯᆐࡍ᎖441μGăNBY8567ଢ଼ࢅ೫
ক࢟ྏᒋLj݀ೝৈ୷ቃࡼ࢟ྏ)D PVU ਜ਼D TBH*ᄐࡔLjᎌ
ଢ଼ࢅ೫Ắ࢟ྏࡼ߅۾ਜ਼ᄏ૩Ljᄴဟࡻ೫భ၊ࡼ
ሣဟပᑞ)ܭ3*ăྙਫݙဧLjTBHೌᒗWPVUă
255
ܭ3/! TBHኀᑵ࢟ྏᒋ
CMAL [5:0]
64-BYTE SHADOW RAM
CMDI [7:0]
CMDO [7:0]
ᅄ24/! OWNஉ৩
COUT (μF)
CSAG (μF)
LINE-TIME DISTORTION
(% typ)
470
—
0.2
100
—
0.4
100
22
0.3
47
47
0.3
Ⴒືመာ)PTE*खည
22
22
0.4
PTEखညোᔊ९ࡀਜ਼ቲೡࣞࡀ)SC1–SC26*
ࡼดྏLjᒙඛጙሷႤࡼೡࣞă
10
10
0.6
PTEྜྷރআ
PTEྜྷރআᏴPTEሷႤਜ਼ၒྜྷ၁ຫቧᒄମቲኡ
ᐋăPTEᅄስྣࣞᎅPTEྜྷރআ)PTEN*ࡀᒦࡼ
PTEဍਜ਼ሆଢ଼ဟମᆡጲૺPTEྜྷރআఎਈဟମᆡ఼
ᒜăকࡀ఼ᒜPTEᅄስྣࣞਜ਼ྻཷࠈݨ0ೡࣞࠈཷᒄ
ମࡼੰăିቃဟମᒙభྣછሷႤLjࡣဵᎌభถᐐ༓
ྻཷࠈݨ0ೡࣞࠈཷăᔢᎁᒙན᎖ဣଔ።ࡼኊཇLj
ፐࠥLjభᎅઓᒙă
၁ຫၒ߲དࣅ
NBY8567۞ᐐፄᆐ3۶ࡼ၁ຫၒ߲དࣅăདࣅᔢࡍ
ၒ߲ڼ७ᆐ3/5W Q.QLjቧࡒࡉ7NI{ )ၱିቃ᎖ࢀ᎖
1/3eC*ăདࣅၒ߲భདࣅೝৈ261Ωܪᓰ၁ຫঌᏲă
࢟ኹၱିኀᑵ
ᄰਭ࢟ኹၱିኀᑵถ৫ଢ଼ࢅၒ߲Ắ࢟ྏࡼ࢟വገཇਜ਼
ᇕಯߛࡁLj݀ሣဟပᑞଢ଼ࡵభ၊ࡼၺຳă࢟ኹၱି
ኀᑵ࣪ᎌ࣪261Ω۳ሶປ࢟ᔜࡼᄴᒷ࢟಄ਜ਼ၒ߲Ắ
࢟ྏᔝ߅ࡼᄰ݆ቲࢅຫޡݗăক࢟വࡼᒏ࢛
20
ࠈቲా
TQJରྏࠈాᒙᔫෝါਜ਼PTEၫăࣗถᑽߒቖቅ
ዩਜ਼ࣗནᓨზ)TUBU*Ăመာࡀၫၒ߲)ENEP*ਜ਼ᔊ
९ࡀၫၒ߲)DNEP*ࡀă
ࣗቖݷᔫ
NBY8567ᑽߒࡉ21NI{ࡼాဟᒩ)TDML*ăᅄ26Ⴥာ
ᆐၫቖྜྷLjᅄ27ᆐ࠭NBY8567ࣗནၫă౯ࢅCSဧถ
ࠈాăᏴTDMLဍዘၫၒྜྷTEJOăࡩCSܤᆐ࢟ຳ
ဟLjၫۻჄࡀᒗၒྜྷࡀăྙਫCSᏴࠅၒᒦମܤᆐ
࢟ຳLjᐌݷࠨ۾ᔫပ૾)ھLjၫᎌۻቖྜྷࡵࡀ
ᒦ*ăCSܤᆐࢅ࢟ຳઁLjୈࢀࡗጙৈၒྜྷࡵTEJOᒦࡼ
ᔊஂLjጲཀྵࢾჅᒊቲၫࠅၒࡼಢቯă
TQJෘഎᆐ27ᆡޠLj9ᆡ)NTC*ࡔܭࡀᒍLjࢅ9ᆡ
)MTC*ࡔܭၫ)ᅄ26ਜ਼ᅄ27*ăᑚᒬᒙᎌೝৈಿᅪ༽ౚǖ
2* መာࡀषᆰჅဧࡼᔈࣅᐐቖྜྷෝါဵጙৈ9ᆡ
ݷᔫ)ᅄ32*ăࡩᒊቲመာࡀᔈࣅᐐቖྜྷݷᔫဟLj
9ᆡᒍဵดޘݝညࡼLjࠈాᒑኊገ9ᆡၫă
3* Ᏼ27ᆡᔫෝါဟLj࠭መာࡀࣗནᔊ९ၫဵ35
ᆡݷᔫ)9ᆡᒍጲૺ27ᆡၫ*Ljݬఠᅄ31ă
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
tCSW
CS
tCSS0
tCSH0
tCL
tCSS1
tCSH1
tCP
tCH
SCLK
tDS
tDH
SDIN
tDO1
tDO4
tDO2
tDO3
SDOUT
ᅄ25/! ࠈాဟኔሮၤ
CS
CS
1
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16
9
2
3
4
5
6
7
8
MSB
SCLK
MSB
SDIN
LSB
0 A6 A5 A4 A3 A2 A1 A0
9
10 11 12 13 14 15 16
SCLK
SDIN
LSB
1 A6 A5 A4 A3 A2 A1 A0
LSB
MSB
D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
D7
X
D6 D5 D4 D3 D2 D1
D0
ᅄ27/! ࣗݷᔫ
ᅄ26/! ቖݷᔫ
CS
CS
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
LSB
MSB
SCLK
SDIN
0
0
0
0
0
1
1
1
MSB
L
B
C
LSB
B
L
K
I
N
V
0
0
0
0
SDIN
0
1
1
X
0
SDOUT
ᅄ28/! Ᏼ9ᆡᔫෝါሆLjቖྜྷᔊ९ၢቶᔊஂ
1
X
X
X
X
MSB
L
B
C
LSB
B
L
K
I
N
V
0
0
0
0
0
ᅄ29/! Ᏼ9ᆡᔫෝါሆLjࣗནᔊ९ၢቶᔊஂ
______________________________________________________________________________________
21
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
CS
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16
9
SCLK
SDIN
0
0
0
0
0
1
1
1
MSB
C
A
7
C
A
6
C C
A A
5 4
C
A
3
C
A
2
C
A
1
LSB
C
A
0
ᅄ2:/! Ᏼ9ᆡਜ਼27ᆡᔫෝါሆLjቖྜྷᔊ९ᒍᔊஂ
CS
1
2
3
4
5
6
7
8
1
0
1
1
X
X
X
X
9
1
10 11 12 13 14 15 16
2
3
4
L
B
C
B
L
K
I
N
V
5
6
7
8
SCLK
SDIN
SDOUT
MSB
C
C
A
A
7
6
X
C C
A A
5 4
C
A
3
C
A
2
C
A
1
LSB
C
A
0
LSB
MSB
0
0
0
0
0
ᅄ31/! Ᏼ27ᆡᔫෝါሆLjࣗནᔊ९ᒍਜ਼ᔊ९ၢቶᔊஂ
আᆡ
CS
1
2
3
4
5
6
7
8
SCLK
MSB
SDIN
LSB
D7 D6 D5 D4 D3 D2 D1 D0
࢟আᆡ
NBY8567ࡼ࢟আᆡ࢟വ)QPS*ᄋጙৈดݝআᆡቧLj
Ᏼ࢟Ꮞ࢟ኹᆮࢾઁఎဪᔫăดݝআᆡቧჅᎌࡀ
আᆡᒗ෦ཱྀᒋLj༹߹መာࡀăࡀআᆡਭ߈ኊ
ገ211μtLjᆐܜ߲ሚݙ໐ᆃࡼஉਫLjᏴᑚ໐ମݙᏤ
ቲࣗ0ቖݷᔫăጙۅᏴ࢟࢟ኹᆮࢾLj݀༦38NI{ဟᒩቧ
ᆮࢾ61ntઁLjመာࡀআᆡLjPTEဧถăઓᏴᑚ
ࣤဟମᒦ።ܜ TQJ ݷᔫLjጲऴᒏ߲ሚݙ໐ᆃࡼஉਫă
61nt! )࢜ቯᒋ*ઁLjభއኯTUBU\7^ཀྵཱྀআᆡဟኔဵ॥ᅲ߅
)ᅄ33*ă
ᅄ32/! ᔈࣅᐐෝါሆࡼቖݷᔫ
22
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
4.75V
SUPPLY
VOLTAGE
0V
XTAL
OSCILLATOR
SPI
REGISTER
RESET
50ms
DISPLAY
MEMORY
CLEAR
50ms
100μs
20μs
POWER
ON
POWER
STABLE
CLOCK
STABLE
POWER-ON
RESET START
POR DEFAULT
STATE
ᅄ33/! ࢟আᆡၿኔ
ྟୈআᆡ
NBY8567ᎌጙৈྟୈআᆡᆡ)WN1\2^*Ljࡩকᆡۻᒙᆐ
࢟ຳဟLjመာࡀ߹༹ۻLj߹೫PTE੨࢟ຳࡀ
)PTECM*LjჅᎌࡼࡀআᆡᆐ෦ཱྀᒋă211μt! )࢜ቯᒋ*
ઁLjభއኯTUBU\7^ཀྵཱྀআᆡਭ߈ဵ॥ᅲ߅ă
፮ୈআᆡ
NBY8567ᄋጙৈ፮ୈআᆡၒྜྷ)RESET*Ljถਜ਼QPS
ሤᄴăࡩRESETۻདࣅᒗࢅ࢟ຳဟLjჅᎌࡀআᆡᒗ
෦ཱྀᒋLjݙถቲࣗ0ቖݷᔫăೂআᆡਭ߈ኊገ≥ 61nt
ࡼRESET൴ߡLjᏴᑚ໐ମݙᏤჇݷᔫăRESET
ဍዘ211μtઁLjჅᎌTQJࡀۻআᆡᒗ෦ཱྀᒋăRESET
ဍዘ31μtઁLjመာࡀࡼჅᎌᆡᒙ࣒ۻআᆡᒗ෦ཱྀ
ᒋ11IăRESETᎁሌ᎖ྟୈআᆡᆡăRESETᅲઁLj
భއኯTUBU\7^ཀྵཱྀআᆡኔဵ॥ᅲ߅ă
______________________________________________________________________________________
23
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
``````````````````````` NBY8567ࡀႁී
ᄰਭܭ4߲೫ჅᎌࡼTQJࡀषᆰNBY8567ݷᔫLj
۞౪መာࡀਜ਼ᔊ९ࡀषᆰࢀăᄰਭTQJ࣡ాݙถ
ᒇषᆰመာਜ਼ᔊ९ࡀă༿ݬఠ ።ቧᇦ ݝॊLj೫
ஊ࣪षᆰࡀჅኊࡼTQJݷᔫݛᒾႁීă
۾ၫᓾ೯ݧࡼࡀৃါᆐ SFHJTUFS`OBNF
\CJU`OVNCFST^ăಿྙLj၁ຫෝါ1ࡀࡼ2ᆡܭၤ
ᆐWN1\2^ă
ܭ4/! ࡀ፯
WRITE
ADDRESS
READ
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
00H
80H
VM0
Video Mode 0
01H
81H
VM1
Video Mode 1
02H
82H
HOS
Horizontal Offset
03H
83H
VOS
Vertical Offset
04H
84H
DMM
Display Memory Mode
05H
85H
DMAH
Display Memory Address High
06H
86H
DMAL
Display Memory Address Low
07H
87H
DMDI
Display Memory Data In
08H
88H
CMM
Character Memory Mode
Character Memory Address High
09H
89H
CMAH
0AH
8AH
CMAL
Character Memory Address Low
0BH
8BH
CMDI
Character Memory Data In
0CH
8CH
OSDM
OSD Insertion Mux
10H
90H
RB0
Row 0 Brightness
11H
91H
RB1
Row 1 Brightness
12H
92H
RB2
Row 2 Brightness
13H
93H
RB3
Row 3 Brightness
14H
94H
RB4
Row 4 Brightness
15H
95H
RB5
Row 5 Brightness
16H
96H
RB6
Row 6 Brightness
17H
97H
RB7
Row 7 Brightness
18H
98H
RB8
Row 8 Brightness
19H
99H
RB9
Row 9 Brightness
1AH
9AH
RB10
Row 10 Brightness
1BH
9BH
RB11
Row 11 Brightness
1CH
9CH
RB12
Row 12 Brightness
1DH
9DH
RB13
Row 13 Brightness
1EH
9EH
RB14
Row 14 Brightness
1FH
9FH
RB15
Row 15 Brightness
6CH
ECH
OSDBL
—
AxH
STAT
—
BxH
DMDO
Display Memory Data Out
—
CxH
CMDO
Character Memory Data Out
OSD Black Level
Status
Y! >! ᇄਈă
24
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ቖᒍ >! 11ILjࣗᒍ >! 91Iă
ࣗ0ቖषᆰǖᇄሢᒜă
2* TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
3* ENN\3^! >! 1Ljመာࡀ)TSBN*ᎌࠀ᎖ࡼ߹༹ۻਭ
߈ᒦă
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
BIT
DEFAULT
7
0
Don’t Care
FUNCTION
6
0
Video Standard Select
0 = NTSC
1 = PAL
5, 4
00
Sync Select Mode (Table 1)
0x = Autosync select (external sync when LOS = 0 and internal sync when LOS = 1)
10 = External
11 = Internal
3
0
Enable Display of OSD Image
0 = Off
1 = On
2
0
Vertical Synchronization of On-Screen Data
0 = Enable on-screen display immediately
1 = Enable on-screen display at the next VSYNC
1
0
Software Reset Bit
When this bit is set, all registers are set to their default values and the display memory is cleared.
When a stable 27MHz clock is present, this bit is automatically cleared internally after typically
100μs. The user does not need to write a 0 afterwards. SPI operations should not be performed
during this time or unpredictable results may occur. The status of the bit can be checked by
reading this register after typically 100μs. This register is not accessible for writing until the display
memory clear operation is finished (typically 20μs).
0
0
Video Buffer Enable
0 = Enable
1 = Disable (VOUT is high impedance)
Y! >! ᇄਈă
______________________________________________________________________________________
25
NBY8567
၁ຫෝါ1ࡀ)WN1*
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
၁ຫෝါ2ࡀ)WN2*
ቖᒍ >! 12ILjࣗᒍ >! 92Iă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
7
0
6, 5, 4
100
3, 2
01
1, 0
11
FUNCTION
Background Mode (See Table 4)
0 = The Local Background Control bit (see DMM[5] and DMDI[7]) sets the state of each character
background.
1 = Sets all displayed background pixels to gray. The gray level is specified by bits VM1[6:4]
below. This bit overrides the local background control bit.
Note: In internal sync mode, the background mode bit is set to 1.
Background Mode Brightness (% of OSD White Level)
000 = 0%
001 = 7%
010 = 14%
011 = 21%
100 = 28%
101 = 35%
110 = 42%
111 = 49%
Blinking Time (BT)
00 = 2 fields (33ms in NTSC mode, 40ms in PAL mode)
01 = 4 fields (67ms in NTSC mode, 80ms in PAL mode)
10 = 6 fields (100ms in NTSC mode, 120ms in PAL mode)
11 = 8 fields (133ms in NTSC mode, 160ms in PAL mode)
Blinking Duty Cycle (On : Off)
00 = BT : BT
01 = BT : (2 x BT)
10 = BT : (3 x BT)
11 = (3 x BT) : BT
ၺຳᆡᒙࡀ)IPT*
ቖᒍ >! 13ILjࣗᒍ >! 93Iă
ࣗ0ቖषᆰǖᇄሢᒜ)ᅄ34*ă
BIT
DEFAULT
7, 6
00
FUNCTION
Don’t Care
Horizontal Position Offset
(OSD video is not inserted into the horizontal blanking interval)
00 0000 = Farthest left (-32 pixels)
5–0
10 0000
10 0000 = No horizontal offset
11 1111 = Farthest right (+31 pixels)
26
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
ࠓᒇᆡᒙࡀ)WPT*
ቖᒍ >! 14ILjࣗᒍ >! 94Iă
ࣗ0ቖषᆰǖᇄሢᒜ)ᅄ34*ă
BIT
DEFAULT
7, 6, 5
000
FUNCTION
Don’t Care
Vertical Position Offset
(OSD video can be vertically shifted into the vertical blanking lines)
0 0000 = Farthest up (+16 pixels)
4–0
1 0000
1 0000 = No vertical offset
1 1111 = Farthest down (-15 pixels)
HSYNC
ROW NO.
VERTICAL POSITION OFFSET
0
HORIZONTAL POSITION OFFSET
DISPLAY AREA:
NTSC: 13 ROWS x 30 COLUMNS
PAL: 16 ROWS x 30 COLUMNS
NTSC: 234 LINES
PAL: 288 LINES
15
VSYNC
360 PIXELS
ᅄ34/! ᔊ९መာཌ
______________________________________________________________________________________
27
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
መာࡀෝါࡀ)ENN*
ቖᒍ >! 15ILjࣗᒍ >! 95Iă
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ENN\3^! >! 1Ljመာࡀᎌࠀ᎖༹߹ਭ߈ă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
7
0
FUNCTION
Don’t Care
Operation Mode Selection
6
28
0
5
0
4
0
3
0
0 = 16-bit operation mode
The 16-bit operation mode increases the speed at which the display memory can be updated.
When writing to the display memory, the attribute byte is not entered through the SPI-compatible
interface. It is entered automatically by copying DMM[5:3] to a character’s attribute byte when a
new character is written, thus reducing the number of SPI write operations per character from two to
one (Figure 19). When in this mode, all characters written to the display memory have the same
attribute byte. This mode is useful because successive characters commonly have the same
attribute. This mode is distinct from the 8-bit operation mode where a character attribute byte must
be written each time a character address byte is written to the display memory (see Table 5). When
reading data from the display memory, both the Character Address byte and Character Attribute
byte are transferred with the SPI-compatible interface (Figure 18).
1 = 8-bit operation mode
The 8-bit operation mode provides maximum flexibility when writing characters to the display
memory. This mode enables writing individual Character Attribute bytes for each character (see
Table 5). When writing to the display memory, DMAH[1] = 0 directs the data to the Character
Address byte and DMAH[1] = 1 directs the Character Attributes byte to the data. This mode is
distinct from the 16-bit operation mode where the attribute bits are automatically copied from
DMM[5:3] when a character is written.
Local Background Control Bit, LBC (see Table 4)
Applies to characters written in 16-bit operating mode.
0 = Sets the background pixels of the character to the video input (VIN) when in external sync
mode.
1 = Sets the background pixels of the character to the background mode brightness level defined
by VM1[6:4] in external or internal sync mode.
Note: In internal sync mode, the local background control bit behaves as if it is set to 1.
Blink Bit, BLK
Applies to characters written in 16-bit operating mode.
0 = Blinking off
1 = Blinking on
Note: Blinking rate and blinking duty cycle data in the Video Mode 1 (VM1) register are used for
blinking control.
In external sync mode: when the character is not displayed, VIN is displayed.
In internal sync mode: when the character is not displayed, background mode brightness is
displayed (see VM1[6:4]).
Invert Bit, INV
Applies to characters written in 16-bit operating mode (see Figure 24).
0 = Normal (white pixels display white, black pixels display black)
1 = Invert (white pixels display black, black pixels display white)
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
BIT
DEFAULT
2
0
1
0
0
0
FUNCTION
Clear Display Memory
0 = Inactive
1 = Clear (fill all display memories with zeros)
Note: This bit is automatically cleared after the operation is completed (the operation requires
20μs). The user does not need to write a 0 afterwards. The status of the bit can be checked by
reading this register.
This operation is automatically performed:
a) On power-up
b) Immediately following the rising edge of RESET
c) Immediately following the rising edge of CS after VM0[1] has been set to 1
Vertical Sync Clear
Valid only when clear display memory = 1, (DMM[2] = 1)
0 = Immediately applies the clear display-memory command, DMM[2] = 1
1 = Applies the clear display-memory command, DMM[2] = 1, at the next VSYNC time
Auto-Increment Mode
Auto-increment mode increases the speed at which the display memory can be written by
automatically incrementing the character address for each successive character written. This mode
reduces the number of SPI commands, and thus the time needed to write a string of adjacent
characters. This mode is useful when writing strings of characters written from left-to-right, top-tobottom, on the display (see Table 5).
0 = Disabled
1 = Enabled
When this bit is enabled for the first time, data in the Display Memory Address (DMAH[0] and
DMAL[7:0]) registers are used as the starting location to which the data is written. When performing
the auto-increment write for the display memory, the 8-bit address is internally generated, and
therefore only 8-bit data is required by the SPI-compatible interface (Figure 21). The content is to
be interpreted as a Character Address byte if DMAH[1] = 0 or a Character Attribute byte if
DMAH[1] = 1. This mode is disabled by writing the escape character 1111 1111.
If the Clear Display Memory bit is set, this bit is reset internally.
______________________________________________________________________________________
29
NBY8567
መာࡀෝါࡀ)ENN*! )ኚ*
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
INVERT
BIT
DMM[3]
EXTERNAL SYNC MODE AND LOCAL
BACKGROUND CONTROL BIT (LBC) = 0
INTERNAL SYNC MODE OR LOCAL
BACKGROUND CONTROL BIT (LBC) = 1
0
1
ᅄ35/! ᔊ९ၢቶᆡဣಿǖनྻਜ਼۾۳ஶ఼ᒜ
30
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
SYNC MODE
BACKGROUND MODE,
VM1[7]
LOCAL BACKGROUND
CONTROL BIT, LBC
DMM[5], DMDI[7]
CHARACTER
BACKGROUND PIXEL
0
0
Input Video
0
1
Gray
External
Internal
1
X
Gray
X
X
Gray
NBY8567
ܭ5/! ᔊ९۳ஶ఼ᒜ
Y! >! ᇄਈă
መာࡀᒍᆡࡀ)ENBI*
ቖᒍ >! 16ILjࣗᒍ >! 96Iă
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ENN\3^! >! 1Ljመာࡀᎌࠀ᎖༹߹ਭ߈ă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
7–2
0000 00
1
0
FUNCTION
Don’t Care
0
Byte Selection Bit
This bit is valid only when in the 8-bit operation mode (DMM[6] = 1).
0 = Character Address byte is written to or read (DMDI[7:0] contains the Character Address byte).
1 = Character Attribute byte is written to or read (DMDI[7:0] contains the Character Attribute byte).
0
Display Memory Address Bit 8
This bit is the MSB of the display-memory address. The display-memory address sets the location
of a character on the display (Figure 10). The lower order 8 bits of the display-memory address is
found in DMAL[7:0].
መာࡀᒍࢅᆡࡀ)ENBM*
ቖᒍ >! 17ILjࣗᒍ >! 97Iă
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ENN\3^! >! 1Ljመာࡀᎌࠀ᎖༹߹ਭ߈ă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
7–0
DEFAULT
0000 0000
FUNCTION
Display Memory Address Bits 7–0
This byte is the lower 8 bits of the display-memory address. The display-memory address sets the
location of a character on the display (Figure 10). The MSB of the display-memory address is
DMAH[0].
______________________________________________________________________________________
31
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
መာࡀၫၒྜྷࡀ)ENEJ*
ቖᒍ >! 18ILjࣗᒍ >! 98Iă
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ENN\3^! >! 1Ljመာࡀᎌࠀ᎖༹߹ਭ߈ă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
FUNCTION
Character Address or Character Attribute byte to be stored in the display memory.
7–0
0000 0000
8-Bit Operation Mode (DMM[6] = 1)
If DMAH[1] = 0, the content is to be interpreted as a Character Address byte, where
Bits 7–0 = Character Address bits, CA[7:0] (Figure 12).
If DMAH[1] = 1, the content is to be interpreted as a Character Attribute byte where
Bit 7 = Local Background Control bit, LBC (Figure 24 and Table 4)
Bit 6 = Blink bit, BLK
Bit 5 = Invert bit, INV (see Figure 24)
Bit 4–0 = 0
(The LBC, BLK, and INV bits are described in the Display Memory Mode register.)
16-Bit Operation Mode (DMM[6] = 0)
The content is always interpreted as a Character Address byte where bits 7–0 =
CA[7:0] (Figure 12).
Auto-Increment Mode (DMM[0] = 1)
The character address CA[7:0] = FFH is reserved for use as an escape character that terminates
the auto-increment mode. Therefore, the character located at address FFH is not available for
writing to the display memory when in auto-increment mode. In all other modes, character FFH is
available.
32
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ቖᒍ >! 19ILjࣗᒍ >! 99Iă
2*! TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
ࣗ0ቖषᆰǖᇄሢᒜă
3*! WN1\4^! >! 1LjPTEۻணᒏă
BIT
DEFAULT
FUNCTION
Only whole characters (54 bytes) can be written to or read from the nonvolatile character memory
(NVM) at one time. This is done through the (64 byte) shadow RAM (Figure 13). The shadow RAM is
accessed through the SPI port one byte at a time. The shadow RAM is written to and read from
NVM by the following procedures:
Writing to NVM
1010 XXXX = Write to NVM array from shadow RAM.
The 64 bytes from shadow RAM are written to the NVM array at the character-memory address
location (CMAH, CMAL) (Figure 13). The character memory is busy for approximately 12ms during
this operation. During this time, STAT[5] is automatically set to 1. The Character Memory Mode
register is cleared and STAT[5] is reset to 0 after the write operation has been completed. The user
does not need to write zeros afterwards.
7–0
0000 0000
Reading from NVM
0101 XXXX = Read from NVM array into shadow RAM.
The 64 bytes corresponding to the character-memory address (CMAH, CMAL) are read from the
NVM array into the shadow RAM (Figure 13). The character memory is busy for approximately 0.5μs
during this operation. The CMM register is cleared after the operation is completed. The user does
not need to write zeros afterwards. During this time, STAT[5] is automatically set to 1. STAT[5] is
reset to 0 when the read operation has been complete.
If the display has been enabled (VM0[3] = 1) or the character memory is busy (STAT[5] = 1), NVM
read/write operation commands are ignored and the corresponding registers are not updated.
However, all the registers can be read at any time.
For all the character-memory operations, the character address is formed with Character Memory
Address High (CMAH[7:0]) and Character Memory Address Low (CMAL[7:0]) register bits (Figures
11, 12, and 13).
Y! >! ᇄਈă
______________________________________________________________________________________
33
NBY8567
ᔊ९ࡀෝါࡀ)DNN*
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ᔊ९ࡀᒍᆡࡀ)DNBI*
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ቖᒍ >! 1:ILjࣗᒍ >! 9:Iă
2*! TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
ࣗ0ቖषᆰǖᇄሢᒜă
3*! WN1\4^! >! 1LjPTEۻணᒏă
BIT
DEFAULT
7–0
0000 0000
FUNCTION
Character Memory Address Bits
These 8 bits point to a character in the character memory (256 characters total in NVM) (Figures 10
and 12).
ᔊ९ࡀᒍࢅᆡࡀ)DNBM*
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ቖᒍ >! 1BILjࣗᒍ >! 9BIă
2*! TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
ࣗ0ቖषᆰǖᇄሢᒜă
3*! WN1\4^! >! 1LjPTEۻணᒏă
BIT
DEFAULT
7, 6
00
5–0
00 0000
FUNCTION
Don’t Care
Character Memory Address Bits
These 6 bits point to one of the 64 bytes (only 54 used) that represent a 4-pixel group in the
character (Figures 10 and 11).
ᔊ९ࡀၫၒྜྷࡀ)DNEJ*
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ቖᒍ >! 1CILjࣗᒍ >! 9CIă
2*! TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
ࣗ0ቖषᆰǖᇄሢᒜă
3*! WN1\4^! >! 1LjPTEۻணᒏă
BIT
DEFAULT
7, 6
NA
Leftmost pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
FUNCTION
5, 4
NA
Left center pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
3, 2
NA
Right center pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
1, 0
NA
Rightmost pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
OB! >! ݙးă
34
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
PTEྜྷރআࡀ)PTEN*
ቖᒍ >! 1DILjࣗᒍ >! 9DIă
ࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
7, 6
00
5, 4, 3
011
2, 1, 0
011
FUNCTION
Don’t Care
OSD Rise and Fall Time—typical transition times between adjacent OSD pixels
000: 20ns (maximum sharpness/maximum crosscolor artifacts )
001: 30ns
010: 35ns
011: 60ns
100: 80ns
101: 110ns (minimum sharpness/minimum crosscolor artifacts)
OSD Insertion Mux Switching Time–typical transition times between input video and OSD pixels
000: 30ns (maximum sharpness/maximum crosscolor artifacts )
001: 35ns
010: 50ns
011: 75ns
100: 100ns
101: 120ns (minimum sharpness/minimum crosscolor artifacts)
Oቲೡࣞࡀ)SC1–SC26*
ᒍ >! 21I! ,! ቲǗቖᒍ >! 21Iᒗ2GILjࣗᒍ >! :1I
ᒗ:GILjࣗ0ቖषᆰǖᇄሢᒜă
BIT
DEFAULT
7–4
0000
3, 2
00
1, 0
01
ጙቲࡼቲᆐ1LjᔢઁጙቲࡼቲᏴOUTDᒜါᒦᆐ24Lj
ᏴQBMᒜါᒦᆐ26 )༿ݬఠᅄ34*ă
FUNCTION
Don’t Care
Character Black Level —All the characters in row N use these brightness levels for the black pixel,
in % of OSD white level.
00 = 0%
01 = 10%
10 = 20%
11 = 30%
Character White Level —All the characters in row N use these brightness levels for the white pixel,
in % of OSD white level.
00 = 120%
01 = 100%
10 = 90%
11 = 80%
______________________________________________________________________________________
35
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
PTE੨࢟ຳࡀ)PTECM*
ቖᒍ >! 7DILjࣗᒍ >! FDIă
ቲኀখăፐࠥLjኀখ5ᆡဟLj၅ሌࣗནকࡀLj
ኀখ5ᆡLjઁቖૄৎቤઁࡼᔊஂă
ࣗ0ቖषᆰǖকࡀᎌ5ৈޣᎾࡼᆡ\4;1^Ljݙถ࣪
BIT
DEFAULT
7–5
000
4
1
0–3
xxxx
FUNCTION
Don’t Care
OSD Image Black Level Control
This bit enables the alignment of the OSD image black level with the input image black level at
VOUT. Always enable this bit following power-on reset to ensure the correct OSD image brightness.
0 = Enable automatic OSD black level control
1 = Disable automatic OSD black level control
These bits are factory preset. To ensure proper operation of the MAX7456, do not change the
values of these bits.
yyyy! >! ޣᎾ—భถဵ27ৈᒋࡼྀੜጙৈăᑚጙၫᒋۻ፼ࡀᏴNBY8567ᒦLj࢟আᆡᑗ፮ୈআᆡઁLjᔐဵૂۻআᆐޣᎾ
ᒋă
ᓨზࡀ)TUBU*
ࣗᒍ >! ByIă
ࣗ0ቖषᆰǖᒑࣗă
BIT
DEFAULT
7
NA
Don’t Care
FUNCTION
6
NA
Reset Mode
0 = Clear when power-up reset mode is complete. Occurs 50ms (typ) following stable VDD (Figure 22)
1 = Set when in power-up reset mode
5
NA
Character Memory Status
0 = Available to be written to or read from
1 = Unavailable to be written to or read from
4
NA
VSYNC Output Level
0 = Active during vertical sync time
1 = Inactive otherwise
3
NA
HSYNC Output Level
0 = Active during horizontal sync time
1 = Inactive otherwise
2
NA
Loss-of-Sync (LOS)
0 = Sync Active. Asserted after 32 consecutive input video lines.
1 = No Sync. Asserted after 32 consecutive missing input video lines.
1
NA
0 = NTSC signal is not detected at VIN
1 = NTSC signal is detected at VIN
0
NA
0 = PAL signal is not detected at VIN
1 = PAL signal is detected at VIN
OB! >! ݙးă
Y! >! ᇄਈă
36
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
NBY8567
መာࡀၫၒ߲ࡀ)ENEP*
ENN\3^! >! 1Ljመာࡀᎌࠀ᎖༹߹ਭ߈ă
ࣗᒍ >! CyIă
ࣗ0ቖषᆰǖᒑࣗă
BIT
DEFAULT
FUNCTION
Character Address or Character Attribute byte to be read from the display memory.
7–0
NA
8-Bit Operation Mode (DMM[6] = 1):
If DMAH[1] = 0, the content is to be interpreted as a Character Address byte, where
Bits 7–0 = Character Address bits, CA[7:0] (Figure 12)
If DMAH[1] = 1, the content is to be interpreted as a Character Attribute byte where
Bit 7 = Local Background Control bit, LBC (see Figure 24 and Table 4)
Bit 6 = Blink bit, BLK
Bit 5 = Invert bit, INV (see Figure 24)
Bit 4–0 = 0
The LBC, BLK, and INV bits are described in the Display Memory Mode register.
16-Bit Operation Mode (DMM[6] = 0):
The content is to be interpreted as a Character Address byte, where
Bits 7–0 = CA[7:0] (see Figure 12)
followed by a Character Attribute byte, where
Bit 7 = 0
Bit 6 = Local Background Control bit, LBC (see Figure 24 and Table 4)
Bit 5 = Blink bit, BLK
Bit 4 = Invert bit, INV (see Figure 24)
Bit 3–0 = 0
The LBC, BLK, and INV bits are described in the Display Memory Mode register.
OB! >! ݙးă
Y! >! ᇄਈă
ᔊ९ࡀၫၒ߲ࡀ)DNEP*
ቖྜྷকࡀဟLjܘኍ൸ᔗጲሆᄟୈǖ
ࣗᒍ >! DyIă
2*! TUBU\6^! >! 1Ljᔊ९ࡀ)OWN*ݙංă
ࣗ0ቖषᆰǖᒑࣗă
3*! WN1\4^! >! 1LjPTEۻணᒏă
BIT
DEFAULT
FUNCTION
7, 6
NA
Leftmost pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
5, 4
NA
Left center pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
3, 2
NA
Right center pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
1, 0
NA
Rightmost pixel. 00 = Black, 10 = White, 01 or 11 = Transparent (see Figure 11)
OB! >! ݙးă
Y! >! ᇄਈă
______________________________________________________________________________________
37
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
``````````````````````````````` ።ቧᇦ
ᔊ९ࡀݷᔫ
ጙࠨᒑถ࠭OWNᔊ९ࡀቖྜྷᑗࣗནཝݝᔊ९)65ᔊ
ஂࡼሷႤၫ*ăᑚభጲᄰਭ)75ᔊஂ*ስSBNဣሚ)༿ݬ
ఠᅄ24*ăᄰਭTQJ࣡ాLjඛࠨषᆰስSBNࡼጙৈᔊஂă
ᄰਭጙᄟTQJෘഎ࠭OWNቖྜྷᑗࣗནስSBNă
:* ቖྜྷDNN\8;1^ > 2121yyyyLjስSBNၫቖྜྷࡵ
OWNᒦ)ᅄ24*ăᏴᑚጙݷᔫਭ߈ᒦLjᔊ९ࡀංࡼ
ဟମ࢜ቯᆐ23ntăభጲࣗནTUBU\6^ཀྵཱྀOWNቖਭ߈
ဵ॥ᅲ߅ă
21* ቖྜྷWN1\4^ > 2LjဧถPTEᅄስመာă
࠭ᔊ९ࡀࣗནᔊ९ᔊஂࡼݛᒾ
2* ቖྜྷWN1\4^ > 1LjணᒏPTEᅄስă
ሶOWNᔊ९ࡀቖྜྷᔊ९ᔊஂࡼݛᒾ
ቖྜྷጙৈቤᔊ९ǖ
3* ቖྜྷDNBI\8;1^ > yyILjኡᐋገࣗནࡼᔊ९)1–366* )ᅄ
21ਜ਼ᅄ24*ă
2* ቖྜྷWN1\4^ > 1LjணᒏPTEᅄስመာă
4* ቖྜྷDNN\8;1^ > 1212yyyyLjᔊ९ၫ࠭OWNࣗྜྷࡵ
ስSBNᒦ)ᅄ24*ă
3* ቖྜྷDNBI\8;1^ > yyILjኡᐋገቖྜྷࡼᔊ९)1–366* )ᅄ
21ਜ਼ᅄ24*ă
4* ቖྜྷDNBM\8;1^ > yyILjኡᐋገቖྜྷᔊ९ᒦࡼ5ৈሷႤ
ᔊஂ)1–74* )ᅄ21ਜ਼ᅄ24*ă
5* ቖྜྷDNEJ\8;1^ > yyILjᒙᔊ९ჅኡݝॊࡼሷႤᒋ
)ᅄ22ਜ਼ᅄ24*ă
6* ᒮআݛᒾ4ਜ਼ݛᒾ5Ljᒇࡵᔊ९ၫࡼჅᎌ65ৈᔊஂۻ
ᓤྜྷࡵስSBNᒦă
7* ቖྜྷDNN\8;1^ > 2121yyyyLj࠭ስSBNቖྜྷࡵOWN
ᑫᒦ)ᅄ24*ăᏴᑚጙݷᔫਭ߈ᒦLjᔊ९ࡀංဟ
ମࡍᏖᆐ23ntăభጲࣗནTUBU\6^ཀྵཱྀOWNቖਭ߈ဵ
॥ᅲ߅ă
8* ቖྜྷWN1\4^ > 2LjဧถPTEᅄስመာă
ኀখጯᎌࡼᔊ९ǖ
2* ቖྜྷWN1\4^ > 1LjணᒏPTEᅄስመာă
3* ቖྜྷDNBI\8;1^ > yyILjኡᐋገኀখࡼᔊ९)1–366* )ᅄ
21ਜ਼ᅄ24*ă
4* ቖྜྷDNN\8;1^ > 1212yyyyLjᔊ९ၫ࠭OWNࣗྜྷࡵ
ስSBNᒦ)ᅄ24*ă
5* ቖྜྷDNBM\8;1^ > yyILjኡᐋገኀখࡼᔊ९ᒦࡼ5ৈሷ
Ⴄᔊஂ)1–74* )ᅄ21ਜ਼ᅄ24*ă
6* ࣗནDNEP\8;1^ > yyILjࣗནገኀখࡼ5ৈሷႤၫᔊ
ஂ)ᅄ22ਜ਼ᅄ24*ă
7* োገཇኀখ5ሷႤᔊஂă
8* ቖྜྷDNEJ\8;1^ > yyILjኀখઁࡼ5ሷႤၫᔊஂቖ
ૄࡵስSBNᒦ)ᅄ22ਜ਼ᅄ24*ă
9* োኊገᒮআݛᒾ5ࡵݛᒾ8LjᒇࡵჅᎌࡼሷႤᓤྜྷࡵ
ስSBNᒦă
38
5* ቖྜྷDNBM\8;1^ > yyILjኡᐋገࣗནࡼᔊ९ᒦࡼ5ৈሷ
Ⴄᔊஂ)1–74* )ᅄ21ਜ਼ᅄ24*ă
6* ࣗནDNEP\8;1^ > yyILjࣗནၫࡼჅኡ5ৈሷႤᔊஂ
)ᅄ22ਜ਼ᅄ24*ă
7* ᒮআݛᒾ5ਜ਼ݛᒾ6Ljࣗན5ሷႤၫࡼჇᔊஂă
8* ቖྜྷWN1\4^ > 2LjဧถPTEᅄስመာă
መာࡀݷᔫ
ጲሆೝৈݛᒾᑽߒ࣪PTEᅄስࡼއఘăࣗቖመာࡀ
ဟݙኊገᑚቋݛᒾǖ
2* ቖྜྷWN1\4^ > 2LjဧถPTEᅄስመာă
3* ቖྜྷPTECM\5^ > 1LjဧถᔈࣅPTE੨࢟ຳ఼ᒜăᑚۣ
ᑺ೫ᑵཀྵࡼPTEᅄስೡࣞăকࡀᎌ5ৈޣᎾ
ࡼᆡ\4;1^LjݙถኀখᑚቋᆡăፐࠥLjኀখ5ᆡဟLj
၅ሌࣗནPTECM\8;1^Ljኀখ5ᆡLjઁቖૄৎቤઁ
ࡼᔊஂă
༹߹መာࡀݛᒾ
ቖྜྷENN\3^ > 2Ljጲࣅ༹߹መာࡀݷᔫăᑚጙݷᔫ
ጙۅኊገ31μtăᏴ༹߹ݷᔫᅲ߅ᒄ༄LjݙถᏳࠨቖྜྷመ
ာࡀෝါࡀăݷᔫᅲ߅ઁLjENN\3^ۻᔈࣅআᆡ
ᒗഃă
Ᏼ9ᆡෝါሆLjቖྜྷመာࡀࡼݛᒾ
ሶመာࡀቖྜྷᔊ९ဟLj9ᆡᔫෝါᔢഉăᑚጙෝ
ါᑽߒᆐඛጙᔊ९ቖྜྷࣖࡼᔊ९ၢቶᔊஂ)༿ݬఠܭ6*ă
ᑚጙෝါݙᄴ᎖27ᆡᔫෝါLjᏴ27ᆡᔫෝါሆLjࡩ
ቖྜྷጙৈᔊ९ဟLj࠭ENN\6;4^ᔈࣅআᒜᔊ९ၢቶᔊஂ
)ᅄ2:*ă
ቖྜྷENN\7^ > 2Ljኡᐋ9ᆡᔫෝါă
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
2* ቖྜྷENBI\2^ > 1Ljጲቖྜྷᔊ९ᒍᔊஂă
3* ቖྜྷENBI\1^ > yLjጲኡᐋNTCLjቖྜྷENBM\8;1^ >
yyILjጲኡᐋገቖྜྷᔊ९ၫᒍࡼࢅᆡၫăক
ᒍཀྵࢾ೫ᔊ९Ᏼመာࡼᆡᒙ)༿ݬఠᅄ21*ă
4* ገቖྜྷመာࡀࡼᔊ९ᒍᔊஂ)DB\8;1^*ቖྜྷࡵ
ENEJ\8;1^ᒦ)༿ݬఠᅄ21Ăᅄ23ਜ਼ᅄ2:*ă
ᏴᔈࣅᐐෝါᒦLjቖྜྷመာࡀࡼݛᒾ
ᔈࣅᐐෝါᔈࣅᐐඛጙೌኚቖྜྷᔊ९ࡼᔊ९ᒍLj
࠭ऎᄋ೫ቖྜྷመာࡀࡼႥࣞăᏴመာ࠭ᔧᒗ
ᎎLj࠭ᒗሆቖᔊ९ࠈဟLjభݧকෝါăᑚጙෝါି
೫TQJෘഎࡼၫ)༿ݬఠܭ6*ă
9ᆡᔫෝါဟǖ
2* ቖྜྷENN\1^ > 2Ljᒙᔈࣅᐐෝါă
ሶመာࡀቖྜྷᔊ९ၢቶᔊஂǖ
3* ቖྜྷENN\7^ > 2Ljᒙ9ᆡᔫෝါă
2* ቖྜྷENBI\2^ > 2Ljጲቖྜྷᔊ९ၢቶᔊஂă
4* ቖྜྷENBI\2^ > 1Ljኡᐋဵ॥ቖྜྷጙৈᔊ९ᒍᔊஂLj
ᑗENBI\2^ > 2Ljኡᐋဵ॥ቖྜྷጙৈᔊ९ၢቶᔊஂă
3* ቖྜྷENBI\1^ > yLjኡᐋNTCLjቖྜྷENBM\8;1^ > yyILj
ጲኡᐋገቖྜྷᔊ९ၫᒍࡼࢅᆡၫăকᒍཀྵࢾ
೫ᔊ९Ᏼመာࡼᆡᒙ)ᅄ21*ă
4* ገቖྜྷመာࡀࡼᔊ९ၢቶᔊஂቖྜྷࡵENEJ\8;1^
ᒦ)༿ݬఠᅄ21ਜ਼ᅄ2:*ă
Ᏼ27ᆡෝါሆLjቖྜྷመာࡀࡼݛᒾ
27ᆡᔫෝါᄋ೫መာࡀၮቤൈăᑚဵፐᆐLjቖ
ྜྷጙৈቤᔊ९ဟLjENN\6;4^ᔈࣅআᒜࡵᔊ९ၢቶᔊஂLj
࠭ऎڳඛৈᔊ९TQJቖݷᔫࡼࠨၫᎅೝࠨଢ଼ࡵጙࠨ)ᅄ2:*ă
ᏴᑚጙෝါሆLjჅᎌቖྜྷመာࡀࡼᔊ९࣒ᎌሤᄴࡼ
ၢቶᔊஂăকෝါ੪ᎌLjፐᆐೌኚᔊ९ᄰޟᎌሤᄴࡼ
ၢቶăকෝါݙᄴ᎖9ᆡᔫෝါLj9ᆡᔫෝါሆLjࡩ
ᔊ९ᒍᔊஂඛࠨቖྜྷࡵመာࡀဟLjܘኍቖྜྷᔊ९
ၢቶᔊஂ)༿ݬఠܭ6*ă
2* ቖྜྷENN\7^ > 1Ljኡᐋ27ᆡᔫෝါă
3* ቖྜྷENN\6;4^ > yyyLjᒙ۾۳ஶ఼ᒜ)MCD*Ă࿑ႄ
)CML*ਜ਼नྻ)JOW*ၢቶᆡLjᏴ27ᆡᔫෝါဟLjᑚቋ
ᒙ።᎖ቖྜྷࡵመာࡀࡼჅᎌᔊ९ă
4* ቖྜྷENBI\1^ > yLjኡᐋገቖྜྷᔊ९ၫᒍࡼNTCLj
ቖྜྷENBM\8;1^ > yyILjኡᐋࢅᆡᒍăকᒍཀྵࢾ
ᔊ९Ᏼመာࡼᆡᒙ)༿ݬఠᅄ21*ă
5* ገቖྜྷࡵመာࡀࡼᔊ९ᒍᔊஂ)DB\8;1^*ቖྜྷ
ࡵENEJ\8;1^ᒦăጙ݀ࡀᑚቋᔊஂਜ਼ᔈENN\6;4^
ࡼᔊ९ၢቶᔊஂ)ᅄ23ਜ਼ᅄ2:*ă
5* ቖྜྷENBI\1^ > yLjᔈࣅᐐᔫဟLjኡᐋဪᒍ
ࡼNTCLjቖྜྷENBM\8;1^Ljኡᐋဪᒍࡼࢅᆡᒍ
ၫăকᒍཀྵࢾᔊ९Ᏼመာࡼᆡᒙ)༿ݬఠᅄ
21ਜ਼ᅄ32*ă
6* ቖྜྷENEJ\8;1^Ljᔊ९ၫ)ᔊ९ᒍᑗᔊ९ၢቶ
ᔊஂ*ࡀࡵࡩ༄ࡼመာࡀᒍᒦăቖݷᔫᒄઁLj
መာࡀᒍᔈࣅᐐăᏴመာ࠭ᔧᒗᎎLj࠭
ᒗሆೌኚቖྜྷઁኚᔊ९)༿ݬఠᅄ21*ăᒮআᑚጙݛ
ᒾLjᒇࡵመာࡀᒍᆘă
7* ቖྜྷENEJ\8;1^ > GGILjஉၦᔈࣅᐐෝါăᓖፀLjᏴ
ᔈࣅᐐෝါሆLjݙถဧࡀᏴDB\8;1^ > GGIࡼ
ᔊ९ă
27ᆡᔫෝါဟǖ
2* ቖྜྷENN\1^ > 2Ljᒙᔈࣅᐐෝါă
3* ቖྜྷENN\7^ > 1Ljᒙ27ᆡᔫෝါă
4* ቖྜྷENN\6;4^ > yyyLjᒙ።᎖Ⴥᎌᔊ९ࡼ۾
۳ஶ఼ᒜ)MCD*Ă࿑ႄ)CML*ਜ਼नྻ)JOW*ၢቶᆡă
5* ቖྜྷENBI\1^ > yLjኡᐋᔈࣅᐐᔫဟဪᒍࡼ
NTCLjቖྜྷ ENBM\8;1^Ljኡᐋဪᒍࡼࢅᆡᒍ
ၫăকᒍཀྵࢾᔊ९Ᏼመာࡼᆡᒙ)༿ݬఠᅄ
21ਜ਼ᅄ32*ă
______________________________________________________________________________________
39
NBY8567
ሶመာࡀቖྜྷᔊ९ᒍᔊஂǖ
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
6* ገቖྜྷࡵመာࡀࡼᔊ९ᒍᔊஂ)DB\8;1^*ቖྜྷ
ࡵENEJ\8;1^ᒦăᑚቋᄴᔈENN\6;4^ࡼᔊ९ၢቶ
ᔊஂጙ݀ࡀ)༿ݬఠᅄ2:*ăቖݷᔫᒄઁLjᔈࣅᐐ
መာࡀᒍăᒮআᑚጙݛᒾLjᒇࡵመာࡀ
ᒍᆘă
7* ቖྜྷ ENEJ\8;1^ > GGILjஉၦᔈࣅᐐෝါăᓖፀLj
ᏴᔈࣅᐐෝါဟLjݙถဧࡀᏴDB\8;1^ > GGIࡼ
ᔊ९ă
9ᆡෝါሆLjࣗནመာࡀࡼݛᒾ
2* ቖྜྷENN\7^ > 2Ljኡᐋ9ᆡᔫෝါă
3* ቖྜྷ ENBI\2^ > 1Ljࣗནᔊ९ᒍᔊஂLjᑗቖྜྷ
ENBI\2^ > 2Ljࣗནᔊ९ၢቶᔊஂă
4* ቖྜྷENBI\1^LjኡᐋኊገࣗནၫࡼᒍNTC )ᅄ21*ă
5* ቖྜྷENBM\8;1^LjኡᐋኊገࣗནၫᒍࡼNTCጲᅪ
ࡼࢅᆡၫ)ᅄ21*ă
6* ࣗནENEP\8;1^Lj࠭መာࡀᒦࡼჅኡᆡᒙࣗནၫ
)ᅄ21*ă
27ᆡෝါሆLjࣗནመာࡀࡼݛᒾ
2* ቖྜྷENN\7^ > 1Ljኡᐋ27ᆡᔫෝါă
3* ቖྜྷENBI\1^ > yLjኡᐋገࣗནᔊ९ၫᒍࡼNTCLj
ቖྜྷENBM\8;1^ > yyILjኡᐋᒍࡼࢅᆡၫăক
ᒍཀྵࢾᔊ९Ᏼመာࡼᆡᒙ)༿ݬఠᅄ21*ă
4* ࣗནENEP\26;1^Lj࠭መာࡀᒦჅኡᆡᒙࣗནᔊ९
ᒍᔊஂਜ਼ᔊ९ၢቶᔊஂăጙৈၫᔊஂဵᔊ९
ᒍ)DB\8;1^*Ljऔৈᔊஂ۞ᔊ९ၢቶᆡ)ᅄ31*ăᓖ
ፀLjࣗནݷᔫဟLjᔊ९ၢቶᔊஂࡼᆡݙᄴ᎖ቖྜྷ
ݷᔫဟࡼᆡă༿ݬఠመာࡀၫၒ߲ࡀ
)ENEP* ݝॊਜ਼ᅄ31Lj೫ஊࣗནݷᔫဟ࣪ၢቶᆡᒦᆡ
ႁීă
ᓖፀǖྙਫดݝመာࡀࣗݷᔫ༿ཇਜ਼TQJመာࡀݷ
ᔫᄴဟखညLjᐌดݷࣗݝᔫ༿ཇLjᏴᑚࣤဟମดLj
ᔊ९መာభถ્ၾဟڗܤă༿ݬఠᄴݛPTEৎቤݝॊă
ᄴݛPTEৎቤ
ྙਫดݝመာࡀࣗݷᔫ༿ཇਜ਼TQJመာࡀݷᔫᄴ
ဟखညLjᔊ९መာ્ၾဟڗܤăᏴޝሿମ໐ମቖྜྷ
መာࡀభጲऴᒏPTEᅄስၾဟڗܤăဧVSYNCᔫ
ᆐᓍ૦ࠀಯᒦࣥLjࣅሶመာࡀቲቖݷᔫጲဣ
ሚᑚጙถăᑗLjᏴቖྜྷመာࡀᒄ༄Ljభᄴݛண
ᒏPTEᅄስLjቖྜྷᒄઁᏳᄴݛဧถ)༿ݬఠWN1\4;3^*ă
ᎌৢဟᒩࡼࣶৈPTE
NBY8567ᄋጙৈUUMဟᒩၒ߲)DMLPVU*Ljభདࣅጙ
ৈNBY8567ࡼDMLJO୭ăဧᅪݝဟᒩདࣅభདࣅ
ೝৈᑗࣶৈNBY8567Ꮔୈăᑚᒬڔభᄰਭጙຢࡒᎌ
ᑩࡼNBY8567ᆐࣶৈNBY8567ᏄୈᄋဟᒩቧLjଢ଼
ࢅᇹᄻ߅)۾ᅄ36*/
ܭ6/! መာࡀषᆰෝါਜ਼TQJݷᔫ
OPERATING
MODE
40
AUTO-INCREMENT
MODE DISABLED
DMM[0] = 0
No. OF READ
OPERATIONS
No. OF WRITE
OPERATIONS
AUTO-INCREMENT
MODE ENABLED
DMM[0] = 1
No. OF WRITE
OPERATIONS
16-Bit Mode
DMM[6] = 0
One-time setup
2
1
One-time setup
6
Per character
3
3
Per character
1
8-Bit Mode
DMM[6] = 1
One-time setup
1
1
One-time setup
6
Per character
6
6
Per character
1
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
NBY8567
+
+5V
MAX7456
+5V
0.1μF
27MHz
1
N.C. 28
N.C.
N.C. 27
2
N.C.
3
DVDD
VOUT 26
4
DGND
SAG 25
5
CLKIN
PVDD 24
6
XFB
7
CLKOUT
CS1
8
CS
AVDD 21
SDIN
9
SDIN
AGND 20
SCLK
10 SCLK
RESET 19
SDOUT
11 SDOUT
HSYNC 18
12 LOS
VSYNC 17
13 N.C.
N.C. 16
14 N.C.
N.C. 15
COUT
75Ω CVBS OUT1
CSAG
0.1μF
PGND 23
0.1μF
CVBS IN1
VIN 22
0.1μF
75Ω
+5V
1kΩ
1kΩ
1kΩ
HS1
VS1
LOS1
+
+5V
0.1μF
MAX7456
+5V
1
N.C.
N.C. 28
2
N.C.
N.C. 27
3
DVDD
VOUT 26
4
DGND
SAG 25
5
CLKIN
PVDD 24
COUT
75Ω
CVBS OUT2
CSAG
0.1μF
CLOCK
DRIVER
CS2
6
XFB
7
CLKOUT
8
CS
AVDD 21
9
SDIN
AGND 20
PGND 23
0.1μF
CVBS IN2
VIN 22
10 SCLK
RESET 19
11 SDOUT
HSYNC 18
12 LOS
VSYNC 17
13 N.C.
N.C. 16
14 N.C.
N.C. 15
75Ω
0.1μF
+5V
1kΩ
1kΩ
1kΩ
HS2
VS2
LOS2
TO OTHER
MAX7456 PARTS
AS NEEDED
ᅄ36/! ࢜ቯࡼᎌተဟᒩࡼࣶৈPTE
______________________________________________________________________________________
41
NBY8567
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
ဟᒩᄏኡᐋ
``````````````````````````````` ୭ᒙ
ኡᐋጙৈ38NI{݀ೊቕᑩࡼຫෝါᄏLjݙኊገᅪݝ
ঌᏲ࢟ྏăຢด۞೫QjfsdfᑩኊገࡼჅᎌ࢟ྏă
TOP VIEW
࢟Ꮞਜ਼വ
NBY8567ݧྯᄟࣖೂࡼ࢟Ꮞሣവăඛጙ࢟Ꮞ࢟ኹܘኍ
Ᏼ,5/86Wᒗ,6/36Wपᆍดăၫᔊ࢟Ꮞਜ਼ෝผ࢟Ꮞጲૺ၁
ຫདࣅ࢟ᏎሣവॊఎLjጲऴᒏຫၫᔊᐅဉẮᒗ၁
ຫၒ߲ăჅᎌྯৈ࢟Ꮞ࣒።ᎌᄴዹࡼᒇഗ࢟ኹăݧ
1/2μG࢟ྏඛጙ࢟ᏎവᒗLj።భถణதJD୭ह
ᒙক࢟ྏăୈᎌ࢟Ꮞኔገཇă
ݚఠ
ᆐဣሚᔢଛቶถLj።భถჁWJOਜ਼WPVUᔓሣăჅ
ᎌୣഗẮ࢟ྏਜ਼86Ωປ࢟ᔜణதୈहᒙLj࢟ᔜ࣡
᎖భణࡼෝผຳෂăᎅ᎖NBY8567! UTTPQॖᓤሆෂᎌ
ൡ)FQ*LjፐࠥLjᏴॖᓤሆෂݙገᔓሣLjጲऴᒏ߲ሚ
വăݬఠNBY8567ຶৰۇᔫᆐQDCݚဣಿă
ᆐࡉࡵྲེࡼLj።FQೌᒗQDCᏄୈݾᄴዹߛࡁࡼ
ăকᄰਭଂৈࣜೌᒗݾᄵށLjጲ
ܣୈྲེăݾᄵཌෂ૩።܈FQཌࡍăፇ
FQೌᒗLjࡣܘဵݙኍࡼăݙገڳFQᔫᆐୈࡼᆎጙ
ೌă
+
N.C. 1
28 N.C.
N.C. 2
27 N.C.
DVDD 3
26 VOUT
DGND 4
25 SAG
CLKIN 5
XFB 6
MAX7456
CLKOUT 7
24 PVDD
23 PGND
22 VIN
CS 8
21 AVDD
SDIN 9
20 AGND
SCLK 10
19 RESET
SDOUT 11
18 HSYNC
LOS 12
17 VSYNC
N.C. 13
16 N.C.
N.C. 14
15 N.C.
TSSOP
``````````````````````````````` በຢቧᇦ
PROCESS: BiCMOS
42
______________________________________________________________________________________
ૹ߅೫FFQSPNࡼ
ᄰࡸĂྻႲືመာ
TSSOP 4.4mm BODY.EPS
AA AA
Nbyjn ۱யࠀူێ
۱ய 9439ቧረ ᎆᑶܠ൩ 211194
ॅ࢟જǖ911!921!1421
࢟જǖ121.7322 62::
ࠅᑞǖ121.7322 63::
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