Intel® Xeon® Processor E74800/8800 v3 Product Families
Datasheet - Volume 1: Electrical, Mechanical and Thermal
May 2015
Reference Number: 332314-001US
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Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume1: EMTS, May 2015
Table of Contents
1
Overview ................................................................................................................... 7
1.1
Introduction ....................................................................................................... 7
1.1.1 Processor Feature Details .......................................................................... 7
1.1.2 Supported Technologies ............................................................................ 7
1.2
Interfaces .......................................................................................................... 8
1.2.1 System Memory Support ........................................................................... 8
1.2.2 PCI Express* ........................................................................................... 8
1.2.3 Direct Media Interface Gen 2 (DMI2)........................................................... 9
1.2.4 Intel® QuickPath Interconnect (Intel® QPI) .............................................. 10
1.2.5 Platform Environment Control Interface (PECI) ........................................... 10
1.3
Power Management Support ............................................................................... 10
1.3.1 Processor Package and Core States........................................................... 10
1.3.2 System States Support ........................................................................... 11
1.3.3 Memory Controller.................................................................................. 11
1.3.4 PCI Express* ......................................................................................... 11
1.3.5 Intel® QPI ............................................................................................ 11
1.4
Thermal Management Support ............................................................................ 11
1.5
Package Summary............................................................................................. 11
1.6
Terminology ..................................................................................................... 11
1.7
Related Documents ........................................................................................... 14
1.8
State of Data .................................................................................................... 14
2
Electrical Specifications ........................................................................................... 15
2.1
Processor Signaling ........................................................................................... 15
2.1.1 System Memory Interface Signal Groups ................................................... 15
2.1.2 PCI Express Signals ................................................................................ 15
2.1.3 DMI2/PCI Express Signals ....................................................................... 15
2.1.4 Intel® QuickPath Interconnect (Intel® QPI) ............................................... 15
2.1.5 Platform Environmental Control Interface (PECI) ........................................ 16
2.1.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)......................... 16
2.1.7 JTAG and Test Access Port (TAP) Signals ................................................... 17
2.1.8 Processor Sideband Signals ..................................................................... 17
2.1.9 Power/Ground and Sense Signals ............................................................. 17
2.1.10 Reserved or Unused Signals..................................................................... 21
2.2
Signal Group Summary ...................................................................................... 22
2.3
Power-On Configuration (POC) Options................................................................. 25
2.4
Fault Resilient Booting (FRB)............................................................................... 26
2.5
Mixing Processors.............................................................................................. 27
2.6
Flexible Motherboard Guidelines (FMB) ................................................................. 28
2.7
Absolute Maximum and Minimum Ratings ............................................................. 28
2.7.1 Storage Conditions Specifications ............................................................. 28
2.8
Power Limit Specifications .................................................................................. 29
2.9
DC Specifications .............................................................................................. 29
2.9.1 Voltage and Current Specifications............................................................ 30
2.9.2 Die Voltage Validation ............................................................................. 34
2.9.3 Signal DC Specifications .......................................................................... 35
2.10 Signal Quality ................................................................................................... 40
2.10.1 Intel® Scalable Memory Interconnect Gen 2 (Intel® SMI2)
Signal Quality Specifications .................................................................... 41
2.10.2 I/O Signal Quality Specifications............................................................... 41
2.10.3 Intel® QuickPath Interconnect Signal Quality Specifications ......................... 41
2.10.4 Input Reference Clock Signal Quality Specifications..................................... 41
2.10.5 Overshoot/Undershoot Tolerance.............................................................. 41
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3
3
Processor Land Listing .............................................................................................45
3.1
Listing by Land Name .........................................................................................45
3.2
Listing by Land Number ......................................................................................69
4
Signal Descriptions ..................................................................................................95
4.1
System Memory Interface ...................................................................................95
4.2
PCI Express Based Interface Signals.....................................................................95
4.3
DMI2/PCI Express Port Signals ............................................................................95
4.4
Intel® QuickPath Interconnect Signals ..................................................................96
4.5
PECI Signal .......................................................................................................96
4.6
System Reference Clock Signals ..........................................................................96
4.7
JTAG and TAP Signals.........................................................................................96
4.8
Serial VID Interface (SVID) Signals ......................................................................97
4.9
PIROM Signals...................................................................................................97
4.10 Processor Asynchronous Sideband and Miscellaneous Signals...................................98
4.11 Processor Power and Ground Supplies ................................................................ 100
5
Thermal Management Specifications ...................................................................... 103
5.1
Package Thermal Specifications ......................................................................... 103
5.1.1 TCASE and DTS Based Thermal Specifications........................................... 104
5.1.2 Intel® Xeon® E7 v3 Processor Thermal Profiles....................................... 105
5.1.3 Thermal Metrology ................................................................................ 116
6
PIROM ................................................................................................................... 117
6.1
Processor Information ROM ............................................................................... 117
6.2
Scratch EEPROM .............................................................................................. 119
6.3
PIROM and Scratch EEPROM Supported SMBus Transactions.................................. 119
6.4
SMBus Memory Component Addressing............................................................... 120
6.5
Managing Data in the PIROM ............................................................................. 121
6.5.1 Header ................................................................................................ 121
6.5.2 Processor Data ..................................................................................... 125
6.5.3 Processor Core Data.............................................................................. 127
6.5.4 Processor Uncore Data .......................................................................... 130
6.5.5 Package Data ....................................................................................... 134
6.5.6 Part Number Data................................................................................. 135
6.5.7 Thermal Reference Data ........................................................................ 137
6.5.8 Feature Data ........................................................................................ 138
6.5.9 Protected Processor Inventory Number .................................................... 140
6.5.10 Checksums .......................................................................................... 141
Figures
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
5-1
5-2
5-3
4
Input Device Hysteresis ......................................................................................16
VR Power-State Transitions .................................................................................20
VCC Static and Transient Tolerance Loadlines – Intel® Xeon® E7 v3 Processor.........33
Load Current Versus Time ...................................................................................34
VCC Overshoot Example Waveform ......................................................................35
BCLK{0/1} Differential Clock Crosspoint Specification .............................................39
BCLK{0/1} Differential Clock Measurement Point for Ringback .................................39
BCLK{0/1} Single-Ended Clock Measurement Points for Absolute Crosspoint, Swing ...40
BCLK{0/1} Single-Ended Clock Measurement Points for Delta Crosspoint ..................40
PWRGOOD Signal Waveform ...............................................................................40
Maximum Acceptable Overshoot/Undershoot Waveform ..........................................43
Tcase: 165 W Thermal Profile ............................................................................ 106
DTS: 165 W Thermal Profile For 10 Core Processors ............................................. 106
DTS: 165 W Thermal Profile For 16 to 18 Core Processors ..................................... 107
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5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
Tcase: 150 W Thermal Profile ........................................................................... 109
DTS: 150 W Thermal Profile.............................................................................. 109
Tcase: 140 W Thermal Profile ........................................................................... 111
DTS: 140 W Thermal Profile For 16 to 18 Core Processors..................................... 111
DTS: 140 W Thermal Profile for 4 Core Processors ............................................... 112
Tcase: 115 W Thermal Profile ........................................................................... 114
DTS: 115 W Thermal Profile for 8 Core Processors ............................................... 114
DTS: 115 W Thermal Profile for 10 to 18 Core Processors ..................................... 115
Case Temperature (TCASE) Measurement Location .............................................. 116
Tables
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
Processor Documents......................................................................................... 14
Public Specifications .......................................................................................... 14
Power and Ground Lands.................................................................................... 17
SVID Address Usage .......................................................................................... 20
VR12.5 Reference Code Voltage Identification (VID) Table ...................................... 21
Signal Description Buffer Types ........................................................................... 22
Signal Groups ................................................................................................... 22
Signals with On-Die Termination ......................................................................... 24
Power-On Configuration Option Lands .................................................................. 25
Fault Resilient Booting (Output Tristate) Signals .................................................... 27
Processor Absolute Minimum and Maximum Ratings ............................................... 28
Storage Condition Ratings .................................................................................. 29
Package C-State Power Specifications .................................................................. 29
Voltage Specification.......................................................................................... 30
Current (ICC_MAX and ICC_TDC) Specification...................................................... 31
VCC Static and Transient Tolerance Intel® Xeon® E7 v3 Processor......................... 32
VCC Overshoot Specifications.............................................................................. 34
PECI DC Specifications ....................................................................................... 35
System Reference Clock (BCLK{0/1}) DC Specifications ......................................... 36
SMBus DC Specifications .................................................................................... 36
JTAG and TAP Signals DC Specifications ............................................................... 36
Serial VID Interface (SVID) DC Specifications........................................................ 37
Processor Asynchronous Sideband DC Specifications .............................................. 37
Miscellaneous Signals DC Specifications................................................................ 38
Processor I/O Overshoot/Undershoot Specifications ............................................... 42
Land Name....................................................................................................... 45
Land Number.................................................................................................... 69
Memory Channel Signals .................................................................................... 95
PCI Express* Port Signals................................................................................... 95
DMI2 to Port 0 Signals ....................................................................................... 95
Intel® QPI Port 0, 1, and 2 Signals ...................................................................... 96
PECI Signals ..................................................................................................... 96
System Reference Clock (BCLK{0/1}) Signals ....................................................... 96
JTAG and TAP Signals ........................................................................................ 96
SVID Signals .................................................................................................... 97
PIROM Signals .................................................................................................. 97
Processor Asynchronous Sideband Signals ............................................................ 98
Miscellaneous Signals ........................................................................................ 99
Power and Ground Signals ................................................................................ 100
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5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
6-1
6-2
6-3
6-4
6-5
6
Intel® Xeon® E7 v3 Processor SKU Summary .................................................... 105
Tcase: 165 W Thermal Specifications.................................................................. 105
165 W Thermal Profile Table.............................................................................. 107
Tcase: 150 W Thermal Specifications.................................................................. 108
150 W Thermal Profile Table.............................................................................. 110
Tcase: 140 W Thermal Specifications.................................................................. 110
140 W Thermal Profile Table.............................................................................. 112
Tcase: 115 W Thermal Specifications.................................................................. 113
115 W Thermal Profile Table ............................................................................. 115
Processor Information ROM Table ...................................................................... 117
Read Byte SMBus Packet .................................................................................. 120
Write Byte SMBus Packet .................................................................................. 120
Memory Device SMBus Addressing ..................................................................... 120
128-Byte ROM Checksum Values ....................................................................... 141
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume1: EMTS, May 2015
Overview
1
Overview
1.1
Introduction
The Intel® Xeon® Processor E7-4800/8800 v3 Product Family Datasheet - Volume One
provides DC and AC electrical specifications, signal integrity, differential signaling
specifications, land and signal definitions, and an overview of additional processor
feature interfaces.
This document is intended to be distributed as a part of the complete datasheet
document which consists of two volumes.
The the next generation of 64-bit, multi-core enterprise processors built on 22nanometer process technology. Throughout this document, the processor may be
referred to as simply the processor. Based on the low-power/high performance Intel®
Xeon® E7 v3 processor microarchitecture, the processor is designed for a three-chip
platform as opposed to the previous four-chip platform. The three-chip platform
consists of a processor, memory buffer, and the Platform Controller Hub (PCH) and
enables higher performance, easier validation, and improved x-y footprint. Intel®
Scalable Memory Interconnect ( capable of up to 8.0 GT/s, up to lanes of PCI Express*
3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a
peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address
space and 48-bit of virtual address space.
Included in this family of processors is integrated I/O (IIO) (such as PCI Express and
DMI2) on a single silicon die. This single die solution is known as a monolithic
processor.
1.1.1
Processor Feature Details
• Each core supports two threads (Intel® Hyper-Threading Technology), up to 30
threads per socket
• 46-bit physical addressing and 48-bit virtual addressing
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data mid-level (L2) cache for each core
• Up to 37.5 MB last level cache (LLC): up to 2.5 MB per core instruction/data last
level cache (LLC), shared among all cores
1.1.2
Supported Technologies
• Intel® Virtualization Technology (Intel® VT)
• Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® 64 Architecture
• Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Advanced Vector Extensions (Intel® AVX)
• Intel® Hyper-Threading Technology
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Overview
• Execute Disable Bit
• Intel® Turbo Boost Technology
• Intel® Intelligent Power Technology
• Enhanced Intel SpeedStep® Technology
1.2
Interfaces
1.2.1
System Memory Support
•
Registered DDR3 and DDR4 DIMMs
®
• LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
• Independent channel mode or lockstep mode
• Data burst length of eight cycles for independent channel mode and burst length of
4 cycles for lockstep mode
• Memory DDR3 and DDR4 data transfer rates of 1066, 1333, 1600 and 1833 MT/s
• 64-bit wide channels plus 8-bits of ECC support for each channel
• DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
• DDR4 standard I/O Voltage of 1.2 V
• 2-Gb, 4-Gb and 8-Gb DDR3 DRAM technologies supported
• Up to 24 DIMMs supported per socket
• RAS Support (including and not limited to):
— Rank Level Sparing
— Demand and Patrol Scrubbing
— DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device failure in lock step mode, and x4 in independent mode
— Data scrambling with address to ease detection of write errors to an
incorrect address
— Error reporting via Machine Check Architecture
— Read Retry during CRC error handling checks by iMC
— Channel mirroring within a memory controller on a socket
• Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
• Memory thermal monitoring support for DIMM temperature via two memory pins,
MEM_HOT_C{1/23}_N
1.2.2
PCI Express*
• The PCI Express* port(s) are fully-compliant to the PCI Express* Base
Specification, Revision 3.0 (PCIe 3.0)
• Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)
• Up to lanes of PCI Express* interconnect for general purpose PCI Express* devices
at PCIe* 3.0 speeds that are configurable for up to independent ports
• 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0),
also can be downgraded to x2 or x1
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Datasheet Volume 1: EMTS, May 2015
Overview
• Negotiating down to narrower widths is supported
— x16 port (Port 3) may negotiate down to x8, x4, x2, or x1
— x8 port (Port 1) may negotiate down to x4, x2, or x1
— x4 port (Port 0) may negotiate down to x2, or x1
— When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Supports receiving and decoding 64 bits of address from PCI Express*
— Memory transactions received from PCI Express* that go above the top of
physical address space (when Intel VT-d is enabled, the check would be against
the translated HPA (Host Physical Address) address) are reported as errors by
the processor
— Outbound access to PCI Express* will always have address bits 63 to 46 cleared
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• Power Management Event (PME) functions
• Message Signaled Interrupt (MSI and MSI-X) messages
• Degraded Mode support and Lane Reversal support
• Static lane numbering reversal and polarity inversion support
1.2.3
Direct Media Interface Gen 2 (DMI2)
• Serves as the chip-to-chip interface to the Intel® C600 Series Chipset PCH
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCI Express* 1.0 or 2.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
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9
Overview
1.2.4
Intel® QuickPath Interconnect (Intel® QPI)
• Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
• Full width port includes 20 data lanes and 1 clock lane
• 64 byte cache-lines
• Home snoop based coherency
• 4-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 9.6 GT/s data rate (up to 16 GB/s per direction peak bandwidth per port)
— Ports 0 and 1 run at same operational frequency
— Port 2 may run at a separate operational frequency
— Reference Clock is 100 MHz
— Slow boot speed initialization at 50 MT/s
• Common reference clocking (same clock generator for both sender and receiver)
• Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
• Polarity and Lane reversal
1.2.5
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master.
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include CPU thermal and estimated power information, control functions
for power limiting, P-state and T-state control, and access for Machine Check
Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
• PECI address determined by SOCKET_ID configuration
• Single domain (Domain 0) is supported
1.3
Power Management Support
1.3.1
Processor Package and Core States
• ACPI C-states as implemented by the following processor C-states:
— Package: PC0, PC1/PC1E, PC3, PC6
— Core: CC0, CC1/CC1E, CC3, CC6
• Enhanced Intel SpeedStep Technology
10
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Overview
1.3.2
System States Support
• S0, S1(transitional only),S4, S5
1.3.3
Memory Controller
• Memory thermal monitoring via MEM_HOT_C1_N and MEM_HOT_C23_N pins
1.3.4
PCI Express*
• L0s and L1 low power states
1.3.5
Intel® QPI
• L0s, and L1 power management capabilities
1.4
Thermal Management Support
• Digital Thermal Sensor with multiple on-die temperature zones
• Adaptive Thermal Monitor
• THERMTRIP_N and PROCHOT_N signal support
• On-Demand mode clock modulation
• Closed Loop Thermal Throttling
• Fan speed control with DTS
• Two integrated SMBus masters for accessing thermal data from DIMMs
• New Memory Thermal Throttling features via MEM_HOT_C{1/23}_N pins
• Running Average Power Limit (RAPL), Processor and DRAM Thermal and Power
Optimization Capabilities
1.5
Package Summary
1.6
Terminology
Term
ASPM
Description
Active State Power Management
BMC
Baseboard Management Controllers
Cbo
Cache and Core Box. It is a term used for internal logic providing ring interface to
LLC and Core.
DDR3
Third generation Double Data Rate SDRAM memory technology that is the
successor to DDR2 SDRAM
DMA
Direct Memory Access
DMI
Direct Media Interface
DMI2
Direct Media Interface Gen 2
DTS
Digital Thermal Sensor
ECC
Error Correction Code
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11
Overview
Term
12
Description
Enhanced Intel
SpeedStep® Technology
Allows the operating system to reduce power consumption when performance is
not needed.
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Flit
Flow Control Unit. The Intel QPI Link layer’s unit of transfer; 1 Flit = 80-bits.
Functional Operation
Refers to the normal operating conditions in which all processor specifications,
including DC, AC, system bus, signal quality, mechanical, and thermal, are
satisfied.
IMC
The Integrated Memory Controller. A Memory Controller that is integrated in the
processor die.
IIO
The Integrated I/O Controller. An I/O controller that is integrated in the
processor die.
Intel® ME
Intel® Management Engine (Intel® ME)
Intel® QuickPath
Interconnect (Intel® QPI)
A cache-coherent, link-based Interconnect specification for Intel processors,
chipsets, and I/O bridge components.
Intel® 64 Technology
64-bit memory extensions to the IA-32 architecture. Further details on Intel 64
architecture and programming model can be found at
http://developer.intel.com/technology/intel64/.
Intel® Turbo Boost
Technology
Intel® Turbo Boost Technology is a way to automatically run the processor core
faster than the marked frequency if the part is operating under power,
temperature, and current specifications limits of the Thermal Design Power
(TDP). This results in increased performance of both single and multi-threaded
applications.
Intel® TXT
Intel® Trusted Execution Technology
Intel® Virtualization
Technology (Intel® VT)
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Intel® VT-d
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
hardware assist for enabling I/O device virtualization. It is under system
software (Virtual Machine Manager or OS) control. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
Integrated Heat Spreader
(IHS)
A component of the processor package used to enhance the thermal
performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
Jitter
Any timing variation of a transition edge or edges from the defined Unit Interval
(UI).
IOV
I/O Virtualization
LLC
Last Level Cache
LRDIMM
Load Reduced Dual In-line Memory Module
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
NEBS
Network Equipment Building System. NEBS is the most common set of
environmental design guidelines applied to telecommunications equipment in the
United States.
PCH
Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCU
Power Control Unit
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Overview
Term
Description
PCI Express* 3.0
The third generation PCI Express* specification that operates 60% faster than
PCI Express* 2.0 (8 Gb/s); however, PCI Express* 3.0 is completely backward
compatible with PCI Express* 1.0 and 2.0.
PCI Express 3
PCI Express* Generation 3.0
PCI Express 2
PCI Express* Generation 2.0
PCI Express 1
PCI Express* Generation 2.0/3.0
PECI
Platform Environment Control Interface
Phit
Physical Unit. An Intel® QPI terminology defining units of transfer at the physical
layer. 1 Phit is equal to 20 bits in ‘full width mode’ and 10 bits in ‘half width
mode’
Processor
The 64-bit, single-core or multi-core component (package)
Processor Core
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
RDIMM
Registered Dual In-line Module
Rank
A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR3
DIMM.
Scalable- 4S, 8S
Targeted for scalable designs, including those using third party Node Controller
chips. In these designs, Node Controller is used to scale the design beyond
two/four/eight sockets.
SCI
System Control Interrupt. Used in ACPI protocol.
SSE
Intel® Streaming SIMD Extensions (Intel® SSE)
SKU
A processor Stock Keeping Unit (SKU) to be installed in either server or
workstation platforms. Electrical, power and thermal specifications for these
SKU’s are based on specific use condition assumptions. Server processors may
be further categorized as Efficient Performance server, workstation and HPC
SKUs. For further details on use condition assumptions, please refer to the latest
Product Release Qualification (PRQ) Report available via your Customer Quality
Engineer (CQE) contact.
SMBus
System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the
system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Philips Semiconductor.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(i.e., unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC
Thermal Averaging Constant
TDP
Thermal Design Power
TSOD
Thermal Sensor on DIMM
UDIMM
Unbuffered Dual In-line Module
Uncore
The portion of the processor comprising the shared cache, IMC, HA, PCU, UBox,
and Intel QPI link interface.
Unit Interval
Signaling convention that is binary and unidirectional. In this binary signaling,
one bit is sent for every edge of the forwarded clock, whether it be a rising edge
or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk
then the UI at instance “n” is defined as:
UI
n
= t n - ()t
n
- 1)
VCC
Processor core power supply
VSS
Processor ground
VVMSEVVMSE
Variable power supply for the processor system memory interface.
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13
Overview
Term
1.7
Description
x1
Refers to a Link or Port with one Physical Lane
x4
Refers to a Link or Port with four Physical Lanes
x8
Refers to a Link or Port with eight Physical Lanes
x16
Refers to a Link or Port with sixteen Physical Lanes
Related Documents
Refer to the following documents for additional information.
Table 1-1.
Table 1-2.
Processor Documents
Document
Document Number
Intel® Xeon® Processor E7-8800/4800 v3 Product Families Datasheet Volume
2: Registers
332315
Intel® Xeon® Processor E7 v3 Product Family Thermal/Mechanical
Specifications and Design Guide
332318
Intel® Xeon® Processor E7 v3 Product Family Specification Update
332317
Intel® Xeon® Processor E7 v3 Product Family BSDL (Boundary Scan
Description Language)
332319
Public Specifications
Document
Document Number/ Location
Advanced Configuration and Power Interface Specification 3.0
http://www.acpi.info
PCI Local Bus Specification 3.0
http://www.pcisig.com/specifications
PCI Express® Base Specification - Revision 2.1 and 1.1
PCI Express® Base Specification - Revision 3.0 DRAFT
http://www.pcisig.com
System Management Bus (SMBus) Specification
http://smbus.org/
DDR3 SDRAM Specification
http://www.jedec.org
Low (JESD22-A119) and High (JESD-A103) Temperature Storage
Life Specifications
http://www.jedec.org
Intel® 64 and IA-32 Architectures Software Developer's Manuals
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
Intel® 64 and IA-32 Architectures Optimization Reference Manual
1.8
http://www.intel.com/products/processor/m
anuals/index.htm
Intel® Virtualization Technology Specification for Directed I/O
Architecture Specification
http://download.intel.com/technology/comp
uting/vptech/Intel(r)_VT_for_Direct_IO.pdf
Intel® Trusted Execution Technology Software Development Guide
http://www.intel.com/technology/security/
State of Data
The data contained within this document is the most accurate information available by
the publication date of this document. The information in this revision of the document
is based on silicon characterization data. Values may change prior to production.
§
14
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2
Electrical Specifications
2.1
Processor Signaling
Intel® Xeon® E7 v3 processors include 2011 lands, which utilize various signaling
technologies. Signals are grouped by electrical characteristics and buffer type into
various signal groups. These include Intel® Scalable Memory Interface Gen 2 (Intel
SMI2) (Reference Clock, Command, Control, and Data), PCI Express*, DMI2, Intel®
QuickPath Interconnect (Intel® QPI), Platform Environmental Control Interface (PECI),
System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface,
Processor Asynchronous Sideband, Miscellaneous, and Power/Other signals. See
Table 2-5.
Intel strongly recommends performing analog simulations of all interfaces. Please refer
to Section 1.7 for signal integrity model availability.
2.1.1
System Memory Interface Signal Groups
The system memory interface utilizes Intel SMI2 technology, which consists of
numerous signal groups. These include: Reference Clocks, Command Signals, Control
Signals, and Data Signals. Each group consists of numerous signals, which may utilize
various signaling technologies. See Table 2-5. Throughout this chapter the system
memory interface maybe referred to as Intel SMI2.
2.1.2
PCI Express Signals
The PCI Express Signal Group consists of PCI Express* ports 1 and 2 and PCI Express
miscellaneous signals. See Table 2-5.
2.1.3
DMI2/PCI Express Signals
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and commands to
the PCH. The DMI2 is an extension of the standard PCI Express specification. The
DMI2/PCI Express signals consist of DMI2 receive and transmit input/output signals
and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. See Table 2-5.
2.1.4
Intel® QuickPath Interconnect (Intel® QPI)
The Intel® Xeon® E7 v3 processor provides three Intel® QPI ports for high-speed
serial transfer between other processors. Each port consists of two unidirectional links
(for transmit and receive). A differential signaling scheme is utilized, which consists of
opposite-polarity (DP, DN) signal pairs.
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2.1.5
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external system management logic and
thermal monitoring devices. The Intel® Xeon® E7 v3 processor contains a Digital
Thermal Sensor (DTS) that reports a relative die temperature as an offset from
Thermal Control Circuit (TCC) activation temperature. Temperature sensors located
throughout the die are implemented as analog-to-digital converters calibrated at the
factory. PECI provides an interface for external devices to read processor temperature,
perform processor manageability functions, and manage processor interface tuning and
diagnostics.
2.1.5.1
Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Please refer to Figure 2-1 and Table 2-20.
Figure 2-1.
Input Device Hysteresis
VTTD
Maximum VP
PECI High Range
Minimum VP
Minimum
Hysteresis
Valid Input
Signal Range
Maximum VN
Minimum VN
PECI Low Range
PECI Ground
2.1.6
System Reference Clocks (BCLK{0/1}_DP,
BCLK{0/1}_DN)
The processor core, processor uncore, Intel® QPI link, PCI Express*, and VMSE
memory interface frequencies are generated from BCLK{0/1}_DP and BCLK{0/1}_DN
signals. There is no direct link between core frequency and Intel® QPI link frequency
(for example, there is no core frequency to Intel® QPI multiplier). The processor
maximum core frequency, Intel® QPI link frequency, and DDR memory frequency are
set during manufacturing. It is possible to override the processor core frequency
setting using software. This permits operation at lower core frequencies than the
factory set maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h);
Bits [15:0].
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
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BCLK{0/1}_DN inputs are provided in Table 2-21. These specifications must be met
while also meeting the associated signal quality specifications outlined in Section 2.10.
2.1.6.1
PLL Power Supply
Disabled for Intel® Xeon® E7 v3 processor.
2.1.7
JTAG and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
2.1.8
Processor Sideband Signals
Intel® Xeon® E7 v3 processors include asynchronous sideband signals that provide
asynchronous input, output, or I/O signals between the processor and the platform or
Platform Controller Hub. See Table 2-5 for details.
All Processor Asynchronous Sideband input signals are required to be
asserted/deasserted for a defined number of BCLKs in order for the processor to
recognize the proper signal state. These are outlined in Table 2-21 (DC specifications).
Refer to Section 2.10 for applicable signal integrity specifications.
2.1.9
Power/Ground and Sense Signals
Processors also include various other signals including power/ground and sense points.
See Table 2-5 for details.
2.1.9.1
Power and Ground Lands
All VCC, VCCPLL, VccIOin, VCC33, VCCPECI, and VVMSE lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane. For clean on-chip power distribution, processors include lands for
all required voltage supplies. See Table 2-1.
Table 2-1.
Power and Ground Lands (Sheet 1 of 2)
Power and
Ground Lands
Number of
Lands
Comments
218
Each VCC land must be supplied with the voltage determined by the
SVID Bus signals. Table 2-3 Defines the voltage level associated with
each core SVID pattern.Table 2-12, Figure 2-2, and Figure 2-4
represent VCC static and transient limits. VCC has a VBOOT setting of
1.7 V.
VCC33
1
VCC33 supplies a fixed 3.3 volt stand by voltage to supply PIROM and
the OEM scratch ROM.
VCCPECI
1
VCCPECI supplies a fixed 1.0 volt voltage to supply PECI for Intel®
Xeon® E7 v3.
VCCPLL
3
Not connected on Intel® Xeon® E7 v3 processors
VCC
VVMSE_01
VVMSE_23
16
Provides power to the processor Intel SMI2 interface with fixed
1.35 V supply.
VccIOin
43
VccIOin,must be supplied by a fixed 1.00 V supply.
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Table 2-1.
Power and Ground Lands (Sheet 2 of 2)
Power and
Ground Lands
2.1.9.2
Number of
Lands
VSA
12
VSS
726
Comments
Not connected on Intel® Xeon® E7 v3 processors
Ground
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Intel® Xeon®
E7 v3 processor is capable of generating large current swings between low and full
power states. This may cause voltages on power planes to sag below their minimum
values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (CBULK),
help maintain the output voltage during current transients, for example coming out of
an idle condition. Care must be taken in the baseboard design to ensure that the
voltages provided to the processor remain within the specifications listed in Table 2-12.
Failure to do so can result in timing violations or reduced lifetime of the processor.
2.1.9.3
Voltage Identification (VID)
The Voltage Identification (VID) specification for the VCC voltage is defined by the
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 12.5
Design Guidelines. The reference voltage or the VID setting is set via the SVID
communication bus between the processor and the voltage regulator controller chip.
The VID settings are the nominal voltages to be delivered to the processor's VCC lands
when current draw equals zero. Table 2-3 specifies the reference voltage level
corresponding to the VID value transmitted over serial VID. The voltage will change
due to temperature and/or current load changes in order to minimize the power and to
maximize the performance of the part. The specifications are set so that a voltage
regulator can operate with all supported frequencies.
The Intel® Xeon® E7 v3 processor uses voltage identification signals to support
automatic selection of VCC power supply voltages. If the processor socket is empty
(SKTOCC_N high), or a “not supported” response is received from the SVID bus, then
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself or not power on. Vout MAX register (30h) is programmed
by the processor to set the maximum supported VID code and if the programmed VID
code is higher than the VID supported by the VR, then VR will respond with a “not
supported” acknowledgement. See the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 12.5 Design Guidelines for further details.
2.1.9.3.1
SVID Commands
The processor supports the following VR commands:
• SetVID_fast (20 mV/µs),
• SetVID_slow (5 mV/µs), and
• Slew Rate Decay (downward voltage only and it’s a function of the output
capacitance’s time constant) commands. Table 2-3 includes SVID step sizes and DC
shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-12.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. The Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 12.5 Design Guidelines contains further details.
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Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
2.1.9.3.2
SetVID Fast Command
The SetVID-fast command contains the target VID in the payload byte. The range of
voltage is defined in the VID table. The VR should ramp to the new VID setting with a
fast slew rate as defined in the slew rate data register typically 20 mV/uS for
server platforms.
The SetVID-fast command is preemptive, the VR interrupts its current processes and
moves to the new VID. The SetVID-fast command operates on 1 VR address at a time.
This command is used in the processor for package C6 fast exit.
2.1.9.3.3
SetVID Slow
The SetVID-slow command contains the target VID in the payload byte. The range of
voltage is defined in the VID table. The VR should ramp to the new VID setting with a
“slow” slew rate as defined in the slow slew rate data register. Typically the
SetVID_Slow is 4x slower than the SetVID_fast slew rate.
The SetVID-slow command is preemptive, the VR interrupts its current processes and
moves to the new VID. This is the instruction used for normal P-state voltage change.
This command is used in the processor for the Intel Enhanced SpeedStep Technology
transitions.
2.1.9.3.4
SetVID Decay
The SetVID-Decay command is the slowest of the DVID transitions. It is normally used
for VID down transitions. The VR does not control the slew rate, the output voltage
declines with the output load current only.
The SetVID- Decay command is preemptive, the VR interrupts its current processes
and moves to the new VID. This command is used in the processor for package C6
entry, allowing capacitor discharge by the leakage, thus saving energy.This command is
normally used in VID down direction in the processor package C6 entry.
2.1.9.3.5
SVID Power State Functions: SetPS
The processor has three power state functions and these will be set seamlessly via the
SVID bus using the SetPS command. Based on the power state command, the SetPS
commands sends information to VR controller to configure the VR to improve efficiency,
especially at light loads. For example, typical power states are:
• PS(00h): Represents full power or active mode
• PS(01h): Represents a light load 5 to 20 A
• PS(02h): Represents a very light load <5 A
The VR may change its configuration to meet the processor’s power needs with greater
efficiency. For example, it may reduce the number of active phases, transition from
CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode,
reduce the switching frequency or pulse skip, or change to asynchronous regulation.
For example, typical power states are 00h = run in normal mode; a command of 01h=
shed phases mode, and an 02h=pulse skip.
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The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(00h)
to PS(02h) for example. There are multiple VR design schemes that can be used to
maintain a greater efficiency in these different power states, please work with your VR
controller suppliers for optimizations.
The SetPS command sends a byte that is encoded as to what power state the VR
should transition to.
If a power state is not supported by the controller, the slave should acknowledge with
command rejected (11b)
Note the mapping of power states 0-n will be detailed in the Voltage Regulator Module
(VRM) and Enterprise Voltage Regulator-Down (EVRD) 12.5 Design Guidelines.
If the VR is in a low power state and receives a SetVID command moving the VID up
then the VR exits the low power state to normal mode (PS0) to move the voltage up as
fast as possible. The processor must reissue low power state (PS1, PS2, or PS3)
command if it is in a low current condition at the new higher voltage. See Figure 2-2 for
VR power state transitions.
Figure 2-2.
VR Power-State Transitions
2.1.9.3.6
SVID Voltage Rail Addressing
The processor addresses one voltage rail control segments within VR12.5 (VCC). The
SVID data packet contains a 4-bit addressing code:
Table 2-2.
20
SVID Address Usage (Sheet 1 of 2)
PWM Address (HEX)
Intel® Xeon® E7 v3 Processor
00
Vcc
01
+1 not used
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Table 2-2.
SVID Address Usage (Sheet 2 of 2)
02
VMSE MC0
03
+1 not used
04
VMSE MC0
05
+1 not used
06
VMSE MC1
07
+1 not used
08
VMSE MC1
Notes:
1.
Check with VR vendors to determine the physical address assignment method for their controllers.
2.
VR addressing is assigned on a per-voltage-rail basis.
3.
Dual VR controllers will have two addresses with the lowest order address, always being the higher
phase count.
4.
For future platform flexibility, the VR controller should include an address offset, as shown with +1
not used.
Table 2-3.
VR12.5 Reference Code Voltage Identification (VID) Table
HEX
VCC, VSA
HEX
VCC, VSA
HEX
VCC, VSA
HEX
VCC, VSA
HEX
VCC, VSA
HEX
VCC, VSA
00
0.00
72
1.63
80
1.77
8E
1.91
9C
2.05
AA
2.19
65
1.50
73
1.64
81
1.78
8F
1.92
9D
2.06
AB
2.20
66
1.51
74
1.65
82
1.79
90
1.93
9E
2.07
AC
2.21
67
1.52
75
1.66
83
1.80
91
1.94
9F
2.08
AD
2.22
68
1.53
76
1.67
84
1.81
92
1.95
A0
2.09
AE
2.23
69
1.54
77
1.68
85
1.82
93
1.96
A1
2.10
AF
2.24
6A
1.55
78
1.69
86
1.83
94
1.97
A2
2.11
B0
2.25
6B
1.56
79
1.70
87
1.84
95
1.98
A3
2.12
B1
2.26
6C
1.57
7A
1.71
88
1.85
96
1.99
A4
2.13
B2
2.27
6D
1.58
7B
1.72
89
1.86
97
2.00
A5
2.14
B3
2.28
6E
1.59
7C
1.73
8A
1.87
98
2.01
A6
2.15
B4
2.29
6F
1.60
7D
1.74
8B
1.88
99
2.02
A7
2.16
B5
2.30
70
1.61
7E
1.75
8C
1.89
9A
2.03
A8
2.17
71
1.62
7F
1.76
8D
1.90
9B
2.04
A9
2.18
Notes:
1.
00h = Off State
2.
VID Range HEX 01-65 are not used by the Intel® Xeon® E7 v3 processor.
3.
VID Range HEX > B5 is not used by the Intel® Xeon® E7 v3 processor.
4.
For VID Ranges supported see Table 2-12.
2.1.10
Reserved or Unused Signals
All Reserved (RSVD) signals must not be connected. Connection of these signals to
power, ground or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Chapter 3 for a land listing of
the processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bidirectional signals
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21
to power or ground. When tying any signal to power or ground, a resistor will also allow
for system testability. Resistor values should be within ± 20% of the impedance of the
baseboard trace, unless otherwise noted.
2.2
Signal Group Summary
Signals are grouped by buffer type and similar characteristics as listed in Table 2-5. The
buffer type indicates which signaling technology and specifications apply to the signals.
Table 2-4.
Signal Description Buffer Types
Signal
Description
Analog
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Asynchronous1
Signal has no timing relationship with any system reference clock.
CMOS
CMOS buffers: 1.05 V or 1.5 V tolerant
DMI2
Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express
2.0 and 1.0 Signaling Environment AC Specifications.
Intel® QPI
Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect
signaling
Intel SMI2
Intel Scalable Memory Interconnect Gen 2. These signals are the interface between
the Intel® Xeon® E7 v3 processor and the scalable memory buffer. The pin names
start with VMSE.
Open Drain CMOS
Open Drain CMOS (ODCMOS) buffers: 1.05V tolerant
PCI Express*
PCI Express interface signals. These signals are compatible with PCI Express 3.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe* specification.
Reference
Voltage reference signal.
SSTL
Source Series Terminated Logic (JEDEC SSTL_15)
Notes:
1.
Table 2-5.
Qualifier for a buffer type.
Signal Groups (Sheet 1 of 3)
Differential/Single
-ended
Signals1
Buffer Type
Intel SMI2 Reference Clocks2
Differential
SSTL Output
Intel SMI2 Command
Single-ended
SSTL Output
Intel SMI2 Data Signals
VMSE{0/1/2/3}_CMD[16:0]
2
Differential
SSTL Input/Output
VMSE{0/1/2/3}_DQS_D[N/P][8:0]
Single-ended
SSTL Input/Output
VMSE{0/1/2/3}_DQ[63:0]
VMSE{0/1/2/3}_ECC[7:0]
SSTL Input
VMSE{0/1/2/3}_ERR_N
Intel SMI2 Miscellaneous
Single-ended
22
VMSE{0/1/2/3}_CLK_D[N/P]
Signals2
Signals2
CMOS Input
VMSE_PWR_OK
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Table 2-5.
Signal Groups (Sheet 2 of 3)
Differential/Single
-ended
Signals1
Buffer Type
PCI Express* Port 1, 2, and 3 Signals
Differential
PCI Express* Input
PE0_RX_[N/P][15:0]
PE1_RX_[N/P][15:0]
Differential
PCI Express* Output
PE0_TX_[N/P][15:0]
PE1_TX_[N/P][15:0]
DMI2/PCI Express* Signals
Differential
DMI2 Input
DMI_RX_D[N/P][3:0]
DMI2 Output
DMI_TX_D[N/P][3:0]
Intel® QuickPath Interconnect (Intel® QPI) Signals
Differential
Intel® QPI Input
QPI{0/1/2}_DRX_D[N/P][19:00]
QPI{0/1/2}_CLKRX_D[N/P]
Intel® QPI Output
QPI{0/1/2}_DTX_D[N/P][19:00]
QPI{0/1/2}_CLKTX_D[N/P]
Platform Environmental Control Interface (PECI)
Single-ended
PECI
PECI
System Reference Clock (BCLK{0/1})
Differential
CMOS1.05v Input
BCLK{0/1}_D[N/P]
Open Drain CMOS
Input/Output
MEM_SCL_C{3:0}
MEM_SDA_C{3:0}
VPPSCL
VPPSDA
CMOS1.05v Input
TCK, TDI, TMS, TRST_N , EAR_N
CMOS1.05v Input/Output
PREQ_N
SMBus
Single-ended
JTAG & TAP Signals
Single-ended
CMOS1.05v Output
Open Drain CMOS
Input/Output
BPM_N[7:0]
Open Drain CMOS Output
TDO, PRDY_N
Serial VID Interface (SVID) Signals
Single-ended
CMOS1.05v Input
SVIDALERT_N
Open Drain CMOS
Input/Output
SVIDDATA
Open Drain CMOS Output
SVIDCLK
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Table 2-5.
Signal Groups (Sheet 3 of 3)
Differential/Single
-ended
Signals1
Buffer Type
Processor Asynchronous Sideband Signals
Single-ended
CMOS1.05v Input
BIST_ENABLE
BMCINIT
FRMAGENT
PWRGOOD
PMSYNC
RESET_N
SOCKET_ID[2:0]
TXT_AGENT
TXT_PLTEN
Open Drain CMOS
Input/Output
CAT_ERR_N
CPU_ONLY_RESET
MEM_HOT_C{01/23}_N
PROCHOT_N
Open Drain CMOS Output
ERROR_N[2:0]
THERMTRIP_N
Miscellaneous Signals
N/A
Output
PROC_ID[1:0]
SKTOCC_N
Power/Other Signals
Power / Ground
VCC, VTT, VVMSE_01, VVMSE_23,VCCPLL, VSA, VCC33, VPECI and
VSS
Sense Points
VCC_SENSE
VSS_VCC_SENSE
VSS_VTT_SENSE
VTT_SENSE
VSA_SENSE
VSS_VSA_SENSE
Notes:
1.
Table 2-6.
Refer to Chapter 4 for signal description details.
Signals with On-Die Termination (Sheet 1 of 2)
Signal Name
24
Pull Up /Pull
Down
Rail
Value
Units
1k-6k
Ohms
BIST_ENABLE
PD
BMCINIT
PD
1k-6k
Ohms
DEBUG_EN_N
PU
VTT
1k-6k
Ohms
EAR_N
PU
VTT
1k-6k
Ohms
EX_LEGACY_SKT
PD
1k-6k
Ohms
FRMAGENT
PD
1k-6k
Ohms
LGSPARE
PU
VTT
1k-6k
Ohms
MSMI_N
PU
VTT
1k-6k
Ohms
NMI
PD
1k-6k
Ohms
PM_FAST_WAKE_N
PU
VTT
1k-6k
Ohms
PWR_DEBUG_N
PU
VTT
1k-6k
Ohms
SAFE_MODE_BOOT
PD
1k-6k
Ohms
Notes
1
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 2-6.
Signals with On-Die Termination (Sheet 2 of 2)
Signal Name
Pull Up /Pull
Down
Rail
Value
Units
1k-6k
Ohms
VTT
1k-6k
Ohms
SOCKET_ID[2:0]
PD
SVID_IDLE_N
PU
TCK
PD
1k-6k
Ohms
TDI
PU
VTT
1k-6k
Ohms
TRST_N
PU
VTT
1k-6k
Ohms
TMS
PU
VTT
1k-6k
Ohms
TXT_AGENT
PD
1k-6k
Ohms
TXT_PLTEN
PU
VTT
1K-6K
Ohms
Notes
Notes:
1.
Please refer to Table 2-19 for details on the RON (Buffer on Resistance) value for this signal.
2.3
Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, please refer to Table 2-7.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Table 2-7.
Power-On Configuration Option Lands
Configuration Option
Output tri state
Land Name
Notes
PROCHOT_N
1
BIST_ENABLE
2
BMCINIT
3
Enable Intel® Trusted Execution Technology (Intel®
TXT) Platform
TXT_PLTEN
3
Power-up Sequence Halt for Intel® In-Target Probe
(Intel® ITP) configuration
EAR_N
3
Enable Bootable Firmware Agent
FRMAGENT
3
Enable Intel Trusted Execution Technology
(Intel TXT) Agent
TXT_AGENT
3
Used in conjunction with FRMAGENT
EX_LEGACY_SKT
3
Configure Socket ID
SOCKET_ID[1:0]
3
Execute BIST (Built-In Self Test)
Enable Service Processor Boot Mode
Notes:
1.
Output tristate option enables Fault Resilient Booting (FRB), for FRB details see Section 2.4. The signal
used to latch PROCHOT_N for enabling FRB mode is RESET_N.
2.
This signal is sampled at cold reset / PWRGOOD-reset and warm reset. This is setup before PWRGOOD
asserts and held after reset deasserts.
3.
This signal is sampled at cold reset / PWRGOOD-reset. This is setup before powergood asserts and held
after reset deasserts.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
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25
2.4
Fault Resilient Booting (FRB)
The Intel® Xeon® E7 v3 processor supports both socket and core level Fault Resilient
Booting (FRB), which provides the ability to boot the system as long as there is one
processor functional in the system. One limitation to socket level FRB is that the system
cannot boot if the legacy socket that connects to an active PCH becomes unavailable
since this is the path to the system BIOS. See Table 2-9 for a list of output tristate
FRB signals.
Socket level FRB will tristate processor outputs via the PROCHOT_N signal. Assertion of
the PROCHOT_N signal through RESET_N assertion will tristate processor outputs.
Note, that individual core disabling is also supported for those cases where disabling
the entire package is not desired.
The Intel® Xeon® E7 v3 processor extends the FRB capability to the core granularity
by maintaining a register in the uncore so that BIOS or another entity can disable one
or more specific processor cores.
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Table 2-8.
Fault Resilient Booting (Output Tristate) Signals
Output Tristate Signal Groups
Signals
Intel®
QPI0_CLKTX_DN[1:0]
QPI0_CLKTX_DP[1:0]
QPI0_DTX_DN[19:00]
QPI0_DTX_DP[19:00]
QPI1_CLKTX_DN[1:0]
QPI1_CLKTX_DP[1:0]
QPI1_DTX_DN[19:00]
QPI1_DTX_DP[19:00]
QPI
SMBus
2.5
MEM_SCL_C[3:0]
MEM_SDA_C[3:0]
VPP_SCL
VPP_SDA
JTAG & TAP
TDO
Processor Sideband
CAT_ERR_N
CPU_ONLY_RESET
ERROR_N[2:0]
MEM_HOT_C01_N
MEM_HOT_C23_N
BPM_N[7:0]
PRDY_N
THERMTRIP_N
PROCHOT_N
PECI
TSC-SYNC
MSMI
PM_FAST_WAKE#
FIVR_FAULT
SVID
SVIDCLK
SVID_DATA
SVID_IDLE_N
Mixing Processors
Intel supports and validates two- and four-processor configurations only, in which all
processors operate with the same Intel® QuickPath Interconnect frequency, core
frequency, and power segment, and all have the same internal cache sizes. Mixing
components operating at different internal clock frequencies is not supported and will
not be validated by Intel. Combining processors from different power segments is also
not supported.
Note:
Processors within a system must operate at the same frequency per bits [15:8] of the
FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep
Technology transitions signal.
Mixing processors of different steppings but the same model (as per CPUID instruction)
is supported.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
27
2.6
Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
Intel® Xeon® E7 v3 processor will have over certain time periods. The values are only
1estimates and actual specifications for future processors may differ. Processors may or
may not have specifications equal to the FMB value in the foreseeable future. System
designers should meet the FMB values to ensure their systems will be compatible with
future Intel® Xeon® E7 v3 processors.
2.7
Absolute Maximum and Minimum Ratings
Table 2-9 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits, but within the absolute maximum and minimum
ratings, the device may be functional, but with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
Although the processor contains protective circuitry to resist damage from ElectroStatic Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.5
Table 2-9.
Processor Absolute Minimum and Maximum Ratings
Symbol
Parameter
Min
Typical
Max
Unit
2.0
V
1.4
V
VCC
Processor core voltage with respect to Vss
-0.3
VccPECI
Processor analog voltage with respect to VSS
-0.3
1.00
VVMSE
Processor VMSE voltage with respect to VSS
-.04
1.35
1.6
V
VccIO_IN
Processor analog IO voltage with respect to VSS
-0.3
1.00
1.4
V
Notes:
1.
For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must
be satisfied.
2.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in
Section 2.10.5. Excessive overshoot or undershoot on any signal will likely result in permanent damage to
the processor.
2.7.1
Storage Conditions Specifications
Environmental storage condition limits define the temperature and relative humidity
limits to which the device is exposed to while being stored in a Moisture Barrier Bag.
The specified storage conditions are for component level prior to board attach (see
notes in Table 2-10 for post board attach limits).
Table 2-10 specifies absolute maximum and minimum storage temperature limits which
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. At conditions outside sustained
limits, but within absolute maximum and minimum ratings, quality, and reliability may
be affected.
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Datasheet Volume 1: EMTS, May 2015
Table 2-10. Storage Condition Ratings
Symbol
Parameter
Min
Max
Unit
Tabsolute storage
The minimum/maximum device storage temperature
beyond which damage (latent or otherwise) may
occur when subjected to for any length of time.
-25
125
°C
Tsustained storage
The minimum/maximum device storage temperature
for a sustained period of time.
-5
40
°C
Tshort term storage
The ambient storage temperature (in shipping media)
for a short period of time.
-20
85
°C
RHsustained storage
The maximum device storage relative humidity for a
sustained period of time.
Timesustained storage
A prolonged or extended period of time; typically
associated with sustained storage conditions
Unopened bag, includes 6 months storage time by
customer.
0
30
months
A short period of time (in shipping media).
0
72
hours
Timeshort term storage
60% @ 24
°C
Notes:
1.
Storage conditions are applicable to storage environments only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
2.
These ratings apply to the Intel component and do not include the tray or packaging.
3.
Failure to adhere to this specification can affect the long-term reliability of the processor.
4.
Nonoperating storage limits post board attach: Storage condition limits for the component once attached to
the application board are not specified. Intel does not conduct component level certification assessments
post board attach given the multitude of attach methods, socket types, and board types used by
customers. Provided as general guidance only, Intel board products are specified and certified to meet the
following temperature and humidity limits: (Nonoperating Temperature Limit: -40 to +70°C and Humidity:
50 to 90%, noncondensing with a maximum wet bulb of 28°C).
5.
Device storage temperature qualification methods follow JEDEC High and Low Temperature Storage Life
Standards: JESD22-A119 (low temperature) and JESD22-A103 (high temperature).
2.8
Power Limit Specifications
The maximum power limits for associated states are listed below.
Table 2-11. Package C-State Power Specifications
TDP SKUs
C0 (Pmax)
C1
C3
C6
Note:
1.
SKU’s are subject to change. Please contact your Intel Field Representative to obtain the latest SKU
information.
2.
C0 is the performance state of the processor, and includes all P-states, including Intel Turbo Boost
Technology.
2.9
DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted.
DC specifications are only valid while meeting specifications for case temperature
(TCASE specified in Chapter 5), clock frequency, and input voltages. Care should be
taken to read all notes associated with each specification.
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29
2.9.1
Voltage and Current Specifications
Table 2-12. Voltage Specification
Symbol
Parameter
VCC VID
VCC VID Range
VCC
Core Voltage
(Launch - FMB)
VVID_STEP
(Vcc)
VID step size during
a transition
VCCPECI
Uncore Voltage
VVMSE
(VVMSE_01,
VVMSE_23)
I/O Voltage for Intel
SMI2 (Standard
Voltage)
VccIO_IN
Uncore Voltage
(Launch - FMB)
Voltage
Plane
Min
Typ
1.5
VCC
Max
Unit
Notes1
1.85
V
2, 3
V
3, 4, 7, 8,
12, 14, 18
mV
10
See Table 2-13 and Figure 2-3
10.0
0.959
1.00
1.036
V
3, 5, 9, 12,
13
VVMSE
1.303
1.35
1.391
V
11, 13, 14,
16, 17
VccIO_IN
0.959
1.00
1.036
V
3, 5, 9, 12,
13
VCCPECI
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on presilicon
characterization and will be updated as further data becomes available.
2.
Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have
different settings.
3.
These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required.
4.
The VCC voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE and
VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 Mohm
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
5.
The VTT voltage specification requirements are measured across the remote sense pin pairs (VTT_SENSE and
VSS_VTT_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 Mohm
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
6.
The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current.
Failure to adhere to this specification can shorten processor lifetime.
7.
Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Section 5,
“Thermal Management Specifications”. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is
capable of drawing ICC_MAX for up to ~0.09375x PL1 Tau seconds. Refer to Figure 2-4 for further details on the average
processor current draw over various time durations.
8.
The processor should not be subjected to any static VTTA, VTTD level that exceeds the VTT_MAX associated with any particular
current. Failure to adhere to this specification can shorten processor lifetime.
9.
This specification represents the VCC reduction or VCC increase due to each VID transition, see Section 2.1.9.3, “Voltage
Identification (VID)”.
10. Baseboard bandwidth is limited to 20 MHz.
11. FMB is the flexible motherboard guidelines. See Section 2.6 for FMB details.
12. DC + AC + Ripple = Total Tolerance
13. For Power State Functions see Section 2.1.9.3.5.
14. VVMSE tolerance at processor pins. Tolerance for VR at remote sense is ±3.0%*VVMSE.
15. The VCCPLL, VVMSE01, VVMSE23 voltage specification requirements are measured across vias on the platform. Choose VCCPLL,
VVMSE01, or VVMSE23 vias close to the socket and measure with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz
for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1 Mohm minimum impedance. The maximum
length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in
the scope probe.
16. VCC has a Vboot setting of 1.7V. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
12.5 Design Guidelines.
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Table 2-13. Current (ICC_MAX and ICC_TDC) Specification
Symbol
ICC_MAX
IPECI_MAX
IVMSE_MAX
ICC33_MAX
ICCIO_IN_MAX
ICC_TDC
IPECI_TDC
IVMSE_TDC
ICC33_TDC
ICCIO_IN_TDC
1.
2.
3.
4.
5.
Voltage
Plane
Current
Unit
Notes1
220
.01
5
.075
0.20
A
A
A
A
A
A
2, 4,6
Max. Processor Current:
(TDP - 150W)
(Launch - FMB)
215
.01
5
.075
020
A
A
A
A
A
2, 4,6
Max. Processor Current:
(TDP - 140W)
(Launch - FMB)
201
.01
5
.075
020
A
A
A
A
A
2, 4,6
Max. Processor Current:
(TDP - 115W)
(Launch - FMB)
165
0.01
5
.075
0.20
A
A
A
A
A
2, 4, 6
100
.01
4.6
.075
0.10
A
A
A
A
A
2, 3, 5
Thermal Design Current:
(TDP - 150W)
(Launch - FMB)
91
.01
4.6
.075
0.10
A
A
A
A
A
2, 3, 5
Thermal Design Current:
(TDP - 140W)
(Launch - FMB)
86
.01
4.6
.075
0.10
A
A
A
A
A
2, 3, 5
Thermal Design Current:
(TDP - 115W)
(Launch - FMB)
71
.01
4.6
.075
0.10
A
A
A
A
A
2, 3, 5
Parameter
Max. Processor Current:
(TDP - 165W)
(Launch - FMB)
Thermal Design Current:
(TDP - 165W)
(Launch - FMB)
VCC
VPECI
VVMSE
VCC33
VCCIO_IN
VCC
VTT
VPECI
VVMSE
VCC33
Unless otherwise noted, all specifications in this table apply to all processors. These specifications are
based on presilicon characterization and will be updated as further data becomes available.
FMB is the flexible motherboard guidelines. See Section 2.6 for FMB details.
ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of
drawing indefinitely and should be used for the voltage regulator thermal assessment. The voltage
regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the
processor of a thermal excursion. Please refer to the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 12.5 Design Guidelines for further details.
Specification is at TCASE = 50°C. Characterized by design (not tested).
Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown
in Section 5, “Thermal Management Specifications”. ICC_MAX is specified at the relative VCC_MAX point on
the VCC load line. The processor is capable of drawing ICC_MAX for up to ~0.09375x PL1 Tau seconds. Refer
to Figure 2-4 for further details on the average processor current draw over various time durations.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
31
6.
ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable of drawing
ICC_MAX for up to ~0.09375x PL1 Tau seconds. Refer to Figure 2-4 for further details on the average
processor current draw over various time durations.
Table 2-14. VCC Static and Transient Tolerance Intel® Xeon® E7 v3 Processor (Sheet 1 of
2)
32
ICC (A)
VCC_MAX (V)
VCC_TYP (V)
VCC_MIN (V)
Notes
0
VID + 0.022
VID - 0.000
VID - 0.022
1,2,3,4,5
5
VID + 0.018
VID - 0.004
VID - 0.026
1,2,3,4,5
10
VID + 0.014
VID - 0.008
VID - 0.030
1,2,3,4,5
15
VID + 0.010
VID - 0.012
VID - 0.034
1,2,3,4,5
20
VID + 0.006
VID - 0.016
VID - 0.038
1,2,3,4,5
25
VID + 0.002
VID - 0.020
VID - 0.042
1,2,3,4,5
30
VID - 0.002
VID - 0.024
VID - 0.046
1,2,3,4,5
35
VID - 0.006
VID - 0.028
VID - 0.050
1,2,3,4,5
40
VID - 0.010
VID - 0.032
VID - 0.054
1,2,3,4,5
45
VID - 0.014
VID - 0.036
VID - 0.058
1,2,3,4,5
50
VID - 0.018
VID - 0.040
VID - 0.062
1,2,3,4,5
55
VID - 0.022
VID - 0.044
VID - 0.066
1,2,3,4,5
60
VID - 0.026
VID - 0.048
VID - 0.070
1,2,3,4,5
65
VID - 0.030
VID - 0.052
VID - 0.074
1,2,3,4,5
70
VID - 0.034
VID - 0.056
VID - 0.078
1,2,3,4,5
75
VID - 0.038
VID - 0.060
VID - 0.082
1,2,3,4,5
80
VID - 0.042
VID - 0.064
VID - 0.086
1,2,3,4,5,6
85
VID - 0.046
VID - 0.068
VID - 0.090
1,2,3,4,5,6
90
VID - 0.050
VID - 0.072
VID - 0.094
1,2,3,4,5,6
95
VID - 0.054
VID - 0.076
VID - 0.098
1,2,3,4,5,6
100
VID - 0.058
VID - 0.080
VID - 0.102
1,2,3,4,5,6
105
VID - 0.062
VID - 0.084
VID - 0.106
1,2,3,4,5,6
110
VID - 0.066
VID - 0.088
VID - 0.110
1,2,3,4,5,6
115
VID - 0.070
VID - 0.092
VID - 0.114
1,2,3,4,5,6
120
VID - 0.074
VID - 0.096
VID - 0.118
1,2,3,4,5,6
125
VID - 0.078
VID - 0.100
VID - 0.122
1,2,3,4,5,6
130
VID - 0.082
VID - 0.104
VID - 0.126
1,2,3,4,5,6
135
VID - 0.086
VID - 0.108
VID - 0.130
1,2,3,4,5,6
140
VID - 0.090
VID - 0.112
VID - 0.134
1,2,3,4,5,6
145
VID - 0.094
VID - 0.116
VID - 0.138
1,2,3,4,5,6
150
VID - 0.098
VID - 0.120
VID - 0.142
1,2,3,4,5,6
155
VID - 0.102
VID - 0.124
VID - 0.146
1,2,3,4,5,6
160
VID - 0.106
VID - 0.128
VID - 0.150
1,2,3,4,5,6
165
VID - 0.110
VID - 0.132
VID - 0.154
1,2,3,4,5,6
170
VID - 0.114
VID - 0.136
VID - 0.158
1,2,3,4,5,6
175
VID - 0.118
VID - 0.140
VID - 0.162
1,2,3,4,5,6
180
VID - 0.122
VID - 0.144
VID - 0.166
1,2,3,4,5,6
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 2-14. VCC Static and Transient Tolerance Intel® Xeon® E7 v3 Processor (Sheet 2 of
2)
ICC (A)
VCC_MAX (V)
VCC_TYP (V)
VCC_MIN (V)
Notes
185
VID - 0.126
VID - 0.148
VID - 0.170
1,2,3,4,5,6
190
VID - 0.130
VID - 0.152
VID - 0.174
1,2,3,4,5,6
195
VID - 0.134
VID - 0.156
VID - 0.178
1,2,3,4,5,6
200
VID - 0.138
VID - 0.160
VID - 0.182
1,2,3,4,5,6
205
VID - 0.142
VID - 0.164
VID - 0.186
1,2,3,4,5,6
210
VID - 0.146
VID - 0.168
VID - 0.190
1,2,3,4,5,6
215
VID - 0.150
VID - 0.172
VID - 0.194
1,2,3,4,5,6
220
VID - 0.154
VID - 0.176
VID - 0.198
1,2,3,4,5,6
Notes:
1.
The loadline specification includes both static and transient limits.
2.
This table is intended to aid in reading discrete points on graph in Figure 2-3.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_VCC_SENSE lands.
Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 12.5 Design
Guidelines for loadline guidelines and VR implementation details.
4.
The Vcc_min and Vcc_max loadlines represent static and transient limits. Please see Section 4 for Vcc
Overshoot specifications.
5.
The Adaptive Loadline Positioning slope is 0.8 mohm, and the tolerance is ±22 mV.
6.
The core Icc ranges are as follows:
• 0 to 220 A for Intel® Xeon® E7 v3 processor (165 W)
• 0 to 201 A for Intel® Xeon® E7 v3 processor (140 W)
• 0 to 165 A for Intel® Xeon® E7 v3 processor (115 W)
Figure 2-3.
VCC Static and Transient Tolerance Loadlines – Intel® Xeon® E7 v3 Processor
VID+0.022
VID
VID-0.022
VCC Maximum
VID-0.044
Vout (V)
VID-0.066
VID-0.088
VID-0.11
VCC Typical
VID-0.132
VID-0.154
VCC Minimum
VID-0.176
VID-0.198
VID-0.22
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150 160 170 180 190 200 210 220
Icc (A)
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
33
2.9.2
Die Voltage Validation
Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-15 when measured across the VCC_SENSE and VSS_VCC_SENSE lands.
Overshoot events that are < 10 ns in duration may be ignored. These measurements
of processor die level overshoot should be taken with a 100 MHz bandwidth
limited oscilloscope.
Figure 2-4.
Load Current Versus Time
Notes:
1.
In an IccMax condition, the CPU will respond to reduce the current within 2 ms. It will then respond in a
step wise fashion to bring the current down to the Icc dynamic condition.
2.
Icc dynamic is not expected to last longer than 10 seconds with a heat sink which meets but does not
significantly exceed the specifications set forth in this document. Current suggested value is 1.2x TDP.
3.
Turbo performance may be impacted by failing to meet durations specified in this graph. Ensure that the
platform design can handle peak and average current based on the specification.
4.
Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
ICC_TDC.
5.
Not 100% tested. Specified by design characterization.
2.9.2.1
VCC Overshoot Specifications
The Intel® Xeon® E7 v3 processor can tolerate short transient overshoot events
where VCC exceeds the VID voltage when transitioning from a high-to-low current load
condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum
allowable overshoot above VID). These specifications apply to the processor die voltage
as measured across the VCC_SENSE and VSS_VCC_SENSE lands.
Table 2-15. VCC Overshoot Specifications
Symbol
Parameter
Min
Max
Units
Figure
VOS_MAX
Magnitude of VCC overshoot above VID
72
mV
2-5
TOS_MAX
Time duration of VCC overshoot above VccMAX
value at the new lighter load
25
µs
2-5
34
Notes
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Figure 2-5.
VCC Overshoot Example Waveform
VOS_MAX
Voltage [V]
VID + VOS_MAX
VccMAX (I1)
TOS_MAX
0
5
10
15
20
25
30
Time [us]
Notes:
1.
VOS_MAX is the measured overshoot voltage.
2.
TOS_MAX is the measured time duration above VccMAX(I1).
3.
Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1.
4.
VccMAX(I1) = VID - I1*RLL + 22 mV
2.9.3
Signal DC Specifications
Table 2-16. PECI DC Specifications
Symbol
Definition and Conditions
Min
Max
Units
-0.150
VccPECI
V
Figure
Notes1
VIn
Input Voltage Range
VHysteresis
Hysteresis
VN
Negative-edge threshold voltage
0.275 * VccPECI
0.50 * VccPECI
V
2-1
2
VP
Positive-edge threshold voltage
0.55 * VccPECI
0.725 * VccPECI
V
2-1
2
RPullup
Pullup Resistance
VOH = 0.75 * VPECI
N/A
50
ohm
ILeak+
High impedance state leakage to VPECI
(Vleak = VOL)
N/A
50
µA
3
ILeak-
High impedance leakage to GND
(Vleak = VOH)
N/A
25
µA
3
CBus
Bus capacitance per node
N/A
10
pF
4,5
VNoise
Signal noise immunity above 300 MHz
0.1 * VccPECI
N/A
Vp-p
Resistance
0.1 * VccPECI
V
Notes:
1.
VccPECI supplies the PECI interface for Intel® Xeon® E7 v3 .
2.
It is expected that the PECI driver will take into account the variance in the receiver input thresholds and consequently, be
able to drive its output within safe limits.
3.
The leakage specification applies to powered devices on the PECI bus.
4.
One node is counted for each client and one node for the system host. Extended trace lengths might appear as
additional nodes.
5.
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit
rate at which the interface can operate.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
35
Table 2-17. System Reference Clock (BCLK{0/1}) DC Specifications
Symbol
Parameter
Signal
Min
VBCLK_diff_ih
VBCLK_diff_il
Differential Input High Voltage
Differential
0.150
Differential Input Low Voltage
Differential
Vcross (abs)
Absolute Crossing Point
Vcross(rel)
Relative Crossing Point
∆Vcross
Max
Unit
Figure
N/A
V
2-7
-0.150
V
2-7
Notes1
Single-ended
0.250
0.550
V
2-6
2-8
2, 4, 7
Single-ended
0.250 +
0.5*(VHavg 0.700)
0.550 +
0.5*(VHavg 0.700)
V
2-6
3, 4, 5
Range of Crossing Points
Single-ended
N/A
0.140
V
2-9
6
Single-ended
Vcross - 0.1
VcrIoss + 0.1
V
1.50
µA
1.1
pF
VTH
Threshold Voltage
IIL
Input Leakage Current
N/A
Cpad
Pad Capacitance
N/A
0.9
8
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling
edge of BCLK{0/1}_DP.
3.
VHavg is the statistical average of the VH measured by the oscilloscope.
4.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5.
VHavg can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.
6.
VCROSS is defined as the total variation of all crossing voltages as defined in Note 3.
7.
The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.
8.
For Vin between 0 and Vih.
Table 2-18. SMBus DC Specifications
Symbol
Parameter
VIL
Input Low Voltage
Min
Max
Unit
0.3*VTT
V
V
VIH
Input High Voltage
VOL
Output Low Voltage
0.2*VTT
VOH
Output High Voltage
VTT(max)
V
RON
Buffer On Resistance
14
W
IL
Leakage Current
Signals MEM_SCL_C[3:0], MEM_SDA_C[3:0]
+100
µA
IL
Leakage Current
Signals VPP_SCL, VPP_SDA
(RTEST = 50 ohm)
+900
µA
0.7*VTT
-100
Notes
V
Table 2-19. JTAG and TAP Signals DC Specifications (Sheet 1 of 2)
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
(RTEST = 500 ohm)
VOH
Output High Voltage
(RTEST = 500 ohm)
RON
Buffer On Resistance
Signals BPM_N[7:0], TDO, EAR_N
IIL
Input Leakage Current
Signals PREQ_N, TCK, TDI, TMS, TRST_N
36
Min
Max
Unit
0.3*VTT
V
0.7*VTT
V
0.12*VTT
V
V
0.88*VTT
-50
Notes
14
W
+50
µA
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 2-19. JTAG and TAP Signals DC Specifications (Sheet 2 of 2)
Symbol
IIL
Parameter
Min
Input Leakage Current
Signals BPM_N[7:0], TDO, EAR_N
(RTEST = 50 ohm)
IO
Output Current
Signal PRDY_N
(RTEST = 500 ohm)
-1.50
Input Edge Rate
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK,
TDI, TMS, TRST_N
0.05
Max
Unit
+900
µA
+1.50
µA
Notes
V/ns
1
Note:
1.
These are measured between VIL and VIH.
Table 2-20. Serial VID Interface (SVID) DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VTT - 3%
1.05
VTT + 3%
V
0.3*VTT
V
1
V
1
VTT
CPU I/O Voltage
VIL
Input Low Voltage
Signals SVIDDATA, SVIDALERT_N
VIH
Input High Voltage
Signals SVIDDATA, SVIDALERT_N
VOH
Output High Voltage
Signals SVIDCLK, SVIDDATA
VTT(max)
V
1
RON
Buffer On Resistance
Signals SVIDCLK, SVIDDATA
14
ohm
2
IIL
Input Leakage Current
Signals SVIDCLK, SVIDDATA
+900
µA
3
IIL
Input Leakage Current
Signal SVIDALERT_N
+500
µA
3
0.7*VTT
-500
Notes:
1.
VTT refers to instantaneous VTT
2.
Measured at 0.31*VTT
3.
Vin between 0 V and VTT
Table 2-21. Processor Asynchronous Sideband DC Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Input Edge Rate
Signals: CAT_ERR_N, CPU_ONLY_RESET,
MEM_HOT_C{01/23}_N, PMSYNC, PROCHOT_N,
PWRGOOD, RESET_N
0.05
Max
Unit
Notes
V/ns
5
V
1,2
V
1,2
V
1,2,4,
V
1,2,4
V
1,2
V
1,2
µA
1,2
CMOS1.0v Signals
VIL_CMOS1.0v
Input Low Voltage
VIH_CMOS1.0v
Input High Voltage
VIL_MAX
Input Low Voltage
Signal PWRGOOD
VIH_MIN
Input High Voltage
Signal PWRGOOD
VOL_CMOS1.0v
Output Low Voltage
VOH_CMOS1.0v
Output High Voltage
IIL_CMOS1.0v
Input Leakage Current
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0.3*VTT
0.7*VTT
0.320
0.640
0.12*VTT
0.88*VTT
-50
+50
37
Table 2-21. Processor Asynchronous Sideband DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
-1.50
+1.50
µA
1,2
IO_CMOS1.0v
Output Current
(RTEST = 500 ohm)
ANM_Rise
Nonmonotonicity Amplitude, Rising Edge
Signal PWRGOOD
0.135
V
4
ANM_Fall
Nonmonotonicity Amplitude, Falling Edge
Signal PWRGOOD
0.165
V
4
0.3*VTT
V
1,2
V
1,2
VTT(max)
V
1,2
+100
µA
3
+900
µA
3
14
ohm
1,2
Open Drain CMOS (ODCMOS) Signals
VIL_ODCMOS
Input Low Voltage
VIH_ODCMOS
Input High Voltage
VOH_ODCMOS
Output High Voltage
Signals: CAT_ERR_N, ERROR_N[2:0],
THERMTRIP_N, PROCHOT_N, CPU_ONLY_RESET
IOL
Output Leakage Current,
Signal MEM_HOT_C{01/23}_N
IOL
Output Leakage Current
(RTEST = 50 ohm)
RON
Buffer On Resistance
Signals: CAT_ERR_N, CPU_ONLY_RESET,
ERROR_N[2:0], MEM_HOT_C{01/23}_N,
PROCHOT_N, THERMTRIP_N
0.7*VTT
-100
Note:
1.
This table applies to the processor sideband and miscellaneous signals specified in Table 2-5.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3.
For Vin between 0 and Voh.
4.
PWRGOOD Non Monotonicity duration (TNM) time is maximum 1.3 ns. See Figure 2-10 “PWRGOOD Signal Waveform”.
5.
These are measured between VIL and VIH.
Table 2-22. Miscellaneous Signals DC Specifications
Symbol
Parameter
Min
Typical
Max
Unit
3.30
3.50
V
1
mA
Notes
SKTOCC_N Signal
VO_ABS_MAX
Output Absolute Max Voltage
IOMAX
Output Max Current
2.9.3.1
PCI Express* DC Specifications
Intel® Xeon® E7 v3 processor DC specifications for the PCI Express* are available in
the PCI Express® Base Specification - Revision 3.0 DRAFT document, which provides
only the processor exceptions to the specification.
2.9.3.2
DMI2/PCI Express DC Specifications
Intel® Xeon® E7 v3 processor DC specifications for the DMI2/PCI Express* are
available in the PCI Express® Base Specification 2.0 and 1.0 document, which provides
only the processor exceptions to the specification.
2.9.3.3
Intel QuickPath Interconnect DC Specifications
Intel® QuickPath Interconnect specifications are defined at the processor lands. In
most cases, termination resistors are not required as these are integrated into the
processor silicon.
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Datasheet Volume 1: EMTS, May 2015
2.9.3.4
Reset and Miscellaneous Signal DC Specifications
For a power-on Reset, RESET_N must stay active for at least 3.5 millisecond after VCC
and BCLK{0/1} have reached their proper specifications. RESET_N must not be kept
asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held
asserted for at least 3.5 millisecond before it is deasserted again. RESET_N must be
held asserted before PWRGOOD is asserted. This signal does not have on-die
termination and must be terminated on the system board.
Figure 2-6.
BCLK{0/1} Differential Clock Crosspoint Specification
650
Crossing Point (mV)
600
550
550 mV
500
550 + 0.5 (VHavg - 700)
450
400
250 + 0.5 (VHavg - 700)
350
300
250 mV
250
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 2-7.
BCLK{0/1} Differential Clock Measurement Point for Ringback
T STABLE
VRB-Differential
VIH = +150 mV
VRB = +100 mV
0.0V
VRB = -100 mV
VIL = -150 mV
REFCLK +
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
T STABLE
VRB-Differential
39
Figure 2-8.
BCLK{0/1} Single-Ended Clock Measurement Points for Absolute Crosspoint,
Swing
VMAX = 1.40V
BCLK_DN
VCROSS MAX = 550mV
VCROSS MIN = 250mV
BCLK_DP
VMIN = -0.30V
Figure 2-9.
BCLK{0/1} Single-Ended Clock Measurement Points for Delta Crosspoint
BCLK_DN
VCROSS DELTA = 140 mV
BCLK_DP
Figure 2-10. PWRGOOD Signal Waveform
Vovershoot
TNM
VIL_MAX
ANM_rise
ANM_fall
VIH_MIN
TNM
Vundershoot
2.10
Signal Quality
Data transfer requires the clean reception of data signals and clock signals. Ringing
below receiver thresholds, non-monotonic signal edges, and excessive voltage swings
will adversely affect system timings. Ringback and signal nonmonotonicity cannot be
40
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Datasheet Volume 1: EMTS, May 2015
tolerated since these phenomena may inadvertently advance receiver state machines.
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate
oxide integrity and can cause device failure if absolute voltage limits are exceeded.
Overshoot and undershoot can also cause timing degradation due to the build up of
intersymbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides
acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation. All specifications are specified at the processor die (pad
measurements).
Specifications for signal quality are for measurements at the processor core only and
are only observable through simulation. Therefore, proper simulation is the only way to
verify proper timing and signal quality.
2.10.1
Intel® Scalable Memory Interconnect Gen 2 (Intel® SMI2)
Signal Quality Specifications
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below VSS. The overshoot/undershoot specifications limit transitions beyond specified
maximum voltages or VSS due to the fast signal edge rates. The processor can be
damaged by single and/or repeated overshoot or undershoot events on any input,
output, or I/O buffer if the charge is large enough (that is, if the over/undershoot is
great enough). Baseboard designs which meet signal integrity and timing requirements
and which do not exceed the maximum overshoot or undershoot limits listed in
Table 2-23 will insure reliable IO performance for the lifetime of the processor.
2.10.2
I/O Signal Quality Specifications
Signal Quality specifications for PCIe Signals are included as part of the PCIe DC
specifications.
2.10.3
Intel® QuickPath Interconnect Signal Quality
Specifications
Signal Quality specifications for Differential Intel® QuickPath Interconnect Signals are
included as part of the Intel QuickPath Interconnect defined in the Intel® QuickPath
Interconnect V1.1 Base Electrical Specification and Validation Methodologies.
2.10.4
Input Reference Clock Signal Quality Specifications
Overshoot/Undershoot and Ringback specifications for BCLK{0/1}_D[N/P] are found in
Table 2-23. Overshoot/Undershoot and Ringback specifications for the DDR3 Reference
Clocks are specified by the DIMM.
2.10.5
Overshoot/Undershoot Tolerance
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below VSS, see Figure 2-11. The overshoot/undershoot specifications limit transitions
beyond VVMSE or VSS due to the fast signal edge rates. The processor can be damaged
by single and/or repeated overshoot or undershoot events on any input, output, or I/O
buffer if the charge is large enough (i.e., if the over/undershoot is great enough).
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Datasheet Volume 1: EMTS, May 2015
41
Baseboard designs which meet signal integrity and timing requirements and which do
not exceed the maximum overshoot or undershoot limits listed in Table 2-23 will insure
reliable IO performance for the lifetime of the processor.
2.10.5.1
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage
reference level. For the processor, both are referenced to VSS. It is important to note
that the overshoot and undershoot conditions are separate and their impact must be
determined independently.
The pulse magnitude and duration must be used to determine if the
overshoot/undershoot pulse is within specifications.
2.10.5.2
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total amount of time that an overshoot/undershoot event
exceeds the overshoot/undershoot reference voltage. The total time could encompass
several oscillations above the reference voltage. Multiple overshoot/undershoot pulses
within a single overshoot/undershoot event may need to be measured to determine the
total pulse duration.
Note:
Oscillations below the reference voltage cannot be subtracted from the total
overshoot/undershoot pulse duration.
Table 2-23. Processor I/O Overshoot/Undershoot Specifications
Signal Group
Intel® QuickPath Interconnect
Intel SMI2
Processor Asynchronous Sideband Signals
Miscellaneous Signals
System Reference Clock (BCLK{0/1})
PWRGOOD Signal
Minimum
Undershoot
Maximum
Overshoot
Overshoot
Duration
Undershoot
Duration
Notes
-0.2
1.2
39 ps
15 ps
1, 2
1.25 ns
0.5 ns
1, 2
0
400
-0.35
1.35
1, 2, 3
-.35
1.35
-0.3V
1.15V
N/A
N/A
1, 2
-0.420V
1.28
N/A
N/A
4
Notes:
1.
These specifications are measured at the processor pad.
2.
Refer to Figure 2-11 for description of allowable overshoot/undershoot magnitude and duration.
3.
For PWRGOOD DC specifications see Table 2-21 and Figure 2-10 “PWRGOOD Signal Waveform”.
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Figure 2-11. Maximum Acceptable Overshoot/Undershoot Waveform
Over Shoot
Over Shoot
Duration
Under Shoot
Duration
VSS
Under Shoot
§
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
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3
Processor Land Listing
This chapter provides sorted land list in Section 3.1 and Section 3.2. Table 3-1 is a listing of all
Datasheet Volume 1: EMTS lands ordered alphabetically by land name. Table 3-2 is a listing of all
processor lands ordered by land number.
3.1
Listing by Land Name
Table 3-1.
Land Name (Sheet 1 of 50)
Land Name
Land No.
Table 3-1.
Land Name (Sheet 2 of 50)
Land Name
Buffer Type Direction
BCLK0_DN
AF46
CMOS
I
EAR_N
BCLK0_DP
AH46
CMOS
I
Land No.
Buffer Type Direction
CY58
CMOS
I/O
ERROR_N[0]
AR11
Open Drain
O
AT10
Open Drain
O
BCLK1_DN
AE9
CMOS
I
ERROR_N[1]
BCLK1_DP
AF10
CMOS
I
ERROR_N[2]
AN11
Open Drain
O
H8
CMOS
I
BIST_ENABLE
AY50
CMOS
I
EX_LEGACY_SKT
BMCINIT
AP50
CMOS
I
FIVR_FAULT
AF36
CMOS
O
AD50
CMOS
I
BPM_N[0]
K58
CMOS
I/O
FRMAGENT
BPM_N[1]
L57
CMOS
I/O
MEM_HOT_C01_N
CB48
Open Drain
I/O
CV12
Open Drain
I/O
BPM_N[2]
E57
CMOS
I/O
MEM_HOT_C23_N
BPM_N[3]
C55
CMOS
I/O
MEM_SCL_C0
CN53
Open Drain
I/O
DA29
Open Drain
I/O
BPM_N[4]
B54
CMOS
I/O
MEM_SCL_C1
BPM_N[5]
A53
CMOS
I/O
MEM_SCL_C2
CB18
Open Drain
I/O
CF6
Open Drain
I/O
BPM_N[6]
D54
CMOS
I/O
MEM_SCL_C3
BPM_N[7]
D56
CMOS
I/O
MEM_SDA_C0
BR47
Open Drain
I/O
I/O
MEM_SDA_C1
CN41
Open Drain
I/O
CATERR_N
AG35
DEBUG_EN_N
BD10
CMOS
MEM_SDA_C2
CJ11
Open Drain
I/O
DMI_RX_N[0]
AY8
CMOS
I
MEM_SDA_C3
BK12
Open Drain
I/O
DMI_RX_N[1]
BB8
CMOS
I
MSMI_N
BE53
CMOS
I/O
AE11
GTL
I
DMI_RX_N[2]
BD8
CMOS
I
NMI
DMI_RX_N[3]
BF8
CMOS
I
PE0_RX_N[0]
W35
PCIEX3
I
Y36
PCIEX3
I
DMI_RX_P[0]
BA7
CMOS
I
PE0_RX_N[1]
DMI_RX_P[1]
BC7
CMOS
I
PE0_RX_N[10]
G45
PCIEX3
I
H46
PCIEX3
I
DMI_RX_P[2]
BE7
CMOS
I
PE0_RX_N[11]
DMI_RX_P[3]
BG7
CMOS
I
PE0_RX_N[12]
W43
PCIEX3
I
Y44
PCIEX3
I
DMI_TX_N[0]
AK8
CMOS
O
PE0_RX_N[13]
DMI_TX_N[1]
AM8
CMOS
O
PE0_RX_N[14]
Y46
PCIEX3
I
W45
PCIEX3
I
DMI_TX_N[2]
AP8
CMOS
O
PE0_RX_N[15]
DMI_TX_N[3]
AT8
CMOS
O
PE0_RX_N[2]
W37
PCIEX3
I
Y38
PCIEX3
I
DMI_TX_P[0]
AL7
CMOS
O
PE0_RX_N[3]
DMI_TX_P[1]
AN7
CMOS
O
PE0_RX_N[4]
W39
PCIEX3
I
Y40
PCIEX3
I
DMI_TX_P[2]
AR7
CMOS
O
PE0_RX_N[5]
DMI_TX_P[3]
AU7
CMOS
O
PE0_RX_N[6]
W41
PCIEX3
I
PE0_RX_N[7]
Y42
PCIEX3
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
45
Table 3-1.
Land Name
Land Name (Sheet 3 of 50)
Land No.
Buffer Type Direction
Table 3-1.
Land Name
Land Name (Sheet 4 of 50)
Land No.
Buffer Type Direction
PE0_RX_N[8]
G43
PCIEX3
I
PE0_TX_P[2]
R39
PCIEX3
O
PE0_RX_N[9]
H44
PCIEX3
I
PE0_TX_P[3]
R35
PCIEX3
O
PE0_RX_P[0]
AA35
PCIEX3
O
PE0_TX_P[4]
T36
PCIEX3
O
PE0_RX_P[1]
AB36
PCIEX3
I
PE0_TX_P[5]
R37
PCIEX3
O
PE0_RX_P[10]
J45
PCIEX3
I
PE0_TX_P[6]
T38
PCIEX3
O
PE0_RX_P[11]
K46
PCIEX3
I
PE0_TX_P[7]
K38
PCIEX3
O
PE0_RX_P[12]
AA43
PCIEX3
I
PE0_TX_P[8]
J39
PCIEX3
O
PE0_RX_P[13]
AB44
PCIEX3
I
PE0_TX_P[9]
K40
PCIEX3
O
PE0_RX_P[14]
AB46
PCIEX3
I
PE1_RX_N[0]
AA11
PCIEX3
I
PE0_RX_P[15]
AA45
PCIEX3
I
PE1_RX_N[1]
W11
PCIEX3
I
PE0_RX_P[2]
AA37
PCIEX3
I
PE1_RX_N[10]
B14
PCIEX3
I
PE0_RX_P[3]
AB38
PCIEX3
I
PE1_RX_N[11]
D14
PCIEX3
I
PE0_RX_P[4]
AA39
PCIEX3
I
PE1_RX_N[12]
E11
PCIEX3
I
PE0_RX_P[5]
AB40
PCIEX3
I
PE1_RX_N[13]
A11
PCIEX3
I
PE0_RX_P[6]
AA41
PCIEX3
I
PE1_RX_N[14]
C11
PCIEX3
I
PE0_RX_P[7]
AB42
PCIEX3
I
PE1_RX_N[15]
A9
PCIEX3
I
PE0_RX_P[8]
J43
PCIEX3
I
PE1_RX_N[2]
U11
PCIEX3
I
PE0_RX_P[9]
K44
PCIEX3
I
PE1_RX_N[3]
R11
PCIEX3
I
PE0_TX_N[0]
N41
PCIEX3
O
PE1_RX_N[4]
N11
PCIEX3
I
PE0_TX_N[1]
P40
PCIEX3
O
PE1_RX_N[5]
L11
PCIEX3
I
PE0_TX_N[10]
G41
PCIEX3
O
PE1_RX_N[6]
J11
PCIEX3
I
PE0_TX_N[11]
P42
PCIEX3
O
PE1_RX_N[7]
G11
PCIEX3
I
PE0_TX_N[12]
N43
PCIEX3
O
PE1_RX_N[8]
H14
PCIEX3
I
PE0_TX_N[13]
P44
PCIEX3
O
PE1_RX_N[9]
F14
PCIEX3
I
PE0_TX_N[14]
N45
PCIEX3
O
PE1_RX_P[0]
AB10
PCIEX3
I
PE0_TX_N[15]
P46
PCIEX3
O
PE1_RX_P[1]
Y10
PCIEX3
I
PE0_TX_N[2]
N39
PCIEX3
O
PE1_RX_P[10]
C13
PCIEX3
I
PE0_TX_N[3]
N35
PCIEX3
O
PE1_RX_P[11]
E13
PCIEX3
I
PE0_TX_N[4]
P36
PCIEX3
O
PE1_RX_P[12]
F10
PCIEX3
I
PE0_TX_N[5]
N37
PCIEX3
O
PE1_RX_P[13]
B10
PCIEX3
I
PE0_TX_N[6]
P38
PCIEX3
O
PE1_RX_P[14]
D10
PCIEX3
I
PE0_TX_N[7]
H38
PCIEX3
O
PE1_RX_P[15]
B8
PCIEX3
I
PE0_TX_N[8]
G39
PCIEX3
O
PE1_RX_P[2]
V10
PCIEX3
I
PE0_TX_N[9]
H40
PCIEX3
O
PE1_RX_P[3]
T10
PCIEX3
I
PE0_TX_P[0]
R41
PCIEX3
O
PE1_RX_P[4]
P10
PCIEX3
I
PE0_TX_P[1]
T40
PCIEX3
O
PE1_RX_P[5]
M10
PCIEX3
I
PE0_TX_P[10]
J41
PCIEX3
O
PE1_RX_P[6]
K10
PCIEX3
I
PE0_TX_P[11]
T42
PCIEX3
O
PE1_RX_P[7]
H10
PCIEX3
I
PE0_TX_P[12]
R43
PCIEX3
O
PE1_RX_P[8]
J13
PCIEX3
I
PE0_TX_P[13]
T44
PCIEX3
O
PE1_RX_P[9]
G13
PCIEX3
I
PE0_TX_P[14]
R45
PCIEX3
O
PE1_TX_N[0]
AA17
PCIEX3
O
PE0_TX_P[15]
T46
PCIEX3
O
PE1_TX_N[1]
W17
PCIEX3
O
46
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name (Sheet 5 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 6 of 50)
Land Name
Land No.
Buffer Type Direction
PE1_TX_N[10]
C17
PCIEX3
O
PWRGOOD
BL55
CMOS
I
PE1_TX_N[11]
Y14
PCIEX3
O
QPI0_CLKRX_DN
A43
Intel® QPI
I
®
I
PE1_TX_N[12]
V14
PCIEX3
O
QPI0_CLKRX_DP
C43
Intel
PE1_TX_N[13]
M14
PCIEX3
O
QPI0_CLKTX_DN
AE53
Intel® QPI
O
®
O
QPI
PE1_TX_N[14]
P14
PCIEX3
O
QPI0_CLKTX_DP
AF52
Intel
PE1_TX_N[15]
T14
PCIEX3
O
QPI0_DRX_DN[0]
F34
Intel® QPI
I
QPI
PE1_TX_N[2]
U17
PCIEX3
O
QPI0_DRX_DN[1]
G35
Intel®
QPI
I
PE1_TX_N[3]
R17
PCIEX3
O
QPI0_DRX_DN[10]
B44
Intel® QPI
I
®
PE1_TX_N[4]
N17
PCIEX3
O
QPI0_DRX_DN[11]
A45
Intel
QPI
I
PE1_TX_N[5]
L17
PCIEX3
O
QPI0_DRX_DN[12]
B46
Intel® QPI
I
®
PE1_TX_N[6]
J17
PCIEX3
O
QPI0_DRX_DN[13]
A47
Intel
QPI
I
PE1_TX_N[7]
G17
PCIEX3
O
QPI0_DRX_DN[14]
B48
Intel® QPI
I
PE1_TX_N[8]
E17
PCIEX3
O
QPI0_DRX_DN[15]
A49
Intel®
QPI
I
PE1_TX_N[9]
A17
PCIEX3
O
QPI0_DRX_DN[16]
B50
Intel® QPI
I
®
PE1_TX_P[0]
AB16
PCIEX3
O
QPI0_DRX_DN[17]
C51
Intel
QPI
I
PE1_TX_P[1]
Y16
PCIEX3
O
QPI0_DRX_DN[18]
D52
Intel® QPI
I
®
PE1_TX_P[10]
D16
PCIEX3
O
QPI0_DRX_DN[19]
E53
Intel
QPI
I
PE1_TX_P[11]
AA13
PCIEX3
O
QPI0_DRX_DN[2]
H36
Intel® QPI
I
PE1_TX_P[12]
W13
PCIEX3
O
QPI0_DRX_DN[3]
A35
Intel®
QPI
I
PE1_TX_P[13]
N13
PCIEX3
O
QPI0_DRX_DN[4]
B36
Intel® QPI
I
®
PE1_TX_P[14]
R13
PCIEX3
O
QPI0_DRX_DN[5]
A37
Intel
QPI
I
PE1_TX_P[15]
U13
PCIEX3
O
QPI0_DRX_DN[6]
B38
Intel® QPI
I
®
PE1_TX_P[2]
V16
PCIEX3
O
QPI0_DRX_DN[7]
A39
Intel
QPI
I
PE1_TX_P[3]
T16
PCIEX3
O
QPI0_DRX_DN[8]
B40
Intel® QPI
I
PE1_TX_P[4]
P16
PCIEX3
O
QPI0_DRX_DN[9]
A41
Intel®
QPI
I
PE1_TX_P[5]
M16
PCIEX3
O
QPI0_DRX_DP[0]
H34
Intel® QPI
I
PE1_TX_P[6]
K16
PCIEX3
O
QPI0_DRX_DP[1]
J35
Intel®
QPI
I
PE1_TX_P[7]
H16
PCIEX3
O
QPI0_DRX_DP[10]
D44
Intel® QPI
I
®
PE1_TX_P[8]
F16
PCIEX3
O
QPI0_DRX_DP[11]
C45
Intel
QPI
I
PE1_TX_P[9]
B16
PCIEX3
O
QPI0_DRX_DP[12]
D46
Intel® QPI
I
®
PECI
AE41
PIROM_ADDR[0]
Y8
PECI
I/O
QPI0_DRX_DP[13]
C47
Intel
QPI
I
I/O
QPI0_DRX_DP[14]
D48
Intel® QPI
I
PIROM_ADDR[1]
L5
I/O
QPI0_DRX_DP[15]
C49
Intel®
QPI
I
PIROM_ADDR[2]
P8
I/O
QPI0_DRX_DP[16]
D50
Intel® QPI
I
®
PM_FAST_WAKE_N
AG11
CMOS
I/O
QPI0_DRX_DP[17]
E51
Intel
QPI
I
PMSYNC
AE45
CMOS
I
QPI0_DRX_DP[18]
F52
Intel® QPI
I
®
PRDY_N
AE39
CMOS
O
QPI0_DRX_DP[19]
G53
Intel
QPI
I
PREQ_N
AE35
CMOS
I
QPI0_DRX_DP[2]
K36
Intel® QPI
I
PROC_ID[0]
AH8
O
QPI0_DRX_DP[3]
C35
Intel®
QPI
I
PROC_ID[1]
AG9
O
QPI0_DRX_DP[4]
D36
Intel® QPI
I
®
PROCHOT_N
AV56
Open Drain
I/O
QPI0_DRX_DP[5]
C37
Intel
QPI
I
PWR_DEBUG_N
BJ9
CMOS
I
QPI0_DRX_DP[6]
D38
Intel® QPI
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
47
Table 3-1.
Land Name (Sheet 7 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 8 of 50)
Land Name
Land No.
Buffer Type Direction
QPI0_DRX_DP[7]
C39
Intel®
QPI
I
QPI0_DTX_DP[9]
AD52
Intel® QPI
O
QPI0_DRX_DP[8]
D40
Intel® QPI
I
QPI1_CLKRX_DN
AF58
Intel® QPI
I
QPI0_DRX_DP[9]
C41
Intel
®
®
I
QPI0_DTX_DN[0]
G49
Intel® QPI
QPI0_DTX_DN[1]
J49
Intel
®
QPI
O
QPI0_DTX_DN[10]
AJ55
Intel® QPI
O
QPI0_DTX_DN[11]
AL55
Intel®
QPI
O
QPI0_DTX_DN[12]
AN55
Intel® QPI
O
QPI0_DTX_DN[13]
AR55
®
Intel
QPI
O
QPI0_DTX_DN[14]
AU55
Intel® QPI
O
QPI0_DTX_DN[15]
AW55
Intel
®
QPI
O
QPI0_DTX_DN[16]
BA55
Intel® QPI
O
QPI0_DTX_DN[17]
BC55
Intel®
QPI
O
QPI0_DTX_DN[18]
BE55
Intel® QPI
O
QPI0_DTX_DN[19]
BG55
Intel
®
QPI
O
QPI0_DTX_DN[2]
L49
Intel® QPI
O
QPI0_DTX_DN[3]
L53
Intel
®
QPI
O
QPI0_DTX_DN[4]
N53
Intel® QPI
O
QPI0_DTX_DN[5]
R53
Intel®
QPI
O
QPI0_DTX_DN[6]
U53
Intel® QPI
O
QPI0_DTX_DN[7]
W53
Intel
®
QPI
O
QPI0_DTX_DN[8]
AA53
Intel® QPI
O
QPI0_DTX_DN[9]
AC53
®
Intel
QPI
O
QPI0_DTX_DP[0]
H48
Intel® QPI
O
QPI0_DTX_DP[1]
K48
Intel®
QPI
O
QPI0_DTX_DP[10]
AK54
Intel® QPI
O
QPI0_DTX_DP[11]
AM54
Intel®
QPI
O
QPI0_DTX_DP[12]
AP54
Intel® QPI
O
QPI0_DTX_DP[13]
AT54
®
Intel
QPI
O
QPI0_DTX_DP[14]
AV54
Intel® QPI
O
QPI0_DTX_DP[15]
AY54
®
Intel
QPI
O
QPI0_DTX_DP[16]
BB54
Intel® QPI
O
QPI0_DTX_DP[17]
BD54
Intel®
QPI
O
QPI0_DTX_DP[18]
BF54
Intel® QPI
O
QPI0_DTX_DP[19]
BH54
®
Intel
QPI
O
QPI0_DTX_DP[2]
M48
Intel® QPI
O
QPI0_DTX_DP[3]
M52
Intel
®
QPI
O
QPI0_DTX_DP[4]
P52
Intel® QPI
O
QPI0_DTX_DP[5]
T52
Intel®
QPI
O
QPI0_DTX_DP[6]
V52
Intel® QPI
O
QPI0_DTX_DP[7]
Y52
Intel
®
QPI
O
QPI0_DTX_DP[8]
AB52
Intel® QPI
O
48
QPI
I
QPI1_CLKRX_DP
AG57
Intel
O
QPI1_CLKTX_DN
AK52
Intel® QPI
O
QPI1_CLKTX_DP
AL51
Intel
®
O
QPI1_DRX_DN[0]
BF58
Intel® QPI
I
QPI1_DRX_DN[1]
BD58
Intel®
QPI
I
QPI1_DRX_DN[10]
AD56
Intel® QPI
I
QPI1_DRX_DN[11]
AB56
®
Intel
QPI
I
QPI1_DRX_DN[12]
Y56
Intel® QPI
I
QPI1_DRX_DN[13]
V56
Intel
®
QPI
I
QPI1_DRX_DN[14]
T56
Intel® QPI
I
QPI1_DRX_DN[15]
P56
Intel®
QPI
I
QPI1_DRX_DN[16]
M56
Intel® QPI
I
QPI1_DRX_DN[17]
K56
Intel
®
QPI
I
QPI1_DRX_DN[18]
H56
Intel® QPI
I
QPI1_DRX_DN[19]
F56
Intel
®
QPI
I
QPI1_DRX_DN[2]
BB58
Intel® QPI
I
QPI1_DRX_DN[3]
AY58
Intel®
QPI
I
QPI1_DRX_DN[4]
AV58
Intel® QPI
I
QPI1_DRX_DN[5]
AT58
Intel
®
QPI
I
QPI1_DRX_DN[6]
AP58
Intel® QPI
I
QPI1_DRX_DN[7]
AM58
Intel
®
QPI
I
QPI1_DRX_DN[8]
AK58
Intel® QPI
I
QPI1_DRX_DN[9]
AH58
Intel®
QPI
I
QPI1_DRX_DP[0]
BG57
Intel® QPI
I
QPI1_DRX_DP[1]
BE57
Intel®
QPI
I
QPI1_DRX_DP[10]
AE55
Intel® QPI
I
QPI1_DRX_DP[11]
AC55
Intel
®
QPI
I
QPI1_DRX_DP[12]
AA55
Intel® QPI
I
QPI1_DRX_DP[13]
W55
Intel
®
QPI
I
QPI1_DRX_DP[14]
U55
Intel® QPI
I
QPI1_DRX_DP[15]
R55
Intel®
QPI
I
QPI1_DRX_DP[16]
N55
Intel® QPI
I
QPI1_DRX_DP[17]
L55
Intel
®
QPI
I
QPI1_DRX_DP[18]
J55
Intel® QPI
I
QPI1_DRX_DP[19]
G55
Intel
®
QPI
I
QPI1_DRX_DP[2]
BC57
Intel® QPI
I
QPI1_DRX_DP[3]
BA57
Intel®
QPI
I
QPI1_DRX_DP[4]
AW57
Intel® QPI
I
QPI1_DRX_DP[5]
AU57
®
Intel
QPI
I
QPI1_DRX_DP[6]
AR57
Intel® QPI
I
QPI
QPI
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name (Sheet 9 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 10 of 50)
Land Name
Land No.
Buffer Type Direction
QPI1_DRX_DP[7]
AN57
Intel®
QPI
I
QPI1_DTX_DP[9]
AN51
Intel® QPI
O
QPI1_DRX_DP[8]
AL57
Intel® QPI
I
QPI2_CLKRX_DN
AF2
Intel® QPI
I
QPI1_DRX_DP[9]
AJ57
Intel
®
®
I
QPI1_DTX_DN[0]
BK52
Intel® QPI
QPI1_DTX_DN[1]
BH52
Intel
®
QPI
O
QPI1_DTX_DN[10]
AL49
Intel® QPI
O
QPI1_DTX_DN[11]
AJ49
Intel®
QPI
O
QPI1_DTX_DN[12]
AG49
Intel® QPI
O
QPI1_DTX_DN[13]
AE49
Intel
®
QPI
O
QPI1_DTX_DN[14]
AC49
Intel® QPI
O
QPI1_DTX_DN[15]
AA49
Intel
®
QPI
O
QPI1_DTX_DN[16]
W49
Intel® QPI
O
QPI1_DTX_DN[17]
U49
Intel®
QPI
O
QPI1_DTX_DN[18]
R49
Intel® QPI
O
QPI1_DTX_DN[19]
N49
®
Intel
QPI
O
QPI1_DTX_DN[2]
BF52
Intel® QPI
O
QPI1_DTX_DN[3]
BD52
Intel
®
QPI
O
QPI1_DTX_DN[4]
BB52
Intel® QPI
O
QPI1_DTX_DN[5]
AY52
Intel®
QPI
O
QPI1_DTX_DN[6]
AV52
Intel® QPI
O
QPI1_DTX_DN[7]
AT52
®
Intel
QPI
O
QPI1_DTX_DN[8]
AP52
Intel® QPI
O
QPI1_DTX_DN[9]
AM52
Intel
®
QPI
O
QPI1_DTX_DP[0]
BL51
Intel® QPI
O
QPI1_DTX_DP[1]
BJ51
Intel®
QPI
O
QPI1_DTX_DP[10]
AM48
Intel® QPI
O
QPI1_DTX_DP[11]
AK48
Intel®
QPI
O
QPI1_DTX_DP[12]
AH48
Intel® QPI
O
QPI1_DTX_DP[13]
AF48
®
Intel
QPI
O
QPI1_DTX_DP[14]
AD48
Intel® QPI
O
QPI1_DTX_DP[15]
AB48
®
Intel
QPI
O
QPI1_DTX_DP[16]
Y48
Intel® QPI
O
QPI1_DTX_DP[17]
V48
Intel®
QPI
O
QPI1_DTX_DP[18]
T48
Intel® QPI
O
QPI1_DTX_DP[19]
P48
®
Intel
QPI
O
QPI1_DTX_DP[2]
BG51
Intel® QPI
O
QPI1_DTX_DP[3]
BE51
Intel
®
QPI
O
QPI1_DTX_DP[4]
BC51
Intel® QPI
O
QPI1_DTX_DP[5]
BA51
Intel®
QPI
O
QPI1_DTX_DP[6]
AW51
Intel® QPI
O
QPI1_DTX_DP[7]
AU51
Intel
®
QPI
O
QPI1_DTX_DP[8]
AR51
Intel® QPI
O
QPI
I
QPI2_CLKRX_DP
AG1
Intel
O
QPI2_CLKTX_DP
AE7
Intel® QPI
O
QPI2_CLKTX_DN
AF6
®
Intel
O
QPI2_DRX_DN[0]
F4
Intel® QPI
I
QPI2_DRX_DN[1]
H4
Intel®
QPI
I
QPI2_DRX_DN[10]
AH2
Intel® QPI
I
QPI2_DRX_DN[11]
AK2
Intel
®
QPI
I
QPI2_DRX_DN[12]
AM2
Intel® QPI
I
QPI2_DRX_DN[13]
AP2
Intel
®
QPI
I
QPI2_DRX_DN[14]
AT2
Intel® QPI
I
QPI2_DRX_DN[15]
AV2
Intel®
QPI
I
QPI2_DRX_DN[16]
AY2
Intel® QPI
I
QPI2_DRX_DN[17]
BB2
®
Intel
QPI
I
QPI2_DRX_DN[18]
BD2
Intel® QPI
I
QPI2_DRX_DN[19]
BF2
Intel
®
QPI
I
QPI2_DRX_DN[2]
H2
Intel® QPI
I
QPI2_DRX_DN[3]
K4
Intel®
QPI
I
QPI2_DRX_DN[4]
M4
Intel® QPI
I
QPI2_DRX_DN[5]
P4
Intel
®
QPI
I
QPI2_DRX_DN[6]
T4
Intel® QPI
I
QPI2_DRX_DN[7]
V4
®
Intel
QPI
I
QPI2_DRX_DN[8]
Y4
Intel® QPI
I
QPI2_DRX_DN[9]
AB4
Intel®
QPI
I
QPI2_DRX_DP[0]
G3
Intel® QPI
I
QPI2_DRX_DP[1]
J3
Intel®
QPI
I
QPI2_DRX_DP[10]
AJ1
Intel® QPI
I
QPI2_DRX_DP[11]
AL1
Intel
®
QPI
I
QPI2_DRX_DP[12]
AN1
Intel® QPI
I
QPI2_DRX_DP[13]
AR1
Intel
®
QPI
I
QPI2_DRX_DP[14]
AU1
Intel® QPI
I
QPI2_DRX_DP[15]
AW1
Intel®
QPI
I
QPI2_DRX_DP[16]
BA1
Intel® QPI
I
QPI2_DRX_DP[17]
BC1
Intel
®
QPI
I
QPI2_DRX_DP[18]
BE1
Intel® QPI
I
QPI2_DRX_DP[19]
BG1
Intel
®
QPI
I
QPI2_DRX_DP[2]
J1
Intel® QPI
I
QPI2_DRX_DP[3]
L3
Intel®
QPI
I
QPI2_DRX_DP[4]
N3
Intel® QPI
I
QPI2_DRX_DP[5]
R3
Intel
®
QPI
I
QPI2_DRX_DP[6]
U3
Intel® QPI
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
QPI
QPI
49
Table 3-1.
Land Name (Sheet 11 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name
Land Name (Sheet 12 of 50)
Land No.
Buffer Type Direction
QPI2_DRX_DP[7]
W3
Intel®
QPI
I
QPI2_DTX_DP[9]
AD6
Intel® QPI
O
QPI2_DRX_DP[8]
AA3
Intel® QPI
I
RESET_N
AF38
CMOS
I
QPI2_DRX_DP[9]
AC3
Intel
®
I
RSVD
AC51
QPI2_DTX_DN[0]
E7
Intel® QPI
O
RSVD
AE37
QPI2_DTX_DN[1]
G7
Intel
®
QPI
O
RSVD
DC3
QPI2_DTX_DN[10]
AG5
Intel® QPI
O
RSVD
DB2
QPI2_DTX_DN[11]
AJ5
Intel®
QPI
O
RSVD
DC55
QPI2_DTX_DN[12]
AL5
Intel® QPI
O
RSVD
DF52
QPI2_DTX_DN[13]
AN5
Intel
®
QPI
O
RSVD
DE53
QPI2_DTX_DN[14]
AR5
Intel® QPI
O
RSVD
CW1
QPI2_DTX_DN[15]
AU5
Intel
®
QPI
O
RSVD
DB4
QPI2_DTX_DN[16]
AW5
Intel® QPI
O
RSVD
BY44
QPI2_DTX_DN[17]
BA5
Intel® QPI
O
RSVD
CT46
QPI2_DTX_DN[18]
BC5
Intel® QPI
O
RSVD
BR45
QPI2_DTX_DN[19]
BE5
Intel® QPI
O
RSVD
DC39
QPI2_DTX_DN[2]
J7
Intel® QPI
O
RSVD
DA3
QPI2_DTX_DN[3]
L7
Intel
®
QPI
O
RSVD
DD6
QPI2_DTX_DN[4]
N7
Intel® QPI
O
RSVD
CU1
QPI2_DTX_DN[5]
R7
Intel®
QPI
O
RSVD
DC5
QPI2_DTX_DN[6]
U7
Intel® QPI
O
RSVD
BD46
QPI2_DTX_DN[7]
W7
Intel® QPI
O
RSVD
BF48
QPI2_DTX_DN[8]
AA7
Intel® QPI
O
RSVD
AR49
QPI2_DTX_DN[9]
AC7
Intel
®
QPI
O
RSVD
AR47
QPI2_DTX_DP[0]
F6
Intel® QPI
O
RSVD
BD48
QPI2_DTX_DP[1]
H6
Intel® QPI
O
RSVD
BE49
QPI2_DTX_DP[10]
AH4
Intel® QPI
O
RSVD
BB48
QPI2_DTX_DP[11]
AK4
Intel®
QPI
O
RSVD
BA49
QPI2_DTX_DP[12]
AM4
Intel® QPI
O
RSVD
BE47
QPI2_DTX_DP[13]
AP4
Intel
®
QPI
O
RSVD
BB46
QPI2_DTX_DP[14]
AT4
Intel® QPI
O
RSVD
AM46
QPI2_DTX_DP[15]
AV4
Intel® QPI
O
RSVD
AV46
QPI2_DTX_DP[16]
AY4
Intel® QPI
O
RSVD
AP46
QPI2_DTX_DP[17]
BB4
Intel®
QPI
O
RSVD
AT46
QPI2_DTX_DP[18]
BD4
Intel® QPI
O
RSVD
AT48
QPI2_DTX_DP[19]
BF4
Intel
®
QPI
O
RSVD
AV48
QPI2_DTX_DP[2]
K6
Intel® QPI
O
RSVD
BA47
QPI2_DTX_DP[3]
M6
Intel® QPI
O
RSVD
AU49
QPI2_DTX_DP[4]
P6
Intel® QPI
O
RSVD
AW47
QPI2_DTX_DP[5]
T6
Intel®
QPI
O
RSVD
AW49
QPI2_DTX_DP[6]
V6
Intel® QPI
O
RSVD
B6
QPI2_DTX_DP[7]
Y6
Intel
®
QPI
O
RSVD
A5
QPI2_DTX_DP[8]
AB6
Intel® QPI
O
RSVD
E3
50
QPI
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name (Sheet 13 of 50)
Land Name
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 14 of 50)
Land No.
Buffer Type Direction
RSVD
F2
TEST_6
BY2
RSVD
A7
TEST_7
CV58
RSVD
C3
TEST_8
AF40
RSVD
D2
TEST_9
AG51
RSVD
H58
TEST_10
DB54
RSVD
F58
TEST_11
AP6
RSVD
G37
TEST_12
BD6
RSVD
J37
TEST_13
BA3
RSVD
B52
THERMTRIP_N
BF46
CMOS
O
RSVD
J53
TMS
AH50
CMOS
I
RSVD
K52
TRST_N
AK46
CMOS
I
RSVD
C5
TSC_SYNC
M54
Open Drain
I/O
RSVD
D4
TXT_AGENT
AK10
CMOS
I
RSVD
AC13
TXT_PLTEN
AJ9
CMOS
I
RSVD
AB14
VCC
A19
PWR
RSVD
BM50
VCC
A21
PWR
RSVD
W47
VCC
A23
PWR
RSVD
AF44
VCC
A33
PWR
RSVD
AD44
VCC
AA21
PWR
RSVD
DA57
VCC
AA25
PWR
RSVD
DB56
SAFE_MODE_BOOT
BF56
CMOS
VCC
AA27
PWR
I
VCC
AA31
PWR
SKTOCC_N
BJ3
O
VCC
AA33
PWR
SM_WP
AP10
I
VCC
AB20
PWR
SMBCLK
AL11
I/O
VCC
AB22
PWR
SMBDAT
AM10
I/O
VCC
AB26
PWR
SOCKET_ID[0]
AK56
CMOS
I
VCC
AB28
PWR
SOCKET_ID[1]
AB54
CMOS
I
VCC
AB32
PWR
SOCKET_ID[2]
V54
CMOS
I
VCC
AC21
PWR
SVIDALERT_N
AU11
CMOS
I
VCC
AC25
PWR
SVIDCLK
AV10
Open Drain
O
VCC
AC27
PWR
SVIDDATA
AW11
Open Drain
I/O
VCC
AC31
PWR
SVID_IDLE_N
CF36
CMOS
O
VCC
AC33
PWR
TCK
BG49
CMOS
I
VCC
AD20
PWR
TDI
BF50
CMOS
I
VCC
AD22
PWR
TDO
AJ47
Open Drain
O
VCC
AD26
PWR
TEST_0
CU35
VCC
AD28
PWR
TEST_1
DE55
VCC
AD32
PWR
TEST_2
BW53
VCC
AE13
PWR
TEST_3
CW15
VCC
AE15
PWR
TEST_4
BV10
VCC
AE17
PWR
TEST_5
BT14
VCC
AE21
PWR
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
51
Table 3-1.
Land Name
Land Name (Sheet 15 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 16 of 50)
Land No.
Buffer Type Direction
VCC
AE25
PWR
VCC
AN13
PWR
VCC
AE27
PWR
VCC
AN15
PWR
VCC
AE31
PWR
VCC
AN17
PWR
VCC
AE33
PWR
VCC
AP12
PWR
VCC
AF12
PWR
VCC
AP14
PWR
VCC
AF14
PWR
VCC
AP16
PWR
VCC
AF16
PWR
VCC
AR13
PWR
VCC
AF20
PWR
VCC
AR15
PWR
VCC
AF22
PWR
VCC
AR17
PWR
VCC
AF26
PWR
VCC
AR43
PWR
VCC
AF28
PWR
VCC
AR45
PWR
VCC
AF32
PWR
VCC
AT12
PWR
VCC
AG13
PWR
VCC
AT14
PWR
VCC
AG15
PWR
VCC
AT16
PWR
VCC
AG17
PWR
VCC
AT42
PWR
VCC
AG21
PWR
VCC
AT44
PWR
VCC
AG25
PWR
VCC
AU13
PWR
VCC
AG27
PWR
VCC
AU15
PWR
VCC
AG31
PWR
VCC
AU17
PWR
VCC
AG33
PWR
VCC
AU43
PWR
VCC
AG37
PWR
VCC
AU45
PWR
VCC
AG39
PWR
VCC
AV12
PWR
VCC
AG41
PWR
VCC
AV14
PWR
VCC
AH12
PWR
VCC
AV16
PWR
VCC
AH14
PWR
VCC
AV42
PWR
VCC
AH16
PWR
VCC
AV44
PWR
VCC
AH42
PWR
VCC
AW43
PWR
VCC
AH44
PWR
VCC
AW45
PWR
VCC
AJ13
PWR
VCC
B20
PWR
VCC
AJ15
PWR
VCC
B22
PWR
VCC
AJ17
PWR
VCC
B24
PWR
VCC
AJ43
PWR
VCC
B32
PWR
VCC
AJ45
PWR
VCC
BA13
PWR
VCC
AK12
PWR
VCC
BA15
PWR
VCC
AK14
PWR
VCC
BA17
PWR
VCC
AK16
PWR
VCC
BB12
PWR
VCC
AK42
PWR
VCC
BB14
PWR
VCC
AK44
PWR
VCC
BB16
PWR
VCC
AL43
PWR
VCC
BB42
PWR
VCC
AL45
PWR
VCC
BB44
PWR
VCC
AM42
PWR
VCC
BC13
PWR
VCC
AM44
PWR
VCC
BC15
PWR
52
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 17 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 18 of 50)
Land No.
Buffer Type Direction
VCC
BC17
PWR
VCC
H22
PWR
VCC
BC43
PWR
VCC
H26
PWR
VCC
BC45
PWR
VCC
H28
PWR
VCC
BD12
PWR
VCC
H32
PWR
VCC
BD14
PWR
VCC
J21
PWR
VCC
BD16
PWR
VCC
J25
PWR
VCC
BD42
PWR
VCC
J27
PWR
VCC
BD44
PWR
VCC
J31
PWR
VCC
BE13
PWR
VCC
J33
PWR
VCC
BE15
PWR
VCC
K20
PWR
VCC
BE17
PWR
VCC
K22
PWR
VCC
BE43
PWR
VCC
K26
PWR
VCC
BE45
PWR
VCC
K28
PWR
VCC
BF12
PWR
VCC
K32
PWR
VCC
BF14
PWR
VCC
L21
PWR
VCC
BF16
PWR
VCC
L25
PWR
VCC
BF42
PWR
VCC
L27
PWR
VCC
BF44
PWR
VCC
L31
PWR
VCC
C19
PWR
VCC
L33
PWR
VCC
C21
PWR
VCC
M20
PWR
VCC
C25
PWR
VCC
M22
PWR
VCC
C33
PWR
VCC
M26
PWR
VCC
D20
PWR
VCC
M28
PWR
VCC
D22
PWR
VCC
M32
PWR
VCC
D26
PWR
VCC
N21
PWR
VCC
D32
PWR
VCC
N25
PWR
VCC
E21
PWR
VCC
N27
PWR
VCC
E25
PWR
VCC
N31
PWR
VCC
E27
PWR
VCC
N33
PWR
VCC
E31
PWR
VCC
P20
PWR
VCC
E33
PWR
VCC
P22
PWR
VCC
F20
PWR
VCC
P26
PWR
VCC
F22
PWR
VCC
P28
PWR
VCC
F26
PWR
VCC
P32
PWR
VCC
F28
PWR
VCC
R21
PWR
VCC
F32
PWR
VCC
R25
PWR
VCC
G21
PWR
VCC
R27
PWR
VCC
G25
PWR
VCC
R31
PWR
VCC
G27
PWR
VCC
R33
PWR
VCC
G31
PWR
VCC
T20
PWR
VCC
G33
PWR
VCC
T22
PWR
VCC
H20
PWR
VCC
T26
PWR
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
53
Table 3-1.
Land Name
Land Name (Sheet 19 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 20 of 50)
Land No.
Buffer Type Direction
VCC
T28
PWR
VTTA
V44
PWR
VCC
T32
PWR
VTTA
V46
PWR
VCC
U21
PWR
VTTA
Y50
PWR
VCC
U25
PWR
VTTQ
AC9
PWR
VCC
U27
PWR
VTTQ
AH56
PWR
VCC
U31
PWR
VTTQ
AJ53
PWR
VCC
U33
PWR
VTTQ
AU53
PWR
VCC
V20
PWR
VTTQ
N9
PWR
VCC
V22
PWR
VTTQ
W9
PWR
VCC
V26
PWR
VCCPECI
AD10
PWR
VCC
V28
PWR
VTTA
A13
PWR
VCC
V32
PWR
VTTA
C15
PWR
VCC
W21
PWR
VTTA
BY24
PWR
VCC
W25
PWR
VTTA
D42
PWR
VCC
W27
PWR
VTTA
E9
PWR
VCC
W31
PWR
VTTA
F12
PWR
VCC
W33
PWR
VTTA
F36
PWR
VCC
Y20
PWR
VTTA
F38
PWR
VCC
Y22
PWR
VTTA
F42
PWR
VCC
Y26
PWR
VTTA
G47
PWR
VCC
Y28
PWR
VTTA
H50
PWR
VCC
Y32
PWR
VTTA
J47
PWR
VTTQ
BY30
PWR
VTTQ
BY36
PWR
VCC_SENSE
AF42
VCC33
BE11
O
PWR
VCCIO_IN
AN9
VTTQ
BY42
PWR
VTTA
BP42
PWR
VTTQ
J15
PWR
VTTA
BT42
PWR
VTTQ
J9
PWR
VTTA
BV42
PWR
VTTQ
K14
PWR
VTT_SENSE
J51
VTTA
AA15
VTTA
VTTA
VSA
AJ3
PWR
PWR
VSA
AJ7
PWR
AB12
PWR
VSA
AK6
PWR
AC47
PWR
VSA
AU3
PWR
VTTA
H54
PWR
VSA
AV8
PWR
VTTA
M12
PWR
VSA
AW9
PWR
VTTA
M42
PWR
VSA
AY10
PWR
VTTA
N15
PWR
VSA
AY6
PWR
VTTA
N47
PWR
VSA
BE3
PWR
VTTA
P50
PWR
VSA
BJ17
PWR
VTTA
T12
PWR
VSA
BL17
PWR
VTTA
U51
PWR
VSA
BN17
PWR
VTTA
V36
PWR
VSA_SENSE
BG5
VTTA
V42
PWR
VMSE_PWR_OK
DC19
54
O
O
SMI2
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 21 of 50)
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 22 of 50)
Land Name
Land No.
Buffer Type Direction
VMSE0_CLK_N
BM44
SMI2
O
VMSE0_DQ[3]
DC53
SMI2
I/O
VMSE0_CLK_P
BN45
SMI2
O
VMSE0_DQ[30]
CN57
SMI2
I/O
VMSE0_CMD[0]
BH44
SMI2
O
VMSE0_DQ[31]
CN55
SMI2
I/O
VMSE0_CMD[1]
BV46
SMI2
O
VMSE0_DQ[32]
CN49
SMI2
I/O
VMSE0_CMD[10]
BM48
SMI2
O
VMSE0_DQ[33]
CM52
SMI2
I/O
VMSE0_CMD[11]
BL47
SMI2
O
VMSE0_DQ[34]
CK48
SMI2
I/O
VMSE0_CMD[12]
BJ49
SMI2
O
VMSE0_DQ[35]
CJ49
SMI2
I/O
VMSE0_CMD[13]
BM46
SMI2
O
VMSE0_DQ[36]
CN51
SMI2
I/O
VMSE0_CMD[14]
BL49
SMI2
O
VMSE0_DQ[37]
CM48
SMI2
I/O
VMSE0_CMD[15]
BH46
SMI2
O
VMSE0_DQ[38]
CJ51
SMI2
I/O
VMSE0_CMD[16]
BJ47
SMI2
O
VMSE0_DQ[39]
CK52
SMI2
I/O
VMSE0_CMD[2]
BV44
SMI2
O
VMSE0_DQ[4]
DF48
SMI2
I/O
VMSE0_CMD[3]
BJ45
SMI2
O
VMSE0_DQ[40]
CF50
SMI2
I/O
VMSE0_CMD[4]
BJ43
SMI2
O
VMSE0_DQ[41]
CE53
SMI2
I/O
VMSE0_CMD[5]
BT46
SMI2
O
VMSE0_DQ[42]
CB52
SMI2
I/O
VMSE0_CMD[6]
BT44
SMI2
O
VMSE0_DQ[43]
CB50
SMI2
I/O
VMSE0_CMD[7]
BW45
SMI2
O
VMSE0_DQ[44]
CF52
SMI2
I/O
VMSE0_CMD[8]
BL43
SMI2
O
VMSE0_DQ[45]
CE49
SMI2
I/O
VMSE0_CMD[9]
BL45
SMI2
O
VMSE0_DQ[46]
CC49
SMI2
I/O
VMSE0_DQ[0]
DE47
SMI2
I/O
VMSE0_DQ[47]
CC53
SMI2
I/O
VMSE0_DQ[1]
DC49
SMI2
I/O
VMSE0_DQ[48]
BV48
SMI2
I/O
VMSE0_DQ[10]
CW51
SMI2
I/O
VMSE0_DQ[49]
BR49
SMI2
I/O
VMSE0_DQ[11]
CU51
SMI2
I/O
VMSE0_DQ[5]
DC47
SMI2
I/O
VMSE0_DQ[12]
CU47
SMI2
I/O
VMSE0_DQ[50]
BV52
SMI2
I/O
VMSE0_DQ[13]
CY48
SMI2
I/O
VMSE0_DQ[51]
BR51
SMI2
I/O
VMSE0_DQ[14]
CT50
SMI2
I/O
VMSE0_DQ[52]
BW49
SMI2
I/O
VMSE0_DQ[15]
CY50
SMI2
I/O
VMSE0_DQ[53]
BT48
SMI2
I/O
VMSE0_DQ[16]
CU53
SMI2
I/O
VMSE0_DQ[54]
BT52
SMI2
I/O
VMSE0_DQ[17]
CY54
SMI2
I/O
VMSE0_DQ[55]
BW51
SMI2
I/O
VMSE0_DQ[18]
CU57
SMI2
I/O
VMSE0_DQ[56]
BT54
SMI2
I/O
VMSE0_DQ[19]
CW57
SMI2
I/O
VMSE0_DQ[57]
BM54
SMI2
I/O
VMSE0_DQ[2]
DC51
SMI2
I/O
VMSE0_DQ[58]
BN57
SMI2
I/O
VMSE0_DQ[20]
CW53
SMI2
I/O
VMSE0_DQ[59]
BK58
SMI2
I/O
VMSE0_DQ[21]
CT54
SMI2
I/O
VMSE0_DQ[6]
DD52
SMI2
I/O
VMSE0_DQ[22]
CY56
SMI2
I/O
VMSE0_DQ[60]
BN53
SMI2
I/O
VMSE0_DQ[23]
CT56
SMI2
I/O
VMSE0_DQ[61]
BR55
SMI2
I/O
VMSE0_DQ[24]
CH54
SMI2
I/O
VMSE0_DQ[62]
BL57
SMI2
I/O
VMSE0_DQ[25]
CH56
SMI2
I/O
VMSE0_DQ[63]
BP58
SMI2
I/O
VMSE0_DQ[26]
CM56
SMI2
I/O
VMSE0_DQ[7]
DF50
SMI2
I/O
VMSE0_DQ[27]
CP58
SMI2
I/O
VMSE0_DQ[8]
CW47
SMI2
I/O
VMSE0_DQ[28]
CG55
SMI2
I/O
VMSE0_DQ[9]
CT48
SMI2
I/O
VMSE0_DQ[29]
CK54
SMI2
I/O
VMSE0_DQS_N[0]
DD50
SMI2
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
55
Table 3-1.
Land Name (Sheet 23 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name
Land Name (Sheet 24 of 50)
Land No.
Buffer Type Direction
VMSE0_DQS_N[1]
CW49
SMI2
I/O
VMSE1_CMD[7]
CY36
SMI2
O
VMSE0_DQS_N[2]
CU55
SMI2
I/O
VMSE1_CMD[8]
CY38
SMI2
O
VMSE0_DQS_N[3]
CM54
SMI2
I/O
VMSE1_CMD[9]
CR41
SMI2
O
VMSE0_DQS_N[4]
CM50
SMI2
I/O
VMSE1_DQ[0]
CC31
SMI2
I/O
VMSE0_DQS_N[5]
CE51
SMI2
I/O
VMSE1_DQ[1]
CF32
SMI2
I/O
VMSE0_DQS_N[6]
BT50
SMI2
I/O
VMSE1_DQ[10]
CJ33
SMI2
I/O
VMSE0_DQS_N[7]
BP56
SMI2
I/O
VMSE1_DQ[11]
CK34
SMI2
I/O
VMSE0_DQS_N[8]
BV56
SMI2
I/O
VMSE1_DQ[12]
CN31
SMI2
I/O
VMSE0_DQS_P[0]
DE49
SMI2
I/O
VMSE1_DQ[13]
CK30
SMI2
I/O
VMSE0_DQS_P[1]
CU49
SMI2
I/O
VMSE1_DQ[14]
CM34
SMI2
I/O
VMSE0_DQS_P[2]
CW55
SMI2
I/O
VMSE1_DQ[15]
CN33
SMI2
I/O
VMSE0_DQS_P[3]
CL55
SMI2
I/O
VMSE1_DQ[16]
CV30
SMI2
I/O
VMSE0_DQS_P[4]
CK50
SMI2
I/O
VMSE1_DQ[17]
DA31
SMI2
I/O
VMSE0_DQS_P[5]
CC51
SMI2
I/O
VMSE1_DQ[18]
CV34
SMI2
I/O
VMSE0_DQS_P[6]
BV50
SMI2
I/O
VMSE1_DQ[19]
CY34
SMI2
I/O
VMSE0_DQS_P[7]
BM56
SMI2
I/O
VMSE1_DQ[2]
CC35
SMI2
I/O
VMSE0_DQS_P[8]
BY56
SMI2
I/O
VMSE1_DQ[20]
CY30
SMI2
I/O
VMSE0_ECC[0]
CD56
SMI2
I/O
VMSE1_DQ[21]
CU31
SMI2
I/O
VMSE0_ECC[1]
BW55
SMI2
I/O
VMSE1_DQ[22]
DA33
SMI2
I/O
VMSE0_ECC[2]
BY58
SMI2
I/O
VMSE1_DQ[23]
CU33
SMI2
I/O
VMSE0_ECC[3]
BU57
SMI2
I/O
VMSE1_DQ[24]
DD32
SMI2
I/O
VMSE0_ECC[4]
BY54
SMI2
I/O
VMSE1_DQ[25]
DC35
SMI2
I/O
VMSE0_ECC[5]
CC55
SMI2
I/O
VMSE1_DQ[26]
DC37
SMI2
I/O
VMSE0_ECC[6]
BV58
SMI2
I/O
VMSE1_DQ[27]
DF38
SMI2
I/O
VMSE0_ECC[7]
CA57
SMI2
I/O
VMSE1_DQ[28]
DF34
SMI2
I/O
VMSE0_ERR_N
BY48
SMI2
I/O
VMSE1_DQ[29]
DE33
SMI2
I/O
VMSE1_CLK_N
CY40
SMI2
O
VMSE1_DQ[3]
CE35
SMI2
I/O
VMSE1_CLK_P
CW41
SMI2
O
VMSE1_DQ[30]
DD38
SMI2
I/O
VMSE1_CMD[0]
DA39
SMI2
O
VMSE1_DQ[31]
DF36
SMI2
I/O
VMSE1_CMD[1]
CW37
SMI2
O
VMSE1_DQ[32]
CK36
SMI2
I/O
VMSE1_CMD[10]
CY44
SMI2
O
VMSE1_DQ[33]
CN37
SMI2
I/O
VMSE1_CMD[11]
CT44
SMI2
O
VMSE1_DQ[34]
CK40
SMI2
I/O
VMSE1_CMD[12]
CW45
SMI2
O
VMSE1_DQ[35]
CM40
SMI2
I/O
VMSE1_CMD[13]
CT42
SMI2
O
VMSE1_DQ[36]
CM36
SMI2
I/O
VMSE1_CMD[14]
CU45
SMI2
O
VMSE1_DQ[37]
CJ37
SMI2
I/O
VMSE1_CMD[15]
CY42
SMI2
O
VMSE1_DQ[38]
CN39
SMI2
I/O
VMSE1_CMD[16]
CW43
SMI2
O
VMSE1_DQ[39]
CJ39
SMI2
I/O
VMSE1_CMD[2]
CT36
SMI2
O
VMSE1_DQ[4]
CE31
SMI2
I/O
VMSE1_CMD[3]
CU39
SMI2
O
VMSE1_DQ[40]
CC37
SMI2
I/O
VMSE1_CMD[4]
CT38
SMI2
O
VMSE1_DQ[41]
CF38
SMI2
I/O
VMSE1_CMD[5]
CU37
SMI2
O
VMSE1_DQ[42]
CC41
SMI2
I/O
VMSE1_CMD[6]
CT40
SMI2
O
VMSE1_DQ[43]
CE41
SMI2
I/O
56
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name (Sheet 25 of 50)
Land Name
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 26 of 50)
Land Name
Land No.
Buffer Type Direction
VMSE1_DQ[44]
CE37
SMI2
I/O
VMSE1_DQS_P[8]
DD42
SMI2
I/O
VMSE1_DQ[45]
CB38
SMI2
I/O
VMSE1_ECC[0]
DF40
SMI2
I/O
VMSE1_DQ[46]
CF40
SMI2
I/O
VMSE1_ECC[1]
DF42
SMI2
I/O
VMSE1_DQ[47]
CB40
SMI2
I/O
VMSE1_ECC[2]
DF44
SMI2
I/O
VMSE1_DQ[48]
CK42
SMI2
I/O
VMSE1_ECC[3]
DE45
SMI2
I/O
VMSE1_DQ[49]
CN43
SMI2
I/O
VMSE1_ECC[4]
DC41
SMI2
I/O
VMSE1_DQ[5]
CB32
SMI2
I/O
VMSE1_ECC[5]
DD40
SMI2
I/O
VMSE1_DQ[50]
CK46
SMI2
I/O
VMSE1_ECC[6]
DC45
SMI2
I/O
VMSE1_DQ[51]
CM46
SMI2
I/O
VMSE1_ECC[7]
DC43
SMI2
I/O
VMSE1_DQ[52]
CM42
SMI2
I/O
VMSE1_ERR_N
CR35
SMI2
I/O
VMSE1_DQ[53]
CJ43
SMI2
I/O
VMSE2_CLK_N
CY18
SMI2
O
VMSE1_DQ[54]
CN45
SMI2
I/O
VMSE2_CLK_P
CV18
SMI2
O
VMSE1_DQ[55]
CJ45
SMI2
I/O
VMSE2_CMD[0]
CW17
SMI2
O
VMSE1_DQ[56]
CE43
SMI2
I/O
VMSE2_CMD[1]
CT14
SMI2
O
VMSE1_DQ[57]
CB44
SMI2
I/O
VMSE2_CMD[10]
CT22
SMI2
O
VMSE1_DQ[58]
CE47
SMI2
I/O
VMSE2_CMD[11]
CU21
SMI2
O
VMSE1_DQ[59]
CC47
SMI2
I/O
VMSE2_CMD[12]
CR23
SMI2
O
VMSE1_DQ[6]
CF34
SMI2
I/O
VMSE2_CMD[13]
CU19
SMI2
O
VMSE1_DQ[60]
CC43
SMI2
I/O
VMSE2_CMD[14]
CY22
SMI2
O
VMSE1_DQ[61]
CF44
SMI2
I/O
VMSE2_CMD[15]
CY20
SMI2
O
VMSE1_DQ[62]
CB46
SMI2
I/O
VMSE2_CMD[16]
CT20
SMI2
O
VMSE1_DQ[63]
CF46
SMI2
I/O
VMSE2_CMD[2]
CW13
SMI2
O
VMSE1_DQ[7]
CB34
SMI2
I/O
VMSE2_CMD[3]
CR17
SMI2
O
VMSE1_DQ[8]
CM30
SMI2
I/O
VMSE2_CMD[4]
CT16
SMI2
O
VMSE1_DQ[9]
CJ31
SMI2
I/O
VMSE2_CMD[5]
CU15
SMI2
O
VMSE1_DQS_N[0]
CE33
SMI2
I/O
VMSE2_CMD[6]
CT18
SMI2
O
VMSE1_DQS_N[1]
CM32
SMI2
I/O
VMSE2_CMD[7]
CY14
SMI2
O
VMSE1_DQS_N[2]
CV32
SMI2
I/O
VMSE2_CMD[8]
CY16
SMI2
O
VMSE1_DQS_N[3]
DE35
SMI2
I/O
VMSE2_CMD[9]
DA19
SMI2
O
VMSE1_DQS_N[4]
CK38
SMI2
I/O
VMSE2_DQ[0]
CK12
SMI2
I/O
VMSE1_DQS_N[5]
CC39
SMI2
I/O
VMSE2_DQ[1]
CN13
SMI2
I/O
VMSE1_DQS_N[6]
CM44
SMI2
I/O
VMSE2_DQ[10]
CW11
SMI2
I/O
VMSE1_DQS_N[7]
CE45
SMI2
I/O
VMSE2_DQ[11]
CR11
SMI2
I/O
VMSE1_DQS_N[8]
DE43
SMI2
I/O
VMSE2_DQ[12]
CU7
SMI2
I/O
VMSE1_DQS_P[0]
CC33
SMI2
I/O
VMSE2_DQ[13]
CY8
SMI2
I/O
VMSE1_DQS_P[1]
CK32
SMI2
I/O
VMSE2_DQ[14]
CT10
SMI2
I/O
VMSE1_DQS_P[2]
CY32
SMI2
I/O
VMSE2_DQ[15]
CV10
SMI2
I/O
VMSE1_DQS_P[3]
DD36
SMI2
I/O
VMSE2_DQ[16]
CK18
SMI2
I/O
VMSE1_DQS_P[4]
CM38
SMI2
I/O
VMSE2_DQ[17]
CN19
SMI2
I/O
VMSE1_DQS_P[5]
CE39
SMI2
I/O
VMSE2_DQ[18]
CK22
SMI2
I/O
VMSE1_DQS_P[6]
CK44
SMI2
I/O
VMSE2_DQ[19]
CM22
SMI2
I/O
VMSE1_DQS_P[7]
CC45
SMI2
I/O
VMSE2_DQ[2]
CK16
SMI2
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
57
Table 3-1.
Land Name
Land Name (Sheet 27 of 50)
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 28 of 50)
Land Name
Land No.
Buffer Type Direction
VMSE2_DQ[20]
CM18
SMI2
I/O
VMSE2_DQ[59]
CV28
SMI2
I/O
VMSE2_DQ[21]
CJ19
SMI2
I/O
VMSE2_DQ[6]
CN15
SMI2
I/O
VMSE2_DQ[22]
CN21
SMI2
I/O
VMSE2_DQ[60]
DA25
SMI2
I/O
VMSE2_DQ[23]
CJ21
SMI2
I/O
VMSE2_DQ[61]
CV24
SMI2
I/O
VMSE2_DQ[24]
DE13
SMI2
I/O
VMSE2_DQ[62]
CY28
SMI2
I/O
VMSE2_DQ[25]
DC15
SMI2
I/O
VMSE2_DQ[63]
DA27
SMI2
I/O
VMSE2_DQ[26]
DC17
SMI2
I/O
VMSE2_DQ[7]
CJ15
SMI2
I/O
VMSE2_DQ[27]
DF18
SMI2
I/O
VMSE2_DQ[8]
CW7
SMI2
I/O
VMSE2_DQ[28]
DF14
SMI2
I/O
VMSE2_DQ[9]
CT8
SMI2
I/O
VMSE2_DQ[29]
DC13
SMI2
I/O
VMSE2_DQS_N[0]
CM14
SMI2
I/O
VMSE2_DQ[3]
CM16
SMI2
I/O
VMSE2_DQS_N[1]
CW9
SMI2
I/O
VMSE2_DQ[30]
DD18
SMI2
I/O
VMSE2_DQS_N[2]
CK20
SMI2
I/O
VMSE2_DQ[31]
DF16
SMI2
I/O
VMSE2_DQS_N[3]
DE15
SMI2
I/O
VMSE2_DQ[32]
CC25
SMI2
I/O
VMSE2_DQS_N[4]
CC27
SMI2
I/O
VMSE2_DQ[33]
CF26
SMI2
I/O
VMSE2_DQS_N[5]
CE21
SMI2
I/O
VMSE2_DQ[34]
CF28
SMI2
I/O
VMSE2_DQS_N[6]
CK26
SMI2
I/O
VMSE2_DQ[35]
CE29
SMI2
I/O
VMSE2_DQS_N[7]
CY26
SMI2
I/O
VMSE2_DQ[36]
CE25
SMI2
I/O
VMSE2_DQS_N[8]
DE23
SMI2
I/O
VMSE2_DQ[37]
CB26
SMI2
I/O
VMSE2_DQS_P[0]
CK14
SMI2
I/O
VMSE2_DQ[38]
CC29
SMI2
I/O
VMSE2_DQS_P[1]
CU9
SMI2
I/O
VMSE2_DQ[39]
CB28
SMI2
I/O
VMSE2_DQS_P[2]
CM20
SMI2
I/O
VMSE2_DQ[4]
CM12
SMI2
I/O
VMSE2_DQS_P[3]
DD16
SMI2
I/O
VMSE2_DQ[40]
CE19
SMI2
I/O
VMSE2_DQS_P[4]
CE27
SMI2
I/O
VMSE2_DQ[41]
CB20
SMI2
I/O
VMSE2_DQS_P[5]
CC21
SMI2
I/O
VMSE2_DQ[42]
CE23
SMI2
I/O
VMSE2_DQS_P[6]
CM26
SMI2
I/O
VMSE2_DQ[43]
CC23
SMI2
I/O
VMSE2_DQS_P[7]
CV26
SMI2
I/O
VMSE2_DQ[44]
CC19
SMI2
I/O
VMSE2_DQS_P[8]
DD22
SMI2
I/O
VMSE2_DQ[45]
CF20
SMI2
I/O
VMSE2_ECC[0]
DF20
SMI2
I/O
VMSE2_DQ[46]
CB22
SMI2
I/O
VMSE2_ECC[1]
DF22
SMI2
I/O
VMSE2_DQ[47]
CF22
SMI2
I/O
VMSE2_ECC[2]
DF24
SMI2
I/O
VMSE2_DQ[48]
CM24
SMI2
I/O
VMSE2_ECC[3]
DD26
SMI2
I/O
VMSE2_DQ[49]
CJ25
SMI2
I/O
VMSE2_ECC[4]
DC21
SMI2
I/O
VMSE2_DQ[5]
CJ13
SMI2
I/O
VMSE2_ECC[5]
DD20
SMI2
I/O
VMSE2_DQ[50]
CM28
SMI2
I/O
VMSE2_ECC[6]
DE25
SMI2
I/O
VMSE2_DQ[51]
CK28
SMI2
I/O
VMSE2_ECC[7]
DC23
SMI2
I/O
VMSE2_DQ[52]
CK24
SMI2
I/O
VMSE2_ERR_N
CU13
SMI2
I/O
VMSE2_DQ[53]
CN25
SMI2
I/O
VMSE3_CLK_N
BK14
SMI2
O
VMSE2_DQ[54]
CJ27
SMI2
I/O
VMSE3_CLK_P
BM14
SMI2
O
VMSE2_DQ[55]
CN27
SMI2
I/O
VMSE3_CMD[0]
BJ15
SMI2
O
VMSE2_DQ[56]
CY24
SMI2
I/O
VMSE3_CMD[1]
BU11
SMI2
O
VMSE2_DQ[57]
CU25
SMI2
I/O
VMSE3_CMD[10]
BW15
SMI2
O
VMSE2_DQ[58]
CU27
SMI2
I/O
VMSE3_CMD[11]
BV14
SMI2
O
58
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 29 of 50)
Land No.
Buffer Type Direction
Table 3-1.
Land Name (Sheet 30 of 50)
Land Name
Land No.
Buffer Type Direction
VMSE3_CMD[12]
BV16
SMI2
O
VMSE3_DQ[35]
CN9
SMI2
I/O
VMSE3_CMD[13]
BR15
SMI2
O
VMSE3_DQ[36]
CJ7
SMI2
I/O
VMSE3_CMD[14]
BT16
SMI2
O
VMSE3_DQ[37]
CK10
SMI2
I/O
VMSE3_CMD[15]
BW13
SMI2
O
VMSE3_DQ[38]
CM10
SMI2
I/O
VMSE3_CMD[16]
BY12
SMI2
O
VMSE3_DQ[39]
CM6
SMI2
I/O
VMSE3_CMD[2]
BU9
SMI2
O
VMSE3_DQ[4]
BK8
SMI2
I/O
VMSE3_CMD[3]
BN13
SMI2
O
VMSE3_DQ[40]
CA1
SMI2
I/O
VMSE3_CMD[4]
BH14
SMI2
O
VMSE3_DQ[41]
CC3
SMI2
I/O
VMSE3_CMD[5]
BW11
SMI2
O
VMSE3_DQ[42]
CG3
SMI2
I/O
VMSE3_CMD[6]
BR13
SMI2
O
VMSE3_DQ[43]
CJ3
SMI2
I/O
VMSE3_CMD[7]
BW9
SMI2
O
VMSE3_DQ[44]
CC5
SMI2
I/O
VMSE3_CMD[8]
BJ13
SMI2
O
VMSE3_DQ[45]
CB2
SMI2
I/O
VMSE3_CMD[9]
BN15
SMI2
O
VMSE3_DQ[46]
CH4
SMI2
I/O
VMSE3_DQ[0]
BK10
SMI2
I/O
VMSE3_DQ[47]
CE5
SMI2
I/O
VMSE3_DQ[1]
BL7
SMI2
I/O
VMSE3_DQ[48]
DA5
SMI2
I/O
VMSE3_DQ[10]
BP2
SMI2
I/O
VMSE3_DQ[49]
DD8
SMI2
I/O
VMSE3_DQ[11]
BP4
SMI2
I/O
VMSE3_DQ[5]
BL11
SMI2
I/O
VMSE3_DQ[12]
BK2
SMI2
I/O
VMSE3_DQ[50]
DE11
SMI2
I/O
VMSE3_DQ[13]
BL5
SMI2
I/O
VMSE3_DQ[51]
DC11
SMI2
I/O
VMSE3_DQ[14]
BN5
SMI2
I/O
VMSE3_DQ[52]
DC7
SMI2
I/O
VMSE3_DQ[15]
BN1
SMI2
I/O
VMSE3_DQ[53]
DB6
SMI2
I/O
VMSE3_DQ[16]
BU7
SMI2
I/O
VMSE3_DQ[54]
DB10
SMI2
I/O
VMSE3_DQ[17]
BU3
SMI2
I/O
VMSE3_DQ[55]
DF10
SMI2
I/O
VMSE3_DQ[18]
BW3
SMI2
I/O
VMSE3_DQ[56]
CR1
SMI2
I/O
VMSE3_DQ[19]
BY4
SMI2
I/O
VMSE3_DQ[57]
CW3
SMI2
I/O
VMSE3_DQ[2]
BP8
SMI2
I/O
VMSE3_DQ[58]
CM4
SMI2
I/O
VMSE3_DQ[20]
BT6
SMI2
I/O
VMSE3_DQ[59]
CR5
SMI2
I/O
VMSE3_DQ[21]
BW7
SMI2
I/O
VMSE3_DQ[6]
BN11
SMI2
I/O
VMSE3_DQ[22]
BY6
SMI2
I/O
VMSE3_DQ[60]
CN3
SMI2
I/O
VMSE3_DQ[23]
BU1
SMI2
I/O
VMSE3_DQ[61]
CT2
SMI2
I/O
VMSE3_DQ[24]
CB16
SMI2
I/O
VMSE3_DQ[62]
CU5
SMI2
I/O
VMSE3_DQ[25]
CC13
SMI2
I/O
VMSE3_DQ[63]
CV4
SMI2
I/O
VMSE3_DQ[26]
CF14
SMI2
I/O
VMSE3_DQ[7]
BN7
SMI2
I/O
VMSE3_DQ[27]
CF16
SMI2
I/O
VMSE3_DQ[8]
BK4
SMI2
I/O
VMSE3_DQ[28]
CB14
SMI2
I/O
VMSE3_DQ[9]
BL1
SMI2
I/O
VMSE3_DQ[29]
CC17
SMI2
I/O
VMSE3_DQS_N[0]
BN9
SMI2
I/O
VMSE3_DQ[3]
BP10
SMI2
I/O
VMSE3_DQS_N[1]
BL3
SMI2
I/O
VMSE3_DQ[30]
CE17
SMI2
I/O
VMSE3_DQS_N[2]
BU5
SMI2
I/O
VMSE3_DQ[31]
CE13
SMI2
I/O
VMSE3_DQS_N[3]
CC15
SMI2
I/O
VMSE3_DQ[32]
CJ9
SMI2
I/O
VMSE3_DQS_N[4]
CK8
SMI2
I/O
VMSE3_DQ[33]
CK6
SMI2
I/O
VMSE3_DQS_N[5]
CD4
SMI2
I/O
VMSE3_DQ[34]
CN7
SMI2
I/O
VMSE3_DQS_N[6]
DC9
SMI2
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
59
Table 3-1.
Land Name (Sheet 31 of 50)
Land Name
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 32 of 50)
Land No.
Buffer Type Direction
VMSE3_DQS_N[7]
CR3
SMI2
I/O
VSS
AC17
GND
VMSE3_DQS_N[8]
CE9
SMI2
I/O
VSS
AC19
GND
VMSE3_DQS_P[0]
BL9
SMI2
I/O
VSS
AC23
GND
VMSE3_DQS_P[1]
BN3
SMI2
I/O
VSS
AC29
GND
VMSE3_DQS_P[2]
BW5
SMI2
I/O
VSS
AC35
GND
VMSE3_DQS_P[3]
CE15
SMI2
I/O
VSS
AC37
GND
VMSE3_DQS_P[4]
CM8
SMI2
I/O
VSS
AC39
GND
VMSE3_DQS_P[5]
CE3
SMI2
I/O
VSS
AC41
GND
VMSE3_DQS_P[6]
DE9
SMI2
I/O
VSS
AC43
GND
VMSE3_DQS_P[7]
CT4
SMI2
I/O
VSS
AC45
GND
VMSE3_DQS_P[8]
CC9
SMI2
I/O
VSS
AC5
GND
VMSE3_ECC[0]
CC7
SMI2
I/O
VSS
AD12
GND
VMSE3_ECC[1]
CF8
SMI2
I/O
VSS
AD14
GND
VMSE3_ECC[2]
CC11
SMI2
I/O
VSS
AD16
GND
VMSE3_ECC[3]
CE11
SMI2
I/O
VSS
AD18
GND
VMSE3_ECC[4]
CE7
SMI2
I/O
VSS
AD24
GND
VMSE3_ECC[5]
CB8
SMI2
I/O
VSS
AD30
GND
VMSE3_ECC[6]
CF10
SMI2
I/O
VSS
AD34
GND
VMSE3_ECC[7]
CB10
SMI2
I/O
VSS
AD36
GND
VMSE3_ERR_N
BT12
SMI2
I/O
VSS
AD38
GND
VPP_SCL
BC11
CMOS
I/O
VSS
AD4
GND
VPP_SDA
BB10
CMOS
I/O
VSS
AD40
GND
VCCPLL
BF10
PWR
VSS
AD42
GND
VCCPLL
BG11
PWR
VSS
AD46
GND
VCCPLL
BH10
PWR
VSS
AD54
GND
VSS
A15
GND
VSS
AD8
GND
VSS
A51
GND
VSS
AE19
GND
VSS
AA19
GND
VSS
AE23
GND
VSS
AA23
GND
VSS
AE29
GND
VSS
AA29
GND
VSS
AE3
GND
VSS
AA47
GND
VSS
AE47
GND
VSS
AA5
GND
VSS
AE5
GND
VSS
AA51
GND
VSS
AE51
GND
VSS
AA9
GND
VSS
AE57
GND
VSS
AB18
GND
VSS
AF18
GND
VSS
AB24
GND
VSS
AF24
GND
VSS
AB30
GND
VSS
AF30
GND
VSS
AB34
GND
VSS
AF34
GND
VSS
AB50
GND
VSS
AF4
GND
VSS
AB8
GND
VSS
AF50
GND
VSS
AC11
GND
VSS
AF54
GND
VSS
AC15
GND
VSS
AF56
GND
60
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 33 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 34 of 50)
Land No.
Buffer Type Direction
VSS
AF8
GND
VSS
AR53
GND
VSS
AG19
GND
VSS
AR9
GND
VSS
AG23
GND
VSS
AT50
GND
VSS
AG29
GND
VSS
AT56
GND
VSS
AG3
GND
VSS
AT6
GND
VSS
AG43
GND
VSS
AU47
GND
VSS
AG45
GND
VSS
AU9
GND
VSS
AG47
GND
VSS
AV50
GND
VSS
AG53
GND
VSS
AV6
GND
VSS
AG55
GND
VSS
AW13
GND
VSS
AG7
GND
VSS
AW15
GND
VSS
AH10
GND
VSS
AW17
GND
VSS
AH52
GND
VSS
AW3
GND
VSS
AH54
GND
VSS
AW53
GND
VSS
AH6
GND
VSS
AW7
GND
VSS
AJ11
GND
VSS
AY12
GND
VSS
AJ51
GND
VSS
AY14
GND
VSS
AK50
GND
VSS
AY16
GND
VSS
AL13
GND
VSS
AY42
GND
VSS
AL15
GND
VSS
AY44
GND
VSS
AL17
GND
VSS
AY46
GND
VSS
AL3
GND
VSS
AY48
GND
VSS
AL47
GND
VSS
AY56
GND
VSS
AL53
GND
VSS
B12
GND
VSS
AL9
GND
VSS
B18
GND
VSS
AM12
GND
VSS
B34
GND
VSS
AM14
GND
VSS
B42
GND
VSS
AM16
GND
VSS
BA11
GND
VSS
AM50
GND
VSS
BA43
GND
VSS
AM56
GND
VSS
BA45
GND
VSS
AM6
GND
VSS
BA53
GND
VSS
AN3
GND
VSS
BA9
GND
VSS
AN43
GND
VSS
BB50
GND
VSS
AN45
GND
VSS
BB56
GND
VSS
AN47
GND
VSS
BB6
GND
VSS
AN49
GND
VSS
BC3
GND
VSS
AN53
GND
VSS
BC47
GND
VSS
AP42
GND
VSS
BC49
GND
VSS
AP44
GND
VSS
BC53
GND
VSS
AP48
GND
VSS
BC9
GND
VSS
AP56
GND
VSS
BD50
GND
VSS
AR3
GND
VSS
BD56
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
61
Table 3-1.
Land Name
Land Name (Sheet 35 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 36 of 50)
Land No.
Buffer Type Direction
VSS
BE9
GND
VSS
BM16
GND
VSS
BF6
GND
VSS
BM2
GND
VSS
BG13
GND
VSS
BM4
GND
VSS
BG15
GND
VSS
BM42
GND
VSS
BG17
GND
VSS
BM52
GND
VSS
BG3
GND
VSS
BM58
GND
VSS
BG43
GND
VSS
BM6
GND
VSS
BG45
GND
VSS
BM8
GND
VSS
BG47
GND
VSS
BN43
GND
VSS
BG53
GND
VSS
BN47
GND
VSS
BG9
GND
VSS
BN49
GND
VSS
BH12
GND
VSS
BN51
GND
VSS
BH16
GND
VSS
BN55
GND
VSS
BH2
GND
VSS
BP12
GND
VSS
BH4
GND
VSS
BP14
GND
VSS
BH42
GND
VSS
BP16
GND
VSS
BH48
GND
VSS
BP44
GND
VSS
BH50
GND
VSS
BP46
GND
VSS
BH56
GND
VSS
BP48
GND
VSS
BH58
GND
VSS
BP50
GND
VSS
BH8
GND
VSS
BP52
GND
VSS
BJ1
GND
VSS
BP54
GND
VSS
BJ11
GND
VSS
BP6
GND
VSS
BJ5
GND
VSS
BR1
GND
VSS
BJ53
GND
VSS
BR11
GND
VSS
BJ55
GND
VSS
BR17
GND
VSS
BJ57
GND
VSS
BR3
GND
VSS
BJ7
GND
VSS
BR43
GND
VSS
BK16
GND
VSS
BR5
GND
VSS
BK42
GND
VSS
BR53
GND
VSS
BK44
GND
VSS
BR57
GND
VSS
BK46
GND
VSS
BR7
GND
VSS
BK48
GND
VSS
BR9
GND
VSS
BK50
GND
VSS
BT10
GND
VSS
BK54
GND
VSS
BT2
GND
VSS
BK56
GND
VSS
BT4
GND
VSS
BK6
GND
VSS
BT56
GND
VSS
BL13
GND
VSS
BT58
GND
VSS
BL15
GND
VSS
BT8
GND
VSS
BL53
GND
VSS
BU13
GND
VSS
BM10
GND
VSS
BU15
GND
VSS
BM12
GND
VSS
BU17
GND
62
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 37 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 38 of 50)
Land No.
Buffer Type Direction
VSS
BU43
GND
VSS
CA19
GND
VSS
BU45
GND
VSS
CA21
GND
VSS
BU47
GND
VSS
CA23
GND
VSS
BU49
GND
VSS
CA25
GND
VSS
BU51
GND
VSS
CA27
GND
VSS
BU53
GND
VSS
CA29
GND
VSS
BU55
GND
VSS
CA3
GND
VSS
BV12
GND
VSS
CA31
GND
VSS
BV2
GND
VSS
CA33
GND
VSS
BV4
GND
VSS
CA35
GND
VSS
BV54
GND
VSS
CA37
GND
VSS
BV6
GND
VSS
CA39
GND
VSS
BV8
GND
VSS
CA41
GND
VSS
BW1
GND
VSS
CA43
GND
VSS
BW17
GND
VSS
CA45
GND
VSS
BW43
GND
VSS
CA47
GND
VSS
BW47
GND
VSS
CA49
GND
VSS
BW57
GND
VSS
CA5
GND
VSS
BY10
GND
VSS
CA51
GND
VSS
BY14
GND
VSS
CA53
GND
VSS
BY16
GND
VSS
CA55
GND
VSS
BY18
GND
VSS
CA7
GND
VSS
BY20
GND
VSS
CA9
GND
VSS
BY22
GND
VSS
CB12
GND
VSS
BY26
GND
VSS
CB24
GND
VSS
BY28
GND
VSS
CB30
GND
VSS
BY32
GND
VSS
CB36
GND
VSS
BY34
GND
VSS
CB4
GND
VSS
BY38
GND
VSS
CB42
GND
VSS
BY40
GND
VSS
CB54
GND
VSS
BY46
GND
VSS
CB56
GND
VSS
BY50
GND
VSS
CB6
GND
VSS
BY52
GND
VSS
CD10
GND
VSS
BY8
GND
VSS
CD12
GND
VSS
C23
GND
VSS
CD14
GND
VSS
C53
GND
VSS
CD16
GND
VSS
C7
GND
VSS
CD18
GND
VSS
C9
GND
VSS
CD20
GND
VSS
CA11
GND
VSS
CD22
GND
VSS
CA13
GND
VSS
CD24
GND
VSS
CA15
GND
VSS
CD26
GND
VSS
CA17
GND
VSS
CD28
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
63
Table 3-1.
Land Name
Land Name (Sheet 39 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 40 of 50)
Land No.
Buffer Type Direction
VSS
CD30
GND
VSS
CG51
GND
VSS
CD32
GND
VSS
CG53
GND
VSS
CD34
GND
VSS
CG7
GND
VSS
CD36
GND
VSS
CG9
GND
VSS
CD38
GND
VSS
CH10
GND
VSS
CD40
GND
VSS
CH12
GND
VSS
CD42
GND
VSS
CH14
GND
VSS
CD44
GND
VSS
CH16
GND
VSS
CD46
GND
VSS
CH18
GND
VSS
CD48
GND
VSS
CH20
GND
VSS
CD50
GND
VSS
CH22
GND
VSS
CD52
GND
VSS
CH24
GND
VSS
CD6
GND
VSS
CH26
GND
VSS
CD8
GND
VSS
CH28
GND
VSS
CE55
GND
VSS
CH30
GND
VSS
CF18
GND
VSS
CH32
GND
VSS
CF30
GND
VSS
CH34
GND
VSS
CF4
GND
VSS
CH36
GND
VSS
CF48
GND
VSS
CH38
GND
VSS
CF54
GND
VSS
CH40
GND
VSS
CF56
GND
VSS
CH42
GND
VSS
CG11
GND
VSS
CH44
GND
VSS
CG13
GND
VSS
CH46
GND
VSS
CG15
GND
VSS
CH48
GND
VSS
CG17
GND
VSS
CH50
GND
VSS
CG19
GND
VSS
CH52
GND
VSS
CG21
GND
VSS
CH6
GND
VSS
CG23
GND
VSS
CH8
GND
VSS
CG25
GND
VSS
CJ17
GND
VSS
CG27
GND
VSS
CJ23
GND
VSS
CG29
GND
VSS
CJ29
GND
VSS
CG31
GND
VSS
CJ41
GND
VSS
CG33
GND
VSS
CJ53
GND
VSS
CG35
GND
VSS
CJ55
GND
VSS
CG37
GND
VSS
CK4
GND
VSS
CG39
GND
VSS
CK56
GND
VSS
CG41
GND
VSS
CL11
GND
VSS
CG43
GND
VSS
CL13
GND
VSS
CG45
GND
VSS
CL15
GND
VSS
CG47
GND
VSS
CL17
GND
VSS
CG49
GND
VSS
CL19
GND
VSS
CG5
GND
VSS
CL21
GND
64
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 41 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 42 of 50)
Land No.
Buffer Type Direction
VSS
CL23
GND
VSS
CP40
GND
VSS
CL25
GND
VSS
CP42
GND
VSS
CL27
GND
VSS
CP44
GND
VSS
CL29
GND
VSS
CP46
GND
VSS
CL3
GND
VSS
CP48
GND
VSS
CL31
GND
VSS
CP50
GND
VSS
CL33
GND
VSS
CP52
GND
VSS
CL35
GND
VSS
CP54
GND
VSS
CL37
GND
VSS
CP56
GND
VSS
CL39
GND
VSS
CP6
GND
VSS
CL41
GND
VSS
CP8
GND
VSS
CL43
GND
VSS
CR13
GND
VSS
CL45
GND
VSS
CR15
GND
VSS
CL47
GND
VSS
CR19
GND
VSS
CL49
GND
VSS
CR21
GND
VSS
CL5
GND
VSS
CR25
GND
VSS
CL51
GND
VSS
CR27
GND
VSS
CL53
GND
VSS
CR31
GND
VSS
CL7
GND
VSS
CR33
GND
VSS
CL9
GND
VSS
CR37
GND
VSS
CN11
GND
VSS
CR39
GND
VSS
CN23
GND
VSS
CR43
GND
VSS
CN29
GND
VSS
CR45
GND
VSS
CN35
GND
VSS
CR47
GND
VSS
CN47
GND
VSS
CR49
GND
VSS
CN5
GND
VSS
CR51
GND
VSS
CP10
GND
VSS
CR53
GND
VSS
CP12
GND
VSS
CR55
GND
VSS
CP14
GND
VSS
CR57
GND
VSS
CP16
GND
VSS
CR7
GND
VSS
CP18
GND
VSS
CR9
GND
VSS
CP2
GND
VSS
CT12
GND
VSS
CP20
GND
VSS
CT24
GND
VSS
CP22
GND
VSS
CT26
GND
VSS
CP26
GND
VSS
CT28
GND
VSS
CP28
GND
VSS
CT30
GND
VSS
CP30
GND
VSS
CT32
GND
VSS
CP32
GND
VSS
CT34
GND
VSS
CP34
GND
VSS
CT58
GND
VSS
CP36
GND
VSS
CT6
GND
VSS
CP38
GND
VSS
CU11
GND
VSS
CP4
GND
VSS
CU17
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
65
Table 3-1.
Land Name
Land Name (Sheet 43 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 44 of 50)
Land No.
Buffer Type Direction
VSS
CU23
GND
VSS
D34
GND
VSS
CU29
GND
VSS
D6
GND
VSS
CU3
GND
VSS
D8
GND
VSS
CU41
GND
VSS
DA11
GND
VSS
CU43
GND
VSS
DA13
GND
VSS
CV14
GND
VSS
DA15
GND
VSS
CV16
GND
VSS
DA17
GND
VSS
CV2
GND
VSS
DA21
GND
VSS
CV20
GND
VSS
DA23
GND
VSS
CV22
GND
VSS
DA35
GND
VSS
CV36
GND
VSS
DA37
GND
VSS
CV38
GND
VSS
DA41
GND
VSS
CV42
GND
VSS
DA43
GND
VSS
CV44
GND
VSS
DA45
GND
VSS
CV46
GND
VSS
DA47
GND
VSS
CV48
GND
VSS
DA49
GND
VSS
CV50
GND
VSS
DA51
GND
VSS
CV52
GND
VSS
DA53
GND
VSS
CV54
GND
VSS
DA55
GND
VSS
CV56
GND
VSS
DA7
GND
VSS
CV6
GND
VSS
DA9
GND
VSS
CV8
GND
VSS
DB14
GND
VSS
CW19
GND
VSS
DB16
GND
VSS
CW21
GND
VSS
DB18
GND
VSS
CW23
GND
VSS
DB20
GND
VSS
CW25
GND
VSS
DB22
GND
VSS
CW27
GND
VSS
DB24
GND
VSS
CW29
GND
VSS
DB26
GND
VSS
CW31
GND
VSS
DB28
GND
VSS
CW33
GND
VSS
DB30
GND
VSS
CW35
GND
VSS
DB32
GND
VSS
CW39
GND
VSS
DB34
GND
VSS
CW5
GND
VSS
DB36
GND
VSS
CY10
GND
VSS
DB38
GND
VSS
CY12
GND
VSS
DB40
GND
VSS
CY2
GND
VSS
DB42
GND
VSS
CY4
GND
VSS
DB44
GND
VSS
CY46
GND
VSS
DB48
GND
VSS
CY52
GND
VSS
DB50
GND
VSS
D12
GND
VSS
DB52
GND
VSS
D18
GND
VSS
DB58
GND
VSS
D24
GND
VSS
DB8
GND
66
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name
Land Name (Sheet 45 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 46 of 50)
Land No.
Buffer Type Direction
VSS
DC33
GND
VSS
F46
GND
VSS
DD10
GND
VSS
F48
GND
VSS
DD12
GND
VSS
F50
GND
VSS
DD14
GND
VSS
F54
GND
VSS
DD24
GND
VSS
F8
GND
VSS
DD34
GND
VSS
G1
GND
VSS
DD44
GND
VSS
G15
GND
VSS
DD46
GND
VSS
G19
GND
VSS
DD48
GND
VSS
G23
GND
VSS
DD54
GND
VSS
G29
GND
VSS
DE17
GND
VSS
G5
GND
VSS
DE19
GND
VSS
G51
GND
VSS
DE21
GND
VSS
G57
GND
VSS
DE37
GND
VSS
G9
GND
VSS
DE39
GND
VSS
H12
GND
VSS
DE41
GND
VSS
H18
GND
VSS
DE51
GND
VSS
H24
GND
VSS
DE7
GND
VSS
H30
GND
VSS
DF12
GND
VSS
H42
GND
VSS
DF26
GND
VSS
H52
GND
VSS
DF46
GND
VSS
J19
GND
VSS
DF8
GND
VSS
J23
GND
VSS
E1
GND
VSS
J29
GND
VSS
E15
GND
VSS
J5
GND
VSS
E19
GND
VSS
J57
GND
VSS
E23
GND
VSS
K12
GND
VSS
E29
GND
VSS
K18
GND
VSS
E35
GND
VSS
K2
GND
VSS
E37
GND
VSS
K24
GND
VSS
E39
GND
VSS
K30
GND
VSS
E41
GND
VSS
K34
GND
VSS
E43
GND
VSS
K42
GND
VSS
E45
GND
VSS
K50
GND
VSS
E47
GND
VSS
K54
GND
VSS
E49
GND
VSS
K8
GND
VSS
E5
GND
VSS
L1
GND
VSS
E55
GND
VSS
L13
GND
VSS
F18
GND
VSS
L15
GND
VSS
F24
GND
VSS
L19
GND
VSS
F30
GND
VSS
L23
GND
VSS
F40
GND
VSS
L29
GND
VSS
F44
GND
VSS
L35
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
67
Table 3-1.
Land Name
Land Name (Sheet 47 of 50)
Land No.
Table 3-1.
Buffer Type Direction
Land Name
Land Name (Sheet 48 of 50)
Land No.
Buffer Type Direction
VSS
L37
GND
VSS
T50
GND
VSS
L39
GND
VSS
T54
GND
VSS
L41
GND
VSS
T8
GND
VSS
L43
GND
VSS
U15
GND
VSS
L45
GND
VSS
U19
GND
VSS
L47
GND
VSS
U23
GND
VSS
L9
GND
VSS
U29
GND
VSS
M18
GND
VSS
U35
GND
VSS
M2
GND
VSS
U37
GND
VSS
M24
GND
VSS
U39
GND
VSS
M30
GND
VSS
U41
GND
VSS
M34
GND
VSS
U43
GND
VSS
M36
GND
VSS
U45
GND
VSS
M38
GND
VSS
U47
GND
VSS
M40
GND
VSS
U5
GND
VSS
M44
GND
VSS
U9
GND
VSS
M46
GND
VSS
V12
GND
VSS
M50
GND
VSS
V18
GND
VSS
M8
GND
VSS
V24
GND
VSS
N19
GND
VSS
V30
GND
VSS
N23
GND
VSS
V34
GND
VSS
N29
GND
VSS
V38
GND
VSS
N5
GND
VSS
V40
GND
VSS
N51
GND
VSS
V50
GND
VSS
P12
GND
VSS
V8
GND
VSS
P18
GND
VSS
W15
GND
VSS
P24
GND
VSS
W19
GND
VSS
P30
GND
VSS
W23
GND
VSS
P34
GND
VSS
W29
GND
VSS
P54
GND
VSS
W5
GND
VSS
R15
GND
VSS
W51
GND
VSS
R19
GND
VSS
Y12
GND
VSS
R23
GND
VSS
Y18
GND
VSS
R29
GND
VSS
Y24
GND
VSS
R47
GND
VSS
Y30
GND
VSS
R5
GND
VSS
Y34
GND
VSS
R51
GND
VSS
Y54
GND
VSS
R9
GND
VSS_VCC_SENSE
AE43
O
VSS
T18
GND
VSS_VTT_SENSE
L51
O
VSS
T24
GND
VSS_VSA_SENSE
BH6
O
VSS
T30
GND
VVMSE01
CD54
PWR
VSS
T34
GND
VVMSE01
CF42
PWR
68
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-1.
Land Name (Sheet 49 of 50)
Land Name
Land No.
Table 3-1.
Buffer Type Direction
Land Name (Sheet 50 of 50)
Land Name
Land No.
Buffer Type Direction
VVMSE01
CJ35
PWR
VVMSE23
CF24
PWR
VVMSE01
CJ47
PWR
VVMSE23
CJ5
PWR
VVMSE01
CR29
PWR
VVMSE23
CN17
PWR
VVMSE01
CT52
PWR
VVMSE23
CP24
PWR
VVMSE01
CV40
PWR
VVMSE23
CY6
PWR
VVMSE01
DB46
PWR
VVMSE23
DB12
PWR
VVMSE23
CF12
PWR
VVMSE23
DC25
PWR
3.2
Listing by Land Number
Table 3-2.
Land Number (Sheet 1 of 50)
Land No.
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 2 of 50)
Land Name
Buffer Type Direction
AA27
VCC
PWR
AA29
VSS
GND
AA3
QPI2_DRX_DP[8]
Intel® QPI
AA31
VCC
PWR
VCC
PWR
A11
PE1_RX_N[13]
PCIEX3
A13
VTTA
A15
VSS
GND
A17
PE1_TX_N[9]
PCIEX3
I
O
PWR
I
A19
VCC
PWR
AA33
A21
VCC
PWR
AA35
PE0_RX_P[0]
PCIEX3
O
AA37
PE0_RX_P[2]
PCIEX3
I
AA39
PE0_RX_P[4]
PCIEX3
I
PE0_RX_P[6]
PCIEX3
I
A23
VCC
PWR
A33
VCC
PWR
A35
A37
A39
A41
A43
A45
A47
A49
A5
A51
QPI0_DRX_DN[3]
Intel
®
QPI
I
AA41
QPI0_DRX_DN[5]
Intel®
QPI
I
AA43
PE0_RX_P[12]
PCIEX3
I
QPI0_DRX_DN[7]
Intel
®
QPI
I
AA45
PE0_RX_P[15]
PCIEX3
I
QPI0_DRX_DN[9]
Intel
®
QPI
I
AA47
VSS
GND
QPI0_CLKRX_DN
Intel®
QPI
I
AA49
QPI1_DTX_DN[15]
Intel® QPI
®
QPI
I
AA5
VSS
GND
VSS
GND
QPI0_DRX_DN[11]
Intel
QPI0_DRX_DN[13]
Intel®
QPI
I
AA51
QPI0_DRX_DN[15]
®
QPI
I
AA53
QPI0_DTX_DN[8]
Intel® QPI
O
AA55
QPI1_DRX_DP[12]
Intel® QPI
I
®
O
Intel
RSVD
VSS
GND
AA7
QPI2_DTX_DN[8]
Intel
CMOS
AA9
VSS
GND
I/O
QPI
A53
BPM_N[5]
A7
RSVD
AB10
PE1_RX_P[0]
PCIEX3
A9
PE1_RX_N[15]
PCIEX3
I
AB12
VTTA
PWR
AA11
PE1_RX_N[0]
PCIEX3
I
AB14
RSVD
O
AB16
PE1_TX_P[0]
PCIEX3
AA13
PE1_TX_P[11]
PCIEX3
AA15
VTTA
PWR
AB18
VSS
GND
AB20
VCC
PWR
AA17
PE1_TX_N[0]
PCIEX3
AA19
VSS
GND
AB22
O
VCC
PWR
VSS
GND
AA21
VCC
PWR
AB24
AA23
VSS
GND
AB26
VCC
PWR
PWR
AB28
VCC
PWR
AA25
O
VCC
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
I
O
69
Table 3-2.
Land No.
Land Number (Sheet 3 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 4 of 50)
Land Name
Buffer Type Direction
AB30
VSS
GND
AC7
QPI2_DTX_DN[9]
Intel® QPI
AB32
VCC
PWR
AC9
VTTQ
PWR
AB34
VSS
GND
AD10
VCCPECI
PWR
AB36
PE0_RX_P[1]
PCIEX3
I
AD12
VSS
GND
AB38
PE0_RX_P[3]
PCIEX3
I
AD14
VSS
GND
AB4
QPI2_DRX_DN[9]
Intel® QPI
I
AD16
VSS
GND
AB40
PE0_RX_P[5]
PCIEX3
I
AD18
VSS
GND
AB42
PE0_RX_P[7]
PCIEX3
I
AD20
VCC
PWR
AB44
PE0_RX_P[13]
PCIEX3
I
AD22
VCC
PWR
AB46
PE0_RX_P[14]
PCIEX3
I
AD24
VSS
GND
O
AD26
VCC
PWR
AD28
VCC
PWR
®
AB48
QPI1_DTX_DP[15]
Intel
AB50
VSS
GND
AB52
QPI0_DTX_DP[8]
Intel®
O
AD30
VSS
GND
AB54
SOCKET_ID[1]
CMOS
I
AD32
VCC
PWR
AB56
QPI1_DRX_DN[11]
Intel® QPI
I
AD34
VSS
GND
AB6
QPI2_DTX_DP[8]
Intel® QPI
O
AD36
VSS
GND
AB8
VSS
GND
AD38
VSS
GND
AC11
VSS
GND
AD4
VSS
GND
QPI
QPI
O
AC13
RSVD
AD40
VSS
GND
AC15
VSS
GND
AD42
VSS
GND
AC17
VSS
GND
AD44
RSVD
AC19
VSS
GND
AD46
VSS
GND
AC21
VCC
PWR
AD48
QPI1_DTX_DP[14]
Intel® QPI
O
AC23
VSS
GND
AD50
FRMAGENT
CMOS
I
AC25
VCC
PWR
AD52
QPI0_DTX_DP[9]
Intel®
AC27
VCC
PWR
AD54
VSS
GND
AC29
VSS
GND
AD56
QPI1_DRX_DN[10]
Intel® QPI
I
AC3
QPI2_DRX_DP[9]
Intel® QPI
AD6
QPI2_DTX_DP[9]
Intel® QPI
O
AC31
VCC
PWR
AD8
VSS
GND
AC33
VCC
PWR
AE11
NMI
GTL
AC35
VSS
GND
AE13
VCC
PWR
AC37
VSS
GND
AE15
VCC
PWR
AC39
VSS
GND
AE17
VCC
PWR
AC41
VSS
GND
AE19
VSS
GND
AC43
VSS
GND
AE21
VCC
PWR
AC45
VSS
GND
AE23
VSS
GND
AE25
VCC
PWR
AE27
VCC
PWR
AE29
VSS
GND
AE3
VSS
GND
O
AE31
VCC
PWR
I
AE33
VCC
PWR
AC47
VTTA
PWR
AC49
QPI1_DTX_DN[14]
Intel® QPI
AC5
VSS
GND
AC51
RSVD
®
AC53
QPI0_DTX_DN[9]
Intel
AC55
QPI1_DRX_DP[11]
Intel® QPI
70
QPI
I
O
QPI
O
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 5 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 6 of 50)
Land Name
Buffer Type Direction
AF6
QPI2_CLKTX_DN
Intel® QPI
AF8
VSS
GND
O
AG1
QPI2_CLKRX_DP
Intel® QPI
I
PECI
I/O
AG11
PM_FAST_WAKE_N
CMOS
I/O
O
AG13
VCC
PWR
CMOS
I
AG15
VCC
PWR
AG17
VCC
PWR
AG19
VSS
GND
AE35
PREQ_N
CMOS
AE37
RSVD
AE39
PRDY_N
CMOS
AE41
PECI
I
AE43
VSS_VCC_SENSE
AE45
PMSYNC
AE47
VSS
GND
AE49
QPI1_DTX_DN[13]
Intel® QPI
O
AE5
VSS
GND
AG21
VCC
PWR
AE51
VSS
GND
AG23
VSS
GND
O
AG25
VCC
PWR
I
AG27
VCC
PWR
®
AE53
QPI0_CLKTX_DN
Intel
AE55
QPI1_DRX_DP[10]
Intel® QPI
AE57
VSS
GND
AG29
VSS
GND
AE7
QPI2_CLKTX_DP
Intel® QPI
O
AG3
VSS
GND
AE9
BCLK1_DN
CMOS
I
AG31
VCC
PWR
AF10
BCLK1_DP
CMOS
I
AG33
VCC
PWR
AF12
VCC
PWR
AG35
CATERR_N
CMOS
AF14
VCC
PWR
AG37
VCC
PWR
AF16
VCC
PWR
AG39
VCC
PWR
AF18
VSS
GND
AG41
VCC
PWR
®
QPI
O
I/O
AF2
QPI2_CLKRX_DN
Intel
AG43
VSS
GND
AF20
VCC
PWR
AG45
VSS
GND
AF22
VCC
PWR
AG47
VSS
GND
AF24
VSS
GND
AG49
QPI1_DTX_DN[12]
Intel® QPI
O
Intel®
O
QPI
I
AF26
VCC
PWR
AG5
QPI2_DTX_DN[10]
AF28
VCC
PWR
AG51
TEST_9
AF30
VSS
GND
AG53
VSS
GND
AF32
VCC
PWR
AG55
VSS
GND
AF34
VSS
GND
AG57
QPI1_CLKRX_DP
Intel® QPI
AF36
FIVR_FAULT
CMOS
O
AG7
VSS
GND
AF38
RESET_N
CMOS
I
AG9
PROC_ID[1]
AF4
VSS
GND
AH10
VSS
GND
AF40
TEST_8
AH12
VCC
PWR
AF42
VCC_SENSE
AH14
VCC
PWR
AF44
RSVD
AH16
VCC
PWR
AF46
BCLK0_DN
AH2
QPI2_DRX_DN[10]
Intel® QPI
I
AH4
QPI2_DTX_DP[10]
Intel
®
O
AH42
VCC
PWR
O
CMOS
®
I
AF48
QPI1_DTX_DP[13]
Intel
AF50
VSS
GND
AF52
QPI0_CLKTX_DP
Intel® QPI
AF54
VSS
GND
QPI
AF56
VSS
GND
AF58
QPI1_CLKRX_DN
Intel® QPI
O
O
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
QPI
I
O
AH44
VCC
PWR
AH46
BCLK0_DP
CMOS
®
AH48
QPI1_DTX_DP[12]
Intel
AH50
TMS
CMOS
QPI
I
QPI
O
I
71
Table 3-2.
Land No.
Land Number (Sheet 7 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 8 of 50)
Land Name
Buffer Type Direction
AH52
VSS
GND
AL13
VSS
GND
AH54
VSS
GND
AL15
VSS
GND
AL17
VSS
GND
AL3
VSS
GND
AH56
VTTQ
PWR
AH58
QPI1_DRX_DN[9]
Intel® QPI
AH6
VSS
GND
AH8
PROC_ID[0]
AJ1
QPI2_DRX_DP[10]
Intel®
AJ11
VSS
GND
QPI
I
AL43
VCC
PWR
O
AL45
VCC
PWR
I
AL47
VSS
GND
AL49
QPI1_DTX_DN[10]
Intel® QPI
O
®
AJ13
VCC
PWR
AL5
QPI2_DTX_DN[12]
Intel
QPI
O
AJ15
VCC
PWR
AL51
QPI1_CLKTX_DP
Intel® QPI
O
AJ17
VCC
PWR
AL53
VSS
GND
AJ3
VSA
PWR
AL55
QPI0_DTX_DN[11]
Intel® QPI
O
I
AJ43
VCC
PWR
AL57
QPI1_DRX_DP[8]
Intel®
AJ45
VCC
PWR
AL7
DMI_TX_P[0]
CMOS
GND
QPI
O
AJ47
TDO
Open Drain
O
AL9
VSS
AJ49
QPI1_DTX_DN[11]
Intel® QPI
O
AM10
SMBDAT
AJ5
QPI2_DTX_DN[11]
®
Intel
O
AM12
VSS
GND
AJ51
VSS
GND
AM14
VSS
GND
AM16
VSS
GND
AM2
QPI2_DRX_DN[12]
Intel® QPI
I
AM4
QPI2_DTX_DP[12]
Intel
®
QPI
O
AM42
VCC
PWR
PWR
O
QPI
AJ53
VTTQ
PWR
AJ55
QPI0_DTX_DN[10]
Intel® QPI
®
AJ57
QPI1_DRX_DP[9]
Intel
AJ7
VSA
PWR
QPI
O
I
I/O
AJ9
TXT_PLTEN
CMOS
I
AM44
VCC
AK10
TXT_AGENT
CMOS
I
AM46
RSVD
AK12
VCC
PWR
AM48
QPI1_DTX_DP[10]
Intel® QPI
AK14
VCC
PWR
AM50
VSS
GND
AK16
VCC
PWR
AM52
QPI1_DTX_DN[9]
Intel® QPI
O
AK2
QPI2_DRX_DN[11]
Intel® QPI
I
AM54
QPI0_DTX_DP[11]
Intel® QPI
O
AK4
QPI2_DTX_DP[11]
®
Intel
O
AM56
VSS
GND
AK42
VCC
PWR
AM58
QPI1_DRX_DN[7]
Intel® QPI
AK44
VCC
PWR
AM6
VSS
GND
AK46
TRST_N
CMOS
AM8
DMI_TX_N[1]
CMOS
AK48
QPI1_DTX_DP[11]
Intel®
AN1
QPI2_DRX_DP[12]
Intel®
AK50
VSS
GND
AN11
ERROR_N[2]
Open Drain
®
QPI
I
QPI
O
AK52
QPI1_CLKTX_DN
Intel
QPI
O
AN13
VCC
PWR
AK54
QPI0_DTX_DP[10]
Intel® QPI
O
AN15
VCC
PWR
AK56
SOCKET_ID[0]
CMOS
I
AN17
VCC
PWR
AK58
QPI1_DRX_DN[8]
Intel® QPI
I
AN3
VSS
GND
AK6
VSA
PWR
AK8
DMI_TX_N[0]
CMOS
AL1
QPI2_DRX_DP[11]
AL11
SMBCLK
72
®
Intel
QPI
AN43
VSS
GND
O
AN45
VSS
GND
I
AN47
VSS
GND
I/O
AN49
VSS
GND
I
O
QPI
I
O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 9 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 10 of 50)
Land Name
Buffer Type Direction
AN5
QPI2_DTX_DN[13]
Intel®
QPI
O
AT12
VCC
PWR
AN51
QPI1_DTX_DP[9]
Intel® QPI
O
AT14
VCC
PWR
AN53
VSS
GND
AN55
QPI0_DTX_DN[12]
Intel® QPI
®
O
AT16
VCC
PWR
AT2
QPI2_DRX_DN[14]
Intel® QPI
I
®
QPI
O
AN57
QPI1_DRX_DP[7]
Intel
AN7
DMI_TX_P[1]
CMOS
AN9
VCCIO_IN
AP10
SM_WP
AP12
VCC
PWR
AT48
RSVD
AP14
VCC
PWR
AT50
VSS
GND
AP16
VCC
PWR
AT52
QPI1_DTX_DN[7]
Intel® QPI
O
AP2
QPI2_DRX_DN[13]
Intel® QPI
I
AT54
QPI0_DTX_DP[13]
Intel® QPI
O
AP4
QPI2_DTX_DP[13]
Intel®
O
AT56
VSS
GND
AP42
VSS
GND
AT58
QPI1_DRX_DN[5]
Intel® QPI
AP44
VSS
GND
AT6
VSS
GND
AP46
RSVD
AT8
DMI_TX_N[3]
CMOS
QPI
I
AT4
QPI2_DTX_DP[14]
Intel
O
AT42
VCC
PWR
AT44
VCC
PWR
AT46
RSVD
I
QPI
AP48
VSS
GND
AP50
BMCINIT
CMOS
AP52
QPI1_DTX_DN[8]
Intel®
AP54
QPI0_DTX_DP[12]
AP56
VSS
GND
AP58
QPI1_DRX_DN[6]
Intel® QPI
I
O
®
AU1
QPI2_DRX_DP[14]
Intel
I
AU11
SVIDALERT_N
CMOS
QPI
O
AU13
VCC
PWR
Intel® QPI
O
AU15
VCC
PWR
AU17
VCC
PWR
AU3
VSA
PWR
AU43
VCC
PWR
AU45
VCC
PWR
I
AU47
VSS
GND
O
AU49
RSVD
I
O
QPI
I
I
AP6
TEST_11
AP8
DMI_TX_N[2]
CMOS
AR1
QPI2_DRX_DP[13]
Intel®
AR11
ERROR_N[0]
Open Drain
AR13
VCC
PWR
AU5
QPI2_DTX_DN[15]
Intel® QPI
O
AR15
VCC
PWR
AU51
QPI1_DTX_DP[7]
Intel® QPI
O
AR17
VCC
PWR
AU53
VTTQ
PWR
AR3
VSS
GND
AU55
QPI0_DTX_DN[14]
Intel® QPI
O
®
I
QPI
AR43
VCC
PWR
AU57
QPI1_DRX_DP[5]
Intel
AR45
VCC
PWR
AU7
DMI_TX_P[3]
CMOS
AR47
RSVD
AU9
VSS
GND
AR49
RSVD
AV10
SVIDCLK
Open Drain
®
AR5
QPI2_DTX_DN[14]
Intel
QPI
O
AV12
VCC
PWR
AR51
QPI1_DTX_DP[8]
Intel® QPI
O
AV14
VCC
PWR
AR53
VSS
GND
AR55
QPI0_DTX_DN[13]
Intel® QPI
AR57
QPI1_DRX_DP[6]
Intel®
AR7
DMI_TX_P[2]
CMOS
AR9
VSS
GND
AT10
ERROR_N[1]
Open Drain
QPI
O
O
VCC
PWR
AV2
QPI2_DRX_DN[15]
Intel® QPI
I
O
I
AV4
QPI2_DTX_DP[15]
O
AV42
VCC
PWR
AV44
VCC
PWR
AV46
RSVD
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
O
AV16
Intel®
O
QPI
QPI
73
Table 3-2.
Land No.
Land Number (Sheet 11 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 12 of 50)
Land Name
Buffer Type Direction
B10
PE1_RX_P[13]
PCIEX3
B12
VSS
GND
I
AV48
RSVD
AV50
VSS
GND
AV52
QPI1_DTX_DN[6]
Intel® QPI
O
B14
PE1_RX_N[10]
PCIEX3
I
AV54
QPI0_DTX_DP[14]
Intel® QPI
O
B16
PE1_TX_P[9]
PCIEX3
O
AV56
PROCHOT_N
Open Drain
I/O
B18
VSS
GND
AV58
QPI1_DRX_DN[4]
Intel® QPI
I
B20
VCC
PWR
AV6
VSS
GND
B22
VCC
PWR
AV8
VSA
PWR
B24
VCC
PWR
I
B32
VCC
PWR
I/O
B34
VSS
GND
®
AW1
QPI2_DRX_DP[15]
Intel
AW11
SVIDDATA
Open Drain
AW13
VSS
GND
B36
QPI0_DRX_DN[4]
Intel® QPI
I
AW15
VSS
GND
B38
QPI0_DRX_DN[6]
Intel® QPI
I
QPI
AW17
VSS
GND
B40
QPI0_DRX_DN[8]
Intel®
QPI
I
AW3
VSS
GND
B42
VSS
GND
AW43
VCC
PWR
B44
QPI0_DRX_DN[10]
Intel® QPI
I
AW45
VCC
PWR
B46
QPI0_DRX_DN[12]
Intel® QPI
I
®
AW47
RSVD
B48
QPI0_DRX_DN[14]
Intel
QPI
I
AW49
RSVD
B50
QPI0_DRX_DN[16]
Intel® QPI
I
CMOS
I/O
PCIEX3
I
AW5
QPI2_DTX_DN[16]
Intel®
QPI
O
B52
RSVD
AW51
QPI1_DTX_DP[6]
Intel® QPI
O
B54
BPM_N[4]
AW53
VSS
GND
AW55
QPI0_DTX_DN[15]
Intel® QPI
®
O
B6
RSVD
B8
PE1_RX_P[15]
®
AW57
QPI1_DRX_DP[4]
Intel
BA1
QPI2_DRX_DP[16]
Intel
AW7
VSS
GND
BA11
VSS
GND
AW9
VSA
PWR
BA13
VCC
PWR
AY10
VSA
PWR
BA15
VCC
PWR
AY12
VSS
GND
BA17
VCC
PWR
AY14
VSS
GND
BA3
TEST_13
AY16
VSS
GND
BA43
VSS
GND
AY2
QPI2_DRX_DN[16]
Intel® QPI
I
BA45
VSS
GND
AY4
QPI2_DTX_DP[16]
®
Intel
O
BA47
RSVD
AY42
VSS
GND
BA49
RSVD
AY44
VSS
GND
BA5
QPI2_DTX_DN[17]
Intel® QPI
O
AY46
VSS
GND
BA51
QPI1_DTX_DP[5]
Intel® QPI
O
AY48
VSS
GND
BA53
VSS
GND
AY50
BIST_ENABLE
CMOS
BA55
QPI0_DTX_DN[16]
Intel® QPI
O
®
I
®
QPI
QPI
I
I
AY52
QPI1_DTX_DN[5]
Intel
QPI
O
BA57
QPI1_DRX_DP[3]
Intel
AY54
QPI0_DTX_DP[15]
Intel® QPI
O
BA7
DMI_RX_P[0]
CMOS
AY56
VSS
GND
BA9
VSS
GND
AY58
QPI1_DRX_DN[3]
Intel® QPI
BB10
VPP_SDA
CMOS
AY6
VSA
PWR
BB12
VCC
PWR
AY8
DMI_RX_N[0]
CMOS
BB14
VCC
PWR
74
I
I
QPI
QPI
I
I
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 13 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 14 of 50)
Land Name
BD52
QPI1_DTX_DN[3]
Intel® QPI
O
I
BD54
QPI0_DTX_DP[17]
Intel® QPI
O
O
BD56
VSS
GND
BD58
QPI1_DRX_DN[1]
Intel® QPI
I
DMI_RX_N[2]
CMOS
I
BE1
QPI2_DRX_DP[18]
Intel®
BE11
VCC33
PWR
BB16
VCC
PWR
BB2
QPI2_DRX_DN[17]
Intel® QPI
BB4
QPI2_DTX_DP[17]
®
Intel
BB42
VCC
PWR
BB44
VCC
PWR
BD6
TEST_12
BB46
RSVD
BD8
QPI
Buffer Type Direction
BB48
RSVD
BB50
VSS
GND
BB52
QPI1_DTX_DN[4]
Intel® QPI
O
BE13
VCC
PWR
BB54
QPI0_DTX_DP[16]
Intel® QPI
O
BE15
VCC
PWR
BB56
VSS
GND
BE17
VCC
PWR
BB58
QPI1_DRX_DN[2]
Intel® QPI
BE3
VSA
PWR
BB6
VSS
GND
BB8
DMI_RX_N[1]
CMOS
®
I
BE43
VCC
PWR
I
BE45
VCC
PWR
I
BE47
RSVD
I/O
BE49
RSVD
QPI
I
BC1
QPI2_DRX_DP[17]
Intel
BC11
VPP_SCL
CMOS
BC13
VCC
PWR
BE5
QPI2_DTX_DN[19]
Intel® QPI
O
BC15
VCC
PWR
BE51
QPI1_DTX_DP[3]
Intel® QPI
O
BC17
VCC
PWR
BE53
MSMI_N
CMOS
I/O
BC3
VSS
GND
BE55
QPI0_DTX_DN[18]
Intel® QPI
O
®
I
QPI
BC43
VCC
PWR
BE57
QPI1_DRX_DP[1]
Intel
BC45
VCC
PWR
BE7
DMI_RX_P[2]
CMOS
BC47
VSS
GND
BE9
VSS
GND
BC49
VSS
GND
BF10
VCCPLL
PWR
BC5
QPI2_DTX_DN[18]
Intel® QPI
O
BF12
VCC
PWR
BC51
QPI1_DTX_DP[4]
Intel® QPI
O
BF14
VCC
PWR
BC53
VSS
GND
BC55
QPI0_DTX_DN[17]
Intel® QPI
®
O
I
BF16
VCC
PWR
BF2
QPI2_DRX_DN[19]
Intel® QPI
I
®
O
BC57
QPI1_DRX_DP[2]
Intel
BC7
DMI_RX_P[1]
CMOS
BC9
VSS
GND
BD10
DEBUG_EN_N
BD12
VCC
PWR
BF48
RSVD
BD14
VCC
PWR
BF50
TDI
QPI
QPI
I
BF4
QPI2_DTX_DP[19]
Intel
I
BF42
VCC
PWR
BF44
VCC
PWR
BF46
THERMTRIP_N
CMOS
O
CMOS
I
®
QPI
BD16
VCC
PWR
BF52
QPI1_DTX_DN[2]
Intel
QPI
O
BD2
QPI2_DRX_DN[18]
Intel® QPI
I
BF54
QPI0_DTX_DP[18]
Intel® QPI
O
BD4
QPI2_DTX_DP[18]
®
Intel
O
BF56
SAFE_MODE_BOOT
CMOS
I
BD42
VCC
PWR
BF58
QPI1_DRX_DN[0]
Intel® QPI
I
BD44
VCC
PWR
BF6
VSS
GND
BD46
RSVD
BF8
DMI_RX_N[3]
CMOS
BD48
RSVD
BD50
VSS
QPI
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
BG1
QPI2_DRX_DP[19]
Intel
BG11
VCCPLL
PWR
®
I
QPI
I
75
Table 3-2.
Land No.
Land Number (Sheet 15 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 16 of 50)
Land Name
Buffer Type Direction
BG13
VSS
GND
BJ5
VSS
GND
BG15
VSS
GND
BJ51
QPI1_DTX_DP[1]
Intel® QPI
BG17
VSS
GND
BJ53
VSS
GND
BG3
VSS
GND
BJ55
VSS
GND
BG43
VSS
GND
BJ57
VSS
GND
BG45
VSS
GND
BJ7
VSS
GND
BG47
VSS
GND
BJ9
PWR_DEBUG_N
CMOS
I
BG49
TCK
CMOS
I
BK10
VMSE3_DQ[0]
SMI2
I/O
O
BK12
MEM_SDA_C3
Open Drain
I/O
Intel® QPI
O
BK14
VMSE3_CLK_N
SMI2
O
O
BG5
VSA_SENSE
BG51
QPI1_DTX_DP[2]
BG53
VSS
GND
BK16
VSS
GND
BG55
QPI0_DTX_DN[19]
Intel® QPI
O
BK2
VMSE3_DQ[12]
SMI2
I/O
BG57
QPI1_DRX_DP[0]
Intel®
I
BK4
VMSE3_DQ[8]
SMI2
I/O
BG7
DMI_RX_P[3]
CMOS
I
BK42
VSS
GND
BG9
VSS
GND
BK44
VSS
GND
BH10
VCCPLL
PWR
BK46
VSS
GND
BK48
VSS
GND
BK50
VSS
GND
QPI
BH12
VSS
GND
BH14
VMSE3_CMD[4]
SMI2
BH16
VSS
GND
BK52
QPI1_DTX_DN[0]
Intel® QPI
BH2
VSS
GND
BK54
VSS
GND
BH4
VSS
GND
BK56
VSS
GND
BH42
VSS
GND
BK58
VMSE0_DQ[59]
SMI2
BH44
VMSE0_CMD[0]
SMI2
O
BK6
VSS
GND
BH46
VMSE0_CMD[15]
SMI2
O
BK8
VMSE3_DQ[4]
SMI2
BH48
VSS
GND
BL1
VMSE3_DQ[9]
SMI2
I/O
BH50
VSS
GND
BL11
VMSE3_DQ[5]
SMI2
I/O
BH52
QPI1_DTX_DN[1]
Intel® QPI
O
BL13
VSS
GND
BH54
QPI0_DTX_DP[19]
Intel® QPI
O
BL15
VSS
GND
BH56
VSS
GND
BL17
VSA
PWR
BH58
VSS
GND
BL3
VMSE3_DQS_N[1]
SMI2
I/O
O
O
I/O
I/O
BH6
VSS_VSA_SENSE
BL43
VMSE0_CMD[8]
SMI2
O
BH8
VSS
GND
BL45
VMSE0_CMD[9]
SMI2
O
BJ1
VSS
GND
BL47
VMSE0_CMD[11]
SMI2
O
BJ11
VSS
GND
BL49
VMSE0_CMD[14]
SMI2
O
BJ13
VMSE3_CMD[8]
SMI2
O
BL5
VMSE3_DQ[13]
SMI2
I/O
BJ15
VMSE3_CMD[0]
SMI2
O
BL51
QPI1_DTX_DP[0]
Intel® QPI
O
BJ17
VSA
PWR
BJ3
SKTOCC_N
BJ43
VMSE0_CMD[4]
BJ45
VMSE0_CMD[3]
BJ47
BJ49
76
O
BL53
VSS
GND
O
BL55
PWRGOOD
CMOS
I
SMI2
O
BL57
VMSE0_DQ[62]
SMI2
I/O
SMI2
O
BL7
VMSE3_DQ[1]
SMI2
I/O
VMSE0_CMD[16]
SMI2
O
BL9
VMSE3_DQS_P[0]
SMI2
I/O
VMSE0_CMD[12]
SMI2
O
BM10
VSS
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 17 of 50)
Land Name
Buffer Type Direction
BM12
VSS
GND
BM14
VMSE3_CLK_P
SMI2
O
Table 3-2.
Land No.
Land Number (Sheet 18 of 50)
Land Name
Buffer Type Direction
BP48
VSS
GND
BP50
VSS
GND
BM16
VSS
GND
BP52
VSS
GND
BM2
VSS
GND
BP54
VSS
GND
BM4
VSS
GND
BP56
VMSE0_DQS_N[7]
SMI2
I/O
BM42
VSS
GND
BP58
VMSE0_DQ[63]
SMI2
I/O
BM44
VMSE0_CLK_N
SMI2
O
BP6
VSS
GND
BM46
VMSE0_CMD[13]
SMI2
O
BP8
VMSE3_DQ[2]
SMI2
BM48
VMSE0_CMD[10]
SMI2
O
BR1
VSS
GND
BM50
RSVD
BR11
VSS
GND
I/O
BM52
VSS
GND
BR13
VMSE3_CMD[6]
SMI2
O
BM54
VMSE0_DQ[57]
SMI2
I/O
BR15
VMSE3_CMD[13]
SMI2
O
BM56
VMSE0_DQS_P[7]
SMI2
I/O
BR17
VSS
GND
BM58
VSS
GND
BR3
VSS
GND
BM6
VSS
GND
BR43
VSS
GND
BM8
VSS
GND
BR45
RSVD
BN1
VMSE3_DQ[15]
SMI2
I/O
BR47
MEM_SDA_C0
Open Drain
I/O
BN11
VMSE3_DQ[6]
SMI2
I/O
BR49
VMSE0_DQ[49]
SMI2
I/O
BN13
VMSE3_CMD[3]
SMI2
O
BR5
VSS
GND
BN15
VMSE3_CMD[9]
SMI2
O
BR51
VMSE0_DQ[51]
SMI2
BR53
VSS
GND
BR55
VMSE0_DQ[61]
SMI2
BR57
VSS
GND
BR7
VSS
GND
BN17
VSA
PWR
BN3
VMSE3_DQS_P[1]
SMI2
I/O
I/O
I/O
BN43
VSS
GND
BN45
VMSE0_CLK_P
SMI2
BN47
VSS
GND
BR9
VSS
GND
BN49
VSS
GND
BT10
VSS
GND
BN5
VMSE3_DQ[14]
SMI2
BT12
VMSE3_ERR_N
SMI2
I/O
BN51
VSS
GND
BT14
TEST_5
BN53
VMSE0_DQ[60]
SMI2
O
BN55
VSS
GND
BN57
VMSE0_DQ[58]
SMI2
BN7
VMSE3_DQ[7]
SMI2
BN9
VMSE3_DQS_N[0]
BP10
VMSE3_DQ[3]
BP12
VSS
GND
BT48
BP14
VSS
GND
BT50
O
I/O
BT16
VMSE3_CMD[14]
SMI2
BT2
VSS
GND
I/O
BT4
VSS
GND
I/O
BT42
VTTA
PWR
SMI2
I/O
BT44
VMSE0_CMD[6]
SMI2
O
SMI2
I/O
BT46
VMSE0_CMD[5]
SMI2
O
VMSE0_DQ[53]
SMI2
I/O
VMSE0_DQS_N[6]
SMI2
I/O
I/O
BP16
VSS
GND
BT52
VMSE0_DQ[54]
SMI2
I/O
BP2
VMSE3_DQ[10]
SMI2
I/O
BT54
VMSE0_DQ[56]
SMI2
I/O
BP4
VMSE3_DQ[11]
SMI2
I/O
BT56
VSS
GND
BP42
VTTA
PWR
BT58
VSS
GND
BP44
VSS
GND
BT6
VMSE3_DQ[20]
SMI2
BP46
VSS
GND
BT8
VSS
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
I/O
77
Table 3-2.
Land No.
Land Number (Sheet 19 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 20 of 50)
Land Name
Buffer Type Direction
BU1
VMSE3_DQ[23]
SMI2
I/O
BW47
VSS
GND
BU11
VMSE3_CMD[1]
SMI2
O
BW49
VMSE0_DQ[52]
SMI2
BU13
VSS
GND
BW5
VMSE3_DQS_P[2]
SMI2
I/O
BU15
VSS
GND
BW51
VMSE0_DQ[55]
SMI2
I/O
BU17
VSS
GND
BU3
VMSE3_DQ[17]
SMI2
SMI2
I/O
BU43
VSS
GND
BW57
VSS
GND
BU45
VSS
GND
BW7
VMSE3_DQ[21]
SMI2
I/O
BU47
VSS
GND
BW9
VMSE3_CMD[7]
SMI2
O
BU49
VSS
GND
BY10
VSS
GND
BU5
VMSE3_DQS_N[2]
SMI2
BY12
VMSE3_CMD[16]
SMI2
BU51
VSS
GND
BY14
VSS
GND
BU53
VSS
GND
BY16
VSS
GND
BU55
VSS
GND
BY18
VSS
GND
BU57
VMSE0_ECC[3]
SMI2
I/O
BY2
TEST_6
BU7
VMSE3_DQ[16]
SMI2
I/O
BY20
VSS
BU9
VMSE3_CMD[2]
SMI2
O
BY22
VSS
GND
BV10
TEST_4
BY24
VTTA
PWR
I/O
I/O
BW53
TEST_2
BW55
VMSE0_ECC[1]
I/O
O
GND
BV12
VSS
GND
BY26
VSS
GND
BV14
VMSE3_CMD[11]
SMI2
O
BY28
VSS
GND
BV16
VMSE3_CMD[12]
SMI2
O
BY30
VTTQ
PWR
BV2
VSS
GND
BY32
VSS
GND
BV4
VSS
GND
BY34
VSS
GND
BV42
VTTA
PWR
BY36
VTTQ
PWR
BV44
VMSE0_CMD[2]
SMI2
O
BY38
VSS
GND
BV46
VMSE0_CMD[1]
SMI2
O
BY4
VMSE3_DQ[19]
SMI2
BV48
VMSE0_DQ[48]
SMI2
I/O
BY40
VSS
GND
BV50
VMSE0_DQS_P[6]
SMI2
I/O
BY42
VTTQ
PWR
BV52
VMSE0_DQ[50]
SMI2
I/O
BY44
RSVD
BV54
VSS
GND
BY46
VSS
GND
BV56
VMSE0_DQS_N[8]
SMI2
I/O
BY48
VMSE0_ERR_N
SMI2
BV58
VMSE0_ECC[6]
SMI2
I/O
BY50
VSS
GND
BV6
VSS
GND
BY52
VSS
GND
BV8
VSS
GND
BY54
VMSE0_ECC[4]
SMI2
I/O
I/O
I/O
BW1
VSS
GND
BY56
VMSE0_DQS_P[8]
SMI2
I/O
BW11
VMSE3_CMD[5]
SMI2
O
BY58
VMSE0_ECC[2]
SMI2
I/O
BW13
VMSE3_CMD[15]
SMI2
O
BY6
VMSE3_DQ[22]
SMI2
I/O
BW15
VMSE3_CMD[10]
SMI2
O
BY8
VSS
GND
BW17
VSS
GND
C11
PE1_RX_N[14]
PCIEX3
I
BW3
VMSE3_DQ[18]
SMI2
C13
PE1_RX_P[10]
PCIEX3
I
BW43
VSS
GND
BW45
VMSE0_CMD[7]
SMI2
78
I/O
O
C15
VTTA
PWR
C17
PE1_TX_N[10]
PCIEX3
O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 21 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 22 of 50)
Land Name
Buffer Type Direction
C19
VCC
PWR
CA5
VSS
GND
C21
VCC
PWR
CA51
VSS
GND
C23
VSS
GND
CA53
VSS
GND
C25
VCC
PWR
CA55
VSS
GND
CA57
VMSE0_ECC[7]
SMI2
CA7
VSS
GND
I/O
C3
RSVD
C33
VCC
PWR
C35
QPI0_DRX_DP[3]
Intel® QPI
I
CA9
VSS
GND
C37
QPI0_DRX_DP[5]
Intel® QPI
I
CB10
VMSE3_ECC[7]
SMI2
C39
QPI0_DRX_DP[7]
Intel
®
QPI
I
CB12
VSS
GND
C41
QPI0_DRX_DP[9]
Intel® QPI
I
CB14
VMSE3_DQ[28]
SMI2
C43
QPI0_CLKRX_DP
®
Intel
QPI
I
CB16
VMSE3_DQ[24]
SMI2
I/O
C45
QPI0_DRX_DP[11]
Intel® QPI
I
CB18
MEM_SCL_C2
Open Drain
I/O
C47
QPI0_DRX_DP[13]
Intel® QPI
I
CB2
VMSE3_DQ[45]
SMI2
I/O
C49
QPI0_DRX_DP[15]
Intel® QPI
I
CB20
VMSE2_DQ[41]
SMI2
I/O
C5
RSVD
I/O
C51
QPI0_DRX_DN[17]
Intel® QPI
I
C53
VSS
GND
C55
BPM_N[3]
CMOS
C7
VSS
C9
VSS
CA1
VMSE3_DQ[40]
SMI2
CB34
CA11
VSS
GND
CB36
CA13
VSS
GND
CB38
VMSE1_DQ[45]
SMI2
CA15
VSS
GND
CB4
VSS
GND
CA17
VSS
GND
CB40
VMSE1_DQ[47]
SMI2
CA19
VSS
GND
CB42
VSS
GND
CA21
VSS
GND
CB44
VMSE1_DQ[57]
SMI2
I/O
CA23
VSS
GND
CB46
VMSE1_DQ[62]
SMI2
I/O
CA25
VSS
GND
CB48
MEM_HOT_C01_N
Open Drain
I/O
CA27
VSS
GND
CB50
VMSE0_DQ[43]
SMI2
I/O
I/O
I/O
I/O
CB22
VMSE2_DQ[46]
SMI2
CB24
VSS
GND
CB26
VMSE2_DQ[37]
SMI2
I/O
CB28
VMSE2_DQ[39]
SMI2
I/O
GND
CB30
VSS
GND
GND
CB32
VMSE1_DQ[5]
SMI2
I/O
VMSE1_DQ[7]
SMI2
I/O
VSS
GND
I/O
I/O
I/O
I/O
CA29
VSS
GND
CB52
VMSE0_DQ[42]
SMI2
CA3
VSS
GND
CB54
VSS
GND
CA31
VSS
GND
CB56
VSS
GND
CA33
VSS
GND
CB6
VSS
GND
CA35
VSS
GND
CB8
VMSE3_ECC[5]
SMI2
I/O
CA37
VSS
GND
CC11
VMSE3_ECC[2]
SMI2
I/O
CA39
VSS
GND
CC13
VMSE3_DQ[25]
SMI2
I/O
CA41
VSS
GND
CC15
VMSE3_DQS_N[3]
SMI2
I/O
CA43
VSS
GND
CC17
VMSE3_DQ[29]
SMI2
I/O
CA45
VSS
GND
CC19
VMSE2_DQ[44]
SMI2
I/O
CA47
VSS
GND
CC21
VMSE2_DQS_P[5]
SMI2
I/O
CA49
VSS
GND
CC23
VMSE2_DQ[43]
SMI2
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
79
Table 3-2.
Land No.
Land Number (Sheet 23 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 24 of 50)
Land Name
Buffer Type Direction
CC25
VMSE2_DQ[32]
SMI2
I/O
CD52
VSS
GND
CC27
VMSE2_DQS_N[4]
SMI2
I/O
CD54
VVMSE01
PWR
CC29
VMSE2_DQ[38]
SMI2
I/O
CD56
VMSE0_ECC[0]
SMI2
CC3
VMSE3_DQ[41]
SMI2
I/O
CD6
VSS
GND
I/O
CC31
VMSE1_DQ[0]
SMI2
I/O
CD8
VSS
GND
CC33
VMSE1_DQS_P[0]
SMI2
I/O
CE11
VMSE3_ECC[3]
SMI2
I/O
CC35
VMSE1_DQ[2]
SMI2
I/O
CE13
VMSE3_DQ[31]
SMI2
I/O
CC37
VMSE1_DQ[40]
SMI2
I/O
CE15
VMSE3_DQS_P[3]
SMI2
I/O
CC39
VMSE1_DQS_N[5]
SMI2
I/O
CE17
VMSE3_DQ[30]
SMI2
I/O
CC41
VMSE1_DQ[42]
SMI2
I/O
CE19
VMSE2_DQ[40]
SMI2
I/O
CC43
VMSE1_DQ[60]
SMI2
I/O
CE21
VMSE2_DQS_N[5]
SMI2
I/O
CC45
VMSE1_DQS_P[7]
SMI2
I/O
CE23
VMSE2_DQ[42]
SMI2
I/O
CC47
VMSE1_DQ[59]
SMI2
I/O
CE25
VMSE2_DQ[36]
SMI2
I/O
CC49
VMSE0_DQ[46]
SMI2
I/O
CE27
VMSE2_DQS_P[4]
SMI2
I/O
CC5
VMSE3_DQ[44]
SMI2
I/O
CE29
VMSE2_DQ[35]
SMI2
I/O
CC51
VMSE0_DQS_P[5]
SMI2
I/O
CE3
VMSE3_DQS_P[5]
SMI2
I/O
CC53
VMSE0_DQ[47]
SMI2
I/O
CE31
VMSE1_DQ[4]
SMI2
I/O
CC55
VMSE0_ECC[5]
SMI2
I/O
CE33
VMSE1_DQS_N[0]
SMI2
I/O
CC7
VMSE3_ECC[0]
SMI2
I/O
CE35
VMSE1_DQ[3]
SMI2
I/O
CC9
VMSE3_DQS_P[8]
SMI2
I/O
CE37
VMSE1_DQ[44]
SMI2
I/O
CD10
VSS
GND
CE39
VMSE1_DQS_P[5]
SMI2
I/O
CD12
VSS
GND
CE41
VMSE1_DQ[43]
SMI2
I/O
CD14
VSS
GND
CE43
VMSE1_DQ[56]
SMI2
I/O
CD16
VSS
GND
CE45
VMSE1_DQS_N[7]
SMI2
I/O
CD18
VSS
GND
CE47
VMSE1_DQ[58]
SMI2
I/O
CD20
VSS
GND
CE49
VMSE0_DQ[45]
SMI2
I/O
CD22
VSS
GND
CE5
VMSE3_DQ[47]
SMI2
I/O
CD24
VSS
GND
CE51
VMSE0_DQS_N[5]
SMI2
I/O
CD26
VSS
GND
CE53
VMSE0_DQ[41]
SMI2
I/O
CD28
VSS
GND
CE55
VSS
GND
CD30
VSS
GND
CE7
VMSE3_ECC[4]
SMI2
I/O
CD32
VSS
GND
CE9
VMSE3_DQS_N[8]
SMI2
I/O
CD34
VSS
GND
CF10
VMSE3_ECC[6]
SMI2
I/O
CD36
VSS
GND
CF12
VVMSE23
PWR
CD38
VSS
GND
CF14
VMSE3_DQ[26]
SMI2
I/O
CD4
VMSE3_DQS_N[5]
SMI2
CF16
VMSE3_DQ[27]
SMI2
I/O
CD40
VSS
GND
CF18
VSS
GND
CD42
VSS
GND
CF20
VMSE2_DQ[45]
SMI2
I/O
CD44
VSS
GND
CF22
VMSE2_DQ[47]
SMI2
I/O
CD46
VSS
GND
CF24
VVMSE23
PWR
CD48
VSS
GND
CF26
VMSE2_DQ[33]
SMI2
I/O
CD50
VSS
GND
CF28
VMSE2_DQ[34]
SMI2
I/O
80
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 25 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 26 of 50)
Land Name
Buffer Type Direction
CF30
VSS
GND
CG7
VSS
GND
CF32
VMSE1_DQ[1]
SMI2
I/O
CG9
VSS
GND
CF34
VMSE1_DQ[6]
SMI2
I/O
CH10
VSS
GND
CF36
SVID_IDLE_N
CMOS
O
CH12
VSS
GND
I/O
CH14
VSS
GND
CH16
VSS
GND
CH18
VSS
GND
CH20
VSS
GND
CF38
VMSE1_DQ[41]
SMI2
CF4
VSS
GND
CF40
VMSE1_DQ[46]
SMI2
CF42
VVMSE01
PWR
I/O
CF44
VMSE1_DQ[61]
SMI2
I/O
CH22
VSS
GND
CF46
VMSE1_DQ[63]
SMI2
I/O
CH24
VSS
GND
CF48
VSS
GND
CH26
VSS
GND
CF50
VMSE0_DQ[40]
SMI2
I/O
CH28
VSS
GND
CF52
VMSE0_DQ[44]
SMI2
I/O
CH30
VSS
GND
CF54
VSS
GND
CH32
VSS
GND
CF56
VSS
GND
CH34
VSS
GND
CF6
MEM_SCL_C3
Open Drain
I/O
CH36
VSS
GND
CF8
VMSE3_ECC[1]
SMI2
I/O
CH38
VSS
GND
CG11
VSS
GND
CH4
VMSE3_DQ[46]
SMI2
CG13
VSS
GND
CH40
VSS
GND
CG15
VSS
GND
CH42
VSS
GND
CG17
VSS
GND
CH44
VSS
GND
CG19
VSS
GND
CH46
VSS
GND
CG21
VSS
GND
CH48
VSS
GND
CG23
VSS
GND
CH50
VSS
GND
CG25
VSS
GND
CH52
VSS
GND
CG27
VSS
GND
CH54
VMSE0_DQ[24]
SMI2
I/O
CG29
VSS
GND
CH56
VMSE0_DQ[25]
SMI2
I/O
CG3
VMSE3_DQ[42]
SMI2
CH6
VSS
GND
CG31
VSS
GND
CH8
VSS
GND
CG33
VSS
GND
CJ11
MEM_SDA_C2
Open Drain
I/O
CG35
VSS
GND
CJ13
VMSE2_DQ[5]
SMI2
I/O
CG37
VSS
GND
CJ15
VMSE2_DQ[7]
SMI2
I/O
CG39
VSS
GND
CJ17
VSS
GND
CG41
VSS
GND
CJ19
VMSE2_DQ[21]
SMI2
I/O
CG43
VSS
GND
CJ21
VMSE2_DQ[23]
SMI2
I/O
CG45
VSS
GND
CJ23
VSS
GND
CG47
VSS
GND
CJ25
VMSE2_DQ[49]
SMI2
I/O
CG49
VSS
GND
CJ27
VMSE2_DQ[54]
SMI2
I/O
CG5
VSS
GND
CJ29
VSS
GND
CG51
VSS
GND
CJ3
VMSE3_DQ[43]
SMI2
I/O
CG53
VSS
GND
CJ31
VMSE1_DQ[9]
SMI2
I/O
CG55
VMSE0_DQ[28]
SMI2
CJ33
VMSE1_DQ[10]
SMI2
I/O
I/O
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
I/O
81
Table 3-2.
Land No.
Land Number (Sheet 27 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 28 of 50)
Land Name
Buffer Type Direction
CJ35
VVMSE01
PWR
CL13
VSS
GND
CJ37
VMSE1_DQ[37]
SMI2
I/O
CL15
VSS
GND
I/O
CL17
VSS
GND
CL19
VSS
GND
CJ39
VMSE1_DQ[39]
SMI2
CJ41
VSS
GND
CJ43
VMSE1_DQ[53]
SMI2
I/O
CL21
VSS
GND
CJ45
VMSE1_DQ[55]
SMI2
I/O
CL23
VSS
GND
CJ47
VVMSE01
PWR
CL25
VSS
GND
CJ49
VMSE0_DQ[35]
SMI2
CL27
VSS
GND
CJ5
VVMSE23
PWR
CL29
VSS
GND
CJ51
VMSE0_DQ[38]
SMI2
CL3
VSS
GND
CJ53
VSS
GND
CL31
VSS
GND
CJ55
VSS
GND
CL33
VSS
GND
CJ7
VMSE3_DQ[36]
SMI2
I/O
CL35
VSS
GND
CJ9
VMSE3_DQ[32]
SMI2
I/O
CL37
VSS
GND
CK10
VMSE3_DQ[37]
SMI2
I/O
CL39
VSS
GND
CK12
VMSE2_DQ[0]
SMI2
I/O
CL41
VSS
GND
CK14
VMSE2_DQS_P[0]
SMI2
I/O
CL43
VSS
GND
CK16
VMSE2_DQ[2]
SMI2
I/O
CL45
VSS
GND
I/O
I/O
CK18
VMSE2_DQ[16]
SMI2
I/O
CL47
VSS
GND
CK20
VMSE2_DQS_N[2]
SMI2
I/O
CL49
VSS
GND
CK22
VMSE2_DQ[18]
SMI2
I/O
CL5
VSS
GND
CK24
VMSE2_DQ[52]
SMI2
I/O
CL51
VSS
GND
CK26
VMSE2_DQS_N[6]
SMI2
I/O
CL53
VSS
GND
CK28
VMSE2_DQ[51]
SMI2
I/O
CL55
VMSE0_DQS_P[3]
SMI2
I/O
CK30
VMSE1_DQ[13]
SMI2
I/O
CL7
VSS
GND
CK32
VMSE1_DQS_P[1]
SMI2
I/O
CL9
VSS
GND
CK34
VMSE1_DQ[11]
SMI2
I/O
CM10
VMSE3_DQ[38]
SMI2
I/O
CK36
VMSE1_DQ[32]
SMI2
I/O
CM12
VMSE2_DQ[4]
SMI2
I/O
CK38
VMSE1_DQS_N[4]
SMI2
I/O
CM14
VMSE2_DQS_N[0]
SMI2
I/O
CK4
VSS
GND
CM16
VMSE2_DQ[3]
SMI2
I/O
CK40
VMSE1_DQ[34]
SMI2
I/O
CM18
VMSE2_DQ[20]
SMI2
I/O
CK42
VMSE1_DQ[48]
SMI2
I/O
CM20
VMSE2_DQS_P[2]
SMI2
I/O
CK44
VMSE1_DQS_P[6]
SMI2
I/O
CM22
VMSE2_DQ[19]
SMI2
I/O
CK46
VMSE1_DQ[50]
SMI2
I/O
CM24
VMSE2_DQ[48]
SMI2
I/O
CK48
VMSE0_DQ[34]
SMI2
I/O
CM26
VMSE2_DQS_P[6]
SMI2
I/O
CK50
VMSE0_DQS_P[4]
SMI2
I/O
CM28
VMSE2_DQ[50]
SMI2
I/O
CK52
VMSE0_DQ[39]
SMI2
I/O
CM30
VMSE1_DQ[8]
SMI2
I/O
CK54
VMSE0_DQ[29]
SMI2
I/O
CM32
VMSE1_DQS_N[1]
SMI2
I/O
CK56
VSS
GND
CM34
VMSE1_DQ[14]
SMI2
I/O
CK6
VMSE3_DQ[33]
SMI2
I/O
CM36
VMSE1_DQ[36]
SMI2
I/O
CK8
VMSE3_DQS_N[4]
SMI2
I/O
CM38
VMSE1_DQS_P[4]
SMI2
I/O
CL11
VSS
GND
CM4
VMSE3_DQ[58]
SMI2
I/O
82
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 29 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 30 of 50)
Land Name
Buffer Type Direction
CM40
VMSE1_DQ[35]
SMI2
I/O
CP16
VSS
GND
CM42
VMSE1_DQ[52]
SMI2
I/O
CP18
VSS
GND
CM44
VMSE1_DQS_N[6]
SMI2
I/O
CP2
VSS
GND
CM46
VMSE1_DQ[51]
SMI2
I/O
CP20
VSS
GND
CM48
VMSE0_DQ[37]
SMI2
I/O
CP22
VSS
GND
CM50
VMSE0_DQS_N[4]
SMI2
I/O
CP24
VVMSE23
PWR
CM52
VMSE0_DQ[33]
SMI2
I/O
CP26
VSS
GND
CM54
VMSE0_DQS_N[3]
SMI2
I/O
CP28
VSS
GND
CM56
VMSE0_DQ[26]
SMI2
I/O
CP30
VSS
GND
CM6
VMSE3_DQ[39]
SMI2
I/O
CP32
VSS
GND
I/O
CP34
VSS
GND
CP36
VSS
GND
CM8
VMSE3_DQS_P[4]
SMI2
CN11
VSS
GND
CN13
VMSE2_DQ[1]
SMI2
I/O
CP38
VSS
GND
CN15
VMSE2_DQ[6]
SMI2
I/O
CP4
VSS
GND
CN17
VVMSE23
PWR
CP40
VSS
GND
CN19
VMSE2_DQ[17]
SMI2
I/O
CP42
VSS
GND
CN21
VMSE2_DQ[22]
SMI2
I/O
CP44
VSS
GND
CN23
VSS
GND
CP46
VSS
GND
CN25
VMSE2_DQ[53]
SMI2
I/O
CP48
VSS
GND
CN27
VMSE2_DQ[55]
SMI2
I/O
CP50
VSS
GND
CN29
VSS
GND
CP52
VSS
GND
CN3
VMSE3_DQ[60]
SMI2
I/O
CP54
VSS
GND
CN31
VMSE1_DQ[12]
SMI2
I/O
CP56
VSS
GND
CN33
VMSE1_DQ[15]
SMI2
I/O
CP58
VMSE0_DQ[27]
SMI2
CN35
VSS
GND
CP6
VSS
GND
CN37
VMSE1_DQ[33]
SMI2
I/O
CP8
VSS
GND
CN39
VMSE1_DQ[38]
SMI2
I/O
CR1
VMSE3_DQ[56]
SMI2
I/O
CN41
MEM_SDA_C1
Open Drain
I/O
CR11
VMSE2_DQ[11]
SMI2
I/O
CN43
VMSE1_DQ[49]
SMI2
I/O
CR13
VSS
GND
CN45
VMSE1_DQ[54]
SMI2
I/O
CR15
VSS
GND
CN47
VSS
GND
CR17
VMSE2_CMD[3]
SMI2
CN49
VMSE0_DQ[32]
SMI2
CR19
VSS
GND
CN5
VSS
GND
CN51
VMSE0_DQ[36]
SMI2
CN53
MEM_SCL_C0
CN55
VMSE0_DQ[31]
CN57
VMSE0_DQ[30]
CN7
VMSE3_DQ[34]
CN9
CP10
CP12
CP14
I/O
CR21
VSS
GND
I/O
CR23
VMSE2_CMD[12]
SMI2
Open Drain
I/O
CR25
VSS
GND
SMI2
I/O
CR27
VSS
GND
SMI2
I/O
CR29
VVMSE01
PWR
SMI2
I/O
CR3
VMSE3_DQS_N[7]
SMI2
VMSE3_DQ[35]
SMI2
I/O
CR31
VSS
GND
VSS
GND
CR33
VSS
GND
VSS
GND
CR35
VMSE1_ERR_N
SMI2
VSS
GND
CR37
VSS
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
I/O
O
O
I/O
I/O
83
Table 3-2.
Land No.
Land Number (Sheet 31 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 32 of 50)
Land Name
Buffer Type Direction
CU1
RSVD
CU11
VSS
GND
CU13
VMSE2_ERR_N
SMI2
I/O
CU15
VMSE2_CMD[5]
SMI2
O
GND
CU17
VSS
GND
GND
CU19
VMSE2_CMD[13]
SMI2
O
CU21
VMSE2_CMD[11]
SMI2
O
CU23
VSS
GND
GND
CU25
VMSE2_DQ[57]
SMI2
I/O
GND
CU27
VMSE2_DQ[58]
SMI2
I/O
VSS
GND
CU29
VSS
GND
VSS
GND
CU3
VSS
GND
CU31
VMSE1_DQ[21]
SMI2
I/O
CU33
VMSE1_DQ[23]
SMI2
I/O
VMSE1_CMD[5]
SMI2
O
CU39
VMSE1_CMD[3]
SMI2
O
CU41
VSS
GND
I/O
CU43
VSS
GND
O
CU45
VMSE1_CMD[14]
SMI2
O
CR39
VSS
GND
CR41
VMSE1_CMD[9]
SMI2
CR43
VSS
GND
CR45
VSS
GND
CR47
VSS
CR49
VSS
CR5
VMSE3_DQ[59]
SMI2
CR51
VSS
GND
CR53
VSS
CR55
VSS
CR57
CR7
CR9
VSS
GND
CT10
VMSE2_DQ[14]
SMI2
CT12
VSS
GND
CU35
TEST_0
CT14
VMSE2_CMD[1]
SMI2
O
CU37
CT16
VMSE2_CMD[4]
SMI2
O
CT18
VMSE2_CMD[6]
SMI2
O
CT2
VMSE3_DQ[61]
SMI2
CT20
VMSE2_CMD[16]
SMI2
O
O
I/O
I/O
CT22
VMSE2_CMD[10]
SMI2
CU47
VMSE0_DQ[12]
SMI2
I/O
CT24
VSS
GND
CU49
VMSE0_DQS_P[1]
SMI2
I/O
CT26
VSS
GND
CU5
VMSE3_DQ[62]
SMI2
I/O
CT28
VSS
GND
CU51
VMSE0_DQ[11]
SMI2
I/O
CT30
VSS
GND
CU53
VMSE0_DQ[16]
SMI2
I/O
CT32
VSS
GND
CU55
VMSE0_DQS_N[2]
SMI2
I/O
CT34
VSS
GND
CU57
VMSE0_DQ[18]
SMI2
I/O
CT36
VMSE1_CMD[2]
SMI2
O
CU7
VMSE2_DQ[12]
SMI2
I/O
CT38
VMSE1_CMD[4]
SMI2
O
CU9
VMSE2_DQS_P[1]
SMI2
I/O
CT4
VMSE3_DQS_P[7]
SMI2
I/O
CV10
VMSE2_DQ[15]
SMI2
I/O
CT40
VMSE1_CMD[6]
SMI2
O
CV12
MEM_HOT_C23_N
Open Drain
I/O
CT42
VMSE1_CMD[13]
SMI2
O
CV14
VSS
GND
CT44
VMSE1_CMD[11]
SMI2
O
CV16
VSS
GND
CT46
RSVD
CV18
VMSE2_CLK_P
SMI2
O
CT48
VMSE0_DQ[9]
SMI2
I/O
CV2
VSS
GND
CT50
VMSE0_DQ[14]
SMI2
I/O
CV20
VSS
GND
CT52
VVMSE01
PWR
CV22
VSS
GND
CT54
VMSE0_DQ[21]
SMI2
I/O
CV24
VMSE2_DQ[61]
SMI2
CT56
VMSE0_DQ[23]
SMI2
I/O
CV26
VMSE2_DQS_P[7]
SMI2
I/O
CT58
VSS
GND
CV28
VMSE2_DQ[59]
SMI2
I/O
CT6
VSS
GND
CV30
VMSE1_DQ[16]
SMI2
I/O
CT8
VMSE2_DQ[9]
SMI2
CV32
VMSE1_DQS_N[2]
SMI2
I/O
84
I/O
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 33 of 50)
Land Name
Buffer Type Direction
CV34
VMSE1_DQ[18]
SMI2
CV36
VSS
GND
I/O
Table 3-2.
Land No.
Land Number (Sheet 34 of 50)
Land Name
Buffer Type Direction
CW57
VMSE0_DQ[19]
SMI2
I/O
CW7
VMSE2_DQ[8]
SMI2
I/O
CW9
VMSE2_DQS_N[1]
SMI2
I/O
CY10
VSS
GND
CV38
VSS
GND
CV4
VMSE3_DQ[63]
SMI2
CV40
VVMSE01
PWR
CY12
VSS
GND
CV42
VSS
GND
CY14
VMSE2_CMD[7]
SMI2
CV44
VSS
GND
CY16
VMSE2_CMD[8]
SMI2
O
CV46
VSS
GND
CY18
VMSE2_CLK_N
SMI2
O
CV48
VSS
GND
CY2
VSS
GND
CV50
VSS
GND
CY20
VMSE2_CMD[15]
SMI2
O
CV52
VSS
GND
CY22
VMSE2_CMD[14]
SMI2
O
CV54
VSS
GND
CY24
VMSE2_DQ[56]
SMI2
I/O
CV56
VSS
GND
CY26
VMSE2_DQS_N[7]
SMI2
I/O
CV58
TEST_7
CY28
VMSE2_DQ[62]
SMI2
I/O
CV6
VSS
GND
CY30
VMSE1_DQ[20]
SMI2
I/O
CV8
VSS
GND
CY32
VMSE1_DQS_P[2]
SMI2
I/O
CW1
RSVD
CY34
VMSE1_DQ[19]
SMI2
I/O
CW11
VMSE2_DQ[10]
SMI2
I/O
CY36
VMSE1_CMD[7]
SMI2
O
CW13
VMSE2_CMD[2]
SMI2
O
CY38
VMSE1_CMD[8]
SMI2
O
CW15
TEST_3
CY4
VSS
GND
I/O
O
CW17
VMSE2_CMD[0]
SMI2
CY40
VMSE1_CLK_N
SMI2
O
CW19
VSS
GND
CY42
VMSE1_CMD[15]
SMI2
O
CW21
VSS
GND
CY44
VMSE1_CMD[10]
SMI2
O
CW23
VSS
GND
CY46
VSS
GND
CW25
VSS
GND
CY48
VMSE0_DQ[13]
SMI2
I/O
CW27
VSS
GND
CY50
VMSE0_DQ[15]
SMI2
I/O
CW29
VSS
GND
CY52
VSS
GND
CW3
VMSE3_DQ[57]
SMI2
CY54
VMSE0_DQ[17]
SMI2
I/O
CW31
VSS
GND
CY56
VMSE0_DQ[22]
SMI2
I/O
CW33
VSS
GND
CY58
EAR_N
CMOS
I/O
CW35
VSS
GND
CW37
VMSE1_CMD[1]
SMI2
CW39
VSS
GND
CW41
VMSE1_CLK_P
SMI2
O
CW43
VMSE1_CMD[16]
SMI2
CW45
VMSE1_CMD[12]
SMI2
O
I/O
CY6
VVMSE23
PWR
CY8
VMSE2_DQ[13]
SMI2
I/O
D10
PE1_RX_P[14]
PCIEX3
I
D12
VSS
GND
O
D14
PE1_RX_N[11]
PCIEX3
I
O
D16
PE1_TX_P[10]
PCIEX3
O
GND
O
CW47
VMSE0_DQ[8]
SMI2
I/O
D18
VSS
CW49
VMSE0_DQS_N[1]
SMI2
I/O
D2
RSVD
CW5
VSS
GND
D20
VCC
PWR
CW51
VMSE0_DQ[10]
SMI2
I/O
D22
VCC
PWR
CW53
VMSE0_DQ[20]
SMI2
I/O
D24
VSS
GND
CW55
VMSE0_DQS_P[2]
SMI2
I/O
D26
VCC
PWR
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
85
Table 3-2.
Land No.
Land Number (Sheet 35 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 36 of 50)
Land Name
Buffer Type Direction
D32
VCC
PWR
DA7
VSS
GND
D34
VSS
GND
DA9
VSS
GND
®
D36
QPI0_DRX_DP[4]
Intel
QPI
I
DB10
VMSE3_DQ[54]
SMI2
D38
QPI0_DRX_DP[6]
Intel® QPI
I
DB12
VVMSE23
PWR
DB14
VSS
GND
I
DB16
VSS
GND
GND
D4
RSVD
D40
QPI0_DRX_DP[8]
Intel® QPI
D42
VTTA
PWR
DB18
VSS
D44
QPI0_DRX_DP[10]
Intel® QPI
I
DB2
RSVD
D46
QPI0_DRX_DP[12]
Intel® QPI
I
DB20
VSS
GND
D48
QPI0_DRX_DP[14]
Intel® QPI
I
DB22
VSS
GND
D50
QPI0_DRX_DP[16]
®
Intel
QPI
I
DB24
VSS
GND
D52
QPI0_DRX_DN[18]
Intel® QPI
I
DB26
VSS
GND
D54
BPM_N[6]
CMOS
I/O
DB28
VSS
GND
D56
BPM_N[7]
CMOS
I/O
DB30
VSS
GND
D6
VSS
GND
DB32
VSS
GND
D8
VSS
GND
DB34
VSS
GND
DA11
VSS
GND
DB36
VSS
GND
DA13
VSS
GND
DB38
VSS
GND
DA15
VSS
GND
DB4
RSVD
DA17
VSS
GND
DB40
VSS
GND
DA19
VMSE2_CMD[9]
SMI2
DB42
VSS
GND
DA21
VSS
GND
DB44
VSS
GND
O
DB46
VVMSE01
PWR
I/O
DB48
VSS
GND
SMI2
I/O
DB50
VSS
GND
Open Drain
I/O
DB52
VSS
GND
DA23
VSS
GND
DA25
VMSE2_DQ[60]
SMI2
DA27
VMSE2_DQ[63]
DA29
MEM_SCL_C1
I/O
DA3
RSVD
DB54
TEST_10
DA31
VMSE1_DQ[17]
SMI2
I/O
DB56
RSVD
DA33
VMSE1_DQ[22]
SMI2
I/O
DB58
VSS
GND
DA35
VSS
GND
DB6
VMSE3_DQ[53]
SMI2
DB8
VSS
GND
DC11
VMSE3_DQ[51]
SMI2
I/O
I/O
DA37
VSS
GND
DA39
VMSE1_CMD[0]
SMI2
DA41
VSS
GND
DC13
VMSE2_DQ[29]
SMI2
I/O
DA43
VSS
GND
DC15
VMSE2_DQ[25]
SMI2
I/O
DA45
VSS
GND
DC17
VMSE2_DQ[26]
SMI2
I/O
DA47
VSS
GND
DC19
VMSE_PWR_OK
SMI2
I
DC21
VMSE2_ECC[4]
SMI2
I/O
DC23
VMSE2_ECC[7]
SMI2
I/O
PWR
O
DA49
VSS
GND
DA5
VMSE3_DQ[48]
SMI2
DA51
VSS
GND
DC25
VVMSE23
DA53
VSS
GND
DC3
RSVD
DA55
VSS
GND
DC33
VSS
GND
DA57
RSVD
DC35
VMSE1_DQ[25]
SMI2
86
I/O
I/O
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 37 of 50)
Land Name
Buffer Type Direction
SMI2
I/O
Table 3-2.
Land No.
Land Number (Sheet 38 of 50)
Land Name
Buffer Type Direction
DE23
VMSE2_DQS_N[8]
SMI2
I/O
DE25
VMSE2_ECC[6]
SMI2
I/O
VMSE1_DQ[29]
SMI2
I/O
VMSE1_DQS_N[3]
SMI2
I/O
DC37
VMSE1_DQ[26]
DC39
RSVD
DC41
VMSE1_ECC[4]
SMI2
I/O
DE33
DC43
VMSE1_ECC[7]
SMI2
I/O
DE35
DC45
VMSE1_ECC[6]
SMI2
I/O
DE37
VSS
GND
DC47
VMSE0_DQ[5]
SMI2
I/O
DE39
VSS
GND
DC49
VMSE0_DQ[1]
SMI2
I/O
DE41
VSS
GND
DC5
RSVD
DE43
VMSE1_DQS_N[8]
SMI2
I/O
DC51
VMSE0_DQ[2]
SMI2
I/O
DE45
VMSE1_ECC[3]
SMI2
I/O
DC53
VMSE0_DQ[3]
SMI2
I/O
DE47
VMSE0_DQ[0]
SMI2
I/O
I/O
DC55
RSVD
DE49
VMSE0_DQS_P[0]
SMI2
DC7
VMSE3_DQ[52]
SMI2
I/O
DE51
VSS
GND
DC9
VMSE3_DQS_N[6]
SMI2
I/O
DE53
RSVD
DD10
VSS
GND
DE55
TEST_1
DD12
VSS
GND
DE7
VSS
GND
DD14
VSS
GND
DE9
VMSE3_DQS_P[6]
SMI2
I/O
DD16
VMSE2_DQS_P[3]
SMI2
I/O
DF10
VMSE3_DQ[55]
SMI2
I/O
DD18
VMSE2_DQ[30]
SMI2
I/O
DF12
VSS
GND
DD20
VMSE2_ECC[5]
SMI2
I/O
DF14
VMSE2_DQ[28]
SMI2
I/O
DD22
VMSE2_DQS_P[8]
SMI2
I/O
DF16
VMSE2_DQ[31]
SMI2
I/O
DD24
VSS
GND
DF18
VMSE2_DQ[27]
SMI2
I/O
DD26
VMSE2_ECC[3]
SMI2
I/O
DF20
VMSE2_ECC[0]
SMI2
I/O
DD32
VMSE1_DQ[24]
SMI2
I/O
DF22
VMSE2_ECC[1]
SMI2
I/O
DD34
VSS
GND
DF24
VMSE2_ECC[2]
SMI2
I/O
DD36
VMSE1_DQS_P[3]
SMI2
I/O
DF26
VSS
GND
DD38
VMSE1_DQ[30]
SMI2
I/O
DF34
VMSE1_DQ[28]
SMI2
I/O
DD40
VMSE1_ECC[5]
SMI2
I/O
DF36
VMSE1_DQ[31]
SMI2
I/O
DD42
VMSE1_DQS_P[8]
SMI2
I/O
DF38
VMSE1_DQ[27]
SMI2
I/O
DD44
VSS
GND
DF40
VMSE1_ECC[0]
SMI2
I/O
DD46
VSS
GND
DF42
VMSE1_ECC[1]
SMI2
I/O
I/O
DD48
VSS
GND
DF44
VMSE1_ECC[2]
SMI2
DD50
VMSE0_DQS_N[0]
SMI2
I/O
DF46
VSS
GND
DD52
VMSE0_DQ[6]
SMI2
I/O
DF48
VMSE0_DQ[4]
SMI2
I/O
DD54
VSS
GND
DF50
VMSE0_DQ[7]
SMI2
I/O
DD6
RSVD
DF52
RSVD
DD8
VMSE3_DQ[49]
SMI2
I/O
DF8
VSS
DE11
VMSE3_DQ[50]
SMI2
I/O
E1
VSS
GND
DE13
VMSE2_DQ[24]
SMI2
I/O
E11
PE1_RX_N[12]
PCIEX3
I
DE15
VMSE2_DQS_N[3]
SMI2
I/O
E13
PE1_RX_P[11]
PCIEX3
I
DE17
VSS
GND
E15
VSS
GND
DE19
VSS
GND
E17
PE1_TX_N[8]
PCIEX3
DE21
VSS
GND
E19
VSS
GND
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
GND
O
87
Table 3-2.
Land No.
Land Number (Sheet 39 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 40 of 50)
Land Name
Buffer Type Direction
E21
VCC
PWR
F44
VSS
GND
E23
VSS
GND
F46
VSS
GND
E25
VCC
PWR
F48
VSS
GND
E27
VCC
PWR
F50
VSS
GND
E29
VSS
GND
F52
QPI0_DRX_DP[18]
Intel® QPI
E3
RSVD
F54
VSS
GND
E31
VCC
PWR
F56
QPI1_DRX_DN[19]
Intel® QPI
I
E33
VCC
PWR
F58
RSVD
E35
VSS
GND
F6
QPI2_DTX_DP[0]
Intel® QPI
O
E37
VSS
GND
F8
VSS
GND
E39
VSS
GND
G1
VSS
GND
E41
VSS
GND
G11
PE1_RX_N[7]
PCIEX3
I
E43
VSS
GND
G13
PE1_RX_P[9]
PCIEX3
I
E45
VSS
GND
G15
VSS
GND
E47
VSS
GND
G17
PE1_TX_N[7]
PCIEX3
E49
VSS
GND
G19
VSS
GND
E5
VSS
GND
G21
VCC
PWR
E51
QPI0_DRX_DP[17]
Intel® QPI
I
G23
VSS
GND
E53
QPI0_DRX_DN[19]
Intel®
I
G25
VCC
PWR
E55
VSS
GND
G27
VCC
PWR
QPI
I
O
E57
BPM_N[2]
CMOS
I/O
G29
VSS
GND
E7
QPI2_DTX_DN[0]
Intel® QPI
O
G3
QPI2_DRX_DP[0]
Intel® QPI
E9
VTTA
PWR
G31
VCC
PWR
F10
PE1_RX_P[12]
PCIEX3
G33
VCC
PWR
F12
VTTA
PWR
G35
QPI0_DRX_DN[1]
Intel® QPI
F14
PE1_RX_N[9]
PCIEX3
I
G37
RSVD
O
G39
PE0_TX_N[8]
PCIEX3
O
G41
PE0_TX_N[10]
PCIEX3
O
F16
PE1_TX_P[8]
PCIEX3
F18
VSS
GND
I
I
I
F2
RSVD
G43
PE0_RX_N[8]
PCIEX3
I
F20
VCC
PWR
G45
PE0_RX_N[10]
PCIEX3
I
F22
VCC
PWR
G47
VTTA
PWR
F24
VSS
GND
G49
QPI0_DTX_DN[0]
Intel® QPI
F26
VCC
PWR
G5
VSS
GND
F28
VCC
PWR
G51
VSS
GND
F30
VSS
GND
G53
QPI0_DRX_DP[19]
Intel® QPI
I
F32
VCC
PWR
G55
QPI1_DRX_DP[19]
Intel® QPI
I
®
F34
QPI0_DRX_DN[0]
Intel
F36
VTTA
PWR
QPI
I
G57
VSS
GND
G7
QPI2_DTX_DN[1]
Intel® QPI
F38
VTTA
PWR
F4
QPI2_DRX_DN[0]
Intel® QPI
F40
VSS
GND
H12
VSS
GND
F42
VTTA
PWR
H14
PE1_RX_N[8]
PCIEX3
88
I
G9
VSS
GND
H10
PE1_RX_P[7]
PCIEX3
O
O
I
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 41 of 50)
Land Name
Buffer Type Direction
H16
PE1_TX_P[7]
PCIEX3
H18
VSS
GND
®
QPI
O
I
Table 3-2.
Land No.
Land Number (Sheet 42 of 50)
Land Name
Buffer Type Direction
J39
PE0_TX_P[8]
PCIEX3
O
J41
PE0_TX_P[10]
PCIEX3
O
H2
QPI2_DRX_DN[2]
Intel
J43
PE0_RX_P[8]
PCIEX3
I
H20
VCC
PWR
J45
PE0_RX_P[10]
PCIEX3
I
H22
VCC
PWR
J47
VTTA
PWR
H24
VSS
GND
J49
QPI0_DTX_DN[1]
Intel® QPI
H26
VCC
PWR
J5
VSS
GND
H28
VCC
PWR
J51
VTT_SENSE
H30
VSS
GND
J53
RSVD
H32
VCC
PWR
J55
QPI1_DRX_DP[18]
Intel® QPI
®
O
H34
QPI0_DRX_DP[0]
Intel
QPI
I
J57
VSS
GND
H36
QPI0_DRX_DN[2]
Intel® QPI
I
J7
QPI2_DTX_DN[2]
Intel® QPI
H38
PE0_TX_N[7]
PCIEX3
O
J9
VTTQ
PWR
H4
QPI2_DRX_DN[1]
Intel® QPI
I
K10
PE1_RX_P[6]
PCIEX3
H40
PE0_TX_N[9]
PCIEX3
O
K12
VSS
GND
H42
VSS
GND
K14
VTTQ
PWR
H44
PE0_RX_N[9]
PCIEX3
I
K16
PE1_TX_P[6]
PCIEX3
H46
PE0_RX_N[11]
PCIEX3
I
K18
VSS
GND
H48
QPI0_DTX_DP[0]
Intel® QPI
O
K2
VSS
GND
H50
VTTA
PWR
K20
VCC
PWR
H52
VSS
GND
K22
VCC
PWR
H54
VTTA
PWR
K24
VSS
GND
H56
QPI1_DRX_DN[18]
Intel® QPI
K26
VCC
PWR
H58
RSVD
K28
VCC
PWR
I
H6
QPI2_DTX_DP[1]
Intel®
H8
EX_LEGACY_SKT
CMOS
J1
QPI2_DRX_DP[2]
Intel®
J11
PE1_RX_N[6]
PCIEX3
J13
PE1_RX_P[8]
PCIEX3
I
J15
VTTQ
PWR
J17
PE1_TX_N[6]
PCIEX3
J19
VSS
GND
J21
VCC
J23
VSS
O
VSS
GND
K32
VCC
PWR
I
K34
VSS
GND
I
K36
QPI0_DRX_DP[2]
Intel® QPI
K38
PE0_TX_P[7]
PCIEX3
O
K4
QPI2_DRX_DN[3]
Intel® QPI
I
K40
PE0_TX_P[9]
PCIEX3
O
K42
VSS
GND
PWR
K44
PE0_RX_P[9]
PCIEX3
I
GND
K46
PE0_RX_P[11]
PCIEX3
I
QPI
O
PWR
K48
QPI0_DTX_DP[1]
Intel
VCC
PWR
K50
VSS
GND
J29
VSS
GND
J3
QPI2_DRX_DP[1]
Intel® QPI
J31
VCC
J33
VCC
RSVD
I
K30
VCC
QPI0_DRX_DP[1]
O
O
J27
J37
I
I
QPI
J25
J35
O
®
QPI
I
O
K52
RSVD
K54
VSS
GND
PWR
K56
QPI1_DRX_DN[17]
Intel® QPI
I
PWR
K58
BPM_N[0]
CMOS
I/O
Intel
®
QPI
I
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
®
K6
QPI2_DTX_DP[2]
Intel
K8
VSS
GND
QPI
O
89
Table 3-2.
Land No.
Land Number (Sheet 43 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 44 of 50)
Land Name
Buffer Type Direction
M34
VSS
GND
M36
VSS
GND
GND
M38
VSS
GND
GND
M4
QPI2_DRX_DN[4]
Intel® QPI
M40
VSS
GND
M42
VTTA
PWR
L1
VSS
GND
L11
PE1_RX_N[5]
PCIEX3
L13
VSS
L15
VSS
L17
PE1_TX_N[5]
PCIEX3
L19
VSS
GND
I
O
I
L21
VCC
PWR
M44
VSS
GND
L23
VSS
GND
M46
VSS
GND
L25
VCC
PWR
M48
QPI0_DTX_DP[2]
Intel® QPI
L27
VCC
PWR
M50
VSS
GND
L29
VSS
GND
M52
QPI0_DTX_DP[3]
Intel® QPI
O
L3
QPI2_DRX_DP[3]
Intel® QPI
M54
TSC_SYNC
Open Drain
I/O
I
I
O
L31
VCC
PWR
M56
QPI1_DRX_DN[16]
Intel®
L33
VCC
PWR
M6
QPI2_DTX_DP[3]
Intel® QPI
L35
VSS
GND
M8
VSS
GND
L37
VSS
GND
N11
PE1_RX_N[4]
PCIEX3
I
L39
VSS
GND
N13
PE1_TX_P[13]
PCIEX3
O
L41
VSS
GND
N15
VTTA
PWR
L43
VSS
GND
N17
PE1_TX_N[4]
PCIEX3
L45
VSS
GND
N19
VSS
GND
L47
VSS
GND
L49
QPI0_DTX_DN[2]
Intel® QPI
L5
L51
QPI
N21
VCC
PWR
O
N23
VSS
GND
PIROM_ADDR[1]
I/O
N25
VCC
PWR
VSS_VTT_SENSE
O
N27
VCC
PWR
O
N29
VSS
GND
I
N3
QPI2_DRX_DP[4]
Intel® QPI
L53
QPI0_DTX_DN[3]
Intel®
L55
QPI1_DRX_DP[17]
Intel® QPI
QPI
O
O
I
L57
BPM_N[1]
CMOS
I/O
N31
VCC
PWR
L7
QPI2_DTX_DN[3]
Intel® QPI
O
N33
VCC
PWR
L9
VSS
GND
N35
PE0_TX_N[3]
PCIEX3
O
M10
PE1_RX_P[5]
PCIEX3
N37
PE0_TX_N[5]
PCIEX3
O
M12
VTTA
PWR
N39
PE0_TX_N[2]
PCIEX3
O
M14
PE1_TX_N[13]
PCIEX3
O
N41
PE0_TX_N[0]
PCIEX3
O
O
I
M16
PE1_TX_P[5]
PCIEX3
N43
PE0_TX_N[12]
PCIEX3
O
M18
VSS
GND
N45
PE0_TX_N[14]
PCIEX3
O
M2
VSS
GND
N47
VTTA
PWR
M20
VCC
PWR
N49
QPI1_DTX_DN[19]
Intel® QPI
O
M22
VCC
PWR
N5
VSS
GND
M24
VSS
GND
N51
VSS
GND
M26
VCC
PWR
N53
QPI0_DTX_DN[4]
Intel® QPI
O
M28
VCC
PWR
N55
QPI1_DRX_DP[16]
Intel® QPI
I
®
O
M30
VSS
GND
N7
QPI2_DTX_DN[4]
Intel
M32
VCC
PWR
N9
VTTQ
PWR
90
QPI
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 3-2.
Land No.
Land Number (Sheet 45 of 50)
Land Name
Buffer Type Direction
P10
PE1_RX_P[4]
PCIEX3
P12
VSS
GND
I
Table 3-2.
Land No.
Land Number (Sheet 46 of 50)
Land Name
Buffer Type Direction
R39
PE0_TX_P[2]
PCIEX3
O
R41
PE0_TX_P[0]
PCIEX3
O
P14
PE1_TX_N[14]
PCIEX3
O
R43
PE0_TX_P[12]
PCIEX3
O
P16
PE1_TX_P[4]
PCIEX3
O
R45
PE0_TX_P[14]
PCIEX3
O
P18
VSS
GND
R47
VSS
GND
P20
VCC
PWR
R49
QPI1_DTX_DN[18]
Intel® QPI
P22
VCC
PWR
R5
VSS
GND
P24
VSS
GND
R51
VSS
GND
P26
VCC
PWR
R53
QPI0_DTX_DN[5]
Intel® QPI
O
P28
VCC
PWR
R55
QPI1_DRX_DP[15]
Intel® QPI
I
®
O
P30
VSS
GND
R7
QPI2_DTX_DN[5]
Intel
P32
VCC
PWR
R9
VSS
GND
P34
VSS
GND
P36
PE0_TX_N[4]
PCIEX3
QPI
T10
PE1_RX_P[3]
PCIEX3
O
T12
VTTA
PWR
O
I
P38
PE0_TX_N[6]
PCIEX3
O
T14
PE1_TX_N[15]
PCIEX3
O
P4
QPI2_DRX_DN[5]
Intel® QPI
I
T16
PE1_TX_P[3]
PCIEX3
O
P40
PE0_TX_N[1]
PCIEX3
O
T18
VSS
GND
P42
PE0_TX_N[11]
PCIEX3
O
T20
VCC
PWR
P44
PE0_TX_N[13]
PCIEX3
O
T22
VCC
PWR
P46
PE0_TX_N[15]
PCIEX3
O
T24
VSS
GND
P48
QPI1_DTX_DP[19]
Intel® QPI
O
T26
VCC
PWR
P50
VTTA
PWR
T28
VCC
PWR
T30
VSS
GND
T32
VCC
PWR
®
P52
QPI0_DTX_DP[4]
Intel
P54
VSS
GND
P56
QPI1_DRX_DN[15]
Intel®
I
T34
VSS
GND
P6
QPI2_DTX_DP[4]
Intel® QPI
O
T36
PE0_TX_P[4]
PCIEX3
QPI
QPI
O
O
P8
PIROM_ADDR[2]
I/O
T38
PE0_TX_P[6]
PCIEX3
O
R11
PE1_RX_N[3]
PCIEX3
I
T4
QPI2_DRX_DN[6]
Intel® QPI
I
R13
PE1_TX_P[14]
PCIEX3
O
T40
PE0_TX_P[1]
PCIEX3
O
R15
VSS
GND
T42
PE0_TX_P[11]
PCIEX3
O
R17
PE1_TX_N[3]
PCIEX3
T44
PE0_TX_P[13]
PCIEX3
O
R19
VSS
GND
T46
PE0_TX_P[15]
PCIEX3
O
O
R21
VCC
PWR
T48
QPI1_DTX_DP[18]
Intel®
QPI
O
R23
VSS
GND
T50
VSS
GND
R25
VCC
PWR
T52
QPI0_DTX_DP[5]
Intel® QPI
O
R27
VCC
PWR
T54
VSS
GND
R29
VSS
GND
T56
QPI1_DRX_DN[14]
Intel® QPI
I
R3
QPI2_DRX_DP[5]
Intel® QPI
T6
QPI2_DTX_DP[5]
Intel® QPI
O
R31
VCC
PWR
T8
VSS
GND
R33
VCC
PWR
U11
PE1_RX_N[2]
PCIEX3
I
R35
PE0_TX_P[3]
PCIEX3
O
U13
PE1_TX_P[15]
PCIEX3
O
R37
PE0_TX_P[5]
PCIEX3
O
U15
VSS
GND
I
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
91
Table 3-2.
Land No.
Land Number (Sheet 47 of 50)
Land Name
Buffer Type Direction
Table 3-2.
Land No.
Land Number (Sheet 48 of 50)
Land Name
Buffer Type Direction
U17
PE1_TX_N[2]
PCIEX3
V44
VTTA
PWR
U19
VSS
GND
V46
VTTA
PWR
U21
VCC
PWR
V48
QPI1_DTX_DP[17]
Intel® QPI
U23
VSS
GND
V50
VSS
GND
U25
VCC
PWR
V52
QPI0_DTX_DP[6]
Intel® QPI
O
U27
VCC
PWR
V54
SOCKET_ID[2]
CMOS
I
V56
QPI1_DRX_DN[13]
Intel®
V6
QPI2_DTX_DP[6]
Intel® QPI
O
O
U29
VSS
GND
U3
QPI2_DRX_DP[6]
Intel® QPI
U31
VCC
PWR
V8
VSS
GND
U33
VCC
PWR
W11
PE1_RX_N[1]
PCIEX3
I
U35
VSS
GND
W13
PE1_TX_P[12]
PCIEX3
O
U37
VSS
GND
W15
VSS
GND
U39
VSS
GND
W17
PE1_TX_N[1]
PCIEX3
U41
VSS
GND
W19
VSS
GND
U43
VSS
GND
W21
VCC
PWR
U45
VSS
GND
W23
VSS
GND
U47
VSS
GND
W25
VCC
PWR
U49
QPI1_DTX_DN[17]
Intel® QPI
W27
VCC
PWR
U5
VSS
GND
W29
VSS
GND
U51
VTTA
PWR
W3
QPI2_DRX_DP[7]
Intel® QPI
®
I
O
QPI
I
O
O
I
U53
QPI0_DTX_DN[6]
Intel
O
W31
VCC
PWR
U55
QPI1_DRX_DP[14]
Intel® QPI
I
W33
VCC
PWR
®
O
W35
PE0_RX_N[0]
PCIEX3
I
W37
PE0_RX_N[2]
PCIEX3
I
W39
PE0_RX_N[4]
PCIEX3
I
W41
PE0_RX_N[6]
PCIEX3
I
QPI
U7
QPI2_DTX_DN[6]
Intel
U9
VSS
GND
V10
PE1_RX_P[2]
PCIEX3
V12
VSS
GND
V14
PE1_TX_N[12]
PCIEX3
O
W43
PE0_RX_N[12]
PCIEX3
I
V16
PE1_TX_P[2]
PCIEX3
O
W45
PE0_RX_N[15]
PCIEX3
I
V18
VSS
GND
W47
RSVD
V20
VCC
PWR
W49
QPI1_DTX_DN[16]
Intel® QPI
O
QPI
I
V22
VCC
PWR
W5
VSS
GND
V24
VSS
GND
W51
VSS
GND
V26
VCC
PWR
W53
QPI0_DTX_DN[7]
Intel® QPI
O
V28
VCC
PWR
W55
QPI1_DRX_DP[13]
Intel® QPI
I
®
O
V30
VSS
GND
W7
QPI2_DTX_DN[7]
Intel
V32
VCC
PWR
W9
VTTQ
PWR
QPI
V34
VSS
GND
Y10
PE1_RX_P[1]
PCIEX3
V36
VTTA
PWR
Y12
VSS
GND
V38
VSS
GND
V4
QPI2_DRX_DN[7]
Intel® QPI
I
Y14
PE1_TX_N[11]
PCIEX3
O
Y16
PE1_TX_P[1]
PCIEX3
O
V40
VSS
GND
Y18
VSS
GND
V42
VTTA
PWR
Y20
VCC
PWR
92
I
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Table 3-2.
Land No.
Land Number (Sheet 49 of 50)
Land Name
Table 3-2.
Buffer Type Direction
Land No.
Land Number (Sheet 50 of 50)
Land Name
Buffer Type Direction
Y22
VCC
PWR
Y42
PE0_RX_N[7]
PCIEX3
I
Y24
VSS
GND
Y44
PE0_RX_N[13]
PCIEX3
I
Y26
VCC
PWR
Y46
PE0_RX_N[14]
PCIEX3
I
Y28
VCC
PWR
Y48
QPI1_DTX_DP[16]
Intel® QPI
O
Y30
VSS
GND
Y50
VTTA
PWR
Y32
VCC
PWR
Y52
QPI0_DTX_DP[7]
Intel® QPI
Y34
VSS
GND
Y36
PE0_RX_N[1]
PCIEX3
I
O
Y54
VSS
GND
Y56
QPI1_DRX_DN[12]
Intel® QPI
I
®
O
Y38
PE0_RX_N[3]
PCIEX3
I
Y6
QPI2_DTX_DP[7]
Y4
QPI2_DRX_DN[8]
Intel® QPI
I
Y8
PIROM_ADDR[0]
Y40
PE0_RX_N[5]
PCIEX3
I
Intel
QPI
I/O
§
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4
Signal Descriptions
This chapter describes the Intel® Xeon® E7 v3 processor signals. They are arranged
in functional groups according to their associated interface or category.
4.1
System Memory Interface
Table 4-1.
Memory Channel Signals
Signal Name
Description
MEM_SCL_C{3:0}
MEM_SDA_C{3:0}
SMBus clock for the dedicated interface to the serial presence detect (SPD)
and thermal sensors (TSoD) on the DIMMs.
VMSE{0/1/2/3}_CLK_N
VMSE{0/1/2/3}_CLK_P
Clocks to the memory buffer. This clock is used to capture the VCMD#
signals.
VMSE{0/1/2/3}_CMD[16:0]
Command signals.
VMSE{0/1/2/3}_DQ[63:0]
Data Bus. DDR3 Data bits.
VMSE{0/1/2/3}_DQS_P[8:0]
VMSE{0/1/2/3}_DQS_N[8:0]
Data strobes. Driven with edges in center of data, receive edges are aligned
with data edges.
VMSE{0/1/2/3}_ECC[7:0]
Check bits. An error correction code is driven along with data on these lines
for DIMMs that support that capability
VMSE{0/1/2/3}_ERR_N
Parity Error detected by Registered DIMM (one for each channel).
VMSE_PWR_OK
Power good input signal used to indicate that the power supply is stable for
memory channels.
4.2
PCI Express Based Interface Signals
Note:
PCI Express Ports 0 and 1 signals are receive and transmit differential pairs.
Table 4-2.
PCI Express* Port Signals
Signal Name
Description
PE{1:0}_RX_N[15:0]
PE{1:0}_RX_P[15:0]
Intel SMI2 Receive Data Input
PE{1:0}_TX_N[15:0]
PE{1:0}_TX_P[15:0]
Intel SMI2 Receive Data Output
4.3
DMI2/PCI Express Port Signals
Table 4-3.
DMI2 to Port 0 Signals
Signal Name
Description
DMI_RX_DN[3:0]
DMI_RX_DP[3:0]
DMI2 Receive Data Input
DMI_TX_DP[3:0]
DMI_TX_DN[3:0]
DMI2 Transmit Data Output
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4.4
Intel® QuickPath Interconnect Signals
Table 4-4.
Intel® QPI Port 0, 1, and 2 Signals
Signal Name
Description
QPI{2:0}_CLKRX_DN/DP
Reference Clock Differential Input. These pins provide the PLL reference
clock differential input. 100 MHz typ.
QPI{2:0}_CLKTX_DN/DP
Reference Clock Differential Output. These pins provide the PLL reference
clock differential input. 100 MHz typ.
QPI{2:0}_DRX_DN/DP[19:00]
Intel® QPI Receive data input.
QPI{2:0}_DTX_DN/DP[19:00]
Intel® QPI Transmit data output.
4.5
PECI Signal
Table 4-5.
PECI Signals
Signal Name
PECI
Description
PECI (Platform Environment Control Interface) is the serial sideband
interface to the processor and is used primarily for thermal, power and error
management. Details regarding the PECI electrical specifications, protocols
and functions can be found in the Platform Environment Control Interface
Specification.
4.6
System Reference Clock Signals
Table 4-6.
System Reference Clock (BCLK{0/1}) Signals
Signal Name
BCLK{0/1}_D[N/P]
Description
Reference Clock Differential input. These pins provide the PLL reference
clock differential input into the processor. 100 MHz typical BCLK0 is the
Intel® QPI reference clock (system clock) and BCLK1 is the PCI Express*
reference clock.
4.7
JTAG and TAP Signals
Table 4-7.
JTAG and TAP Signals (Sheet 1 of 2)
Signal Name
96
Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the processor
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
EAR_N
External Alignment of Reset, used to bring the processor up into a
deterministic state. This signal is pulled up on the die.
PRDY_N
Probe Mode Ready is a processor output used by debug tools to determine
processor debug readiness.
PREQ_N
Probe Mode Request is used by debug tools to request debug operation of
the processor.
TCK
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
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Table 4-7.
JTAG and TAP Signals (Sheet 2 of 2)
Signal Name
Description
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TMS
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must
be driven low during power on Reset.
4.8
Serial VID Interface (SVID) Signals
Table 4-8.
SVID Signals
Signal Name
SVIDALERT_N
Description
Serial VID alert.
SVIDCLK
Serial VID clock.
SVIDDATA
Serial VID data out.
SVID_IDLE_N
Output pin used to indicate when the SVID bus is IDLE. When asserted true
(low), it will assert for two SVID clock cycles. It guarantees that the SVID
bus will remain idle for two SVID clocks after it deasserts.
4.9
PIROM Signals
Table 4-9.
PIROM Signals
Signal Name
Description
PIROM_ADDR[2:0]
Address for PIROM (Processor Information ROM/OEM scratchpad).
SM_WP
WP (Write Protect) can be used to write protect the Scratch EEPROM. The
Scratch EEPROM is write-protected when this input is pulled high to
VCCSTBY33.
SMBCLK
The SMBus Clock (SMBCLK) signal is an input clock which is required for
operation of PIROM. This clock is driven by the SMBus controller and is
asynchronous to other clocks in the processor.
SMBDAT
The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This
signal provides the single-bit mechanism for transferring data between
SMBus devices.
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4.10
Processor Asynchronous Sideband and
Miscellaneous Signals
Table 4-10. Processor Asynchronous Sideband Signals (Sheet 1 of 2)
Signal Name
98
Description
CAT_ERR_N
Indicates that the system has experienced a fatal or catastrophic error and cannot continue
to operate. The processor will assert CAT_ERR_N for nonrecoverable machine check errors
and other internal unrecoverable errors. It is expected that every processor in the system
will wire-OR CAT_ERR_N for all processors. Since this is an
I/O land, external agents are allowed to assert this land which will cause the processor to
take a machine check exception.
On Intel® Xeon® E7 v3 processors, CAT_ERR_N is used for signaling the following types
of errors:
• Legacy MCERRs, CAT_ERR_N is asserted for 16 BCLKs, and samples it for 28 BCLKs to
determine if it is driven by an external agent indicating a fatal or uncorrected error.
• Legacy IERRs, CAT_ERR_N remains asserted until warm or cold reset.
ERROR_N[2:0]
Error status signals for integrated I/O (IIO) unit:
• 0 = Hardware correctable error (no operating system or firmware action necessary)
• 1 = Nonfatal error (operating system or firmware action required to contain and recover)
• 2 = Fatal error (system reset likely required to recover)
MEM_HOT_C01_N
MEM_HOT_C23_N
Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes
of operation – input and output mode.
Input mode is externally asserted and is used to detect external events such as VR_HOT#
from the memory voltage regulator and causes the processor to throttle the appropriate
memory channels.
Output mode is asserted by the processor and has two modes - level mode and duty cycle
mode. In level mode, the output indicates that a particular branch of memory subsystem is
hot. In duty cycle mode, the output indicates the hottest DIMM’s temperature by altering the
percentage of assertion (duty cycle).
MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used for
memory channels 2 & 3.
PMSYNC
Power Management Sync. A sideband signal to communicate power management status
from the Platform Controller Hub (PCH) to the processor.
PROCHOT_N
PROCHOT_N will go active when the processor temperature monitoring sensor detects that
the processor has reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit has been activated, if enabled. This signal can also be
driven to the processor to activate the Thermal Control Circuit.
If PROCHOT_N is asserted at the assertion of RESET_N, the processor will tristate its
outputs.
PWRGOOD
Power good input signal used to indicate that the VCC power supply is stable. The processor
requires this signal to be a clean indication that all processor clocks and power supplies are
stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state. PWRGOOD can
be driven inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. The signal must be supplied to the processor; it is
used to protect internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
RESET_N
Asserting the RESET_N signal resets the processor to a known state and invalidates its
internal caches without writing back any of their contents. Note some PLL, Intel QuickPath
Interconnect and error states are not effected by reset and only PWRGOOD forces them to a
known state.
SAFE_MODE_BOO
T
NC on production system. Pullup on die.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 4-10. Processor Asynchronous Sideband Signals (Sheet 2 of 2)
Signal Name
Description
THERMTRIP_N
Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical overtemperature conditions: One, the processor junction temperature has reached a level
beyond which permanent silicon damage may occur and Two, the system memory interface
has exceeded a critical temperature limit set by BIOS. Measurement of the processor
junction temperature is accomplished through multiple internal thermal sensors that are
monitored by the Digital Thermal Sensor (DTS). Simultaneously, the Power Control Unit
(PCU) monitors external memory temperatures via the dedicated SMBus interface to the
DIMMs. If any of the DIMMs exceed the BIOS defined limits, the PCU will signal
THERMTRIP_N to prevent damage to the DIMMs. Once activated, the processor will stop all
execution and shut down all PLLs. To further protect the processor, its core voltage (VCC),
VccIO_IN, VSA, VCCPLL, VVMSE supplies must be removed following the assertion of
THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is asserted.
While the assertion of the RESET_N signal may deassert THERMTRIP_N, if the processor's
junction temperature remains at or above the trip level, THERMTRIP_N will again be asserted
after RESET_N is deasserted. This signal can also be asserted if the system memory
interface has exceeded a critical temperature limit set by BIOS.
TSC_SYNC
Time stamp counter sync. Used to help align the time stamp counters of a newly onlined
socket to the time stamp counters of existing sockets.
Table 4-11. Miscellaneous Signals (Sheet 1 of 2)
Signal Name
Description
BIST_ENABLE
Input which allows the platform to enable or disable built-in self test (BIST) on the
processor. This signal is pulled up on the die. This strap is latched during all reset
modes.
BMCINIT
Indicates whether Service Processor Boot Mode should be used. Used in conjunction
with FRMAGENT and SOCKET_ID inputs.
• 0: No Service Processor boot. Example boot modes: Local PCH (this processor
hosts a legacy PCH with firmware behind it), Intel® QPI Link Boot (for processors
one hop away from the FW agent), or Intel® QPI Link Init (for processors more
than one hop away from the firmware agent).
• 1: Service Processor boot. In this mode of operation, the processor performs the
absolute minimum internal configuration and then waits for the Service Processor
to complete its initialization. The socket boots after receiving a “GO” handshake
signal via a firmware scratchpad register.
Needs 240 Ohm pull up/pull down (see boot mode).
DEBUG_EN_N
This pin is used to enable certain features used by ITP (e.g. probe mode). This pin
should be connected to the Intel ITP XDP_PRESENT_N# signal as a security measure
to validate user had physical access to the target platform Intel® Xeon® E7 v3
processors only. Needs 240 Ohm pull up.
EX_LEGACY_SKT
BMCINIT, FRMAGENT, LEGACY_SKT together determine the boot mode (SSP,
Intel® QPI Link boot modes, DCF boot), whether local or remote, whether the boot
PCH is attached, whether the socket is legacy and whether port0 is DMI or Intel SMI2
(Gen1/2). With one exception, this input configuration strap indicates to the processor
that it is the legacy socket. The legacy SKT must be strapped for NODE ID 0, via the
SKIT-ID pins. There is only 1 legacy SKT in a partition. Needs 240 Ohm pull up/pull
down (see boot mode).
FIVR_FAULT
Intel® Xeon® E7 v3 processor only. Indicates IVR-failure. Accompanied by THERMTRIP
# assertion. See the for proper connectivity.
FRMAGENT
This input configuration strap indicates to the processor that it is a bootable firmware
agent, i.e. that the firmware flash ROM is located behind the local PCH attached to the
processor via the DMI2 interface.This signal is pulled down on the die, refer to
Table 2-6 for details. Needs 240 Ohm pull up/pull down (see boot mode).
MSMI_N
MSMI_N is supported by the Intel® Xeon® E7 v3 processor and not supported by the
Intel® Xeon® E7 v2 family processor. When eMCA2 is not enabled, the MSMI_N pin is
not used. When eMCA2 is enabled in Intel® Xeon® E7 v3 processor, CATERR_N will no
longer be driven. The processor will instead drive MSMI_N. Platforms that enable
eMCA2, should monitor MSMI_N for uncorrectable and fatal events, and at a minimum,
reset the system on fatal events as is the case for CATERR_N.
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Table 4-11. Miscellaneous Signals (Sheet 2 of 2)
Signal Name
4.11
Description
PROC_ID[1:0]
These outputs can be used by the platform to determine if the installed processor is an
Intel® Xeon® E7 v3 processor or a future processor planned for the platform. In the
order of PROC_ID1, PROC_ID0, 00 refers to a Intel® Xeon® Processor E7 v2 Family
processor. 11 refers to a Intel® Xeon® E7 v3 processor. There is no connection to the
processor silicon for this signal.
NMI
Interrupt input. Active high. Indicates Non-Maskable Interrupt.
PM_FAST_WAKE_N
Intel® Xeon® E7 v3 processor Only
PWR_DEBUG_N
This is a debug signal for power debug using Intel ITP on Intel® Xeon® E7 v3
processor.
RSVD
RESERVED. All signals that are RSVD must be left unconnected on the board.
SKTOCC_N
SKTOCC_N (Socket occupied) will be pulled to ground in the processor package to
indicate that the processor is present. There is no connection to the processor silicon
for this signal. 4.7 kW pull-up to 3.3V
SOCKET_ID[2:0]
Socket identification configuration straps for establishing the PECI address, Intel® QPI
Node ID, and other settings. Each processor socket consumes one Node ID, and there
are 128 Home Agent tracker entries..
TEST[13:0]
Test[13:0] must be individually connected to an appropriate power source or ground
through a resistor for proper processor operation.
TXT_AGENT
Indicates the Intel® Trusted Execution Technology (Intel® TXT) Agent. This feature is
disabled by default via internal pull-down resistor. Strap to VCCIO on the legacy socket
only via 240 Ohm resistor to enable the feature.
TXT_PLTEN
Intel® TXT disable. This feature is enabled by default via an internal pull-up resistor.
Strap to 0 on all sockets to disable the feature. Use a zero ohm resistor if future
flexibility is desirable.
Processor Power and Ground Supplies
Table 4-12. Power and Ground Signals (Sheet 1 of 2)
Signal Name
100
Description
VCC
Variable power supply for the processor cores, last level caches (LLC), ring interface,
and home agent. It is provided by a VRM/EVRD12.5 compliant regulator for each CPU
socket. The valid voltage of this supply is indicated by the processor using the serial
voltage ID (SVID) interface.
VCC_SENSE
VSS_VCC_SENSE
VCC_SENSE and VSS_VCC_SENSE provide an isolated, low impedance connection to
the processor core power and ground. These signals must be connected to the voltage
regulator feedback circuit, which insures the output voltage (that is, processor
voltage) remains within specification.
VCC33
VCC33 supplies 3.3 V to PIROM/OEM Scratch ROM. This supply is required for PIROM
usage.
VCCIO_IN
Intel® Xeon® E7 v3 processors only power supply.
VCCPLL
Fixed power supply (1.8 V) for the processor phased lock loop (PLL). Also known as
VCCsfr.
VTTA and VTTQ
Combined fixed analog and quiet analog supply for VMSE, Power Control Unit (PCU),
miscellaneous IO, Direct Media Interface Gen 2 (DMI2) interface, Intel® QPI interface
and PCI Express* interface at VTT voltage (1.0 V). Not connected for Intel® Xeon® E7
v3 processors.
VTT_SENSE
VSS_VTT_SENSE
VTT_SENSE and VSS_VTT_SENSE provide an isolated, low impedance connection to
the processor I/O power plane. These signals must be connected to the voltage
regulator feedback circuit, which insures the output voltage (that is, processor
voltage) remains within specification.
VCCPECI
Power supply for PECI. Intel® Xeon® E7 v3 processor only.
VSA
Variable power supply for the processor system agent units. These include logic (nonI/O) for the integrated I/O controller, the integrated memory controller (iMC), and the
Intel® QPI agent.
Intel® Xeon® Processor E7-4800/8800 v3 Product Families
Datasheet Volume 1: EMTS, May 2015
Table 4-12. Power and Ground Signals (Sheet 2 of 2)
Signal Name
Description
VSA_SENSE
VSS_VSA_SENSE
VSA_SENSE and VSS_VSA_SENSE provide an isolated, low impedance connection to
the processor system agent (VSA) power plane. These signals must be connected to
the voltage regulator feedback circuit, which insures the output voltage (that is,
processor voltage) remains within specification.
VSS
Processor ground node.
VVMSE01 and
VVMSE23
1.35 V power supply for the processor system memory interface. VVMSE is generic for
VVMSE01, VVMSE23.
Note: The processor must be provided VVMSE011 and VVMSE23 for proper
operation, even in configurations where no memory is populated.
§
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5
Thermal Management
Specifications
5.1
Package Thermal Specifications
The Intel® Xeon® E7 v3 processor requires a thermal solution to maintain
temperatures within operating limits. Any attempt to operate the processor outside
these limits may result in permanent damage to the processor and potentially other
components within the system. Maintaining the proper thermal environment is key to
reliable, long-term system operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor integrated heat spreader (IHS). Typical system level thermal
solutions may consist of system fans combined with ducting and venting.
This section provides data necessary for developing a complete thermal solution.
Thermal Specifications
To allow optimal operation and long-term reliability of Intel processor-based systems,
the processor must remain within the minimum and maximum case temperature
(TCASE) specifications as defined by the applicable thermal profile. Thermal solutions
not designed to provide sufficient thermal capability may affect the long-term reliability
of the processor and system.
The Intel® Xeon® E7 v3 processors implement a methodology for managing
processor temperatures which is intended to support acoustic noise reduction through
fan speed control and to assure processor reliability. Selection of the appropriate fan
speed is based on the relative temperature data reported by the processor’s Platform
Environment Control Interface (PECI).
If the DTS value is less than TCONTROL, then the case temperature is permitted to
exceed the Thermal Profile, but the DTS value must remain at or below TCONTROL.
For TCASE implementations, if DTS is greater than TCONTROL, then the case
temperature must meet the TCASE based Thermal Profiles.
For DTS implementations:
• TCASE thermal profile can be ignored during processor run time.
• If DTS is greater than Tcontrol then follow DTS thermal profile specifications for fan
speed optimization.
The temperature reported over PECI is always a negative value and represents a delta
below the onset of thermal control circuit (TCC) activation, as indicated by
PROCHOT_N. Systems that implement fan speed control must be designed to use this
data. Systems that do not alter the fan speed need to guarantee the case temperature
meets the thermal profile specifications.
With single thermal profile, it is expected that the Thermal Control Circuit (TCC) would
be activated for very brief periods of time when running the most power intensive
applications. Using a thermal solution that does not meet the thermal profile violates
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the thermal specifications and may result in permanent damage to the processor. The
upper point of the thermal profile consists of the Thermal Design Power (TDP) and the
associated TCASE value.
(x = TDP and y = TCASE_MAX @ TDP) represents a thermal solution design
point. In actuality the processor case temperature will not reach this value due
to TCC activation.
Intel recommends that complete thermal solution designs target the Thermal Design
Power (TDP). The Adaptive Thermal Monitor feature is intended to help protect the
processor in the event that an application exceeds the TDP recommendation for a
sustained time period. To ensure maximum flexibility for future requirements, systems
should be designed to the Flexible Motherboard (FMB) guidelines, even if a processor
with lower power dissipation is currently planned. The Adaptive Thermal Monitor
feature must be enabled for the processor to remain within its specifications.
5.1.1
TCASE and DTS Based Thermal Specifications
To simplify compliance to thermal specifications at processor run time, the Intel®
Xeon® E7 v3 processor has added a Digital Thermal Sensor (DTS) based thermal
specification. Digital Thermal Sensor reports a relative die temperature as an offset
from TCC activation temperature. TCASE thermal based specifications are used for heat
sink sizing and DTS based specs are used for acoustic and fan speed optimizations. For
the Intel® Xeon® E7 v3 processor family, firmware (for example, BMC or other
platform management devices) will have DTS based specifications for all SKUs
programmed by the customer. SKUs may share TCASE thermal profiles but they will
have separate TDTS based thermal profiles.
The processor fan speed control is managed by comparing DTS thermal readings via
PECI against the processor-specific fan speed control reference point, or Tcontrol. Both
Tcontrol and DTS thermal readings are accessible via the processor PECI client. At a
one time readout only, the Fan Speed Control firmware will read the following:
• IA32_TEMPERATURE_TARGET MSR
• Tcontrol via PECI - RdPkgConfig()
• TDP via PECI - RdPkgConfig()
• Core Count - RdPCIConfigLocal()
DTS PECI commands will also support DTS temperature data readings.
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5.1.2
Intel® Xeon® E7 v3 Processor Thermal Profiles
Table 5-1.
Intel® Xeon® E7 v3 Processor SKU Summary
Thermal Profile
TDP SKUs
Note:
Tcase
DTS
165 W
Figure 5-1
Figure 5-2, Figure 5-3
150 W
Figure 5-6
Figure 5-5
140 W
Figure 5-6
Figure 5-5
115 W
Figure 5-9
Figure 5-10, Figure 5-11
SKUs are subject to change. Please contact your Intel Field Representative to obtain the latest SKU
information.
5.1.2.1
165 W Thermal Specifications
Table 5-2.
Tcase: 165 W Thermal Specifications
Thermal Design Power
Minimum TCASE
Maximum TCASE (°C)
Notes
165 W
0°C
See Figure 5-1 and Table 5-3.
1 2 3 4 5
, , , ,
Notes:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the
processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC.
2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum TCASE.
3. These specifications are based on post silicon measurements, which will be updated as further characterization
data becomes available.
4. Power specifications are defined at all VIDs. The Intel® Xeon® E7 v3 processor may be delivered under
multiple VIDs for each frequency.
5. FMB (flexible motherboard) guidelines provide a design target for meeting all planned processor frequency
requirements.
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105
Figure 5-1.
Tcase: 165 W Thermal Profile
Notes:
1.
Please refer to Table 5-3 for discrete points that constitute this thermal profile.
Figure 5-2.
DTS: 165 W Thermal Profile For 10 Core Processors
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-3 for discrete points that constitute the thermal profile.
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Figure 5-3.
DTS: 165 W Thermal Profile For 16 to 18 Core Processors
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-3 for discrete points that constitute the thermal profile.
Note:
Table 5-3.
165 W Thermal Profile Table (Sheet 1 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 10c DTS (°C)
Maximum 12c-18c DTS (°C)
0
49.0
49.0
49.0
5
49.9
50.5
50.3
10
50.8
52.0
51.5
15
51.8
53.5
52.8
20
52.7
54.9
54.1
25
53.6
56.4
55.4
30
54.5
57.9
56.6
35
55.5
59.4
57.9
40
56.4
60.9
59.2
45
57.3
62.4
60.5
50
58.2
63.8
61.7
55
59.2
65.3
63.0
60
60.1
66.8
64.3
65
61.0
68.3
65.5
70
61.9
69.8
66.8
75
62.8
71.3
68.1
80
63.8
72.8
69.4
85
64.7
74.2
70.6
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107
Table 5-3.
165 W Thermal Profile Table (Sheet 2 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 10c DTS (°C)
Maximum 12c-18c DTS (°C)
90
65.6
75.7
71.9
95
66.5
77.2
73.2
100
67.4
78.7
74.5
105
68.3
80.2
75.7
110
69.2
81.7
77.0
115
70.1
83.2
78.3
120
71.1
84.6
79.5
125
72.0
86.1
80.8
130
72.9
87.6
82.1
135
73.8
89.1
83.4
140
74.7
90.6
84.6
145
75.7
92.1
85.9
150
76.6
93.5
87.2
155
77.5
95.0
88.5
160
78.4
96.5
89.7
165
79.3
98.0
91.0
5.1.2.2
150 W Thermal Specifications
Table 5-4.
Tcase: 150 W Thermal Specifications
Thermal Design Power
Minimum TCASE
Maximum TCASE (°C)
150 W
0°C
See Figure 5-1 and Table 5-3.
Notes
1
, 2, 3, 4, 5
Notes:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the
processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC.
2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum TCASE.
3. These specifications are based on post silicon measurements, which will be updated as further
characterization data becomes available.
4. Power specifications are defined at all VIDs. The Intel® Xeon® E7 v3 processor may be delivered under
multiple VIDs for each frequency.
5. FMB (flexible motherboard) guidelines provide a design target for meeting all planned processor frequency
requirements.
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Figure 5-4.
Tcase: 150 W Thermal Profile
Notes:
1.
Please refer to Table 5-3 for discrete points that constitute this thermal profile.
Figure 5-5.
DTS: 150 W Thermal Profile
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-3 for discrete points that constitute the thermal profile.
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109
Table 5-5.
150 W Thermal Profile Table
Power (W)
Maximum TCASE (°C)
Maximum DTS (°C)
0
49.0
49
5
49.9
50.2
10
50.8
51.4
15
51.8
52.6
20
52.7
53.8
25
53.6
55
30
54.5
56.2
35
55.4
57.4
40
56.4
58.6
45
57.3
59.8
50
58.2
61
55
59.1
62.2
60
60.0
63.4
65
61.0
64.6
70
61.9
65.8
75
62.8
67
80
63.7
68.2
85
64.6
69.4
90
65.6
70.6
95
66.5
71.8
100
67.4
73
105
68.3
74.2
110
69.2
75.4
115
70.2
76.6
120
71.1
77.8
125
72.0
79
130
72.9
80.2
135
73.8
81.4
140
74.8
82.6
145
75.7
83.8
150
76.6
85
5.1.2.3
140 W Thermal Specifications
Table 5-6.
Tcase: 140 W Thermal Specifications
Thermal Design Power
Minimum TCASE
Maximum TCASE (°C)
140 W
0°C
See Figure 5-6 and Table 5-7.
Notes
1
, 2, 3, 4, 5
Notes:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the
processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC.
2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum TCASE.
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3. These specifications are based on post silicon measurements, which will be updated as further characterization
data becomes available.
4. Power specifications are defined at all VIDs. The Intel® Xeon® E7 v3 processor may be delivered under
multiple VIDs for each frequency.
5. FMB (flexible motherboard) guidelines provide a design target for meeting all planned processor frequency
requirements.
Figure 5-6.
Tcase: 140 W Thermal Profile
Notes:
1.
Please refer to Table 5-7 for discrete points that constitute this thermal profile.
Figure 5-7.
DTS: 140 W Thermal Profile For 16 to 18 Core Processors
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111
Figure 5-8.
DTS: 140 W Thermal Profile for 4 Core Processors
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-7 for discrete points that constitute the thermal profile.
Refer to the Ivy Bridge-EX
Notes: Processor Thermal/Mechanical Design Guide for system and environmental implementation details.
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-7 for discrete points that constitute the thermal profile.
3.
Refer to the Ivy Bridge-EX Processor Thermal/Mechanical Design Guide for system and environmental
implementation details.
Table 5-7.
112
140 W Thermal Profile Table (Sheet 1 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 4 Core
DTS(°C)
Maximum 16-18 Core
DTS(°C)
0
49.0
49.0
49.0
5
49.9
50.6
50.3
10
50.8
52.3
51.5
15
51.8
53.9
52.8
20
52.7
55.6
54.0
25
53.6
57.2
55.3
30
54.5
58.9
56.5
35
55.5
60.5
57.8
40
56.4
62.1
59.0
45
57.3
63.8
60.3
50
58.2
65.4
61.5
55
59.2
67.1
62.8
60
60.1
68.7
64.0
65
61.0
70.4
65.3
70
61.9
72.0
66.5
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Table 5-7.
140 W Thermal Profile Table (Sheet 2 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 4 Core
DTS(°C)
Maximum 16-18 Core
DTS(°C)
75
62.8
73.6
67.8
80
63.8
75.3
69.0
85
64.7
76.9
70.3
90
65.6
78.6
71.5
95
66.5
80.2
72.8
100
67.5
81.9
74.0
105
68.4
83.5
75.3
110
69.3
85.1
76.5
115
70.2
86.8
77.8
120
71.2
88.4
79.0
125
72.1
90.1
80.3
130
73.0
91.7
81.5
135
73.9
93.4
82.8
140
74.8
95
84
5.1.2.4
115 W Thermal Specifications
Table 5-8.
Tcase: 115 W Thermal Specifications
Thermal Design Power
Minimum TCASE
115 W
0°C
Maximum TCASE (°C)
See Figure 5-9 and Table 5-9.
Notes
1
,
2
, 3, 4, 5
Notes:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the
processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC.
2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum TCASE.
3. These specifications are based on post silicon measurements, which will be updated as further
characterization data becomes available.
4. Power specifications are defined at all VIDs. The Intel® Xeon® E7 v3 processor may be delivered under
multiple VIDs for each frequency.
5. FMB (flexible motherboard) guidelines provide a design target for meeting all planned processor frequency
requirements.
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113
Figure 5-9.
Tcase: 115 W Thermal Profile
Notes:
1.
Please refer to Table 5-9 for discrete points that constitute the thermal profile.
2.
Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Ivy BridgeEX Processor Thermal/Mechanical Design Guide for system and environmental implementation details.
Figure 5-10. DTS: 115 W Thermal Profile for 8 Core Processors
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-9 for discrete points that constitute this thermal profile.
3.
Refer to the Ivy Bridge-EX Processor Thermal/Mechanical Design Guide for system and environmental
implementation details.
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Figure 5-11. DTS: 115 W Thermal Profile for 10 to 18 Core Processors
Notes:
1.
Some processor units may be tested to lower TDP and the IA32_TEMPERATURE_TARGET MSR will be
aligned to that lower TDP.
2.
Please refer to Table 5-9 for discrete points that constitute this thermal profile.
3.
Refer to the Ivy Bridge-EX Processor Thermal/Mechanical Design Guide for system and environmental
implementation details.
§
Table 5-9.
115 W Thermal Profile Table (Sheet 1 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 8c DTS (°C)
Maximum 10c-18c DTS (°C)
0
49.0
49.0
49.0
5
49.9
50.2
50.1
10
50.8
51.4
51.3
15
51.7
52.7
52.4
20
52.6
53.9
53.5
25
53.5
55.1
54.7
30
54.4
56.3
55.8
35
55.3
57.5
56.9
40
56.2
58.7
58.0
45
57.1
60.0
59.2
50
58.0
61.2
60.3
55
59.0
62.4
61.4
60
59.9
63.6
62.6
65
60.8
64.8
63.7
70
61.7
66.0
64.8
75
62.6
67.3
66.0
80
63.5
68.5
67.1
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Table 5-9.
5.1.3
115 W Thermal Profile Table (Sheet 2 of 2)
Power (W)
Maximum TCASE (°C)
Maximum 8c DTS (°C)
Maximum 10c-18c DTS (°C)
85
64.4
69.7
68.2
90
65.3
70.9
69.3
95
66.2
72.1
70.5
100
67.1
73.3
71.6
105
68.0
74.6
72.7
110
68.9
75.8
73.9
115
69.8
77.0
75.0
Thermal Metrology
The minimum and maximum case temperatures (TCASE) specified in Table 5-3 through
Table 5-9 are measured at the geometric top center of the processor integrated heat
spreader (IHS). Figure 5-12 illustrates the location where TCASE temperature
measurements should be made. For detailed guidelines on temperature measurement
methodology, refer to the Ivy Bridge-EX Processor Thermal/Mechanical Design Guide.
Figure 5-12. Case Temperature (TCASE) Measurement Location
Notes:
1.
Figure is not to scale and is for reference only.
2.
See the processor package mechanical drawing for the dimensions of the features.
§
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6
PIROM
6.1
Processor Information ROM
The Processor Information ROM (PIROM) is a memory device located on the processor
and is accessible via the System Management Bus (SMBus) which contains information
regarding the processor’s features. These features are listed in Table 6-1.
The PIROM resides in the lower half of the memory component (addresses 00 to 7Fh),
which is permanently write-protected by Intel. The upper half comprises the Scratch
EEPROM (addresses 80 to FFh).
Table 6-1.
Offset/
Section
Processor Information ROM Table (Sheet 1 of 3)
# of
Bits
Function
Notes
Examples
Header
00h
01-02h
8
16
Data Format Revision
Two 4-bit hex digits
Start with 00h
PIROM Size
Size in bytes (MSB first)
Use a decimal to hex transfer; 128
bytes = 0080h:
03h
8
Processor Data Address
Byte pointer, 00h if not present
0Eh
04h
8
Processor Core Data Address
Byte pointer, 00h if not present
1Bh
05h
8
Processor Uncore Data Address
Byte pointer, 00h if not present
2A
06h
8
Package Data Address
Byte pointer, 00h if not present
4Ch
07h
8
Part Number Data Address
Byte pointer, 00h if not present
54h
08h
8
Thermal Reference Data Address
Byte pointer, 00h if not present
66h
09h
8
Feature Data Address
Byte pointer, 00h if not present
6Ch
0Ah
8
Other Data Address
Byte pointer, 00h if not present
77h
Reserved
Reserved for future use
000000h
0B-0Dh
16
Processor Data
0E to 13h
S-spec/QDF Number
Six 8-bit ASCII characters
Sample/Production
First seven bits reserved
0b = Sample, 1b = Production
00000001 = production
6
2
Number of Cores
Number of Threads
[7:2] = Number of cores
[1:0] = Threads per core
00111110 = 15 cores with 2
threads each
16 to 17h
16
System Clock Speed
Four 4-bit hex digits (Mhz)
0100h = 100MHz1
18 to 1A
16
Reserved
Reserved for future use
000000h
14h
15
48
7/1
Processor Core Data
1B to 1Ch
16
CPUID
Four 4-bit hex digits
1D to 1Eh
16
Reserved
Reserved for future use
0000h
Maximum P1 Core Frequency
Non-Intel Turbo Boost Technology
(Mhz)
Four 4-bit hex digits (Mhz)
2500h = 2500 MHz1
Maximum P0 Core Frequency
Intel Turbo Boost Technology
(Mhz)
Four 4-bit hex digits (Mhz)
2800h = 2800 MHz1
Maximum Core Voltage ID
Four 4-bit hex digits (mV)
1350h = 1350 mV1
1F to 20h
16
21 to 22h
16
23 to 24h
16
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Table 6-1.
Processor Information ROM Table (Sheet 2 of 3)
Offset/
Section
# of
Bits
25 to 26h
16
27h
28h
29h
8
8
8
Function
Notes
Examples
Minimum Core Voltage ID
Four 4-bit hex digits (mV)
0800h = 800 mV1
Core Voltage Tolerance, High
Allowable positive DC shift
Two 4-bit hex digits (mV)
15h = 15mV1
Core Voltage Tolerance, Low
Allowable negative DC shift
Two 4-bit hex digits (mV)
15h = 15mV1
Reserved
Reserved for future use
00h
Processor Uncore Data
16
Maximum Intel® QPI Link
Transfer Rate
Four 4-bit hex digits (in MT/s)
9600h = 9.600 GT/s1
16
Maximum Intel PCIe Link Transfer
Rate
Four 4-bit hex digits (in MT/s)
8000h = 8000 GT/s1
32
Intel® QPI Version Number
Four 8-bit ASCII Characters
01.1
Intel TXT
First seven bits reserved
00000001 = supported
00000000 = unsupported
16
Maximum Intel SMI2
Performance Transfer Rate
Four 4-bit hex digits (in MT/s)
2666h = 2.666GT/s1
16
Maximum Intel SMI2 Lock Step
Transfer Rate
Four 4-bit hex digits (in MT/s)
1600h = 1.600GT/s1
37 to 38h
16
Maximum VSA VID
Four 4-bit hex digits (mV)
1200h = 1200 mV1
39 to 3Ah
16
Minimum VSA VID
Four 4-bit hex digits (mV)
0600h = 600 mV1
3B to 3Eh
32
Reserved
Reserved for future use
00000000h
3F to 40h
16
2A to 2Bh
2C to 2Dh
2E to 31h
32h
33 to 34h
35 to 36h
41 to 42h
7/1
16
L2 Cache Size
Decimal (Kb) Per CPU Core
0100h = 256Kb
L3 Cache Size
Decimal (Kb)
6000h = 24576Kb, 4800h =
18432Kb, 3000h = 12288Kb
43 to 44
16
VVMSE Nominal Voltage
Four 4-bit hex digits (mV)
1350h = 1350 mV1
45 to 46h
16
VccIO_IN Nominal Voltage
Four 4-bit hex digits (mV)
1000h = 1000 mV1
47 to 4Bh
40
Reserved
Reserved for future use
0000000000h
Package
4C to 4Fh
32
Package Revision
Four 8-bit ASCII characters
01.0
50h
6/2
Substrate Revision Software ID
First 6 bits reserved
000000**
51 to 53h
24
Reserved
Reserved for future use
000000h
Part Numbers
54 to 5Ah
56
Processor Family Number
Seven 8-bit ASCII characters
CM80645
5B to 62h
64
Processor SKU Number
Seven 8-bit ASCII characters
1272834
63 to 65h
24
Reserved
Reserved for future use
000000h
Thermal Reference
66h
67h
68h
69 to 6Ah
6Bh
118
8
Recommended THERMALERT_N
assertion threshold value
MSB is Reserved
0h = 0C1
8
Thermal calibration offset value
MSB is Reserved
0h = 0C1
8
TCASE Maximum
Maximum case temperature
Two 4-bit hex digits (mV)
69h = 69°C1
Thermal Design Power
Four 4-bit hex digits (in Watts)
0130h = 130 Watts1
Reserved
Reserved for future use
00h
16
8
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Table 6-1.
Offset/
Section
Processor Information ROM Table (Sheet 3 of 3)
# of
Bits
Function
Notes
Examples
Features
6C to 6Fh
70h
71h
72
73h
74 to 75h
76h
32
8
8
6/2
4/4
16
8
Processor Core Feature Flags
From CPUID function 1, EDX
contents
4387FBFFh
Processor Feature Flags
Eight features - Binary
1 indicates functional feature
10001101
Additional Processor Feature
Flags
Eight additional features - Binary
1 indicates functional feature
01110101
Multiprocessor Support
00b = UP, 01b = DP, 10b = S2S,
11b = MP/SMS
00000011 = MP/SMS
Number of Devices in TAP Chain
First four bits reserved
One 4-bit hex digit - Bits
*0h1
Reserved
Reserved for future use
0000h
Static Checksum
1 byte checksum
Add up by byte and take 2’s
complement.
PPIN
Coded binary
N/A
PPIN Checksum
1 byte checksum
Add up by byte and take 2’s
complement.
Other
77 to 7Eh
7Fh
64
8
Notes:
1. Uses Binary Coded Decimal (BCD) translation.
6.2
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which
may be used for other data at the system or processor vendor’s discretion. The data in
this EEPROM, once programmed, can be write-protected by asserting the active-high
SM_WP signal. This signal has a weak pull-down (10 kohm) to allow the EEPROM to be
programmed in systems with no implementation of this signal. The Scratch EEPROM
resides in the upper half of the memory component (addresses 80 - FFh). The lower
half comprises the Processor Information ROM (addresses 00 - 7Fh), which is
permanently write-protected by Intel.
6.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands. Table 6-2 illustrates the Read Byte command. Table 6-3 illustrates the
Write Byte command.
In the tables, ‘S’ represents a SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
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The SMBus host controller should transmit 8 bits with the most significant bit indicating
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
Table 6-2.
Read Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 6-3.
6.4
Write Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
SMBus Memory Component Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the
SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the
memory component. These address pins are pulled down weakly (10 k) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be
generated by an SMBus master.
Table 6-4 describes the address pin connections and how they affect the addressing of
the memory component.
Table 6-4.
Memory Device SMBus Addressing
Upper Address1
Device Select
R/W
Address (Hex)
Bits 7-4
SKTID[2]
SKTID[1] Bit 2
SKTID[0] Bit 1
Bit 0
A0h/A1h
10100
10100
0
0
X
A2h/A3h
10100
10100
0
1
X
A4h/A5h
10100
10100
1
0
X
A6h/A7h
10100
10100
1
1
X
Notes:
1. This addressing scheme will support up to four processors on a single SMBus.
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6.5
Managing Data in the PIROM
The PIROM consists of the following sections:
• Header
• Processor Data
• Processor Core Data
• Processor Uncore Data
• Cache Data
• Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
Details on each of these sections are described below.
Note:
Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not
rely on this model.
6.5.1
Header
To maintain backward compatibility, the Header defines the starting address for each
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
Example: Code looking for the processor uncore data of a processor would read offset
05h to find a value of 29. 29 is the first address within the 'Processor Uncore Data'
section of the PIROM.
6.5.1.1
DFR: Data Format Revision
This location identifies the data format revision of the PIROM data structure. Writes to
this register have no effect.
Offset:
00h
Bit
Description
Data Format Revision
The data format revision is used whenever fields within the PIROM are redefined. The initial
definition will begin at a value of 1. If a field, or bit assignment within a field, is changed such that
software needs to discern between the old and new definition, then the data format revision field will
be incremented.
7:0
00h:Reserved
01h:Initial definition
02h:Second revision
03h:Third revision
04h:Fourth revision
05h:Fifth revision (Defined by this document)
06h-FFh: Reserved
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6.5.1.2
PISIZE: PIROM Size
This location identifies the PIROM size. Writes to this register have no effect.
Offset:
01h-02h
Bit
15:0
6.5.1.3
Description
PIROM Size
The PIROM size provides the size of the device in hex bytes. The MSB is at location 01h; the LSB is
at location 02h.
0000h - 007Fh: Reserved
0080h: 128 byte PIROM size
0081- FFFFh: Reserved
PDA: Processor Data Address
This location provides the offset to the Processor Data Section. Writes to this register
have no effect.
Offset:
03h
Bit
Description
Processor Data Address
Byte pointer to the Processor Data section
7:0
6.5.1.4
00h: Processor Data section not present
01h - 0Dh: Reserved
0Eh: Processor Data section pointer value
0Fh-FFh: Reserved
PCDA: Processor Core Data Address
This location provides the offset to the Processor Core Data Section. Writes to this
register have no effect.
Offset:
Bit
04h
Description
Processor Core Data Address
Byte pointer to the Processor Core Data section
7:0
122
00h: Processor Core Data section not present
01h - 09h: Reserved
1Ah: Processor Core Data section pointer value
1Bh-FFh: Reserved
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6.5.1.5
PUDA: Processor Uncore Data Address
This location provides the offset to the Processor Uncore Data Section. Writes to this
register have no effect.
Offset:
05h
Bit
Description
Processor Uncore Data Address
Byte pointer to the Processor Uncore Data section
7:0
6.5.1.6
00h: Processor Uncore Data section not present
01h - 28h: Reserved
29h: Processor Uncore Data section pointer value
2Ah-FFh: Reserved
PDA: Package Data Address
This location provides the offset to the Package Data Section. Writes to this register
have no effect.
Offset:
06h
Bit
Description
Package Data Address
Byte pointer to the Package Data section
7:0
6.5.1.7
00h: Package Data section not present
01h - 4Ah: Reserved
4Bh: Package Data section pointer value
4Ch-FFh: Reserved
PNDA: Part Number Data Address
This location provides the offset to the Part Number Data Section. Writes to this
register have no effect.
Offset:
07h
Bit
Description
Part Number Data Address
Byte pointer to the Part Number Data section
7:0
00h: Part Number Data section not present
01h - 52h: Reserved
53h: Part Number Data section pointer value
54h-FFh: Reserved
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6.5.1.8
TRDA: Thermal Reference Data Address
This location provides the offset to the Thermal Reference Data Section. Writes to this
register have no effect.
Offset:
08h
Bit
Description
Thermal Reference Data Address
Byte pointer to the Thermal Reference Data section
7:0
6.5.1.9
00h: Thermal Reference Data section not present
01h - 64h: Reserved
65h: Thermal Reference Data section pointer value
66h-FFh: Reserved
FDA: Feature Data Address
This location provides the offset to the Feature Data Section. Writes to this register
have no effect.
Offset:
09h
Bit
Description
Feature Data Address
Byte pointer to the Feature Data section
7:0
6.5.1.10
00h: Feature Data section not present
01h - 6Ah: Reserved
6Bh: Feature Data section pointer value
6Ch-FFh: Reserved
ODA: Other Data Address
This location provides the offset to the Other Data Section. Writes to this register have
no effect.
Offset:
0Ah
Bit
Description
Other Data Address
Byte pointer to the Other Data section
7:0
6.5.1.11
00h: Other Data section not present
01h - 78h: Reserved
79h: Other Data section pointer value
7Ah- FFh: Reserved
RES1: Reserved 1
This location is reserved. Writes to this register have no effect.
Offset:
0Bh-0Dh
Bit
23:0
124
Description
RESERVED
000000h-FFFFFFh: Reserved
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6.5.2
Processor Data
This section contains three pieces of data:
• The S-spec/QDF of the part in ASCII format.
• (1) 2-bit field to declare if the part is a preproduction sample or a production unit.
• The system bus speed in BCD format
6.5.2.1
SQNUM: S-Spec QDF Number
This location provides the S-Spec or QDF number of the processor. The S-spec/QDF
field is six ASCII characters wide and is programmed with the same S-spec/QDF value
as marked on the processor. If the value is less than six characters in length, leading
spaces (20h) are programmed in this field. Writes to this register have no effect.
For example, a processor with a QDF mark of QWFZ contains the following in field 0E13h: 20h, 20h, 51h, 57h, 46h, 5Ah. This data consists of two blanks at 0Eh and 0Fh
followed by the ASCII codes for QEU5 in locations 10 - 13h.
Offset:
0Eh-13h
Bit
47:40
Description
Character 6
S-Spec or QDF character or 20h
00h-0FFh: ASCII character
39:32
Character 5
S-Spec or QDF character or 20h
00h-0FFh: ASCII character
31:24
Character 4
S-Spec or QDF character
00h-0FFh: ASCII character
23:16
Character 3
S-Spec or QDF character
00h-0FFh: ASCII character
15:8
Character 2
S-Spec or QDF character
00h-0FFh: ASCII character
7:0
Character 1
S-Spec or QDF character
00h-0FFh: ASCII character
6.5.2.2
SAMPROD: Sample/Production
This location contains the sample/production field, which is a two-bit field and is LSB
aligned. All Q-spec material will use a value of 00b. All S-spec material will use a value
of 01b. All other values are reserved. Writes to this register have no effect.
For example, a processor with a Qxxx mark (engineering sample) will have offset 14h
set to 00h. A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.
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Offset:
14h
Bit
7:2
Description
RESERVED
000000b-111111b: Reserved
Sample/Production
Sample or Production indictor
1:0
6.5.2.3
00b: Sample
01b: Production
10b-11b: Reserved
Processor Thread and Core Information
This location contains information regarding the number of cores and threads on the
processor. Writes to this register have no effect. Data format is binary.
For example, the Intel® Xeon® E7 v3 processor has up to 18 cores and two threads
per core.
Offset:
15h
Bit
6.5.2.4
Description
7:2
Number of cores
1:0
Number of threads per core
SCS: System Clock Speed
This location contains the system clock frequency information. Systems may need to
read this offset to decide if all installed processors support the same system clock
speed. The data provided is the speed, rounded to a whole number, and reflected in
binary coded decimal. Writes to this register have no effect.
For example, a processor with system bus speed of 100 MHz will have a value
of 0100h.
Offset:
16h-17h
Bit
15:0
6.5.2.5
Description
System Bus Speed
0000h-FFFFh: MHz
RES2: Reserved 2
This location is reserved. Writes to this register have no effect.
Offset:
18h-2Ah
Bit
23:0
126
Description
RESERVED
000000h-FFFFFFh: Reserved
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6.5.3
Processor Core Data
This section contains silicon-related data relevant to the processor cores.
6.5.3.1
CPUID: CPUID
This location contains the CPUID, Processor Type, Family, Model and Stepping. The
CPUID field is a copy of the results in EAX[15:0] from Function 1 of the CPUID
instruction. Writes to this register have no effect. Data format is hexadecimal.
Offset:
1Bh-1Ch
Bit
15:13
12:12
11:8
7:4
3:0
6.5.3.2
Description
Reserved
00b-11b: Reserved
Processor Type
0b-1b: Processor Type
Processor Family
0h-Fh: Processor Family
Processor Model
0h-Fh: Processor Model
Processor Stepping
0h-Fh: Processor Stepping
RES3: Reserved 3
This locations are reserved. Writes to this register have no effect.
Offset:
1Dh-1Eh
Bit
15:0
6.5.3.3
Description
RESERVED
0000h-FFFFh: Reserved
MP1CF: Maximum P1 Core Frequency
This location contains the maximum non-Intel Turbo Boost Technology core frequency
for the processor. The frequency should equate to the markings on the processor
and/or the QDF/S-spec speed even if the parts are not limited or locked to the intended
speed. Format of this field is in megahertz, rounded to a whole number, and encoded in
binary coded decimal. Writes to this register have no effect.
Example: A 2.666 GHz processor will have a value of 2666h.
Offset:
1F-20h
Bit
15:0
Description
Maximum P1 Core Frequency
0000h-FFFFh: MHz
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6.5.3.4
MP0CF: Maximum P0 Core Frequency
This location contains the maximum Intel Turbo Boost Technology core frequency for
the processor. This is the maximum intended speed for the part under any functional
conditions. Format of this field is in megahertz, rounded to a whole number, and
encoded in binary coded decimal. Writes to this register have no effect.
Example: A processor with a maximum Intel Turbo Boost Technology frequency of
2.666 GHz will have a value of 2666h.
Offset:
21h-22h
Bit
15:0
6.5.3.5
Description
Maximum P0 Core Frequency
0000h-FFFFh: MHz
MAXVID: Maximum Core VID
This location contains the maximum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in
millivolts and is reflected in binary coded decimal. Writes to this register have no effect.
Example: A voltage of 1.350 V maximum core VID would contain 1350h.
Offset:
23h-24h
Bit
15:0
6.5.3.6
Description
Maximum Core VID
0000h-FFFFh: mV
MINVID: Minimum Core VID
This location contains the Minimum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and
is reflected in binary coded decimal. Writes to this register have no effect.
Example: A voltage of 1.000 V maximum core VID would contain 1000h.
Offset:
25h-26h
Bit
15:0
128
Description
Maximum Core VID
0000h-FFFFh: mV
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6.5.3.7
VTH: Core Voltage Tolerance, High
This location contains the maximum Core Voltage Tolerance DC offset high. This field,
rounded to the next thousandth, is in millivolts and is reflected in binary coded decimal.
Writes to this register have no effect. A value of FF indicates that this value is
undetermined. Writes to this register have no effect.
Example: 15 mV tolerance would be saved as 15h.
Offset:
27h
Bit
7:0
6.5.3.8
Description
Core Voltage Tolerance, High
00h-FFh: mV
VTL: Core Voltage Tolerance, Low
This location contains the maximum Core Voltage Tolerance DC offset low. This field,
rounded to the next thousandth, is in millivolts and is reflected in binary coded decimal.
Writes to this register have no effect. A value of FF indicates that this value is
undetermined. Writes to this register have no effect.
Example: 15 mV tolerance would be saved as 15h.
Offset:
28h
Bit
7:0
6.5.3.9
Description
Core Voltage Tolerance, Low
00h-FFh: mV
RES3: Reserved 3a
This locations are reserved. Writes to this register have no effect.
Offset:
29h
Bit
7:0
Description
RESERVED
00h-FFh: Reserved
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6.5.4
Processor Uncore Data
This section contains silicon-related data relevant to the processor Uncore.
6.5.4.1
MAXQPI: Maximum Intel® QPI Transfer Rate
Systems may need to read this offset to decide if all installed processors support the
same Intel® QPI Link Transfer Rate. The data provided is the transfer rate, rounded to
a whole number, and reflected in binary coded decimal. Writes to this register have
no effect.
Example: The Intel® Xeon® E7 v3 processor supports a maximum Intel® QPI link
transfer rate of 9.6 GT/s. Therefore, offset 2Ah-2Bh has a value of 9600.
Offset:
2Ah-2Bh
Bit
15:0
6.5.4.2
Description
Maximum Intel
®
QPI Transfer Rate
0000h-FFFFh: MHz
MAXPCI: Maximum Intel PCIeTransfer Rate
Systems may need to read this offset to decide if all installed processors support the
same Intel PCIe Link Transfer Rate. The data provided is the transfer rate, rounded to a
whole number, and reflected in binary coded decimal. Writes to this register have
no effect.
For example, the Intel® Xeon® E7 v3 processor supports a maximum Intel PCIe2 link
transfer rate of 8.0 GT/s. Therefore, offset 2Ah-2Bh has a value of 8000.
Offset:
2Ch-2Dh
Bit
15:0
6.5.4.3
Description
Minimum Intel
®
QPI Transfer Rate
0000h-FFFFh: MHz
QPIVN: Intel® QPI Version Number
The Intel® QPI Version Number is provided as four 8-bit ASCII characters. Writes to
this register have no effect.
For example, the Intel® Xeon® E7 v3 processor supports Intel® QPI Version Number
1.1. Therefore, offset 2Eh-31h has an ASCII value of “01.1”, which is 30, 31, 2E, 31.
Offset:
2Eh-31h
Bit
31:0
130
Description
Intel
®
QPI Version Number
00000000h-FFFFFFFFh: MHz
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6.5.4.4
TXT: TXT
This location contains the Intel TXT location, which is a two-bit field and is LSB aligned.
A value of 00b indicates Intel TXT is not supported. A value of 01b indicates Intel TXT is
supported. Writes to this register have no effect.
Example: A processor supporting Intel TXT will have offset 32h set to 01h.
Offset:
32h
Bit
7:2
Description
RESERVED
000000b-111111b: Reserved
TXT
TXT support indicator
1:0
6.5.4.5
00b: Not supported
01b: Supported
10b-11b: Reserved
MAXSMP: Maximum Intel SMI2 Performance Transfer Rate
Systems may need to read this offset to decide on compatible processors and Jordan
Creek capabilities. The data provided is the transfer rate, rounded to a whole number,
and reflected in binary coded decimal. Writes to this register have no effect.
Example: The Intel® Xeon® E7 v3 processor supports a maximum Intel SMI2
performance transfer rate of 3.2 GT/s. Therefore, offset 33h-34h has a value of 3200h.
Offset:
33h-34h
Bit
15:0
6.5.4.6
Description
Maximum Intel SMI Transfer Rate
0000h-FFFFh: MHz
MAXSML: Maximum Intel SMI2 Lock Step Transfer Rate
Systems may need to read this offset to decide on compatible processors and Jordan
Creek scalable memory buffer capabilities. The data provided is the transfer rate,
rounded to a whole number, and reflected in binary coded decimal. Writes to this
register have no effect.
Example: The Intel® Xeon® E7 v3 processor supports a maximum Intel SMI 2 lock
step transfer rate of 1.866 GT/s. Therefore, offset 33h-34h has a value of 1866h.
Offset:
35h-36h
Bit
15:0
Description
Minimum Intel SMI Transfer Rate
0000h-FFFFh: MHz
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6.5.4.7
MXSAVD: MAX VSA VID
Offset 37h-38h is the Processor Vsa maximum VID (Voltage Identification) field and
contains the maximum voltage requested via the VID pins. This field, rounded to the
next thousandth, is in mV and is reflected in binary coded decimal. Some systems read
this offset to determine if all processors support the same default VID setting. Writes to
this register have no effect.
Example: A voltage of 1.200 V maximum core VID would contain 1200h in Offset 3637h.
Offset:
37h-38h
Bit
15:0
6.5.4.8
Description
MAX VSA VID
0000h-FFFFh: mV
MNSAVD: MIN VSA VID
Offset 39h-4Ah is the Processor Vsa minimum VID (Voltage Identification) field and
contains the minimum voltage requested via the VID pins. This field, rounded to the
next thousandth, is in mV and is reflected in binary coded decimal. Some systems read
this offset to determine if all processors support the same default VID setting. Writes to
this register have no effect.
Example: A voltage of 0.600 V maximum core VID would contain 600h in Offset
39- 4Ah.
Offset:
39-4Ah
Bit
15:0
6.5.4.9
Description
MIN VSA VID
0000h-FFFFh: mV
RES4: Reserved 4
This location is reserved. Writes to this register have no effect.
Offset:
3Bh-3Eh
Bit
31:0
6.5.4.10
Description
RESERVED
00000000h-FFFFFFFFh: Reserved
L2SIZE: L2 Cache Size
This location contains the size of the level-two cache in kilobytes. Writes to this register
have no effect. Data format is decimal.
Example: The Intel® Xeon® E7 v3 processor has a 2.5 MB L2 cache. Thus, offset
3Fh-40h will contain a value of 1400.
132
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Offset:
3Fh-40h
Bit
15:0
6.5.4.11
Description
L2 Cache Size
0000h-FFFFh: KB
L3SIZE: L3 Cache Size
This location contains the size of the level-three cache in kilobytes. Writes to this
register have no effect. Data format is decimal.
Example: The Intel® Xeon® E7 v3 processor has up to a 45 MB L3 cache. Thus,
offset 41h-42h will contain a value of B400.
Offset:
41h-42h
Bit
15:0
6.5.4.12
Description
L3 Cache Size
0000h-FFFFh: KB
VVMSE: VVMSE
This field contains the voltage requested for the VVMSE pins. This field is in mV and is
reflected in hex. Some systems read this offset to determine if all processors support
the same default VMSE settings. Writes to this register have no effect.
Example: A voltage of 1.350 VVMSE would contain an Offset 43-44h value of 1350h.
Offset:
43h-44h
Bit
15:0
6.5.4.13
Description
Cache Voltage ID
0000h-FFFFh: mV
VCCIO: VCCIO_IN
This field contains the voltage requested for the VccIO_IN pins. This field is in mV and
is reflected in hex. Some systems read this offset to determine if all processors support
the same default VccIO_IN settings. Writes to this register have no effect.
Example: A voltage of 1.000 VccIO_IN would contain an Offset 43-44h value of 1000h.
Offset:
45-46h
Bit
15:0
Description
Cache Voltage Tolerance, High
0000h-FFFFh: mV
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6.5.4.14
RES5: Reserved 5
This location is reserved. Writes to this register have no effect.
Offset:
47h-4Bh
Bit
39:0
6.5.5
Description
RESERVED
0000000000h-FFFFFFFFFFh: Reserved
Package Data
This section contains substrate and other package related data.
6.5.5.1
PREV: Package Revision
This location tracks the highest level package revision. It is provided in an ASCII format
of four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,
2.0, etc. If only three ASCII characters are consumed, a leading space is provided in
the data field. Writes to this register have no effect.
For example, the Intel® Xeon® E7 v3 processor utilizes the second revision of the
LGA-2011 package. Thus, at offset 4C-4F-35h, the data is a space followed by 2.0. In
hex, this would be 20h, 32h, 2Eh, 30h.
Offset:
4Ch-4Fh
Bit
31:24
Description
Character 4
ASCII character or 20h
00h-0FFh: ASCII character
23:16
Character 3
ASCII character
00h-0FFh: ASCII character
15:8
Character 2
ASCII character
00h-0FFh: ASCII character
7:0
Character 1
ASCII character
00h-0FFh: ASCII character
6.5.5.2
Substrate Revision Software ID
This location is a place holder for the Substrate Revision Software ID. Writes to this
register have no effect.
Offset:
50h
Bit
7:0
134
Description
Substrate Revision Software ID
00h-FFh: Reserved
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6.5.5.3
RES6: Reserved 6
This location is reserved. Writes to this register have no effect.
Offset:
51h-53h
Bit
23:0
6.5.6
Description
RESERVED
000000h-FFFFFFh: Reserved
Part Number Data
This section provides device traceability.
6.5.6.1
PFN: Processor Family Number
This location contains seven ASCII characters reflecting the Intel® family number for
the processor. This number is the same on all Intel® Xeon® E7 v3 processors.
Combined with the Processor SKU Number below, this is the complete processor part
number. This information is typically marked on the outside of the processor. If the part
number is less than 15 total characters, a leading space is inserted into the value. The
part number should match the information found in the marking specification. Writes to
this register have no effect.
For example, a processor with a part number of AT80604******** will have the
following data found at offset 38-3Eh: 41h, 54h, 38h, 30h, 36h, 30h, 34h.
Offset:
54h-5Ah
Bit
55:48
Description
Character 7
ASCII character or 20h
00h-0FFh: ASCII character
47:40
Character 6
ASCII character or 20h
00h-0FFh: ASCII character
39:32
Character 5
ASCII character or 20h
00h-0FFh: ASCII character
31:24
Character 4
ASCII character
00h-0FFh: ASCII character
23:16
Character 3
ASCII character
00h-0FFh: ASCII character
15:8
Character 2
ASCII character
00h-0FFh: ASCII character
7:0
Character 1
ASCII character
00h-0FFh: ASCII character
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6.5.6.2
PSN: Processor SKU Number
This location contains eight ASCII characters reflecting the SKU number for the
processor. Added to the end of the Processor Family Number above, this is the
complete processor part number. This information is typically marked on the outside of
the processor. If the part number is less than 15 total characters, a leading space is
inserted into the value. The part number should match the information found in the
marking specification. Writes to this register have no effect.
Example: A processor with a part number of *******003771AA will have the following
data found at offset 58-62h: 30h, 30h, 33h, 37h, 37h, 31h, 41h, 41h.
Offset:
5Bh=62h
Bit
63:56
55:48
Description
Character 8
00h-0FFh: ASCII character
Character 7
ASCII character or 20h
00h-0FFh: ASCII character
47:40
Character 6
ASCII character or 20h
00h-0FFh: ASCII character
39:32
Character 5
ASCII character or 20h
00h-0FFh: ASCII character
31:24
Character 4
ASCII character
00h-0FFh: ASCII character
23:16
Character 3
ASCII character
00h-0FFh: ASCII character
15:8
Character 2
ASCII character
00h-0FFh: ASCII character
7:0
Character 1
ASCII character
00h-0FFh: ASCII character
6.5.6.3
RES7: Reserved 7
This location is reserved. Writes to this register have no effect.
Offset:
63h-65h
Bit
23:0
136
Description
RESERVED
000000h-FFFFFFh: Reserved
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6.5.7
Thermal Reference Data
6.5.7.1
TUT: Thermalert Upper Threshold
This location is a place holder for the Thermalert Upper Threshold Byte. Writes to this
register have no effect.
Offset:
66h
Bit
7:0
6.5.7.2
Description
Thermalert Upper Threshold
0000h-FFFFh: Reserved
TCO: Thermal Calibration Offset
This location is a place holder for the Thermal Calibration Offset Byte. Writes to this
register have no effect.
Offset:
67h
Bit
7:0
6.5.7.3
Description
Thermal Calibration Offset
0000h-FFFFh: Reserved
TCASE: TCASE Maximum
This location provides the maximum TCASE for the processor. The field reflects
temperature in degrees Celsius in binary coded decimal format. The thermal
specifications are specified at the case Integrated Heat Spreader (IHS). Writes to this
register have no effect.
Example: A temperature of 66°C would contain a value of 66h.
Offset:
68h
Bit
7:0
6.5.7.4
Description
TCASE Maximum
00h-FFh: Degrees Celsius
TDP: Thermal Design Power
This location contains the maximum Thermal Design Power for the part. The field
reflects power in watts in binary coded decimal format. Writes to this register have no
effect. A zero value means that the value was not programmed.
Example: A 130 W TDP would be saved as 0130h.
Offset:
69h-6Ah
Bit
15:0
Description
Thermal Design Power
0000h-FFFFh: Watts
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6.5.7.5
RES7: Reserved 8
This location is reserved. Writes to this register have no effect.
Offset:
6Bh
Bit
7:0
6.5.8
Description
RESERVED
00h-FFh: Reserved
Feature Data
This section provides information on key features that the platform may need to
understand without powering on the processor.
6.5.8.1
PCFF: Processor Core Feature Flags
This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID
instruction. These details provide instruction and feature support by product family.
Writes to this register have no effect.
Example: A value of BFEBFBFFh can be found at offset 6C - 6Fh.
Offset:
6Ch-6Fh
Bit
31:0
6.5.8.2
Description
Processor Core Feature Flags
00000000h-FFFFFFFFF: Feature Flags
PFF: Processor Feature Flags
This location contains additional feature information from the processor. Writes to this
register have no effect.
Note:
Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).
Offset:
70h
Bit
Description
7
Multi-Core (set if the processor is a multicore processor)
6
Serial signature (set if there is a serial signature at offset 5B- 62h)
5
Electronic signature present (set if there is a electronic signature at 5B- 62h)
4
Thermal Sense Device present (set if an SMBus thermal sensor is on package)
3
Reserved
2
OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)
1
Core VID present (set if there is a VID provided by the processor)
0
L3 Cache present (set if there is a level-3 cache on the processor)
Bits are set when a feature is present, and cleared when they are not.
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6.5.8.3
APFF: Additional Processor Feature Flags
This location contains additional feature information from the processor. Writes to this
register have no effect.
Offset:
71h
Bit
Description
7
Reserved
6
Intel® Cache Safe Technology
5
Extended Halt State (C1E)
4
Intel Virtualization Technology
3
Execute Disable
2
Intel® 64
1
Intel® Thermal Monitor 2
0
Enhanced Intel SpeedStep® Technology
Bits are set when a feature is present, and cleared when they are not.
6.5.8.4
MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are LSB aligned where 00b equates to
nonscalable 2 socket (2S) operation, 01b to scalable 2 socket (S2S), 10 to scalable 4
socket (S4S), and scalable 8 socket (S8S). The Intel® Xeon® E7 v3 processor is a
S2S, S4S, or S8S processor. The first six bits in this field are reserved for future use.
Writes to this register have no effect.
Example: A scalable 8-socket processor will have a value of 03h at offset 71h.
Offset:
72h
Bit
7:2
Description
RESERVED
000000b-111111b: Reserved
Multiprocessor Support
2S, S2S, S4S or S8S indicator
1:0
6.5.8.5
00b:
01b:
10b:
11b:
Nonscalable 2 Socket
Scalable 2 Socket
Scalable 4 Socket
Scalable 8 Socket
TCDC: Tap Chain Device Count
At offset 73, a 4-bit hex digit is used to tell how many devices are in the TAP Chain. A
Intel® Xeon® E7 v3 processor with ten cores, this field would be set to Ah.
Offset:
73h
Bit
7:0
Description
TAP Chain Device Count
0000h-FFFFh: Reserved
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6.5.8.6
RES9: Reserved 9
This location is reserved. Writes to this register have no effect.
Offset:
74h-75h
Bit
15:0
6.5.8.7
Description
RESERVED
0000h-FFFFh: Reserved
STTCKS: Static Checksum
This location provides the checksum of the static values per SKU. Writes to this register
have no effect.
Offset:
76h
Bit
7:0
Description
Static Checksum
One-byte checksum of the Static Checksum
00h- FFh: See Section 6.5.10 for calculation of this value.
6.5.9
Protected Processor Inventory Number
This section contains the Protected Processor Inventory Number and checksum. It
replaces the previous Electronic Data Signature.
6.5.9.1
PPIN: Protected Processor Inventory Number
This location contains a 64-bit identification number. The value in this field is the PPIN
number, which will be the same value as the PPIN accessed through the BIOS MSR.
Writes to this register have no effect.
Offset:
77h-7Eh
Bit
63:0
Description
Electronic Signature
0000000000000000h-FFFFFFFFFFFFFFFFh: Electronic Signature
6.5.9.2
PPINCKS: PPIN Checksum
This location provides the checksum for the PPIN Section. Writes to this register have
no effect.
Offset:
7Fh
Bit
7:0
Description
PPIN Checksum
One-byte checksum of the PPIN Checksum
00h- FFh: See Section 6.5.10 for calculation of this value.
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6.5.10
Checksums
The PIROM includes multiple checksums. Table 6-5 includes the checksum values for
each section defined in the 128-byte ROM.
Table 6-5.
128-Byte ROM Checksum Values
Section
Checksum Address
Static Features
76h
Electronic Signature
7Fh
Checksums are automatically calculated and programmed by Intel. The first step in
calculating the checksum is to add each byte from the field to the next subsequent
byte. This result is then negated to provide the checksum.
Example: For a byte string of AA445Ch, the resulting checksum will be B6h.
AA = 10101010
44 = 01000100
5C = 01011100
AA + 44 + 5C = 01001010
Negate the sum: 10110101 +1 = 10110110 (B6h)
§
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