TPS54672 Typical Size (6,4 mm X 9,7 mm ) SLVS397A – JULY 2001 – REVISED AUGUST 2001 TRACKING/TERMINATION SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FEATURES D Tracks Externally Applied Reference Voltage D 30-mΩ, 12-A Peak MOSFET Switches for High D D D D Efficiency at 6-A Continuous Output Source or Sink Current 6% to 90% VIN Output Tracking Range PWM Frequency Range: Fixed 350 kHz or Adjustable 280 to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Component Count As a member of the SWIFT family of dc/dc regulators, the TPS54672 tracking/termination synchronous PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; a slow-start control to limit in-rush currents; and a status output to indicate valid operating conditions. The TPS54672 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. APPLICATIONS D DDR Memory Termination Voltage D Active Termination of GTL and STL D D DESCRIPTION High-Speed Logic Families DAC Controlled High Current Output Stage Precision Point of Load Power Supply Typical DDR Memory Termination Regulator Circuit Input Voltage 3V–6V 0.56 µH VIN CIN CIN VTTQ PH ENA LOAD TRANSIENT RESPONSE Output Voltage (50 mV/div AC Coupled) COUT BOOT CBOOT PGND VDDQ TPS54672 Output Current (2A/div) REFIN VBIAS VSENSE AGND COMP CBIAS 10 µs/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 PWP PACKAGE (TOP VIEW) AGND VSENSE COMP STATUS BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15 RT ENA REFIN VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND AVAILABLE OPTIONS PACKAGE TA PLASTIC HTSSOP (PWP)† – 40°C to 85°C TPS54672PWP † The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54672PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡ Input voltage range, VI: VIN, ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V VSENSE, REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 17 V Output voltage range, VO: VBIAS, COMP, STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V Source current, IO: PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited COMP, VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mA Sink current, IS: PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mA STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Voltage differential, AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.6 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www.ti.com TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 PACKAGE DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR† POWER RATING ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 28 Pin PWP with solder 3.58 W 0.0358 mW/°C 1.96 W 1.43 W 28 Pin PWP without solder 1.78 W 0.0178 mW/°C 0.98 W 0.71 W † Test Board Conditions: 1. Thickness: 0.062” 2. 3” x 3” 3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering 4. Copper areas located on the top and bottom of the PCB for soldering 5. Power and ground planes, 1 oz. Copper (0.036 mm thick) 6. Thermal vias, 0,33 mm diameter, 1,5 mm pitch (See applications section in this datasheet) 7. Thermal isolation of power plane For more information on the PWP package, refer to TI technical brief, literature number SLMA002. ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS398 AND SLVS400) DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE TPS54610 Adjustable TPS54611 0.9 V TPS54614 1.8 V TPS54612 1.2 V TPS54615 2.5 V TPS54613 1.5 V TPS54616 3.3 V electrical characteristics, TJ = –40°C to +125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS Input voltage range, VIN VID I(Q) Differential voltage, AGND to PGND Quiescent current MIN TYP MAX UNIT 3.0 6.0 V –0.30 0.30 V Switching freq. = 350 kHz, RT open 10 Switching freq. = 500 kHz, RT = 100 kΩ 16 24 1 1.4 2.95 3.00 Shutdown, SS/ENA = 0 V Start threshold voltage, UVLO 16 mA V Stop threshold voltage, UVLO 2.70 2.80 V Hysteresis voltage, UVLO 0.14 0.16 V 2.70 2.80 Rising and falling edge deglitch, UVLO See Note 1 Output voltage, VBIAS I(VBIAS) = 0 See Note 2 Output current, VBIAS µs 2.5 Cumulative regulation accuracy (relative to REFIN) IO = – 6A to 6A, Switching freq. = 350 kHz, REFIN = 1.25 V (see Note 1) Internally set—free running frequency RT open 280 Externally set—free running frequency range RT = 68 kΩ to 180 kΩ 280 Externally set—free running frequency accuracy RT = 100 kΩ (1% resistor to AGND) 460 –1.5% Ramp valley 2.90 V 100 µA 1.5% 350 500 420 kHz 700 kHz 540 kHz 0.75 Ramp amplitude (peak-to-peak) V 1 Minimum controllable on time See Note 1 Maximum duty cycle See Note 1 Error amplifier open loop voltage gain 1 kΩ COMP to AGND (see Note 1) Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (see Note 1) V 200 ns 90% 90 110 3 5 dB MHz NOTE 1: Ensured by design 2. Static resistive loads only www.ti.com 3 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 electrical characteristics, TJ = –40°C to +125°C, VI = 3 V to 6 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MAX UNIT Error amplifier common mode rejection ratio See Note 1 65 Input bias current, VSENSE VSENSE = REFIN = 1 V 60 250 nA Input bias current, REFIN VSENSE = REFIN = 1.25 V 60 250 nA Input offset voltage, REFIN VSENSE = REFIN = 1.25 V –1.5 1.5 mV Input voltage range, REFIN See Note 1 0 1.8 0 1 Common mode output voltage range, range COMP IO = 3 mA IO = –3 mA PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive (see Note 1) Enable threshold voltage, ENA 2.85 V dB 1.4 V V/µs 2.65 V 0.2 0.95 70 85 ns 1.20 1.40 V Enable hysteresis voltage, ENA See Note 1 0.03 V Falling edge deglitch, ENA See Note 1 2.5 µs Leakage current, ENA VI= 5.5 V I(sink) = 2.5 mA Output saturation voltage, STATUS Leakage current, STATUS Current limit trip point 0.18 VI = 5.5 V VIN = 3 V, (see Note 1) 7 10 VIN = 6 V, (see Note 1) 10 12 Current limit leading edge blanking time 100 Current limit total response time 200 150 µA V 1 µA A ns ns See Note 1 Thermal shutdown hysteresis See Note 1 10 26 47 Low/high side N-MOSFET Low/high-side N MOSFET IO = 6A, VI = 6 V (see Note 3) IO = 6A, VI = 3 V (see Note 3) 36 65 www.ti.com 135 1 0.3 Thermal shutdown trip point NOTES: 1: Ensured by design 2. Static resistive loads only 3. Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) ensured by design 4 TYP See Note 1 Output voltage slew rate (symmetric), COMP rDS(on) MIN Error amplifier common mode input voltage range 165 _C _C mΩ TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 Terminal Functions TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD to AGND. BOOT 5 Bootstrap output. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE ENA 27 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and places device in low quiescent current state. PGND 15–19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6–14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. REFIN 26 External reference input. High impedance input to slow-start and error amplifier circuits. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency. STATUS 4 Open drain output. Asserted low when VIN < UVLO threshold, VBIAS and internal reference are not settled or thermal shutdown active. Otherwise STATUS is high. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. 20–24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. VIN VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider. www.ti.com 5 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 internal block diagram VBIAS AGND Enable Comparator Falling Edge Deglitch ENA 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator 2.95 V Hysteresis: 0.16 V VDDQ VIN ILIM Comparator Thermal Shutdown 150°C VIN Leading Edge Blanking Falling and Rising Edge Deglitch VIN REG VBIAS SHUTDOWN 100 ns BOOT Sense Fet 30 mΩ 2.5 µs SS_DIS SHUTDOWN PH REFIN Slow-start (0.25 V/ms minimum) + – R Q Error Amplifier S PWM Comparator LOUT CO Adaptive Dead-Time and Control Logic 25 ns Adaptive Dead Time VIN 30 mΩ PGND OSC TPS54672 STATUS SS_DIS VSENSE 6 COMP RT www.ti.com Vtt TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 detailed description under voltage lock out (UVLO) The TPS54672 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Note that hysteresis in the UVLO comparator and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. enable (ENA) The enable pin, ENA, provides a digital control to enable or disable (shutdown) the TPS54672. An input voltage of 1.4 V or greater ensures that the TPS54672 is enabled. An input of 0.9 V or less ensures that device operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs. When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from 0 V. slow-start The slow-start circuit provides start-up slope control of the output voltage to limit in-rush currents. The nominal internal slow-start rate is 0.25 V/ms with the maximum rate being 0.35 V/ms. When the voltage on REFIN rises faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the reference voltage on REFIN rises more slowly, then the output rises at about the same rate as REFIN. VBIAS regulator (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and that loads with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. oscillator frequency (RT) The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected (floating). If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground. The operating frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency + 100 kW R 500 [kHz] (1) The following table summarizes the frequency selection configurations: FREE RUNNING FREQUENCY RT PIN 350 kHz, internally set Float Externally set 280 kHz to 700 kHz R = 68 k to 180 k www.ti.com 7 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 detailed description (continued) error amplifier (REFIN, VSENSE, COMP) The high performance voltage error amplifier, with wide 5MHz bandwidth, low 1.5 mV-max offset, 1.4 V/µs slew rate, and ground rail input range differentiates the TPS54672 from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. The REFIN input range includes ground which allows 0% duty cycle during transient conditions. The user should note that steady state regulation accuracy of voltages less than 0.84 V is limited by the minimum controllable ON time. PWM control Signals from the error amplifier output, oscillator and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch and portions of the adaptive dead time and control logic block. During steady state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as REFIN. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54672 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET on to decrease the output current. This process is repeated each cycle in which the current limit comparator is tripped. dead-time control and MOSFET drivers Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver does not turn on until the voltage at the junction of the power MOSFETs (PH pin) is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The bootstrap switch is turned on when the low-side FET is on to charge the BOOT capacitor. The low resistance of the bootstrap switch improves drive efficiency and reduces external component count. 8 www.ti.com TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 detailed description (continued) overcurrent protection The cycle by cycle current limiting is achieved using a sense-FET on the high-side MOSFET and differential amplifier with preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of the voltage on the sense-FET exceeding the current limit threshold. A 100-ns leading edge blanking circuit prevents false tripping of the current limit when the high-side switch is turning on. Current limit detection occurs only when current flows from VIN to PH when current is being sourced to the output filter. Load protection during current sink operation is provided by thermal shutdown. thermal shutdown Thermal shutdown turns off the power MOSFETs and disables the control circuits if the junction temperature exceeds the 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C, and starts up under control of the slow-start circuit. status (STATUS) The status pin is an open drain output that indicates when internal conditions are sufficient for proper operation. STATUS can be coupled back to a system controller or monitor circuit to indicate that the termination or tracking regulator is ready for start up. STATUS is high impedance when the TPS54672 is operating or ready to be enabled. STATUS is active low if any of the following occur: • • • VIN < UVLO threshold VBIAS or internal reference have not settled. Thermal shutdown is active. www.ti.com 9 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE IO = 6 A 50 40 IO = 3 A 30 20 10 0 25 85 TJ – Junction Temperature – °C f – Internally Set Oscillator Frequency – kHz VIN = 3.3 V 0 –40 VIN = 5 V 50 IO = 6 A 40 30 IO = 3 A 20 10 0 –40 125 0 25 85 TJ – Junction Temperature – °C Figure 1 125 250 –40 0 600 500 400 300 1.255 1.250 1.245 85 0 125 1.251 1.250 1.249 1.248 1 2 3 4 5 3 6 3.5 Figure 5 SLOW-START TIME vs JUNCTION TEMPERATURE 0 –40 –60 80 Phase –80 –100 60 –120 40 Gain 20 –140 9 Slow-Start Time – ms 100 10 –20 Phase – Degrees 120 –160 0 4 4.5 5 IO – Input Voltage – V Figure 6 ERROR AMPLIFIER OPEN LOOP RESPONSE RL = 10 kΩ, CL = 160 pF, TA = 25°C 8 7 6 –180 –20 1 10 100 1k 10 k 100 k 1 M 125 TA = 85°C REFIN = 1.25 V, IO = 3 A 1.252 IO – Output Current – A Figure 4 140 85 1.247 1.240 25 25 1.253 VO – Output Voltage Regulation – V VO – Output Voltage Regulation – V 700 Gain – dB 300 OUTPUT VOLTAGE REGULATION vs INPUT VOLTAGE TA = 85°C REFIN = 1.25 V TJ – Junction Temperature – °C –200 10 M 5 –40 f – Frequency – Hz 0 25 85 TJ – Junction Temperature – °C Figure 7 10 350 Figure 3 1.260 0 400 TJ – Junction Temperature – °C OUTPUT VOLTAGE REGULATION vs OUTPUT CURRENT 800 200 –40 450 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE f – Externally Set Oscillator Frequency – kHz INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 60 60 Drain Source On-State Resistance – m Ω Drain Source On-State Resistance – m Ω DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE Figure 8 www.ti.com 125 5.5 6 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical DDR memory or GTL bus termination application using the TPS54672. The TPS54672 (U1) can provide greater than 6 A of output current. For proper operation, the exposed thermal PowerPAD underneath the integrated circuit package needs to be soldered to the printed-circuit board. VI C4 10 µF U1 TPS54672 1 2 R2 3 4.75 kΩ 4 5 C2 2700 pF 6 C1 100 pF C6 0.047 µF 7 8 9 10 R1 10 kΩ R3 182 Ω 11 12 13 14 C3 0.01 µF VDDQ RT AGND 28 R6 10 kΩ 27 VSENSE ENA 26 REFIN COMP 25 STATUS VBIAS 24 BOOT VIN 23 PH VIN 22 PH VIN 21 PH VIN 20 PH VIN 19 PH PGND 18 PH PGND 17 PGND PH 16 PH PGND 15 PH PGND PwrPad L1 0.56 µH C9 0.1 µF R7 10 kΩ C8 10 µF VTTQ + C7 150 µF + C10 150 µF C11 1 µF Figure 9. Application Circuit Optimized For Size And Performance component selection The values for the components used in this design example were selected for best load transient and tracking response. Additional design information is available at www.ti.com. input voltage The input voltage range is 3 to 5.5 VDC. The input filter (C4) is a 10-µF ceramic capacitor (Taiyo Yuden). C8, also a 10-µF ceramic capacitor (Taiyo Yuden) that provides high frequency decoupling of the TPS54672 from the input supply, must be located as close as possible to the device. Ripple current is carried in both C8 and C4, and the return path to PGND should avoid the current circulating in the output capacitors C7 and C10. feedback circuit R1, R2, R3, C1, C2 and C3 form the loop compensation network for the circuit. For this design, a Type 3 topology is used. The compensation network, along with the output filter inductor and capacitor delivers a crossover frequency of 135 kHz with 50° of phase margin. www.ti.com 11 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION operating frequency In the application circuit, RT is grounded through a 71.5-kΩ resistor to select the maximum frequency of 700 kHz. To set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 28) and analog ground or leave RT floating to select the default 350 kHz. The resistance can be calculated using the following equation: R+ 500 kHz SwitchingFrequency 100 [kW] (2) output filter The output filter is composed of a 0.56-µH Coilcraft inductor (D01813P–561HC) and two 150-µF Cornell Dublier capacitors (ESRD151M06R). The inductor is a low dc resistance type. The capacitors used are 4 V POSCAP types with a maximum ESR of 0.040 Ω. grounding Maintaining proper grounding is important for optimum circuit performance. For this design, separate analog and power grounds, tied together at a single point, are used. The power ground is tied to the negative leads of the input and output filter capacitors, as well as the PGND pins (15–19) of the TPS54672. All other ground pins in the circuit are tied to the analog ground including the AGND pin and thermal PowerPAD of the TPS54672. The single connection point for the analog and power grounds can be made near the IC pins, or connection can be made near the negative leads of the output filter capacitor to marginally improve output regulation accuracy. In either case, the input ripple current return path should be strictly avoided. The voltage differential between AGND pins or PowerPAD and the PGND pins should be limited to 300 mVPP to avoid spurious operation. Refer to the layout examples in the user guides for the TPS54672 EVM, TPS54610 EVM (SLVU054) and TPS54614 EVM (SLVU053). layout considerations for thermal performance For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 6 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance thermal performance should be included in areas not under the device package. 12 www.ti.com TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 APPLICATION INFORMATION 8 PL Ø 0.0130 4 PL Ø 0.0180 Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside PowerPAD Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area is Extended. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.0150 0.06 0.0339 0.0650 0.0500 0.3478 0.0500 0.1900 0.0500 0.0256 0.0650 0.0339 Exposed Copper Area For PowerPAD 0.1700 0.1250 Minimum Recommended Top Side Analog Ground Area 0.1000 0.0600 Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD EFFICIENCY vs OUTPUT CURRENT LOAD TRANSIENT RESPONSE 95 VI = 3.3 V, VO = 1.25 V, L = 2.2 uH Output Voltage (50 mV/div AC Coupled) 90 Efficiency – % 85 Output Current (2A/div) 80 75 VI = 3.3 V, VO = 0.9 V, L = 0.56 uH 70 65 VI = 5 V, VO = 1.75 V, L = 0.56 uH 60 55 50 0 1 2 3 4 5 6 7 IO – Output Current – A 10 µs/div Figure 12 Figure 11 www.ti.com 13 TPS54672 SLVS397A – JULY 2001 – REVISED AUGUST 2001 MECHANICAL DATA PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. 14 www.ti.com IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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