ESMT
F50L512M41A
Flash
3.3V 512 Mbit
SPI-NAND Flash Memory
PRODUCT LIST
Parameters
Values
VCC
VCCQ1
Width
Frequency
Internal ECC Correction
Transfer Rate
Loading Throughput
Power-up Ready Time
Max Reset Busy Time
Note: 1. VCCQ should be the same as VCC.
2. x2 PROGRAM operation is not defined.
3.3V
3.3V
x1, x22, x4
104MHz
1-bit
10ns
104MT/s
1ms (maximum value)
1ms (maximum value)
FEATURES
z
z
z
z
z
z
z
Voltage Supply: 3.3V (2.7V~3.6V)
Organization
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
Page Read Operation
- Page Size: (2K + 64) Byte
- Read from Cell to Register with Internal ECC: 100us
Memory Cell: 1bit/Memory Cell
Support SPI-Mode 0 and SPI-Mode 31
Fast Write Cycle Time
- Program time:400us
- Block Erase time: 4ms
z
z
z
z
z
z
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- Internal ECC Requirement: 1bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
NOP: 4 cycles
OTP Operation
Bad-Block-Protect
Note: 1. Mode 0: CPOL = 0, CPHA = 1; Mode 3: CPOL = 1, CPHA = 1
ORDERING INFORMATION
Product ID
F50L512M41A -104RAG
Speed
104MHz
Package
8-contact LGA
Elite Semiconductor Memory Technology Inc.
Comments
8x6mm
Pb-free
Publication Date: May 2014
Revision: 1.1
1/36
ESMT
F50L512M41A
GENERAL DESCRIPTION
The serial electrical interface follows the industry-standard serial
peripheral interface (SPI), providing a cost-effective non-volatile
memory storage solution in systems where pin count must be
kept to a minimum. The device is a 512Mb SLC SPI-NAND
Flash memory device based on the standard parallel NAND
Flash, but new command protocols and registers are defined for
SPI operation. It is also an alternative to SPI-NOR, offering
superior write performance and cost per bit over SPI-NOR.
The command set resembles common SPI-NOR command set,
modified to handle NAND-specific functions and new features.
New features include user-selectable internal ECC. With internal
ECC enabled, ECC code is generated internally when a page is
written to the memory array. The ECC code is stored in the
spare area of each page. When a page is read to the cache
register, the ECC code is calculated again and compared with
the stored value. Errors are corrected if necessary. The device
either outputs corrected data or returns an ECC error status.
Elite Semiconductor Memory Technology Inc.
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased. The device contains 512 blocks, composed by 64
pages consisting in two NAND structures of 32 series connected
Flash cells. Each page consists 2112-Byte and is further divided
into a 2048-Byte data storage area with a separate 64-Byte
spare area. The 64-Byte area is typically used for memory and
error management.
The pins serve as the ports for signals. The device has six signal
lines plus VCC and ground (GND, VSS). The signal lines are SCK
(serial clock), SI (command and data input), SO (response and
data output), and control signals CS#, HOLD#, WP#.
Publication Date: May 2014
Revision: 1.1
2/36
ESMT
F50L512M41A
PIN CONFIGURATION (TOP VIEW)
8-Contact LGA
(LGA 8C, 8mmx6 mm Body, 1.27mm Contact Pitch)
CS#
1
8
VCC
SO (IO1)
2
7
HOLD# (IO3)
WP# (IO2)
3
6
SCK
VSS
4
5
SI (IO0)
Pin Description
Pin Name
CS#
HOLD# / IO3
WP# / IO2
SCK
SI / IO0
SO / IO1
VCC 6
VSS 6
NC
Functions
Chip Select (Input)
The device is activated1/deactivated2 as CS# is driven LOW/HIGH.
After power-on, the device requires a falling-edge on CS# before any command can be
written. The device goes to standby mode when no PROGRAM, ERASE, or WRITE
STATUS REGISTER operation is in progress.
Hold (Input) / IO3 (Input/Output)
Hold pauses any serial communication with the device without deselecting it3. When driven
LOW, SO is at high impedance (Hi-Z), and all inputs in SI and SCK are ignored; CS# also
should be driven LOW.
HOLD# must not be driven during x4 operation.
Write Protect (Input) / IO2 (Input/Output)
WP# is driven LOW to prevent overwriting the block-lock bits (BP0, BP1, and BP2) if the
block register write disable (BRWD) bit is set4.
WP# must not be driven during x4 operation.
Serial Clock (Input)
SCK provides serial interface timing.
Address, commands, and data in SI are latched on the rising edge of SCK.
Output (data in SO) is triggered after the falling-edge of SCK.
The clock is valid only when the device is active.5
Serial Data Input (Input) / IO0 (Input/Output)
SI transfers data serially into the device. Device latches addresses, commands, and program
data in SI on the rising-edge of SCK.
SI must not be driven during x2 or x4 READ operation.
Serial Data Output (Output) / IO1 (Input/Output)
SO transfers data serially out of the device on the falling-edge of SCK.
SO must not be driven during x2 or x4 PROGRAM operation.
Power
VCC is the power supply for device.
Ground
No Connection
Not internally connected.
Note:
1. CS# places the device in active power mode.
2. CS# deselects the device and places SO at high impedance.
3. It means HOLD# input doesn’t terminate any READ, PROGRAM, or ERASE operation currently in progress.
4. If the BRWD bit is set to 1 and WP# is LOW, the block protect bits can’t be altered.
5. SI and SO can be triggered only when the clock is valid.
6. Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
3/36
ESMT
F50L512M41A
BLOCK DIAGRAM
ARRAY ORGANIZATION
Array Address
Data Bits
0
1
2
3
4
5
6
7
1st byte
2nd byte
3rd byte
4th byte
5th byte
A0
A8
A12
A20
*L
A1
A9
A13
A21
*L
A2
A10
A14
A22
*L
A3
A11
A15
A23
*L
A4
*L
A16
A24
*L
A5
*L
A17
A25
*L
A6
*L
A18
A26
*L
A7
*L
A19
*L
*L
Address
Column Address
Column Address
Row Address
Row Address
Dummy Address
Note:
Column Address: Starting Address of the Register.
*L must be set to “Low”.
The device ignores any additional input of address cycles than required.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
4/36
ESMT
F50L512M41A
COMMAND SET
Function
BLOCK ERASE
1
GET FEATURE
SET FEATURE
WRITE DISABLE
WRITE ENABLE
PROGRAM LOAD
2
PROGRAM LOAD x4
PROGRAM LOAD RANDOM
DATA
PROGRAM LOAD RANDOM
2
DATA x4
PROGRAM EXECUTE
PAGE READ
READ FROM CACHE
READ FROM CACHE x2
2
READ FROM CACHE x4
3
READ ID
RESET
Op Code
Address Byte
Dummy Byte
Data Bytes
D8h
3
0
0
0Fh
1
0
1
1Fh
04h
06h
02h
1
0
0
2
0
0
0
0
1
0
0
1 to 2112
32h
2
0
1 to 2112
84h
2
0
1 to 2112
34h
2
0
1 to 2112
10h
13h
03h, 0Bh
3Bh
3
3
2
2
0
0
1
1
0
0
1 to 2112
1 to 2112
6Bh
2
1
1 to 2112
9Fh
1
0
2
FFh
0
0
0
Note:
1. Refer to Feature Register.
2. Command/Address is 1-bit input per clock period, data is 4-bit input/output per clock period.
3. Address is 00h to get JEDEC ID
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
5/36
ESMT
F50L512M41A
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Temperature Under Bias
VCC
VIN
VI/O
TBIAS
-0.6 to +4.6
-0.6 to +4.6
-0.6 to VCC + 0.3 (< 4.6)
-40 to +125
℃
Storage Temperature
TSTG
-65 to +150
℃
Short Circuit Current
IOS
5
mA
Voltage on any pin relative to VSS
V
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended Operating Conditions
(Voltage reference to GND, TA = 0 to 70℃)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
2.6
0
3.3
0
3.6
0
V
V
Supply Voltage
Supply Voltage
DC and Operation Conditions
(Recommended operating conditions otherwise noted)
Parameter
Page Read with
Serial Access
Program
Erase
Symbol
Test Conditions
ILI
fC=104MHz, CS#=VIL,
IOUT=0mA
CS#=VIH,
WP#=0V/VCC
CS#= VCC -0.2,
WP#=0V/ VCC
VIN=0 to VCC (max)
Output Leakage Current
ILO
VOUT=0 to VCC (max)
Input High Voltage
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
VIH1
VIL1
VOH
VOL
IOH=-20uA
IOL=1mA
Operating
Current
ICC1
ICC2
ICC3
Stand-by Current (TTL)
ISB1
Stand-by Current (CMOS)
ISB2
Input Leakage Current
Min.
Typ.2
-
12
-
12
12
-
Max.
Unit
20
mA
-
1
mA
-
10
50
uA
-
-
±10
uA
-
-
±10
uA
0.7 x VCC
-0.3
0.7 x VCC
-
-
VCC +0.3
0.2 x VCC
VCC +0.3
0.15 x VCC
V
V
V
V
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =3.3V, TA=25℃. Not 100% tested.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
6/36
ESMT
F50L512M41A
Valid Block and Error Management
Description
Minimum / Maximum number of valid block number of block
Bad block mark
Mark location
Requirement
502 / 512
Non FFh
Column 2048 of page 0 and page 1
Note:
1. The device may include initial invalid blocks when first shipped. The number of valid blocks is presented as first shipped. Invalid
blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do
not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial
invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to
be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
7/36
ESMT
F50L512M41A
AC Test Condition
(TA=0 to 70℃, VCC=2.7V~3.6V)
Parameter
Condition
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
0.2VCC to 0.8VCC
Max: 2.4ns
VCC /2
1 TTL Gate and CL=15pF
Capacitance
(TA=25℃, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min.
Max.
Unit
CI/O
CIN
VIL = 0V
VIN = 0V
-
8
8
pF
pF
Input / Output Capacitance
Input Capacitance
Note: Capacitance is periodically sampled and not 100% tested.
Read / Program / Erase Timing Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Average Program Time
Number of Partial Program Cycles in the
Same Page
Block Erase Time
Data Transfer from Cell to Register with
Internal ECC
tPROG
-
400
900
us
NOP
-
-
4
Cycle
tBERS
-
4
10
ms
tRD
-
-
100
us
General Timing Characteristic
Parameter
Clock frequency
Hold# non-active hold time relative to SCK
Hold# hold time relative to SCK
Command deselect time
CS# Setup Time
CS# Hold Time
The last valid Clock low to CS# high
Output disable time
Hold# non-active setup time relative to SCK
Hold# setup time relative to SCK
Data input setup time
Data input hold time
Output hold time
Hold# to output Hi-Z
Hold# to output Low-Z
Clock low to output valid
Clock high time
Clock low time
Clock rise time (slew rate)
Clock fall time (slew rate)
WP# setup time
WP# hold time
Resetting time during Idle/Read/Program/Erase
Symbol
fC
tCD
tCH
tCS
tCSS
tCSH
tCSCL
tDIS
tHC
tHD
tSUDAT
tHDDAT
tHO
tHZ
tLZ
tV
tWH
tWL
tCRT
tCFT
tWPS
tWPH
tRST
Min.
Max.
104MHz
5ns
5ns
100ns
5ns
5ns
5ns
20ns
7ns
5ns
2ns
5ns
0ns
15ns
15ns
8ns
4.5ns
4.5ns
0.1V/ns
0.1V/ns
20ns
100ns
5/100/900/500us
Note: For first RESET condition after power up, tRST will be 1ms MAX.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
8/36
ESMT
F50L512M41A
Technical Notes
Bus Operation
SPI NAND supports two SPI modes:
(Mode 0) CPOL (clock polarity) = 0, CPHA (clock phase) = 0
(Mode 3) CPOL=1, CPHA=1
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.
When CS# is high, keep SCK at VCC (Mode 0) or VSS (Mode 3). Do not begin toggling SCK until after CS# is driven LOW.
SPI Modes Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
9/36
ESMT
F50L512M41A
Feature Operations
The GET FEATURE (0Fh) and SET FEATURE (1Fh) commands are used to alter the device behavior from the default power-on
behavior. These commands use a 1-Byte feature address to determine which feature is to be read or modified.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise specified in
Feature Setting Table, once the device is set, it remains set, even if a RESET (FFh) command is issued.
Feature Settings Table
Register
Block Lock
A0h
OTP
B0h
Status
Output
Driver
Data Bits
Address
C0h
4
D0h
7
6
5
4
3
2
1
0
BRWD1
OTP
Protect
Reserved
Reserved
OTP
Enable
Reserved
BP2
BP0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECC_S1
BP1
ECC
Enable2
ECC_S0
P_Fail
E_Fail
WEL
Reserved
DRV_S1
DRV_S0
Reserved
Reserved
Reserved
Reserved
3
OIP
Reserved
Note:
1. BRWD is not protected (fixed) even when BRWD is enabled and WP# is LOW; (38h) is the default data byte value for Block Lock
Register after power-up.
2. 1-bit internal ECC for all READ and PROGRAM operations can be enabled (ECC enable = 1) or disabled (ECC enable = 0); (10h)
is the default data byte value for OTP Register after power-up.
3. WEL = 0 is the default data bit value for Status Register after power-up.
4. (20h) is the default data byte value for Output Driver Register after power-up.
Block Protect Bits of Block Lock Register Table
BP2 (5)
BP1 (4)
BP0 (3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Protected Rows
None; all unlocked
Upper 1/64 locked
Upper 1/32 locked
Upper 1/16 locked
Upper 1/8 locked
Upper 1/4 locked
Upper 1/2 locked
All locked (default)
OTP State Bits of OTP Register Table
OTP Protect Bit (7)
OTP Enable Bit (6)
State
0
0
1
1
0
1
0
1
Normal operation (read array)
Access OTP space
Not applicable
Lock the OTP area
Driver Strength Bits of Output Driver Register Table
DRV_S1
DRV_S0
0
0
1
1
0
1
0
1
Elite Semiconductor Memory Technology Inc.
Driver Strength
100 %
75 %
50 %
25%
Publication Date: May 2014
Revision: 1.1
10/36
ESMT
F50L512M41A
GET FEATURE (0Fh) Timing
SET FEATURE (1Fh) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
11/36
ESMT
F50L512M41A
Array Write Enable / Disable
The WRITE ENABLE (06h) command sets the WEL bit (in status register) to 1. This is required in the following WRITE operations that
change the contents of the memory array: PAGE PROGRAM, BLOCK ERASE, and OTP PROGRAM.
Contrarily, the WRITE DISABLE (04h) command sets the WEL bit to 0. This disables PAGE PROGRAM, BLOCK ERASE, and OTP
PROGRAM.
WRITE ENABLE (06h) Timing
WRITE DISABLE (04h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
12/36
ESMT
F50L512M41A
Status Register
Software can read status register during the NAND device operation by issuing GET FEATURE (0Fh) command, followed by the
feature address C0h. The status register will output the status of the operation, refer to Feature Setting Table, Bits of Status Register
Table and ECC Status Bits of Status Register Table.
Bits of Status Register Table
Bit Name
Mode
Program fail (Bit 3)
R
Erase fail (Bit 2)
R
Write enable latch (Bit 1)
W
Operation in progress (Bit 0)
R
ECC_status1 (Bit 5)
ECC_status0 (Bit 4)
R
Description
P_Fail is set to 1 as a program failure has occurred. P_Fail = 1 will also be set if
the user attempts to program an invalid address or a locked region.
P_Fail is set to 0 during the PROGRAM EXECUTE command sequence or the
RESET command.
E_Fail is set to 1 as an erase failure has occurred. E_Fail = 1 will also be set if
the user attempts to erase a locked region, or if ERASE operation fails.
E_Fail is set to 0 at the start of the BLOCK ERASE command sequence or the
RESET command.
WEL must be set to 1 to indicate the current status of the write enable latch,
prior to issuing PROGRAM EXECUTE or BLOCK ERASE command. It is set
by issuing WRITE ENABLE command.
WEL is disabled (WEL=0) by issuing the WRITE DISABLE command.
OIP is set to 1 when the device is busy; it means a PROGRAM EXECUTE,
PAGE READ, BLOCK ERASE, or RESET command is executing.
OIP is cleared to 0 as the interface is in ready state.
ECC Status Bits of Status Register Table shows the ECCS definitions.
ECC_S is set to 00h either following a RESET, or at the beginning of the
READ. It is then updated after the device completes a valid READ operation.
ECC_S is invalid if ECC is disabled (via a SET FEATURE command to Bit 4 in
OTP register).
After power-up RESET, ECC_S is set to reflect the contents of block 0, page 0.
ECC Status Bits of Status Register Table
ECCS1 (5)
ECCS0 (4)
0
0
1
1
0
1
0
1
Elite Semiconductor Memory Technology Inc.
Description
No errors
1-bit error detected and corrected
2-bit errors detected and not corrected
Reserved
Publication Date: May 2014
Revision: 1.1
13/36
ESMT
F50L512M41A
Error Management
Mask Out Initial Invalid Blocks
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The
information regarding the initial invalid blocks is called the initial invalid block information. Devices with initial invalid blocks have the
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block does not affect
the performance of valid blocks because it is isolated from the bit line and the common source line by a select transistor. The system
design must be able to mask out the initial invalid blocks via address mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte
ECC.
Identifying Initial invalid Blocks
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the 1st byte column address in the spare area.
Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop
with Flash memory usage.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
14/36
ESMT
F50L512M41A
Algorithm for Bad Block Scanning
Check “FFh” at the 1st Byte column
address in the spare area of the 1st and
2nd page in the block.
For (i=0; i<Num_of_LUs; i++)
{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;
Read_Page(lu=i, block=j, page=0);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh)
Defect_Block_Found=True;
Read_Page(lu=i, block=j, page=1);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh)
Defect_Block_Found=True;
If (Defect_Block_Found)
Mark_Block_as_Defective(lu=i, block=j);
}
}
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
15/36
ESMT
F50L512M41A
Block Replacement
Within its lifetime, number of invalid blocks may increase with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of failure after ERASE or
PROGRAM in status register, block replacement should be done. Because PROGRAM status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block.
In case of READ, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification
failure due to single bit error be reclaimed by ECC without any block replacement. The additional block failure rate does not include
those reclaimed blocks.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
16/36
ESMT
F50L512M41A
ECC Protection
ECC is enabled after device power-up, so the default PROGRAM and READ commands operate with internal ECC in the active state.
During a PROGRAM operation, the device calculates an ECC code on the 2KB page in the cache register, before the page is written to
the NAND Flash array. The ECC code is stored in the spare area of the page in array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared
with the ECC code value read from the array. If a single-bit data error is discovered, the error is corrected in the cache register and only
the corrected data is on the output bus.
ECC Protection Table
Max Byte Address
Min Byte Address
1FFh (511)
3FFh (1023)
5FFh (1535)
7FFh (2047)
800h (2048)
803h (2051)
807h (2055)
80Fh (2063)
810h (2064)
813h (2067)
817h (2071)
81Fh (2079)
820h (2080)
823h (2083)
827h (2087)
82Fh (2095)
830h (2096)
833h (2099)
837h (2103)
83Fh (2111)
FFFh (4095)
000h (0)
200h (512)
400h (1024)
600h (1536)
800h (2048)
801h (2049)
804h (2052)
808h (2056)
810h (2064)
811h (2065)
814h (2068)
818h (2072)
820h (2080)
821h (2081)
824h (2084)
828h (2088)
830h (2096)
831h (2097)
834h (2100)
838h (2104)
840h (2112)
ECC Protected
Area
Description
Yes
Main 0
User data 01
Yes
Main 1
User data 11
Yes
Main 2
User data 21
Yes
Main 3
User data 31
No
Reserved
No
ECC for main 0
Yes
ECC for spare 02
Yes
2
Spare 0
1
User meta data 0
No
Reserved
No
ECC for main 12
Yes
ECC for spare 12
Yes
Spare 1
User meta data 11
No
Reserved
No
ECC for main 2
Yes
ECC for spare 22
Yes
2
Spare 2
1
User meta data 2
No
Reserved
No
ECC for main 32
Yes
ECC for spare 3
Yes
No
2
Spare 3
User meta data 31
Reserved
Note:
1. The user areas must be programmed within a single partial-page programming operation so the NAND Flash device can calculate
the proper ECC bytes.
2. When internal ECC is enabled, these areas are prohibited to be programming.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
17/36
ESMT
F50L512M41A
Addressing for Program Operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most
significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.
Operations and Timing Diagrams
Read Operations and Serial Output
The command sequence is follows:
13h (PAGE READ to cache)
0Fh (GET FEATURE command to read the status)
0Bh or 03h (READ FROM CACHE x1) / 3Bh (x2) / 6Bh (x4)
PAGE READ command requires 24-bit address with 9 dummy and a 15-bit row address. After row address is registered, the device
starts the transfer from the main array to the cache register, and is busy for tR time. During this time, GET FEATURE command can be
issued to monitor the status of the operation. Following a status of successful completion, READ FROM CACHE command must be
issued to read the data out of the cache.
READ FROM CACHE command requires 16-bit address with 4 dummy bits and a 12-bit column address for the starting byte. The
starting byte can be 0 to 2011, but after the end of the cache register is reached, the data does not wrap around and SO goes to a Hi-Z
state.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
18/36
ESMT
F50L512M41A
PAGE READ (13h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
19/36
ESMT
F50L512M41A
READ FROM CACHE (03h or 0Bh) Timing
NOTE: Final data (LSB in the 2112th Byte for x1) would be reset to Hi-Z at SCK rising edge.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
20/36
ESMT
F50L512M41A
READ FROM CACHE x2 (3Bh) Timing
th
NOTE: Final data (last 2-bit in the 2112 Byte for x2) would be reset to Hi-Z at SCK rising edge.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
21/36
ESMT
F50L512M41A
READ FROM CACHE x4 (6Bh) Timing
th
NOTE: Final data (last 4-bit in the 2112 Byte for x4) would be reset to Hi-Z at SCK rising edge.
Serial Output Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
22/36
ESMT
F50L512M41A
Program Operations and Serial Input
Page Program
The command sequence is follows:
06h (WRITE ENABLE)
02h (PROGRAM LOAD x1) / 32h (x4)
10h (PROGRAM EXECUTE)
0Fh (GET FEATURE command to read the status)
The page program operation sequence programs 1 byte to 2112 bytes of data within a page. If WRITE ENABLE command is not
issued (WEL bit is not set), then the rest of the program sequence is ignored. PROGRAM LOAD command requires 16-bit address with
4 dummy and a 12-bit column address, then the data bytes to be loaded into cache register. Only four partial page programs are
allowed on a single page. If more than 2112 bytes are loaded, then those additional bytes are ignored by the cache register.
After the data is loaded, PROGRAM EXECUTE command must be issued to transfer the data from cache register to main array, and is
busy for tPROG time. PROGRAM EXECUTE command requires 24-bit address with 9 dummy bits and a 15-bit row address.
PROGRAM LOAD (02h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
23/36
ESMT
F50L512M41A
PROGRAM LOAD x4 (32h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
24/36
ESMT
F50L512M41A
PROGRAM EXECUTE (10h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
25/36
ESMT
F50L512M41A
Random Data Program
The command sequence is follows:
06h (WRITE ENABLE)
84h (PROGRAM LOAD RANDOM DATA x1) / 34h (x4)
10h (PROGRAM EXECUTE)
0Fh (GET FEATURE command to read the status)
The random data program operation sequence programs or replaces data in a page with existing data. PROGRAM LOAD RANDOM
DATA command requires 16-bit address with 4 dummy bits and a 12-bit column address. New data is loaded in the column address
provided. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA command must be issued with a new
column address. After the data is loaded, PROGRAM EXECUTE command can be issued to start the programming operation.
PROGRAM LOAD RANDOM DATA (84h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
26/36
ESMT
F50L512M41A
PROGRAM LOAD RANDOM DATA x4 (34h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
27/36
ESMT
F50L512M41A
Serial Input and tCSCL Timing
Internal Data Move
The command sequence is follows:
13h (PAGE READ to cache)
06h (WRITE ENABLE)
84h (PROGRAM LOAD RANDOM DATA x1) / 34h (x4); this is OPTIONAL in sequence.
10h (PROGRAM EXECUTE)
0Fh (GET FEATURE command to read the status)
The INTERNAL DATA MOVE operation sequence programs or replaces data in a page with existing data. Prior to performing an
INTERNAL DATA MOVE operation, the target page content must be read into the cache register. PAGE READ command must be
followed with a WRITE ENABLE command to change the contents of memory array.
Erase Operation
The command sequence is follows:
06h (WRITE ENABLE)
D8h (BLOCK ERASE)
0Fh (GET FEATURE command to read the status)
BLOCK ERASE command requires 24-bit address with 9 dummy bits and a 15-bit row address. If WRITE ENABLE command is not
issued (WEL bit is not set), then the rest of the erase sequence is ignored. After the row address is registered, the control logic
automatically controls the timing and the erase-verify operations, and the device is busy for tBERS time. BLOCK ERASE command
operates on one block at a time.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
28/36
ESMT
F50L512M41A
BLOCK ERASE (D8h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
29/36
ESMT
F50L512M41A
Read ID
The device contains a product identification mode, initiated by writing 9Fh to the command register, followed by an address input of
rd
th
th
00h. Five read cycles sequentially output the manufacturer code (C8h), and the device code and 3 , 4 , 5 cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it.
READ ID Timing
ID Definition Table
Product ID
1st Cycle
(Maker Code)
2nd Cycle
(Device Code)
3rd Cycle
4th Cycle
5th Cycle
F50L512M41A
C8h
20h
7Fh
7Fh
7Fh
Description
st
1 Byte
2nd Byte
3rd Byte
4th Byte
th
5 Byte
Maker Code
Device Code
JEDEC Maker Code Continuation Code, 7Fh
JEDEC Maker Code Continuation Code, 7Fh
JEDEC Maker Code Continuation Code, 7Fh
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
30/36
ESMT
F50L512M41A
WP# Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
31/36
ESMT
F50L512M41A
HOLD# Timing
HOLD# input provides a method to pause serial communication with the device but doesn’t terminate any READ, PROGRAM, or
ERASE operation currently in progress.
Hold mode starts at the falling edge of HOLD# provided SCK is also Low. If SCK is High when HOLD# goes Low, hold mode begins
after the next falling edge of SCK. Similarly, hold mode is exited at the rising edge of HOLD# provided SCK is also Low. If SCK is High,
hold mode ends after the next falling edge of SCK.
During hold mode, SO is Hi-Z, and SI and SCK inputs are ignored.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
32/36
ESMT
F50L512M41A
Power-Up
During power transitions, VCC is internally monitored. 250us after VCC has reached 2.5V, WP# is taken High, the device automatically
performs the RESET command. The first access to the SPI NAND device can occur 1ms after WP# goes High, and then CS# can be
driven Low, SCK can start, and the required command can be issued to the device.
Power-Up and RESET Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
33/36
ESMT
F50L512M41A
PACKING
DIMENSIONS
8-Contact
LGA ( 8x6 mm )
Symbol
A
b
D
D1
E
E1
e
L
Min
0.70
0.35
7.90
3.30
5.90
4.20
0.45
Dimension in mm
Min
0.75
0.40
8.00
3.40
6.00
4.30
1.27 BSC
0.50
Min
0.80
0.48
8.10
3.50
6.10
4.40
Min
0.028
0.014
0.311
0.130
0.232
0.165
0.55
0.018
Dimension in inch
Norm
0.030
0.016
0.315
0.134
0.236
0.169
0.050 BSC
0.020
Max
0.031
0.019
0.319
0.138
0.240
0.173
0.022
Controlling dimension : millimeter
(Revision date : Feb 13 2014)
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
34/36
ESMT
F50L512M41A
Revision History
Revision
Date
0.1
2013.01.30
Original
0.2
2013.05.21
Add packing dimension
0.3
2013.07.16
1. Add 16-pin SOIC package
2. Add Bad-Bloack-Protect and the specification of tCSCL
3. Modify the description of Identifying Initial Invalid
Block(s) and Block Replacement Management
4. Modify the description of feature operations and ECC_S
bits
5. Delete Automatic Read
6. Modify the specification of tHC and tRST
7. Modify ECC protection table and ID definition table
8. Add the note for Read Operation and the description of
HOLD# Timing
0.4
2013.08.23
Delete 16-pin SOIC package
0.5
2014.02.19
Add LGA package
1.0
2014.04.17
1. Delete "Preliminary"
2. Delete WSON package
1.1
2014.05.27
Modify the description of Identifying Initial Invalid Blocks
Elite Semiconductor Memory Technology Inc.
Description
Publication Date: May 2014
Revision: 1.1
35/36
ESMT
F50L512M41A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
36/36