ESMT F25D08QA Flash 8 Mbit Serial Flash Memory with Dual and Quad FEATURES y Single supply voltage 1.65~2V y Speed - Fast Read for SPI mode - Read max frequency: 33MHz - Fast Read max frequency: 104MHz - Fast Read Dual/Quad max frequency: 84MHz/104MHz (168MHz equivalent Dual SPI; 416MHz equivalent Quad SPI) - Fast Read for QPI mode - Fast Read max frequency: 84MHz - Fast Read Quad max frequency: 104MHz (416MHz equivalent Quad QPI) - 8/ 16/ 32/ 64 byte Wrap-Around Burst Read Mode y Low power consumption - Active current: 15mA (typ.) - Standby current: 30 μ A (typ.) - Deep Power Down current: 5 μ A (typ.) y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Page programming time: 0.4 ms (typical) y Page Programming - 256 byte per programmable page ORDERING INFORMATION Product ID Speed Package y Program/Erase Suspend y Erase - Chip Erase time 2 sec (typical) - 64K bytes Block Erase time 130 ms (typical) - 32K bytes Block Erase time 100 ms (typical) - 4K bytes Sector Erase time 30 ms (typical) y Status and Security Register Feature y Command Reset y Advanced Security Features - Flexible Block Protection (BP0-BP3) y Lockable 512 bytes OTP security sector y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y Support Serial Flash Discoverable Parameters (SFDP) mode y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant Comments F25D08QA –104PIG 104MHz 8-lead SOIC 150 mil Pb-free F25D08QA –104PAIG 104MHz 8-lead SOIC 200 mil Pb-free F25D08QA –104VIG 104MHz 8-lead VSOP 150 mil Pb-free F25D08QA –104HIG 104MHz 8-contact WSON 6x5 mm Pb-free Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 1/69 ESMT F25D08QA GENERAL DESCRIPTION The F25D08QA is a 8 Megabit, 1.8V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), a Dual/Quad SPI and QPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array is divided into 256 uniform sectors with 4K byte each; 32 uniform blocks with 32K byte each; 16 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. FUNCTIONAL BLOCK DIAGRAM Page Address Latch / Counter Memory Array High Voltage Generator Page Buffer Status Register Byte Address Latch / Counter Y-Decoder Command and Conrol Logic Serial Interface CE SCK SI (SIO0) SO WP HOLD (SIO1) (SIO2) (SIO3) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 2/69 ESMT F25D08QA PIN CONFIGURATIONS 8-Lead SOIC / 8-Lead VSOP (SOIC 8L, 150mil Body, 1.27mm Pin Pitch) (SOIC 8L, 208mil Body, 1.27mm Pin Pitch) (SOIC 8L, 150mil Body with thickness 0.88mm, 1.27mm Pin Pitch) CE 1 8 VDD SO / SIO1 2 7 HOLD / SIO3 WP / SIO2 3 6 SCK VSS 4 5 SI / SIO0 8- Contact WSON (WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch) CE 1 8 VDD SO / SIO1 2 7 HOLD / SIO3 WP / SIO2 3 6 SCK VSS 4 5 SI / SIO 0 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 3/69 ESMT F25D08QA PIN DESCRIPTION Symbol Pin Name SCK Serial Clock SI / SIO0 Serial Data Input / Serial Data Input Output 0 SO / SIO1 Serial Data Output / Serial Data Input Output 1 CE Chip Enable WP / SIO2 Write Protect / Serial Data Input Output 2 The Write Protect ( WP ) pin is used to enable/disable BPL bit in the Status Register. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). HOLD / SIO3 Hold / Serial Data Input Output 3 To temporality stop serial communication with SPI flash memory without resetting the device. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). VDD Power Supply VSS Ground Elite Semiconductor Memory Technology Inc. Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK(for Dual/Quad mode). To transfer data serially out of the device. Data is shifted out on the falling edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Dual/Quad mode). To activate the device when CE is low. To provide power. Publication Date: Jul. 2013 Revision: 1.1 4/69 ESMT F25D08QA SECTOR STRUCTURE Table 1: Sector Address Table 64KB Block 32KB Block 31 15 30 29 14 28 27 13 26 Sector Sector Size (Kbytes) Address range 255 : 248 247 : 240 4KB : 4KB 4KB : 4KB 0FF000h – 0FFFFFh : 0F8000h – 0F8FFFh 0F7000h – 0F7FFFh : 0F0000h – 0F0FFFh 239 : 232 231 : 224 223 : 216 215 : 208 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 0EF000h – 0EFFFFh : 0E8000h – 0E8FFFh 0E7000h – 0E7FFFh : 0E0000h – 0E0FFFh 0DF000h – 0DFFFFh : 0D8000h – 0D8FFFh 0D7000h – 0D7FFFh : 0D0000h – 0D0FFFh 47 : 40 39 : 32 31 : 24 23 : 16 15 : 8 7 : 0 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 02F000h – 02FFFFh : 028000h – 028FFFh 027000h – 027FFFh : 020000h – 020FFFh 01F000h – 01FFFFh : 018000h – 018FFFh 017000h – 017FFFh : 010000h – 010FFFh 00F000h – 00FFFFh : 008000h – 008FFFh 007000h – 007FFFh : 000000h – 000FFFh individual 16 sectors unit: 4KB individual block unit: 64KB 5 2 4 3 1 2 1 0 0 Elite Semiconductor Memory Technology Inc. individual 16 sectors unit: 4KB Publication Date: Jul. 2013 Revision: 1.1 5/69 ESMT F25D08QA STATUS REGISTER The Software Status Register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the Status Register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the Software Status Register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write 0 R 0 R 0 0 0 0 R/W R/W R/W R/W 0 R/W 0 R/W Status Register 0 BUSY 1 WEL 2 3 4 5 BP0 BP1 BP2 BP3 6 QE 7 BPL 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) 1 = Quad enabled 0 = Quad disabled 1 = BP3, BP2,BP1,BP0 are read-only bits 0 = BP3, BP2,BP1,BP0 are read/writable Note: 1. BUSY and WEL are read only. 2. BP0~3, QE and BPL bits are non-volatile. Write Enable Latch (WEL) BUSY The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: The BUSY bit determines whether there is an internal Erase or Program operation in progress. A “1” for the BUSY bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. • • • • • • • • • • • • • Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instruction completion Signal Block Lock (SBLK) instruction completion Signal Block Unlock (SBULK) instruction completion Gang Block Lock (GBLK) instruction completion Gang Block Unlock (GBULK) instruction completion Write Security Register (WRSCUR) instruction completion Write Protect Selection (WPSEL) instruction completion Elite Semiconductor Memory Technology Inc. Quad Enable (QE) When the Quad Enable bit is reset to “0” (factory default), WP and HOLD pins are enabled. When QE pin is set to “1”, Quad SIO2 and SIO3 are enabled. (The QE should never be set to “1” during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the VDD or VSS.). When in QPI mode, QE bit is not required for setting. Publication Date: Jul. 2013 Revision: 1.1 6/69 ESMT F25D08QA Table 3: Block Protection Table Protection Level BP3 0 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks All Blocks All Blocks Bottom 1/2 Bottom 3/4 Bottom 7/8 Bottom 15/16 All Blocks 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status Register Bit BP2 BP1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 Protected Memory Area 64KB Block Range 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 None Block 15 Block 14~15 Block 12~15 Block 8~15 Block 0~15 Block 0~15 Block 0~15 Block 0~15 Block 0~15 Block 0~15 Block 0~7 Block 0~11 Block 0~13 Block 0~14 Block 0~15 Block Protection (BP3, BP2, BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP3, BP2, BP1, BP0) bits define the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When BP3, BP2, BP1 and BP0 bits as long as WP is high or the Block- Protection-Look (BPL) bit is 0. Chip Erase can only be executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory default setting for Block Protection Bit (BP3 ~ BP0) is 0. the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. Table 4: 512 bytes Secured OTP Definition Address range Size Standard Factory Lock Customer Lock XXX000 ~ XXX00F XXX010 ~ XXX1FF 16-byte 496-byte ESN (electrical serial number) N/A Determined by customer Additional 512K bytes secured OTP for unique identifier: to provide 512K bytes one-time program area for setting device unique serial number - Which may be set by factory or system customer. Security register bit 0 indicates whether the chip is locked by factory or not. To program the 512K bytes secured OTP by entering 512K bytes secured OTP mode (with Enter Security OTP (ENSO) command), and going through normal program procedure, and then exiting 512K bytes secured OTP mode by writing Exit Security OTP (EXSO) command. Elite Semiconductor Memory Technology Inc. - - Customer may lock-down the customer lockable secured OTP by writing WRSCUR (write security register) command to set customer lock-down bit1 as "1". Please refer to Table 9 of "security register definition" for security register bit definition and Table 4 of "512K bytes secured OTP definition" for address range definition. Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512K bytes secured OTP mode, array access is not allowed. Publication Date: Jul. 2013 Revision: 1.1 7/69 ESMT F25D08QA HOLD OPERATION HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 35 for Hold timing. The HOLD function is only available for Standard SPI and Dual SPI operation, not during Quad SPI because this pin is used for SIO3 when the QE bit of Status Register is set for Quad I/O or during QPI mode. S CK HO L D A ctive A ctive Ho ld Ho ld A ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION The device provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the Status Register. The Block-Protection bits (BP3, BP2, BP1, BP0 and BPL) in the Status Register provide Write protection to the memory array and the Status Register. When the QE bit of Status Register is set for Quad I/O or the system enter QPI mode, the WP pin function is not available since this pin is used for SIO2. Table 5: Conditions to Execute Write-Status- Register (WRSR) Instruction WP BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed Write Protect Pin ( WP ) The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the Status Register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 5). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 8/69 ESMT F25D08QA Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing 35H command, the QPI mode is enable. CE 0 1 2 3 4 5 6 7 MODE3 SCK MODE0 SI 35 MSB SO HIGH IMPEDANCE Quad Peripheral Interface (QPI) operation To use QPI protocol, the host drives CE low then sends the Fast Read command, 0BH, followed by 6 address cycles and 4 dummy cycles. Most significant bit (MSB) comes first (Please refer to Figure 8-2). After the dummy cycle, the Quad Peripheral Interface (QPI) Flash Memory outputs data on the falling edge of the SCK signal starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on CE . The internal address pointer automatically increases until the highest memory address is reached. When reached the highest memory address, the address pointer returns to the beginning of the address space. Reset QPI mode By issuing F5H command, the device is reset to 1-I/O SPI mode. CE MODE3 SCK MODE0 SIO3~ SIO0 0 1 F5 Fast Read Quad I/O mode (4READ) To increase the code transmission speed, the device provides a "Fast Read Quad I/O Mode" (4READ). By issuing command code EBH, the 4READ mode is enabled. The number of dummy cycle increase from 4 to 6 cycles. The read cycle frequency will increase from 84MHz to 104MHz. (Please refer to Figure 10-2) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 9/69 ESMT F25D08QA INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25D08QA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 6. All instructions are entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. significant bit. CE must be driven low before an instruction is Table 6-1: Device Operation Instruction (SPI) Max. Freq Operation Read Fast Read 12, Fast Read Dual Output 17 1 2 SIN SOUT SIN SOUT 33 MHz 03H Hi-Z A23-A16 Hi-Z 0BH Hi-Z A23-A16 Hi-Z 104MHz 3BH A23-A16 SPI Bus Cycle 1~3 3 4 5 SIN SOUT SIN SOUT SIN SOUT A15-A8 Hi-Z A7-A0 Hi-Z X DOUT0 A15-A8 Hi-Z A7-A0 Hi-Z X X 6 SIN X X N SOUT DOUT1 DOUT0 SIN SOUT X X cont. cont. A15-A8 A7-A0 X DOUT0~1 cont. A7-A0, X DOUT0~1 cont. - - A15-A8 A7-A0 X DOUT0~3 cont. X, DOUT 0~2 Cont. - - - X, DOUT0~1 DOUT2~6 cont. - - 12, 13 Fast Read Dual I/O 84MHz A23-A8 BBH (2READ) 12, 18 104MHz Fast Read Quad Output 6BH A23-A16 Fast Read Quad I/O14 84MHz E7H A23-A0, M7-M0 (4 dummy cycles) (W4READ) Fast Read Quad I/O12, 14 EBH A23-A0, M7-M0 (4READ) 4 Sector Erase - 4KB (SE) 20H Hi-Z A23-A16 Hi-Z Block Erase 32KB 5 52H Hi-Z A23-A16 Hi-Z (BE32K) 5 Block Erase (BE) D8H Hi-Z A23-A16 Hi-Z 60H / Chip Erase (CE) Hi-Z C7H Program / Erase Suspend B0H Hi-Z Program / Erase Resume 30H Hi-Z Page Program (PP) Dual Input Fast Program Quad Page Program (single address) 19 Quad Page Program (4PP)15 Mode Bit Reset16 Read Status Register 7 (RDSR) Write Status Register 10 (WRSR) Write Enable (WREN) 10 Write Disable (WRDI) Hi-Z A23-A16 02H 104MHz Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - - - - - - - - - - - - - - - - - - - DIN0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z A2H A23-A16 A15-A8 A7-A0 DIN0~1 32H A23-A16 A15-A8 A7-A0 DIN0~3 38h A23~A0, DIN 0 DIN 1~4 DIN 5~8 DIN 9~12 Up to DIN1 Hi-Z 256 Hi-Z bytes Up to 256 DIN2~3 byte Up to 256 DIN4~7 byte Up to 256 DIN 13~16 byte FFH Hi-Z - - - - - - - - - - - - 05H Hi-Z X DOUT (S7-S0) - - - - - - - - - - 01H Hi-Z Hi-Z - - -. - - - - - - - - - - - - - - - - - - 06H 04H DIN (S7-S0) Hi-Z Hi-Z - Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 10/69 ESMT F25D08QA Table 6-1: Device Operation Instruction (SPI) - Continued Max. Freq Operation 1 2 SPI Bus Cycle 1~3 3 4 5 SOUT SIN SOUT SIN SOUT SIN SOUT 34H - - - - X 74H - - - - X X F4H - - - - X 00H 01H A7-A0 - 34H Hi-Z Hi-Z Hi-Z - X X X - 8CH 34H X - X X X - 34H 8CH DOUT0 - - - X cont. - - - - - - - - - - - - - -. - - - - - - - - - - - - - - - - - - X DOUT - - - - - - - - - - Hi-Z - - - - - - - - - - - - 66H Hi-Z - - - - - - - - - - - - 99H Hi-Z - - - - - - - - - - - - 36H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - 39H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - 3CH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - 7EH Hi-Z - - - - - - - - - - - - 98H Hi-Z - - - - - - - - - - - - 68H Hi-Z - - - - - - - - - - - - Set Burst Length (SBL) C0H Hi-Z DIN Hi-Z - - - - - - - - - - Enable Quad I/O (EQIO) 35H Hi-Z - - - - - - - - - - - - NOP 00H Hi-Z - - - - - - - - - - - - Reset Memory (RST) 6 Signal Block Lock (SBLK) Signal Block Unlock (SBULK) Block Protect Read (RDBLOCK) Gang Block Lock (GBLK) Gang Block Unlock (GBULK) Write Protect Selection (WPSEL) 104MHz SIN SOUT SIN ABH Hi-Z X X X X X X X ABH Hi-Z X X X X X X ABH Hi-Z X X X X X 9FH Hi-Z X 8CH X 25H 90H Hi-Z 00H Hi-Z 00H Hi-Z 5AH B9H Hi-Z A23-A16 Hi-Z - ABH Hi-Z - - - B1H Hi-Z - - C1H Hi-Z - 2BH Hi-Z 2FH N SOUT Reset Enable (RSTEN) SOUT 6 SIN Read Electronic 8 Signature (RES) RES in secured OTP mode & not lock down 104MHz RES in secured OTP mode & lock down Read ID (RDID) 9 Read Electronic ID (REMS)11 Read SFDP (RDSFDP) 33MHz Deep Power Down (DP) Release from Deep Power Down (RDP) Enter secured OTP mode (ENSO) Exit OTP (EXSO) Read Security Register (RDSCUR) Write Security Register (WRSCUR) SIN Elite Semiconductor Memory Technology Inc. Hi-Z - A15-A8 Hi-Z - Publication Date: Jul. 2013 Revision: 1.1 11/69 ESMT F25D08QA Table 6-2: Device Operation Instruction (QPI) 1 SIO 0BH 2 SIO A23-A16 3 SIO A15-A8 QPI Bus Cycle 1~3 4 5 6 SIO SIO SIO A7-A0 M7-M0 X EBH A23-A16 A15-A8 A7-A0 M7-M0 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 - - Program / Erase Suspend Program / Erase Resume 20H 52H D8H 60H / C7H B0H 30H - Page Program (PP) 02H Mode Bit Reset16 Read Status Register (RDSR) 7 Write Status Register 10 (WRSR) Write Enable (WREN) 10 Write Disable (WRDI) Read Electronic Signature (RES) 8 RES in secured OTP mode & not lock down RES in secured OTP mode & lock down Deep Power Down (DP) Release from Deep Power Down (RDP) Exit OTP (EXSO) Enter secured OTP mode (ENSO) Read Security Register (RDSCUR) Write Security Register (WRSCUR) Reset Enable (RSTEN) Reset Memory (RST) 6 Signal Block Lock (SBLK) Signal Block Unlock (SBULK) Block Protect Read (RDBLOCK) Gang Block Lock (GBLK) Gang Block Unlock (GBULK) Write Protect Selection (WPSEL) Set Burst Length (SBL) QPI ID Read (QPIID) 9 Reset Quad I/O (RSTQIQ) NOP FFH Operation Fast Read Fast Read Quad I/O12, 14 (4READ) Sector Erase4 - 4KB (SE) Block Erase 32KB 5 (BE32K) Block Erase5 (BE) Max. Freq 84MHz Chip Erase (CE) SIO DOUT1 cont. X X DOUT0 cont. - - - - - - - - - - - - - - - - - A23-A16 A15-A8 A7-A0 DIN0 DIN1 DIN2 DIN3 FFH FFH - - - - - - - - - - - - - - - - - - 06H 04H FFH DOUT (S7-S0) DIN (S7-S0) - Up to 256 bytes - - - - - - - - ABH X X X 34H - - - - ABH X X X 74H - - - - ABH X X X F4H - - - - B9H - - - - - - - - ABH - - - - - - - - C1H - - - - - - - - B1H - - - - - - - - 2BH DOUT - - - - - - - 2FH - - - - - - - - 66H 99H 36H 39H A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 - - - - - 3CH A23-A16 A15-A8 A7-A0 - - - - - 7EH 98H - - - - - - - - 68H - - - - - - - - C0H AFH F5H 00H DIN 8CH - 25H - 34H - - - - - - 05H 01H 104MHz 8 7 SIO DOUT0 N SIO Notes: 1. 2. 3. 4. Operation: SIN = Serial In, SOUT = Serial Out, SIO = Serial In/Out. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One SPI bus cycle is eight clock periods; one QPI bus cycle is two clock periods. 4K byte Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 12/69 ESMT 5. F25D08QA 6. 32K byte Block Earse addresses: use AMS -A15, remaining addresses can be VIL or VIH 64K byte Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The Read ID is output first byte 8CH as manufacture ID; second byte 25H as memory type; third byte 34H as memory capacity. 10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. A successful WRSR can reset WREN. 8. 9. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual and Quad commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 13. M7-M0: Mode bits. Dual input address: IO0 = (A22, A20, A18, A16, A14, A12, A10, A8) (A6, A4, A2, A0, M6, M4, M2, M0) IO1 = (A23, A21, A19, A17, A15, A13, A11, A9) (A7, A5, A3, A1, M7, M5, M3, M1) Bus Cycle-2 Bus Cycle-3 14. M7-M0: Mode bits. Quad input address: IO0 = (A20, A16, A12, A8, A4, A0, M4, M0) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3) Bus Cycle-2 Fast Read Quad I/O data: IO0 = (X, X), (X, X), (D4, D0), (D4, D0) IO1 = (X, X), (X, X), (D5, D1), (D5, D1) IO2 = (X, X), (X, X), (D6, D2), (D6, D2) IO3 = (X, X), (X, X), (D7, D3), (D7, D3) DOUT0 DOUT1 (D4, D0), (D4, D0), (D4, D0), (D4, D0) (D5, D1), (D5, D1), (D5, D1), (D5, D1) (D6, D2), (D6, D2), (D6, D2), (D6, D2) (D7, D3), (D7, D3), (D7, D3), (D7, D3) DOUT2 Bus Cycle-3 DOUT3 DOUT4 DOUT5 Bus Cycle-4 15. The instruction is initiated by executing command code, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input address and data: IO0 = (A20, A16, A12, A8, A4, A0, D4, D0) IO1 = (A21, A17, A13, A9, A5, A1, D5, D1) IO2 = (A22, A18, A14, A10, A6, A2, D6, D2) IO3 = (A23, A19, A15, A11, A7, A3, D7, D3) SPI Bus Cycle 16. This instruction is recommended when using the Dual or Quad Mode bit feature. 17. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 18. Quad output data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3) DOUT0 DOUT1 DOUT2 DOUT3 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 13/69 ESMT F25D08QA 19. The instruction is initiated by executing command code, followed by address bits into SI (SIO0) before DIN, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3) DIN0 DIN1 DIN2 DIN3 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 14/69 ESMT F25D08QA (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, WRSR, SBLK, SBULK, GBLK, GBULK, WRSCUR and WPSEL, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CE goes low → sending WREN instruction code → CE goes high. (Please refer to Figure 2-1 and Figure 2-2) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CE goes low → sending WRDI instruction code → CE goes high. (Please refer to Figure 3-1 and Figure 3-2) The WEL bit is reset by following situations: - Power-up - Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction - Completion of Page Program (PP) instruction - Completion of Quad Page Program (4PP) instruction - Completion of Quad Page Program (single address) instruction - Completion of Dual Input Fast Program instruction - Completion of Sector Erase (SE) instruction - Completion of Block Erase 32KB (BE32K) instruction - Completion of Block Erase (BE) instruction - Completion of Chip Erase (CE) instruction - Program/Erase Suspend - Signal Block Lock (SBLK) instruction - Signal Block Unlock (SBULK) instruction - Gang Block Lock (GBLK) instruction - Gang Block Unlock (GBULK) instruction - Write Security Register (WRSCUR) instruction - Write Protect Selection (WPSEL) instruction (3) Read Identification (RDID) The RDID instruction is to read the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The ESMT Manufacturer ID is 8CH, the memory type ID is 25H as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 8) The sequence of issuing RDID instruction is: CE goes low → sending RDID instruction code → 24-bits ID data out on SO → to end RDID operation can drive CE to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CE goes high, the device is at standby stage. (Please refer Figure 4) (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in Program/Erase/Write Status Register condition). It is recommended to check the BUSY bit before sending a new instruction when a Program, Erase, or Write Status Register operation is in progress. The sequence of issuing RDSR instruction is: CE goes low → sending RDSR instruction code → Status Register data out on SO. (Please refer to Figure 5-1 and Figure 5-2) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 15/69 ESMT F25D08QA (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 3). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Block Protection Lock-Down (BPL) bit in accordance with Write Protection ( WP /SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (BUSY) of the Status Register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CE goes low→ sending WRSR instruction code→ Status Register data on SI→ CE goes high. (Please refer to Figure 6-1 and Figure 6-2) The CE must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Enable ( CE ) goes high. The BUSY bit still can be check out during the Write Status Register cycle is in progress. The BUSY sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 7. Protection Modes Mode Status register condition WP and BPL bit status Software protection mode (SPM) Status Register can be written in (WEL bit is set to "1") and the BPL, BP0-BP3 bits can be changed or WP =0 and BPL bit=0, The BPL, BP0-BP3 of Status Register bits cannot be changed WP =0, BPL bit=1 Hardware protection mode (HPM) WP =1 and BPL bit=0, Memory The protected area cannot be program or erase. or WP =1 and BPL=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When BPL bit=0, no matter WP /SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of BPL, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When BPL bit=1 and WP /SIO2 is high, the WREN instruction may set the WEL bit can change the values of BPL, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). Note: If BPL bit=1 but WP /SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When BPL bit=1, and then WP /SIO2 is low (or WP /SIO2 is low before BPL bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP /SIO2 to against data modification. Note: To exit the hardware protected mode requires WP /SIO2 driving high once the hardware protected mode is entered. If the WP /SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 16/69 ESMT F25D08QA (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCK, and data shifts out on the falling edge of SCK at a maximum frequency FRSCLK. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS goes low → sending READ instruction code → 3-byte address on SI → data out on SO → to end READ operation can use CS to high at any time during data out. (Please refer to Figure 7) (7) Read Data Bytes at Higher Speed (FAST_READ) The Fast Read instruction is for quickly reading data out. The address is latched on rising edge of SCK, and data of each bit shifts out on the falling edge of SCK at a maximum frequency FSCLK. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Fast Read instruction. The address counter rolls over to 0 when the highest address has been reached. SPI mode The sequence of issuing Fast Read instruction is: CE goes low → sending Fast Read instruction code → 3-byte address on SI → 1-dummy byte (default) address on SI → data out on SO → to end Fast Read operation can use CE to high at any time during data out. (Please refer to Figure 8-1) QPI mode The sequence of issuing Fast Read instruction is: CE goes low → sending Fast Read instruction code, 2 cycle → 24-bit address on SIO3~SIO0 → 4 dummy cycle → data out interleave on SIO3~SIO0 → to end QPI Fast Read operation can use CE to high at any time during data out. (Please refer to Figure 8-2) In the performance-enhancing mode, M[7:4] must be toggling with M[3:0] ; likewise M[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once M[7:4] is no longer toggling with M[3:0]; likewise M[7:0]=FFh, 00h, AAh or 55h and afterwards CE is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, Fast Read instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Fast Read Dual I/O (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCK at a maximum frequency FTSCLK1. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CE goes low → sending 2READ instruction → 24-bit address interleave on SIO1 & SIO0 → 4 dummy cycles on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 → to end 2READ operation can use CE to high at any time during data out (Please refer to Figure 9). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 17/69 ESMT F25D08QA (9) Fast Read Quad I/O (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of Status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCK at a maximum frequency FTSCLK2. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. SPI mode The sequence of issuing 4READ instruction is: CE goes low → sending 4READ instruction → 24-bit address interleave on SIO3,~SIO0 → 2+4 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0 → to end 4READ operation can use CE to high at any time during data out. (Please refer to Figure 10-1) W4READ instruction (E7) is also available is SPI mode for 4 I/O read. The sequence is similar to 4READ, but with only 4 dummy cycles. The clock rate runs at 84MHz. QPI mode The sequence of issuing 4READ instruction is: CE goes low → sending 4READ instruction→ 24-bit address interleave on SIO3~SIO0 → 2+4 dummy cycles → data out interleave on SIO3~SIO0 → to end 4READ operation can use CE to high at any time during data out. (Please refer to Figure 10-2) Another sequence of issuing 4 READ instruction especially useful in random access is : CE goes low → sending 4READ instruction → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit M[7:0] → 4 dummy cycles → data out still CE goes high → CE goes low (reduce 4 Read instruction) → 24-bit random access address (Please refer to Figure 22). In the performance-enhancing mode, M[7:4] must be toggling with M[3:0] ; likewise M[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once M[7:4] is no longer toggling with M[3:0]; likewise M[7:0]=FFh, 00h, AAh or 55h and afterwards CE is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 18/69 ESMT F25D08QA (10) Burst Read The device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. Next 4 clocks is to define wrap around depth. Definition as following table: Data Wrap Around Wrap Depth Data Wrap Around Wrap Depth 1xh No X 00h Yes 8-byte 1xh No X 01h Yes 16-byte 1xh No X 02h Yes 32-byte 1xh No X 03h Yes 64-byte The wrap around unit is defined within the 256-byte page, with random initial address. It’s defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is required to issue another “C0” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around enable. The device id default without Burst read. SPI Mode CE MODE3 0 1 2 3 4 5 6 7 8 1 0 9 10 11 12 13 14 15 SCK MODE0 SIO 1 0 0 0 0 0 H H H H L L L L QPI Mode CE MODE3 0 1 2 3 SCK MODE0 SIO3~ SIO 0 C0 H0 L0 MSB LSB MSB = Most Significant Bit LSB = Least Significant Bit Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 19/69 ESMT F25D08QA (11) Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure 11-1 and Figure 11-2) Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CE go high, the device will stay in the read mode and treat CE go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode. (12) Mode Bit Reset (FFh) To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh command code, 8 clocks, should be issued in Signal I/O sequence. In QPI mode, FFFFFFFFh command code, 8 clocks, in 4 I/O should be issue (Please refer to Figure 23) (13) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table of memory organization) is a valid address for Sector Erase (SE) instruction. The CE must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [AMS-A12] (AMS is the most significant address) select the sector address. The sequence of issuing SE instruction is: CE goes low → sending SE instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 14-1 and Figure 14-2) The self-timed Sector Erase Cycle time (TSE) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Sector Erase cycle is in progress. The BUSY sets 1 during the TSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 20/69 ESMT F25D08QA (14) 32K Byte Block Erase (BE32K) The 32K Byte Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see table of memory organization) is a valid address for Block Erase (BE32K) instruction. The CE must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CE goes low → sending BE32K instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 15-1 and Figure 15-2) The self-timed Block Erase Cycle time (TBE1) is initiated as soon as Chip Enable ( CE ) goes high. The BUSY bit still can be check out during the Block Erase cycle is in progress. The BUSY sets 1 during the TBE1 timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE32K) instruction will not be executed on the block. (15) 64K Byte Block Erase (BE) The 64K Byte Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to table of memory organization) is a valid address for Block Erase (BE) instruction. The CE must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CE goes low → sending BE instruction code → 3-byte address on SI → CE goes high. (Please refer to Figure 16-1 and Figure 16-2) The self-timed Block Erase Cycle time (TBE2) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Block Erase cycle is in progress. The BUSY sets 1 during the TBE2 timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. (16) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CE must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CE goes low → sending CE instruction code → CE goes high. (Please refer to Figure 17-1 and Figure 17-2) The self-timed Chip Erase Cycle time (TCE) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Chip Erase cycle is in progress. The BUSY sets 1 during the TCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 21/69 ESMT F25D08QA (17) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CE goes low → sending PP instruction code → 3-byte address on SI → at least 1-byte on data on SI → CE goes high. (Please refer to Figure 12-1 and Figure 12-2) The CE must be kept to low during the whole Page Program cycle; The CE must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (TPP) is initiated as soon as CE goes high. The BUSY bit still can be check out during the Page Program cycle is in progress. The BUSY sets 1 during the TPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (18) Quad Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad Page Program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CE goes low → sending 4PP instruction code → 3-byte address on SIO[3:0] → at least 1-byte on data on SIO[3:0] → CE goes high. (19) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CE goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CE goes low → sending DP instruction code → CE goes high. (Please refer to Figure 18-1 and Figure 18-2) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and software reset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction, the CE must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as CE goes high, a delay of TDP is required before entering the Deep Power-down mode. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 22/69 ESMT F25D08QA (20) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving CE High. When CE is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by TRES2, and CE must remain High for at least TRES2 (max), as specified in Table 15. AC Characteristics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The sequence is shown as Figure 19-1, Figure 19-2, Figure 20-1 and Figure 20-2. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The RES instruction is ended by CE goes high after the ID has been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCK while CE is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of TRES2 to transit to standby mode, and CE must remain high at least TRES2 (max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. (21) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CE pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for ESMT (8Ch) and the Device ID are shifted out on the falling edge of SCK with most significant bit (MSB) first as shown in Figure 21. The Device ID values are listed in Table 8 of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CE high. (22) QPI ID Read (QPIID) The QPIID Read instruction identifies the devices as F25D08QA and manufacturer as ESMT. The sequence of issue QPIID instruction is CE goes low → sending QPI ID instruction → Data out on SO → CE goes high. Most significant bit (MSB) first. Immediately following the command cycle the device outputs data on the falling edge of the SCK signal. The data output stream is continuous until terminated by a low-to-high transition of CE . The device outputs three bytes of data: manufacturer, device type, and device ID. Table 8. ID Definitions Command Type RDID (JEDEC ID) RES REMS F25D08QA manufacturer ID memory type memory density 8C 25 34 electronic ID in secured OTP mode & non lock down in secured OTP mode & lock down 34 74 F4 manufacturer ID device ID 8C 34 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 23/69 ESMT F25D08QA (23) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 512 bytes secured OTP mode. The additional 512 bytes secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CE goes low → sending ENSO instruction to enter Secured OTP mode → CE goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. (24) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 512 bytes secured OTP mode. The sequence of issuing EXSO instruction is: CE goes low→ sending EXSO instruction to exit Secured OTP mode→ CE goes high. (25) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in Program/Erase/Write Status Register/Write Security Register condition) and continuously. The sequence of issuing RDSCUR instruction is: CE goes low → sending RDSCUR instruction → Security Register data out on SO→ CE goes high. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512 bytes Secured OTP area cannot be update any more. While it is in 512 bytes secured OTP mode, main array access is not allowed. Table 9. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WPSEL E_FAIL P_FAIL Reserved Erase Suspend bit Program Suspend bit LDSO (indicate if lock-down) Secured OTP indicator bit 0 = normal WP mode 1 = individual mode (default = 0) 0 = normal Erase succeed 1 = individual Erase failed (default = 0) 0 = normal Program succeed 1= indicate Program failed (default = 0) - 0 = Erase is not suspended 1= Erase suspended (default = 0) 0 = Program is not suspended 1= Program suspended (default = 0) 0 = not lock-down 1 = lock-down (cannot program/erase OTP) 0 = non-factory lock 1 = factory lock Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit Non-volatile bit (OTP) Non-volatile bit (OTP) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 24/69 ESMT F25D08QA (26) Write Security Register (WRSCUR) The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 512 bytes Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can not be altered any more. The sequence of issuing WRSCUR instruction is: CE goes low → sending WRSCUR instruction → CE goes high. The CE must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. (27) Write Protection Selection (WPSEL) When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. The WREN (Write Enable) instruction is required before issuing WPSEL instruction. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods. The sequence of issuing WPSEL instruction is: CE goes low → sending WPSEL instruction to enter the individual block protect mode → CE goes high. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. Once WPSEL is set, it cannot be changed. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 25/69 ESMT F25D08QA WPSEL instruction function flow is as follows: WPSEL Flow Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 26/69 ESMT F25D08QA (28) Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using AMS-A16 or (AMS-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CE goes low → send SBLK/SBULK (36h/39h) instruction → send 3 address bytes assign one block (or sector) to be protected on SI pin → CE goes high. The CE must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. SBLK/SBULK instruction function flow is as follows: Block Lock Flow Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 27/69 ESMT F25D08QA Block Unlock Flow Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 28/69 ESMT F25D08QA (29) Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMS-A16 (or AMS-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has been protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CE goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CE goes high. (30) Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CE goes low → send GBLK/GBULK (7Eh/98h) instruction → CE goes high. The CE must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (31) Program/ Erase Suspend/ Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. Details as follows. To enter the suspend / resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable). Read security register bit2 (PSB) and bit3 (ESB) (please refer to Table 9) to check suspend ready information. Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during erase operation ESB=1, when erase operation resumes, ESB will be reset to "0". (31-1) Erase Suspend Erase suspend allow the interruption of all erase operations. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, 90h, 05h, 2Bh, B1h, C1h, 3Ch, 30h, 66h, 99h, C0h, 00h, ABh ) After issue erase suspend command, latency time 20us is needed before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note Figure 26-1, Figure 26-2 and Figure 26-3. ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. When issue a suspend command during program operation ESB=1, when erase operation resumes, ESB will be reset to "0". When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset. See Figure 26-1 for Suspend to Read latency. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 29/69 ESMT F25D08QA (31-2) Program Suspend Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, 90h, 05h, 2Bh, B1h, C1h,3Ch, 30h, 66h, 99h, C0h, 00h, ABh ) After issue program suspend command, latency time 20us is needed before issue another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note Figure 26-1, Figure 26-2 and Figure 26-3. PSB bit (Program Suspend Bit) indicates the status of Program suspend operation. When issue a suspend command during program operation PSB=1, when program operation resumes, PSB will be reset to "0". (32) Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status Register will be changed back to “0” The operation of Write-Resume is as follows: CE drives low → send write resume command cycle (30h) → drive CE high. By polling Busy Bit in Status Register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. When Erase Suspend is being resumed, the WEL bit need to be set again if user desire to conduct the program or erase operation. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disable, the write-resume command is effective. (33) No Operation (NOP) The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. (34) Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the F25D08QA the host drives CE low, sends the Reset-Enable command (66h), and drives CE high. Next, the host drives CE low again, sends the Reset command (99h), and drives CE high. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. A successful command execution will reset the device to SPI stand-by read mode, which are their respective default states, see Figure 27. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more latency time than recovery from other operations. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 30/69 ESMT F25D08QA (35) Fast Read Dual Output The Fast Read Dual Output instruction enable double data output in read mode. The address is latched on rising edge of SCK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCK at a maximum frequency FTSCLK1. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Fast Read Dual Output instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Fast Read Dual Output instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing Fast Read Dual Output instruction is: CE goes low → sending Fast Read Dual Output instruction → 24-bit address interleave on SIO0 → 8 dummy cycles → data out interleave on SIO1 & SIO0 → to end Fast Read Dual Output operation can use CE to high at any time during data out (Please refer to Figure 28). While Program/Erase/Write Status Register cycle is in progress, Fast Read Dual Output instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (36) Fast Read Quad Output The Fast Read Quad Output instruction enable quad data output in read mode. A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction. The address is latched on rising edge of SCK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCK at a maximum frequency FTSCLK1. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Fast Read Quad Output instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Fast Read Quad Output instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing Fast Read Quad Output instruction is: CE goes low → sending Fast Read Quad Output instruction→ 24-bit address interleave on SIO0 → 8 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0 → to end Fast Read Quad Output operation can use CE to high at any time during data out. (Please refer to Figure 29) While Program/Erase/Write Status Register cycle is in progress, Fast Read Quad Output instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (37) Quad Page Program (single address) The Quad Page Program (single address) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (single address). The Quad Page Program (single address) takes four pins: SIO0, SIO1, SIO2, and SIO3 as data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad Page Program (single address) cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing Quad Page Program (single address) instruction is: CE goes low → sending Quad Page Program (single address) instruction code → 24-bit address interleave on SIO0 → at least 1-byte on data on SIO[3:0] → CE goes high. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 31/69 ESMT F25D08QA (38) Daul Input Fast Program The Dual Input Fast Program instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit must be set to "1" before sending the Dual Input Fast Program. The Dual Input Fast Program takes two pins: SIO0, SIO1 as data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Dual Input Fast Program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing Dual Input Fast Program instruction is: CE goes low → sending Dual Input Fast Program instruction code → 24-bit address interleave on SIO0 → at least 1-byte on data on SIO[1:0] → CE goes high. (39) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SPI mode The sequence of issuing RDSFDP instruction is same as FAST_READ: CE goes low → send RDSFDP instruction (5Ah) → send 3-byte address on SI pin → send 1 dummy byte on SI pin → read SFDP code on SO → to end RDSFDP operation can use CE to high at any time during data out. (Please refer to Figure 32) SFDP is a standard of JEDEC. JESD216. v1.0. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 32/69 ESMT F25D08QA Table 10: Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 00h 06h 23:16 01h 01h Unused Contains 0xFFh and can never be changed 07h 31:24 FFh FFh ID number (JEDEC) 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Parameter Table Minor Revision Number Start from 0x00h 09h 15:08 00h 00h Parameter Table Major Revision Number Start from 0x01h 0Ah 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h Unused Contains 0xFFh and can never be changed 0Fh 31:24 FFh FFh ID number ( manufacturer ID) it indicates manufacturer ID 10h 07:00 8Ch 8Ch Parameter Table Minor Revision Number Start from 0x00h 11h 15:08 00h 00h Parameter Table Major Revision Number Start from 0x01h 12h 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h Parameter Table Pointer (PTP) First address of Flash Parameter table 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Unused Contains 0xFFh and can never be changed Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 33/69 ESMT F25D08QA Table 11: Parameter Table (0): JEDEC Flash Parameter Table Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) 01:00 01b Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b Write Enable Instruction Requested for Writing to Volatile Status Registers 0: Nonvolatile status bit 1: Volatile status bit (BP status register bit) 03 0b Write Enable Opcode Select for Writing to Volatile Status Registers 0: use 50h opcode, 1: use 06h opcode Note: If target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b Unused Contains 111b and can never be changed 07:05 111b 15:08 20h 16 0b 18:17 00b 19 0b 20 1b 4KB Erase Opcode 30h 31h E5h (1-1-2) Fast Read 2 0=not support, 1=support Address Bytes Number used in addressing flash array 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved Double Transfer Rate (DTR) Clocking 0=not support, 1=support (1-2-2) Fast Read 0=not support, 1=support (1-4-4) Fast Read 0=not support, 1=support 21 1b (1-1-4) Fast Read 0=not support, 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of 3 Wait states 0 0000b: Wait states (Dummy Clocks) not support (1-4-4) Fast Read Number of Mode Bits 4 000b: Mode Bits not support (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support (1-1-4) Fast Read Number of Mode Bits 000b: Mode Bits not support (1-1-4) Fast Read Opcode Elite Semiconductor Memory Technology Inc. FFh 007FFFFFh 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 44h 3Ah 3Bh 20h F0h 38h 39h Data (h) EBh 48h 23:21 010b 31:24 6Bh 6Bh Publication Date: Jul. 2013 Revision: 1.1 34/69 ESMT F25D08QA Table 11: Parameter Table (0): JEDEC Flash Parameter Table - Continued Description Add (Byte) Comment (1-1-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support (1-1-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 3Dh 0 0000b: Wait states(Dummy Clocks) not support (1-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 3Fh 0=not support, 1=support Unused (4-4-4) Fast Read Unused Unused (2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support Unused 0 0000b: Wait states (Dummy Clocks) not support (4-4-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 010b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 48h 04h BBh 0b 04 1b 07:05 111b 43h:41h 31:08 0xFFh 0xFFh 45h:44h 15:00 0xFFh 0xFFh 20:16 0 0000b 23:21 000b 47h 31:24 FFh FFh 49h:48h 15:00 0xFFh 0xFFh 20:16 0 0100b 23:21 010b 4Bh 31:24 EBh EBh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh FEh 00h 4Ah (4-4-4) Fast Read Opcode 3Bh 111b 46h (2-2-2) Fast Read Opcode (4-4-4) Fast Read Number of Wait states 07:05 00 Unused 0 0000b: Wait states (Dummy Clocks) not support 0 1000b Data (h) 03:01 40h 0=not support, 1=support (2-2-2) Fast Read Number of Wait states 04:00 3Eh (1-2-2) Fast Read Opcode (2-2-2) Fast Read Data1 (h/b) 3Ch (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number of Wait states DW Add (Bit) 44h 5 Sector Type 1 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 4 erase Opcode Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 35/69 ESMT F25D08QA Table 12: Parameter Table (1): Flash Parameter Table Description Comment Add (Byte) DW Add (Bit) Data1 (h/b) Data (h) VCC Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 20h 00h 20h VCC Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 50h 16h 50h 16h HW RESET pin 0=not support, 1=support 00 1b HW HOLD pin 0=not support, 1=support 01 1b Deep Power Down Mode 0=not support, 1=support 02 1b SW Reset 0=not support, 1=support 03 1b SW Reset Opcode Should be issue Reset Enable (66h) before Reset cmd. 11:04 1001 1001b (99h) Program Suspend/Resume 0=not support, 1=support 12 1b Erase Suspend/Resume 0=not support, 1=support 13 1b 14 1b 15 1b 66h 23:16 C0h C0h 67h 31:24 64h 64h 65h:64h Unused Wrap-Around Read mode 0=not support, 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support, 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile, 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect, 1=unprotect 6Bh:68h Secured OTP 0=not support, 1=support 11 1b Read Lock 0=not support, 1=support 12 0b Permanent Lock 0=not support, 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh F99Dh C8D9h FFh Notes: 1. 2. 3. 4. 5. 6. 7. h/b is hexadecimal or binary. (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4). Wait States is required dummy clock cycles after the address bits or optional mode bits. Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg, read performance enhance toggling bits) 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh. The maximum clock rate=33MHz when reading SFDP area. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 36/69 ESMT F25D08QA POWER-ON STATE The device is at below states when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VDD achieves below correct level: - VDD minimum at power-up stage and then after a delay of TVSL - GND at power-down Please note that a pull-up resistor on CE may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VDD is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VDD reaching the VWI level, a TPUW time delay is required before the device is fully accessible for commands like Write Enable (WREN), Page Program (PP), Quad Page Program (4PP), Quad Page Program (single address), Dual Input Fast Program, Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE), Chip Erase (CE), WRSCUR and Write Status Register (WRSR). If the VDD does not reach the VDD minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - TPUW after VDD reached VWI level - TVSL after VDD reached VDD minimum level The device can accept read command after VDD reached VDD minimum and a time delay of TVSL, even time of TPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VDD level, the VDD rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VDD drops below VWI level, all operations are disabled and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 37/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 06 SI MSB HIGH IMPEDANCE SO Figure 2-1: Write Enable (WREN) Sequence (SPI Mode) CE SCK 0 1 MODE3 MODE0 06 SIO3~ SIO0 Figure 2-2: Write Enable (WREN) Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 04 SI MSB SO HIGH IMPEDANCE Figure 3-1: Write Disable (WRDI) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 38/69 ESMT F25D08QA CE 0 1 MODE3 MODE0 SCK 04 SIO3~ SIO0 Figure 3-2: Write Disable (WRDI) Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031 9F SI MSB HIGH IMPEDANCE SO 8C Memory type MSB Memory density MSB MSB Figure 4: Read Identification (RDID) Sequence (SPI Mode) CE MODE3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE0 05 SI MSB SO HIGH IMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB Status Register Data Out Figure 5-1: Read Status Register (RDSR) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 39/69 ESMT F25D08QA CE MODE3 0 1 2 3 SCK MODE0 SIO3~SIO0 05 H0 L0 MSB LSB Status Register Data Out (Byte) Figure 5-2: Read Status Register (RDSR) Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 Stauts Register Data In 01 06 SI MSB 7 6 5 4 3 2 1 0 MSB HIGH IMPEDANCE SO Figure 6-1: Write Enable (WREN) and Write Status Register (WRSR) Sequence (SPI Mode) CE MODE3 0 1 2 3 SCK MODE0 SIO0 C4, C0 4 0 SIO1 C5, C1 5 1 SIO2 C6, C2 6 2 SIO3 C7, C3 7 3 CMD (01H) Status Register Data In (Byte) Figure 6-2: Write Status Register (WRSR) Sequence (QPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 40/69 ESMT F25D08QA CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 03 SI 15 1 6 ADD. MSB 23 24 ADD. 31 32 3 9 40 47 48 55 56 70 63 64 A DD. MSB HIGH IMPEDANCE SO N N+1 N+2 N+3 N+4 D OU T DOUT DOUT D OU T D OU T 39 40 47 48 55 56 63 64 71 72 MSB Figure 7: Read Sequence CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 ADD. 0B SI 15 16 MSB 23 24 ADD. 31 32 ADD. 80 X MSB HIGH IMPEDANCE SO N N+1 N+2 N+3 N+4 DOUT DOUT DOUT D OUT DOUT MSB Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 8-1: Fast Read Sequence (SPI Mode) CE MODE3 SCK MODE0 SIO3~SIO0 0 1 0B 2 A5 3 A4 4 5 6 7 A3 A2 A1 A0 24 bit address Data In 8 X 9 X 10 X 11 X 12 H0 MSB 13 L0 14 15 H1 L1 LSB MSB Data Out 1 (Byte) H2 LSB MSB Data Out 2 (Byte) Figure 8-2: Fast Read Sequence (QPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 41/69 ESMT F25D08QA CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 31 32 35 36 39 40 IO0 switches from Input to Ouput 22 20 18 16 14 12 10 8 BB SIO0 6 4 2 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 0 MSB SIO1 HIG H IMPEDANCE 23 21 19 17 15 13 11 9 A23-16 7 A15-8 5 3 DOUT D OU T DOUT DOUT DOUT N N+1 N+2 N+3 N+4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 1 A7-0 Figure 9: Fast Read Dual I/O (2READ) Sequence CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IO0 switches from Input to Ouput Dummy EB SIO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 7 3 MSB SIO1 SIO2 SIO3 HIGH IMPE DANCE HIGH IMPEDANCE HIGH IMP EDANCE A 23-0 M7 -0 N N+1 N+2 DOUT DOUT DOUT Figure 10-1: Fast Read Quad I/O (4READ) Sequence (SPI Mode) CE MODE3 SCK MODE0 SIO3~SIO0 0 EB 1 2 A5 3 A4 4 5 6 7 A3 A2 A1 A0 24 bit address Data In 8 9 M 7-4 M 3-0 10 X 11 X 12 13 X X 4 dummy 14 H0 MSB 15 16 17 L0 H1 L1 LSB MSB Data Out 1 (Byte) LSB Data Out 2 (Byte) Figure 10-2: Fast Read Quad I/O (4READ) Sequence (QPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 42/69 ESMT F25D08QA CE 0 1 2 3 MODE3 SCK MODE0 4 5 6 7 8 9 10 11 12 13 14 15 16 IO0 switches from Input to Ouput Dummy 20 16 1 2 8 4 0 4 0 4 0 4 0 4 0 SIO1 21 1 7 13 9 5 1 5 1 5 1 5 1 5 1 SIO2 22 18 1 4 1 0 6 2 6 2 6 2 6 2 6 2 SIO3 23 19 1 5 11 3 7 3 7 3 7 3 7 3 SIO0 7 A23-0 M7-0 N N+1 N+2 D OUT D OU T D OU T Note: The mode b its [M3 -M0] are “don’t care”. However , the IO pins sho uld be high-imped ance prior to the falling edg e of the first da ta clock. Figure 11-1: Fast Read Quad I/O (4READ) enhance performance Sequence (SPI Mode) CE MODE3 SCK MODE0 SIO3~SIO0 0 A5 1 A4 2 3 4 A3 A2 A1 5 6 7 A0 M7- 4 M 3-0 8 X 24 bit address 9 10 X X 4 dummy 11 X 12 H0 MSB 13 L0 15 H1 L1 LSB MSB Data O ut 1 (Byte) Data In 14 LSB Data Out 2 (Byte) Figure 11-2: Fast Read Quad I/O (4READ) enhance performance Sequence (QPI Mode) CE MODE3 SCK MODE0 SS 23 24 31 32 39 SS 02 SI MSB SO 15 16 0 1 2 3 4 5 6 7 8 ADD. MSB HIGH IMPEDANCE ADD. A DD. D IN 0 DIN1 SS SS D IN25 5 MSB LSB SS Figure 12-1: Page Program (PP) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 43/69 ESMT F25D08QA CE SS MODE3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 ............................... SS SCK MODE0 SIO3~SIO0 02 A5 A4 A3 A2 A1 A0 H0 MSB 24 bit address L0 LSB MSB Data In 1 (Byte) Data In H1 L1 H2 LSB MSB Data In 2 (Byte) L2 SS SS LSB H255 L255 MSB Data In 3 (Byte) LSB Data In 256 (Byte) Figure 12-2: Page Program (PP) Sequence (QPI Mode) CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 15 1 6 17 18 19 20 21 22 23 2425 SS MSB 38 SIO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 SS 4 0 2117 13 9 5 1 5 1 5 1 5 1 5 1 SS 5 1 SS 6 2 SS 7 3 MSB SIO1 SIO2 SIO3 A2 3-0 D IN 0 DIN1 DIN2 DIN3 D IN25 5 Figure 13: Quad Page Program (4PP) Sequence CE MODE 3 SCK MODE0 0 1 2 3 4 5 6 7 8 20 SI MSB SO 15 16 ADD. 23 24 ADD. 31 ADD. MSB HIGH IMPEDANCE Figure 14-1: Sector Erase (SE) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 44/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 SIO3~SIO0 1 2 20 3 A5 A4 4 5 6 7 A3 A2 A1 A0 MSB 24 bit address Data In Figure 14-2: Sector Erase (SE) Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 15 16 ADD. 52 SI MSB 23 24 ADD. 31 ADD. MSB HIGH IMPEDANCE SO Figure 15-1: 32K-byte Block Erase (BE32K) Sequence (SPI Mode) CE MODE3 SCK MODE0 SIO3~SIO0 0 52 1 2 A5 3 A4 4 5 6 7 A3 A2 A1 A0 MSB 24 bit address Data In Figure 15-2: 32K-byte Block Erase (BE32K) Sequence (QPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 45/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 15 16 ADD. D8 SI MSB 23 24 ADD. 31 ADD. MSB HIGH IMPEDANCE SO Figure 16-1: 64K-byte Block Erase (BE) Sequence (SPI Mode) CE MODE3 SCK MODE0 SIO3~SIO0 0 1 2 D8 A5 3 A4 4 5 6 7 A3 A2 A1 A0 MSB 24 bit address Data In Figure 16-2: 64K-byte Block Erase (BE) Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 SI 60 or C7 MSB SO HIGH IMPEDANCE Figure 17-1: Chip Erase (CE) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 46/69 ESMT F25D08QA CE SCK 0 1 MODE3 MODE0 60 or C7 SIO3~ SIO0 Figure 17-2: Chip Erase (CE) Sequence (QPI Mode) CE MODE3 0 1 2 3 4 5 6 7 T DP SCK MODE0 B9 SI MSB Standby Current Deep Power Down Current (ISB2) Figure 18-1: Deep Power-down (DP) Instruction (SPI Mode) CE TDP MODE3 SCK 0 1 MODE0 SIO3~ SIO0 B9 Standby current Deep P ower Down current Figure 18-2: Deep Power-down (DP) Instruction (QPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 47/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 30 9 31 32 33 34 35 36 37 38 TRES2 SS 3 Dummy Bytes SS AB SI MSB HIGH IMPEDANCE SO SS Electronic-Signature Data Out MSB Deep Power Down Current (ISB2) Standby Current Figure 19-1: Read Electronic Signature (RES) Sequence (SPI Mode) CE MODE3 SCK MODE0 0 SIO3~SIO0 1 AB 2 A5 3 A4 4 5 6 7 A3 A2 A1 A0 MSB 8 9 H0 L0 MSB LSB 24 bit address Data Out Data In Deep Power Down Current Standby Current Figure 19-2: Read Electronic Signature (RES) Sequence (QPI Mode) CE MODE3 0 1 2 3 4 5 6 7 SCK MODE0 T RES1 AB SI MSB HIGH IMPEDANCE SO Deep Power Down Current (ISB2) Standby Current Figure 20-1: Release from Deep Power Down (RDP) Instruction (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 48/69 ESMT F25D08QA CE TRES1 0 1 MODE3 SCK MODE0 AB SIO3~ SIO0 Standby current Deep Po wer Down current Figure 20-2: Release from Deep Power Down (RDP) Instruction (QPI Mode) CE MODE3 SCK MODE0 15 16 0 1 2 3 4 5 6 7 8 90 SI 00 39 40 47 4 8 55 56 63 1 00 ADD MSB MSB SO 31 32 23 24 HIGH IMPEDANCE 8C Device ID 8C Device ID HIGH IMPEDA NCE MSB Note: The Manufacture’s an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE. 1. 00H will output the Manufacture’s ID first a nd 01H will output Device ID first b efore toggling between the two. Figure 21: Read Electronic Manufacture ID and Device ID (REMS) Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 49/69 ESMT F25D08QA CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 IO0 switches from Input to Ouput Dummy E7 SIO0 20 16 12 8 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 MSB HIGH IMPE DANCE SIO1 HIGH IMPEDANCE SIO2 HIGH IMP EDANCE SIO3 A 23-0 N N+1 N+2 DOUT DOUT DOUT Figure 22: Fast Read Quad I/O (4 dummy cycles) Sequence (SPI Mode) Mode bit Re set for Quad I/O CE MODE3 SCK MODE0 0 1 2 3 4 SIO0 FF (SPI ) FFFFFFFF (QPI) SIO 1 Don’t Care (SPI) FFFFFFFF (QPI ) SIO2 Don’t Care (SPI) FFFFFFFF (QPI) SIO3 Don’t Care (SPI) FFFFFFFF (QPI) 5 6 7 Figure 23: Mode Bit Reset Sequence (SPI and QPI Mode) CE 0 1 2 3 4 5 6 7 MODE3 SCK MODE0 MODE3 0 1 2 3 4 5 6 7 MODE0 SI 66 MSB SO 99 MSB HIGH IMPEDANCE Figure 24-1: Reset Sequence (SPI Mode) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 50/69 ESMT F25D08QA TC EH CE SCK 0 1 MODE3 MODE0 66 SIO3~ SIO0 99 Figure 24-2: Reset Sequence (QPI Mode) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 35 SI MSB SO HIGH IMPEDANCE Figure 25: Enable Quad I/O (EQIQ) Sequence Programe latency: 20us Erase latency: 20us CE Suspend Command [B0] Read Command Figure 26-1: Suspend to Read Latency Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 51/69 ESMT F25D08QA TSE / TBE / T PP CE Resume Command [30] Read Command Figure 26-2: Resume to Read Latency 1ms CE Resume Command [30] Suspend Command [B0] Figure 26-3: Resume to Suspend Latency Standy-by Mode 66 CE 99 TRCR TRCP TRCE Mode TR CR: 20us (Recovery Time from Read) TR CP: 20us (Recovery Time from Progam) TR CE: 12ms (Recovery Time from Erase) Figure 27: Software Reset Recovery Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 52/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 3B ADD. MSB ADD. 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 ADD. MSB HIGH IMPEDANCE SIO1 55 56 51 52 IO0 switches from In put to Ouput Dummy SIO0 47 48 D OUT DOUT D OU T D OU T D OUT N N+1 N+2 N+3 N+4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 Note: The input data durin g the dummy clocks is “don’t care”. However , the IO0 pin should be high-impedance prior to the falling edge of the first data clock. Figure 28: Fast Read Dual Output Sequence CE MODE3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 4142 43 44 45 46 47 48 MODE0 Dummy 6B SIO0 ADD. MSB MSB SIO1 SIO2 SIO3 HIGH IMPEDANCE ADD. A DD. IO0 switches from Input to Ouput 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 HIGH IMPEDANCE 6 2 HIGH IMPEDANCE 7 3 N N+1 N+2 N+3 N+4 D OU T DOUT DOUT D OU T D OUT Note: The input data du ring the dummy clocks is “don’t care”. However , the IO pins should be high-impeda nce pri or to the falling edge of the first data clock. Figure 29: Fast Read Quad Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 53/69 ESMT F25D08QA CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 15 1 6 23 24 31 32 33 34 35 36 37 3839 SS 32 SIO0 MSB ADD. MSB ADD. A DD. SIO1 4 0 4 0 4 0 4 0 SS 4 0 5 1 5 1 5 1 5 1 SS 5 1 SS 6 2 SS 7 3 SIO2 SIO3 D IN 0 D IN 1 DIN2 DIN3 DIN2 55 Figure 30: Quad Page Program (single address) Sequence CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 23 24 31 32 33 34 35 36 37 3839 SS A2 SIO0 ADD. MSB MSB SIO1 15 1 6 HIGH IMPEDANCE ADD. A DD. 6 4 2 0 6 4 2 0 SS 2 0 7 5 3 1 7 5 3 1 SS 3 1 D IN 0 D IN1 DIN 255 Figure 31: Dual Input Fast Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 54/69 ESMT F25D08QA CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 5A SI MSB SO 15 16 ADD. 23 24 ADD. 31 32 ADD. 39 40 47 48 55 56 63 64 71 72 80 X MSB HIGH IMPENANCE N N+1 N+2 N+3 N+4 DOUT DOUT DOUT D OUT DOUT MSB Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 32: Read Serial Flash Discoverable Parameter (RDSFDP) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 55/69 ESMT F25D08QA ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+1.0V TABLE 13: AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz See Figures 38 and 39 TABLE 14: OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 1.65~2 V Ambient Operating Temperature TA -40 ~ +85 ℃ TABLE 15: DC OPERATING CHARACTERISTICS Symbol Parameter Min Limits Typ. Max Unit Test Condition IDDR1 Read Current @ 84MHz 10 15 mA CE =0.1 VDD/0.9 VDD, SO=open IDDR2 Read Current @ 104MHz 15 20 mA CE =0.1 VDD/0.9 VDD, SO=open IDDW Program and Write Status Register Current 15 20 mA CE =VDD Sector and Block Erase Current 15 20 mA CE =VDD Chip Erase Current 15 20 mA CE =VDD IDDE ISB1 Standby Current ISB2 Deep Power Down Current ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 25 -0.5 0.8 x VDD VDD-0.2 Elite Semiconductor Memory Technology Inc. 30 50 µA CE =VDD, VIN =VDD or VSS 5 15 ±2 ±2 0.2 x VDD VDD +0.4 0.2 µA CE =VDD, VIN =VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max µA µA V V V V IOL=100uA IOH=-100 µA Publication Date: Jul. 2013 Revision: 1.1 56/69 ESMT F25D08QA TABLE 16: LATCH UP CHARACTERISTIC Symbol ILTH1 Parameter Latch Up Minimum Unit Test Method 100 + IDD mA JEDEC Standard 78 Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 17: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter Description COUT1 Output Pin Capacitance CIN1 Input Capacitance Test Condition Maximum VOUT = 0V 8 pF VIN = 0V 6 pF Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 18: AC OPERATING CHARACTERISTICS Symbol Parameter Min. Typ. Max. Unit FSCLK Serial Clock Frequency for FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR instruction 104 MHz FRSCLK Serial Clock Frequency for READ instruction 33 MHz FTSCLK1 Serial Clock Frequency for 2READ instruction 84 MHz FTSCLK25 Serial Clock Frequency for 4READ instruction TSCKH Serial Clock High Time TSCKL Serial Clock Low Time TCLCH2 84/ 104 MHz Serial (FSCLK) 4.5 ns Normal Read (FRSCLK) 12 ns Serial (FSCLK) 4.5 ns Normal Read (FRSCLK) 12 ns Clock Rise Time (peak to peak) 0.1 V/ns TCHCL2 Clock Fall Time (peak to peak) 0.1 V/ns TCES1 CE Active Setup Time 5 ns TCEH1 CE Active Hold Time 5 ns TCHS1 CE Not Active Setup Time 5 ns TCHH1 CE Not Active Hold Time 5 ns TCPH Read 12 ns CE High Time Write / Erase / Program 30 ns TCHZ CE High to High-Z Output TCLZ SCK Low to Low-Z Output 0 ns TDS Data In Setup Time 2 ns TDH Data In Hold Time 5 ns THLS HOLD Low Setup Time 5 ns THHS HOLD High Setup Time 5 ns Elite Semiconductor Memory Technology Inc. 8 ns Publication Date: Jul. 2013 Revision: 1.1 57/69 ESMT F25D08QA TABLE 18: AC OPERATING CHARACTERISTICS - Continued Symbol Parameter Min. Typ. Max. Unit THLH HOLD Low Hold Time 5 ns THHH HOLD High Hold Time 5 ns THZ3 HOLD Low to High-Z Output 8 ns TLZ3 HOLD High to Low-Z Output 8 ns TOH Output Hold from SCK Change TV Output Valid from SCK TWHSL4 0 ns Loading: 30pF 8 ns Loading: 15pF 6 ns Write Protect Setup Time before CE Low 20 ns TSHWL4 Write Protect Hold Time after CE High 100 ns TDP3 CE High to Deep Power Down Mode 10 us TRES13 CE High to Standby Mode ( for DP) 10 us TRES23 CE High to Standby Mode (for RES) 10 us CE High to next Instruction after Suspend 20 us TRCR Recovery time to read 20 us TRCP Recovery time to program 20 us TRCE Recovery time to erase 12 ms TSUS 3 Note: 1. 2. 3. 4. 5. Relative to SCK. TSCKH + TSCKL must be less than or equal to 1/ FCLK. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a Write Status Register instruction when Block- Protection-Look (BPL) bit is set at 1. When dummy cycle = 4, clock rate = 84 MHz; when dummy cycle = 6, clock rate =104 MHz Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 58/69 ESMT F25D08QA TABLE 19: ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Symbol Typ2 Max3 Unit Sector Erase Time (4KB) TSE 30 200 ms Block Erase Time (32KB) TBE1 100 200 ms Block Erase Time (64KB) TBE2 130 250 ms Chip Erase Time TCE 2 6 s Write Status Register Time TW 40 ms Page Programming Time TPP 0.4 0.8 ms 100,000 - Cycles 20 - Years Erase/Program Cycles1 Data Retention Notes: 1. 2. 3. Not 100% Tested, Excludes external system level over head. Typical values measured at 25°C, 1.8V. Maximum values measured at 85°C, 1.65V. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 59/69 ESMT F25D08QA Figure 33: Serial Input Timing Diagram Figure 34: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 60/69 ESMT F25D08QA CE SCK SO SI HOLD Figure 35: HOLD Timing Diagram WP T WHSL TSHWL CE SCK SI HIGH IMPEDANCE SO Figure 36: Write Protect setup and hold timing during WRSR when BPL = 1 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 61/69 ESMT F25D08QA VDD VDD (max) Program, Erase and Write command is ignored CE must track VDD VDD (min) TVSL Reset State Read command is allowed Device is fully accessible VWI TPUW Time Figure 37: Power-Up Timing Diagram Table 20: Power-Up Timing and VWI Threshold Parameter Unit Symbol Min. VDD(min) to CE low TVSL 300 Time Delay before Write instruction TPUW 1 10 ms VWI 1 1.4 V Write Inhibit Threshold Voltage Max. us Note: These parameters are characterized only. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 62/69 ESMT F25D08QA Input timing reference level Output timing reference level 0.8VDD 0.7V DD 0.3VDD 0.2VDD AC Measurement Level 0.5V DD Note : Input pulse rise and fall time are <5ns Figure 38: AC Input/Output Reference Waveforms Figure 39: A Test Load Example Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 63/69 ESMT DIMENSIONS SOIC ( 150 mil ) 5 GAUGE PLANE 0 0.25 E 8 H PACKING 8-LEAD F25D08QA L DETAIL "X" 1 4 e b L1 "X" A1 A2 A C D SEATING PLANE Dimension in mm Dimension in inch Symbol Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A 1.35 1.60 1.75 0.053 0.063 0.069 D 4.80 4.90 5.00 0.189 0.193 0.197 A1 0.10 0.15 0.25 0.004 0.006 0.010 E 3.80 3.90 4.00 0.150 0.154 0.157 A2 1.25 1.45 1.55 0.049 0.057 0.061 L 0.40 0.66 0.86 0.016 0.026 0.034 b 0.33 0.406 0.51 0.013 0.016 0.020 e c 0.19 0.203 0.25 0.0075 0.008 0.010 L1 1.00 1.05 1.10 0.039 0.041 0.043 H 5.80 6.00 6.20 0.228 0.236 0.244 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 64/69 ESMT F25D08QA PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( official name – 208 mil ) 5 1 4 E1 8 E θ b e A A2 D L A1 L1 SEATING PLANE Dimension in mm Dimension in inch Symbol DETAIL "X" Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A --- --- 2.16 --- --- 0.085 E 7.70 7.90 8.10 0.303 0.311 0.319 A1 0.05 0.15 0.25 0.002 0.006 0.010 E1 5.18 5.28 5.38 0.204 0.208 0.212 A2 1.70 1.80 1.91 0.067 0.071 0.075 L 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e c 0.19 0.20 0.25 0.007 0.008 0.010 L1 1.27 1.37 1.47 0.050 0.054 0.058 D 5.13 5.23 5.33 0.202 0.206 0.210 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 65/69 ESMT PACKING 8-LEAD F25D08QA DIMENSIONS VSOP (150 mil) D A2 See Detail "A" B E1 E 0 B L A1 Pin 1 identifier Detail "A" b b1 c1 A c Base metal with plating -Ce Symbol A A1 A2 b b1 c c1 D E E1 L e Y Θ b Y Min Dimension in mm Norm - - 0.05 0.65 0.35 0.35 0.09 0.09 4.80 5.80 3.80 0.40 0.10 - 0° 0.70 0.42 - 4.90 6.00 3.90 0.71 1.27 BSC - Detail "B"-"B" Seating plane Min Dimension in inch Norm - - 0.002 0.026 0.014 0.014 0.004 0.004 0.189 0.228 0.150 0.016 0.004 0.028 0.017 Max 0.88 0.15 0.75 0.48 0.46 0.16 0.16 5.00 6.20 4.00 1.27 0.10 10° 0° - - 0.193 0.236 0.154 0.028 0.050 BSC - Max 0.034 0.006 0.030 0.019 0.018 0.006 0.006 0.197 0.244 0.157 0.050 0.004 10° (Revision date : Jan 03 2013) Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 66/69 ESMT F25D08QA PACKING DIMENSIONS 8-CONTACT WSON ( 6x5 mm ) D E A PIN# 1 A1 L DETAIL : "B" "A" E2 b e D2 DETAIL : "A" "B" PIN# 1 Symbol A A1 b D D2 E E2 e L Min 0.70 0.00 0.35 5.90 3.30 4.90 3.90 0.55 Dimension in mm Norm 0.75 0.02 0.40 6.00 3.40 5.00 4.00 1.27 BSC 0.60 Max 0.80 0.05 0.45 6.10 3.50 5.10 4.10 Min 0.028 0.000 0.014 0.232 0.130 0.193 0.154 0.65 0.022 Dimension in inch Norm 0.030 0.001 0.016 0.236 0.134 0.197 0.157 0.050 BSC 0.024 Max 0.031 0.002 0.018 0.240 0.138 0.201 0.161 0.026 Controlling dimension : millimeter Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 67/69 ESMT F25D08QA Revision History Revision Date 0.1 2012.03.26 Original 0.2 2012.06.05 1. Modify speed from 104MHz to 100MHz 2. Correct WRSCUR command 3. Correct D2(Min), D2(Max), E2(Min) and E2(Max) value of WSON packing dimensions 0.3 2012.07.27 1. Return speed to 104MHz 2. Modify product ID and ambient operating temperature 3. Add 8 lead SOIC (150 mil) package 0.4 2012.08.08 Modify data retention 0.5 2012.09.05 Add VVSOP package 0.6 2012.09.27 Modify the specification of TBE1 and TBE2 0.7 2012.10.30 1. Modify VVSOP to VSOP and the thickness 2. Correct the description of Block Protection, Block Protection Lock-Down 0.8 2013.01.09 Modify Product ID of VSOP (150mil) 1.0 2013.03.11 Delete "Preliminary" 2013.07.30 1. Add typical value of current 2. Modify the specification of ISB2, TSCKH and TSCKL 3. Add SBLK, SBULK, GBLK, GBULK, WRSCUR and WPSEL into the description of WEL, WREN and WRDI 4. Correct the command of 2READ for SPI mode and of Fast Read for QPI mode 5. Correct features 6. Correct the unit of TRCP 7. Add secured OTP definition 1.1 Elite Semiconductor Memory Technology Inc. Description Publication Date: Jul. 2013 Revision: 1.1 68/69 ESMT F25D08QA Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 69/69