PWM, Step-Down DC-to-DC Controller with Margining and Tracking ADP1822 FEATURES GENERAL DESCRIPTION Wide input voltage range: 1 V to 24 V Wide output voltage range: 0.6 V to 85% of input voltage 1% accuracy, 0.6 V reference voltage Output voltage margining control Output voltage tracking All N-channel MOSFET 300 kHz, 600 kHz, or up to 1.2 MHz synchronized frequency No current sense resistor required Power-good output Programmable soft start with reverse current protection Current-limit protection Thermal overload protection Overvoltage protection Undervoltage lockout 1 μA shutdown supply current Small, 24-lead QSOP package The ADP1822 is a versatile and inexpensive synchronous voltagemode PWM step-down controller. It drives an all N-channel power stage to regulate an output voltage as low as 0.6 V. The ADP1822 regulated output can track another power supply and be dynamically adjusted up or down with the controller’s margining-control inputs, making it ideal for high reliability applications. It is well suited for a wide range of high power applications, such as DSP power and processor core power in telecom, medical imaging, high performance servers, and industrial applications. It operates from a 3.0 V to 5.5 V supply with power input voltage ranging from 1.0 V to 24 V. The ADP1822 can operate at any frequency between 300 kHz and 1.2 MHz either by synchronizing with an external source or an internally generated, logic-controlled clock of 300 kHz or 600 kHz. It includes an adjustable soft start to allow sequencing and quick power-up while preventing input inrush current. Output reverse-current protection at startup prevents excessive output voltage excursions. The adjustable, virtually lossless current-limit scheme reduces external part count and improves efficiency. APPLICATIONS Telecom and networking systems High performance servers Medical imaging systems DSP core power supplies Microprocessor core power supplies Mobile communication base stations Distributed power SHDN FREQ SYNC PWGD MAR MSEL DH SW CSL DL PGND 0.1µF 96 IRF3711 1µH 1000µF 4V IRF3711 2.2pF TRKP 1nF 158kΩ 3.3V OUTPUT 95 6.18kΩ OUTPUT 1.8V, 15A 20kΩ FB TRKN COMP MDN SS AGND DGND MUP 80.6kΩ 309pF BST VCC ADP1822 97 POWER INPUT 2.25V TO 24V 94 10kΩ 93 1.8V OUTPUT 92 91 90 316kΩ 100nF TRACKING SIGNAL INPUT Figure 1. Typical Operating Circuit 89 05311-006 VCC 1µF 15pF 180µF 20V EFFICIENCY (%) 1µF CMOSH-3 10Ω 05311-001 BIAS INPUT 5V The ADP1822 operates over the −40°C to +85°C temperature range and is available in a 24-lead QSOP package. 88 87 0 2 4 6 8 10 12 14 16 LOAD CURRENT (A) Figure 2. Efficiency vs. Load Current, 5 V Input Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADP1822 TABLE OF CONTENTS Features .............................................................................................. 1 Switching Frequency Control ................................................... 13 Applications....................................................................................... 1 Compensation............................................................................. 13 General Description ......................................................................... 1 Power-Good Indicator............................................................... 13 Revision History ............................................................................... 2 Shutdown Control...................................................................... 13 Specifications..................................................................................... 3 Application Information................................................................ 14 Absolute Maximum Ratings............................................................ 5 Selecting the Input Capacitor ................................................... 14 ESD Caution.................................................................................. 5 Output LC Filter ......................................................................... 14 Simplified Block Diagram ............................................................... 6 Selecting the MOSFETS ............................................................ 15 Pin Configuration and Function Descriptions............................. 7 Setting the Current Limit .......................................................... 15 Typical Performance Characteristics ............................................. 9 Feedback Voltage Divider ......................................................... 16 Theory of Operation ...................................................................... 12 Setting the Voltage Margin........................................................ 16 Current-Limit Scheme............................................................... 12 Compensating the Regulator .................................................... 16 Output Voltage Margining ........................................................ 12 Setting the Soft Start Period...................................................... 19 Output Voltage Tracking ........................................................... 12 Synchronizing the Converter.................................................... 19 Soft Start ...................................................................................... 12 Setting the Output Voltage Tracking ....................................... 19 High-Side Driver (BST and DH).............................................. 13 Application Circuits ....................................................................... 20 Low-Side Driver (DL) ................................................................ 13 Outline Dimensions ....................................................................... 21 Input Voltage Range ................................................................... 13 Ordering Guide .......................................................................... 21 Setting the Output Voltage ........................................................ 13 REVISION HISTORY 8/06—Rev. A to Rev. B Change to Title.................................................................................. 1 Change to General Description ...................................................... 1 Changes to Figure 6.......................................................................... 9 Changes to Output Voltage Margining Section.......................... 12 Changes to Table 4.......................................................................... 12 1/06—Rev. 0 to Rev. A Changes to Figure 1.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Input Voltage Range Section .................................... 13 Changes to Selecting the Input Capacitor Section ..................... 14 Added Equation 1; Renumbered Sequentially............................ 14 Changes to Equation 7 and Equation 8 ....................................... 15 Changes to Selecting the MOSFETS Section.............................. 15 Added Equation 9; Renumbered Sequentially ........................... 15 Changes to Equation 10................................................................. 15 Changes to Equation 22................................................................. 17 Changes to Compensating the Regulator Section...................... 17 Changes to Figure 19 and Figure 20............................................. 17 Changes to Equation 27................................................................. 17 Changes to Equation 34................................................................. 18 7/05—Revision 0: Initial Version Rev. B | Page 2 of 24 ADP1822 SPECIFICATIONS VVCC = VPVCC = VSHDN = VFREQ = VTRKN = 5 V, SYNC = MAR = MSEL = GND. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TA = 25°C, unless otherwise specified. Table 1. Parameter POWER SUPPLY Input Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Quiescent Current Shutdown Current Power Stage Supply Voltage ERROR AMPLIFER FB Regulation Voltage FB Input Bias Current Error Amplifier Open-Loop Voltage Gain COMP Output Sink Current COMP Output Source Current PWM CONTROLLER PWM Peak Ramp Voltage DL Minimum On Time SOFT START SS Pull-Up Resistance SS Pull-Down Resistance OSCILLATOR Oscillator Frequency Synchronization Range SYNC Minimum Pulse Width CURRENT SENSE CSL Threshold Voltage CSL Output Current Current Sense Blanking Period GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DL Low to DH High Dead Time DH Low to DL High Dead Time VOLTAGE MARGINING High Output Voltage Margin Resistance Low Output Voltage Margin Resistance TRACKING Tracking Comparator Input Offset Tracking Comparator Delay Tracking Comparator Common-Mode Input Voltage Range TRKP Pull-Up Resistance Conditions VVCC rising VVCC IVCC + IVCC, not switching SHDN = GND Min 3.0 2.5 Typ 2.7 0.1 1 1.0 600 +1 70 600 110 Max Unit 5.5 2.9 V V V mA μA V 2 10 24 TA = −40°C to +85°C 594 –100 606 +100 mV nA dB μA μA FREQ = VCC (300 kHz) 140 1.25 170 200 V ns SS = GND VSS = 0.6 V 1.65 95 2.5 4.2 kΩ kΩ FREQ = GND, TA = −40°C to +85°C FREQ = VCC, TA = −40°C to +85°C FREQ = GND FREQ = VCC 250 470 300 600 310 570 375 720 600 1200 80 kHz kHz kHz kHz ns Relative to PGND VCSL = 0 V, TA = −40°C to +85°C −30 42 0 50 160 +30 54 mV μA ns CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V CGATE = 3 nF, VDL = VIN CGATE = 3 nF, VDL = 0 V 16 12 19 13 33 42 ns ns ns ns ns ns MUP to FB, VMAR = VMSEL = 5 V MDN to FB, VMAR = 5 V, VMSEL = 0 V 20 20 Ω Ω –200 +200 100 0 Pull-up to VCC Rev. B | Page 3 of 24 VVCC 200 mV ns V kΩ ADP1822 Parameter TRKN Pull-Down Resistance LOGIC THRESHOLDS (SHDN, SYNC, FREQ, MAR, MSEL) Input High Voltage Input Low Voltage SYNC, FREQ Input Leakage Current SHDN, MAR, MSEL Pull-Down Resistance THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PWGD OUTPUT FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis PWGD Off Current PWGD Low Voltage Conditions Min VVCC = 3.0 V to 5.5 V VVCC = 3.0 V to 5.5 V SYNC = FREQ = GND 2.0 VFB rising VFB rising VPWGD = 5 V IPWGD = 10 mA Rev. B | Page 4 of 24 Typ 200 0.1 100 Max 0.8 1 Unit kΩ V V μA kΩ 145 10 °C °C 750 35 550 35 mV mV mV mV μA mV 150 1 500 ADP1822 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC, SHDN, SYNC, FREQ, COMP, SS, FB, TRKP, TRKN, MAR, MSEL, MUP, and MDN to GND; PVCC to PGND; BST to SW BST to GND CSL to GND DH to GND DL to PGND SW to GND PGND to GND θJA, 2-Layer (SEMI Standard Board) θJA, 4-Layer (JEDEC Standard Board) Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Maximum Soldering Lead Temperature Rating −0.3 V to +6 V −0.3 V to +30 V −1 V to +30 V (VSW − 0.3 V) to (VBST + 0.3 V) −0.3 V to (VPVCC + 0.3 V) −2 V to +30 V ±2 V 122°C/W 82°C/W −40°C to +85°C −55°C to +125°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 24 ADP1822 SIMPLIFIED BLOCK DIAGRAM SHDN ADP1822 VCC UVLO LOGIC FAULT BST THERMAL SHUTDOWN GND DH FREQ S OSCILLATOR SYNC Q PWM COMP R MAR SW PVCC Q DL DECODE MSEL VCC PGND CSL MUP MDN TRKP DGND TRKN FB VREF 0.8V UV PWGD 2.5kΩ FAULT UVLO THSD Figure 3. Simplified Block Diagram Rev. B | Page 6 of 24 05311-002 SS OV REFERENCE 100kΩ ADP1822 BST 1 24 NC DH 2 23 PVCC SW 3 22 DL SYNC 4 21 PGND FREQ 5 20 CSL MAR 6 19 VCC TRKN 7 TRKP 8 SHDN ADP1822 TOP VIEW (Not to Scale) 18 MUP 17 MDN 9 16 MSEL PWGD 10 15 COMP DGND 11 14 FB GND 12 13 SS NC = NO CONNECT 05311-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic BST 2 DH 3 SW 4 SYNC 5 FREQ 6 MAR 7 TRKN 8 TRKP 9 SHDN 10 PWGD 11 12 13 DGND GND SS 14 FB 15 COMP 16 MSEL Description High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver DH. The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 μF or greater ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate driver. High-Side Gate Driver Output. Connect DH to the gate of the external high-side N-channel MOSFET switch. DH is powered from the capacitor between SW and BST and its voltage swings between VSW and VBST. Power Switch Node. SW is the power switching node. Connect the source of the high-side N-channel MOSFET switch and the drain of the low-side N-channel MOSFET synchronous rectifier to SW. SW powers the output through the output LC filter. Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the converter switching frequency to the applied signal. The maximum SYNC frequency is limited to 2× the nominal internal frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND. Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or high to select 600 kHz. Do not leave FREQ unconnected. Margin Control Input. MAR is used with MSEL to control output voltage margining. MAR chooses between high voltage and low voltage margining when MSEL is driven high. If not used, connect MAR to GND. Tracking Comparator Negative Input. Drive TRKN from the voltage that the ADP1822 output voltage tracks. TRKN voltage is limited to VCC. See the Output Voltage Tracking section. Tracking Comparator Positive Input. Drive TRKP from the output voltage. TRKP voltage is limited to VCC. See the Output Voltage Tracking section. Active Low DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter. Drive it low to turn it off. Connect SHDN to VCC for automatic startup. Open-Drain Power-Good Output. PWGD sinks current to GND when the output voltage is above or below the regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator. Digital Ground. Connect DGND to GND at a single point as close as possible to the IC. Analog Ground. Connect GND to PGND at a single point as close as possible to the IC. Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded, SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF to 1 μF capacitor from SS to GND to set the soft start period. See the Soft Start section. Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage. See the Setting the Output Voltage section. Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation control system. See the Compensation section. Margin Select Input. Drive MSEL high to activate the voltage margining feature. Drive MSEL low to regulate the output voltage to the nominal value. If not used, connect MSEL to GND. Rev. B | Page 7 of 24 ADP1822 Pin No. 17 Mnemonic MDN 18 MUP 19 VCC 20 CSL 21 22 PGND DL 23 PVCC 24 NC Description Margin Down Input. Connect a resistor from MDN to the output voltage to set the low margining voltage. See the Setting the Voltage Margin section. Margin Up Input. Connect a resistor from MUP to GND to set the high margining voltage. See the Setting the Voltage Margin section. Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with 0.1 μF or greater capacitor connected as close as possible to the IC. Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit. See the Setting the Current Limit section. Power Ground. Connect GND to PGND at a single point as close as possible to the IC. Low-Side Gate Driver Output. Connect DL to the gate of the low-side N-channel MOSFET synchronous rectifier. The DL voltage swings between PGND and PVCC. Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver DL. Bypass PVCC to PGND with 1 μF or greater capacitor connected as close as possible to the IC. No Connection. Not internally connected. Rev. B | Page 8 of 24 ADP1822 TYPICAL PERFORMANCE CHARACTERISTICS 0.6003 97 96 0.6002 FEEDBACK VOLTAGE (V) 3.3V OUTPUT 95 EFFICIENCY (%) 94 93 1.8V OUTPUT 92 91 90 0.6001 0.6000 0.5999 0.5998 89 0 2 4 6 8 10 12 14 LOAD CURRENT (A) –10 10 30 50 70 90 110 Figure 8. FB Regulation Voltage vs. Temperature 94 700 600 SWITCHING FREQUENCY (kHz) 92 3.3V OUTPUT 90 EFFICIENCY (%) –30 TEMPERATURE (°C) Figure 5. Efficiency vs. Load Current, VIN = 5 V, VOUT = 3.3 V, 1.8 V 88 1.8V OUTPUT 86 84 05311-007 82 80 05311-009 0.5996 –50 16 0 2 4 6 8 10 12 14 16 LOAD CURRENT (A) 600kHz 500 400 300 300kHz 200 100 0 –50 05311-010 87 0.5997 05311-006 88 0 50 100 TEMPERATURE (°C) Figure 6. Efficiency vs. Load Current, VIN = 12 V, VOUT = 3.3 V, 1.8 V Figure 9. Switching Frequency vs. Temperature 1400 OUTPUT VOLTAGE (20mV/DIV) 1000 800 600 400 200 0 05311-011 LOAD CURRENT (5A/DIV) 05311-008 VCC CURRENT (µA) 1200 0 1 2 3 4 5 6 VCC VOLTAGE (V) Figure 10. Load Transient Response, 1.5 A to 15 A Figure 7. VCC Supply Current vs. Voltage Rev. B | Page 9 of 24 ADP1822 OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (50mV/DIV) SHDN (5V/DIV) 05311-012 Figure 11. Power-On Response 05311-015 INPUT VOLTAGE (5V/DIV) PWGD (5V/DIV) Figure 14. Line Transient Response, 10 V to 16 V OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (100mV/DIV) SHDN (5V/DIV) 05311-013 Figure 12. Power-On Response, Prebiased Output 05311-016 MAR VOLTAGE (5V/DIV) PWGD (5V/DIV) Figure 15. Output Voltage Margin-Down Response OUTPUT VOLTAGE (100mV/DIV) OUTPUT VOLTAGE (1V/DIV) LOAD CURRENT (10A/DIV) Figure 13. Output Short-Circuit Response and Recovery 05311-017 05311-014 MAR VOLTAGE (5V/DIV) Figure 16. Output Voltage Margin-Up Response Rev. B | Page 10 of 24 ADP1822 TRACKING VOLTAGE (1V/DIV) 05311-018 OUTPUT VOLTAGE (1V/DIV) Figure 17. Output Voltage Tracking Response Rev. B | Page 11 of 24 ADP1822 THEORY OF OPERATION The ADP1822 is a versatile, economical, synchronous-rectified, fixed frequency, voltage-mode, pulse-width modulated (PWM) step-down controller capable of generating an output voltage as low as 0.6 V. It is ideal for a wide range of high power applications, such as DSP and processor core power in telecom, medical imaging, and industrial applications. The ADP1822 controller runs from 3.0 V to 5.5 V and accepts a power input voltage between 1.0 V and 20 V. The ADP1822 includes circuitry to implement output voltage margining and can track an external voltage, making it ideal for high reliability applications with multiple dc-to-dc converters. It operates at a fixed, internally set 300 kHz or 600 kHz switching frequency that is controlled by the state of the FREQ input. The high frequency reduces external component size and cost while maintaining high efficiency. For noise sensitive applications where the switching frequency needs to be more tightly controlled, synchronize the ADP1822 to an external signal whose frequency is between 300 kHz and 1.2 MHz. OUTPUT VOLTAGE MARGINING The ADP1822 features output voltage margining. MAR enables voltage margining, and MSEL controls whether the voltage is margined up or down. The voltage is margined by switching a resistor from FB to GND (for the high margin) or from FB to the output voltage (for the low margin). The switches from FB are internal to the ADP1822 through the MUP and MDN terminals. Table 4 shows the states of MAR and MSEL and the resulting voltage margin setting. See the Setting the Voltage Margin section for more information. Table 4. Voltage Margining Control MSEL X H L MAR L H H Voltage Margin None (FB not changed) High margin (FB connected to MUP) Low margin (FB connected to MDN) OUTPUT VOLTAGE TRACKING The ADP1822 includes adjustable soft start with output reversecurrent protection, and a unique, adjustable, lossless current limit. It operates over the −40°C to +85°C temperature range and is available in a space-saving, 24-lead QSOP package. CURRENT-LIMIT SCHEME The ADP1822 employs a unique, programmable cycle-by-cycle lossless current-sensing scheme that uses an inexpensive resistor to set the current limit. A 50 μA current source is forced out of CSL to a programming resistor connected to SW. The resulting voltage across the current sense resistor sets the current-limit threshold. When on-state voltage of the low-side MOSFET synchronous rectifier exceeds the programmed threshold, the low-side MOSFET remains on, preventing another on cycle and reducing the inductor current. Once the MOSFET voltage and thus the inductor current is below the current-sense threshold, the synchronous rectifier is allowed to turn off and another cycle begins. When the ADP1822 senses an overcurrent condition, SS sinks current from the soft start capacitor through an internal 2.5 kΩ resistor, reducing the voltage at SS and thus reducing the regulated output voltage. The ADP1822 remains in this mode for as long as the over-current condition persists. When the over-current condition is removed, operation resumes in soft start mode. This ensures that when the overload condition is removed, the output voltage smoothly transitions back to regulation while providing protection for overload and shortcircuit conditions. The ADP1822 features an internal comparator that forces the output voltage to track an external voltage at startup, which prevents the output voltage from exceeding the tracking voltage. The comparator turns off the high-side switch if the positive tracking (TRKP) input voltage exceeds the negative tracking (TRKN) input voltage. Connect TRKP to the output voltage and drive TRKN with the voltage to be tracked. If the voltage at TRKN is below the regulation voltage, the output voltage is limited to the voltage at TRKN. If the voltage at TRKN is above the regulation voltage, the output voltage regulates the desired voltage set by the voltage divider. For more information, see the Setting the Output Voltage Tracking section. SOFT START When powering up or resuming operation after shutdown, overload, or short-circuit conditions, the ADP1822 employs an adjustable soft start feature that reduces input current transients and prevents output voltage overshoot at start-up and overload conditions. The soft start period is set by the value of the soft start capacitor, CSS, between SS and GND. When starting the ADP1822, CSS is initially discharged. It is enabled by either driving SHDN high or by bringing VCC above the undervoltage lockout threshold, and CSS begins charging to 0.8 V through an internal 100 kΩ resistor. As CSS charges, the regulation voltage at FB is limited to the lesser of either the voltage at SS or the internal 0.6 V reference voltage. As the voltage at SS rises, the output voltage rises proportionally until the voltage at SS exceeds 0.6 V. At this time, the output voltage is regulated to the desired voltage. Rev. B | Page 12 of 24 ADP1822 If the output voltage is precharged prior to turn-on, the ADP1822 prevents reverse inductor current that would discharge the output voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage, the reverse current is re-enabled to allow the output voltage regulation to be independent of load current. to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage is set to voltages as low as 0.6 V and as high as 85% of the minimum power input voltage (see the Feedback Voltage Divider section). To override the soft start feature, leave SS unconnected. This allows the output voltage to rise as quickly as possible and eliminates the soft start period. The ADP1822 has a logic-controlled frequency select input, FREQ, that sets the switching frequency to 300 kHz or 600 kHz. Drive FREQ low for 300 kHz and drive it high for 600 kHz. HIGH-SIDE DRIVER (BST AND DH) The SYNC input is used to synchronize the converter switching frequency to an external signal. The synchronization range is 300 kHz to 1.2 MHz. The acceptable synchronization frequency range is limited to twice the nominal switching frequency set by FREQ. For lower frequency synchronization, between 300 kHz and 600 kHz, connect FREQ to GND. For higher frequency synchronization, between 480 kHz and 1.2 MHz, connect FREQ to VCC (see the Synchronizing the Converter section for more information). Gate drive for the high-side power MOSFET is generated by a flying capacitor boost circuit. This circuit allows the high-side N-channel MOSFET gate to be driven above the input voltage, allowing full enhancement of and a low voltage drop across the MOSFET. The circuit is powered from a flying capacitor from SW to BST that in turn is powered from the PVCC gate driver voltage. When the low-side switch is turned on, SW is driven to PGND, and the flying capacitor is charged from PVCC through an external Schottky rectifier. The capacitor stores sufficient charge to power BST to drive DH high and to fully enhance the high-side N-channel MOSFET. Use a flying capacitor value greater than 100× the high-side MOSFET input capacitance. LOW-SIDE DRIVER (DL) DL is the gate drive for the low-side power MOSFET synchronous rectifier. Synchronous rectification reduces conduction losses developed by a conventional rectifier by replacing it with a low resistance MOSFET switch. DL turns on the synchronous rectifier by driving the gate voltage to PVCC. The MOSFET is turned off by driving the gate voltage to PGND. An active dead time reduction circuit reduces the break-beforemake time of the switching to limit the losses due to current flowing through the synchronous rectifier body diode or external Schottky rectifier. INPUT VOLTAGE RANGE The ADP1822 takes its internal power from the VCC and PVCC inputs. PVCC powers the low-side MOSFET gate drive (DL), and VCC powers the internal control circuitry. Both of these inputs are limited to between 3.0 V and 5.5 V. Bypass PVCC to PGND with a 1 μF or greater capacitor. Bypass VCC to GND with a 0.1 μF or greater capacitor. The power input to the dc-to-dc converter can range between 1.2× the output voltage up to 24 V. Bypass the power input to PGND with a suitably large capacitor. See the Selecting the Input Capacitor section. SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider drops the output voltage SWITCHING FREQUENCY CONTROL COMPENSATION The control loop is compensated by an external series RC network from COMP to FB and sometimes requires a series RC in parallel with the top voltage divider resistor. COMP is the output of the internal error amplifier. The internal error amplifier compares the voltage at FB to the internal 0.6 V reference voltage. The difference between the two (the feedback voltage error) is amplified by the error amplifier. To optimize the ADP1822 for stability and transient response for a given set of external components and input/output voltage conditions, choose the compensation components. For more information on choosing the compensation components, see the Compensating the Regulator section. POWER-GOOD INDICATOR The ADP1822 features an open-drain power-good output, PWGD, that sinks current when the output voltage drops 8.3% below or 25% above the nominal regulation voltage. Two comparators measure the voltage at FB to set these thresholds. The PWGD output also sinks current if overtemperature or input undervoltage conditions are detected. It is operational with VCC voltage as low as 1.0 V. Use this output as a simple power-good signal by connecting a pull-up resistor from PWGD to an appropriate supply voltage. SHUTDOWN CONTROL The ADP1822 dc-to-dc converter features a low power shutdown mode that reduces quiescent supply current to 1 μA. To shut down the ADP1822, drive SHDN low. To turn it on, drive SHDN high. For automatic startup, connect SHDN to VCC. Rev. B | Page 13 of 24 ADP1822 APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR The input capacitor absorbs the switched input current of the dc-to-dc converter, allowing the input source to deliver smooth dc current. Choose an input capacitor whose impedance at the switching frequency is lower than the input source impedance. Use low equivalent series resistance (ESR) capacitors, such as low ESR tantalum, ceramic, or organic electrolyte (such as Sanyo OS-CON) types. For all types of capacitors, make sure that the current rating of the capacitor is greater than the input rms ripple current, which is approximately I IN_RMS ≅ I LOAD × VOUT VIN × −1 VIN VOUT (1) OUTPUT LC FILTER The output LC filter smoothes the switched voltage at SW, making the output an almost dc voltage. Choose the output LC filter to achieve the desired output ripple voltage. Since the output LC filter is part of the regulator negative-feedback control loop, the choice of the output LC filter components affects the regulation control-loop stability. Choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current. Using a larger value inductor results in a physical size larger than required, and using a smaller value results in increased losses in the inductor and/or MOSFET switches. Choose the inductor value by L= ⎡ V ⎤ 1 VOUT ⎢1 − OUT ⎥ ( f SW )(ΔI L ) VIN ⎦ ⎣ (2) where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. ΔIL is the inductor ripple current, typically 1/3 of the maximum dc load current. Choose the output capacitor to set the desired output voltage ripple. The ADP1822 functions with output capacitors that have both high and low ESR. For high ESR capacitors, such as tantalum or electrolytic types, many parallel connected capacitors may be required to achieve the desired output ripple voltage. When choosing an output capacitor, consider ripple current rating, capacitance, and ESR. Make sure that the ripple current rating is higher than the maximum inductor ripple current (ΔIL). The output ripple voltage is a function of the inductor ripple current and the capacitor impedance at the switching frequency. For high ESR capacitors, the impedance is dominated by the ESR, while for low ESR capacitors the impedance is dominated by the capacitance. Determine if the capacitor is high ESR or low ESR by comparing the zero frequency formed by the capacitance and the ESR to the switching frequency: f ESRZ = 1 2π(COUT )(ESR ) (3) where: fESRZ is the frequency of the output capacitor ESR zero. COUT is the output capacitance. ESR is the equivalent series resistance of the capacitor. If fESRZ is much less than the switching frequency, then the capacitor is high ESR, and the ESR dominates the impedance at the switching frequency. If fESRZ is much greater than the switching frequency, the capacitor is low ESR, and the impedance is dominated by the capacitance at the switching frequency. When using capacitors whose impedance is dominated by ESR at the switching frequency (such as tantalum or aluminum electrolytic capacitors), approximate the output voltage ripple current by ΔVOUT ≅ ΔI L (ESR) (4) where: ΔVOUT is the output ripple voltage. ΔIL is the inductor ripple current. ESR is the total equivalent series resistance of the output capacitor (or the parallel combination of ESR of all parallelconnected output capacitors). Make sure that the ripple current rating of the output capacitor(s) is greater than the maximum inductor ripple current. For output capacitors whose ESR is much lower than the capacitive impedance at the switching frequency, the capacitive impedance dominates the output ripple current. In this case, determine the ripple voltage by ΔVOUT ≅ ΔI L 8(COUT )( f SW ) where: fSW is the switching frequency. COUT is the output capacitance. Rev. B | Page 14 of 24 (5) ADP1822 When fESRZ is approximately the same as the switching frequency, the square-root sum of the squares of the two ripples applies, or ΔVOUT ⎤ ⎡ ΔI L ≅ [ΔI L (ESR)] + ⎢ ⎥ ⎣ 8(COUT )( f SW ) ⎦ 2 2 (6) SELECTING THE MOSFETS The choice of MOSFET directly affects the dc-to-dc converter performance. The MOSFET must have low on resistance to reduce I2R losses and low gate charge to reduce transition losses. In addition, the MOSFET must have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on time and carries all the transitions losses of the converter. Typically, the lower the MOSFET on resistance, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by ⎛V PC ≅ (I LOAD )2 (RON )⎜⎜ OUT ⎝ VIN ⎞ ⎟ ⎟ ⎠ (7) ⎤ ⎡ V PLS ≅ (I LOAD )2 (RON )⎢1 − OUT ⎥ VIN ⎦ ⎣ The gate-charging loss is approximated by (8) where: PT = gate-charging loss power. VPVCC = gate driver supply voltage. QG = MOSFET total gate charge. fSW = converter switching frequency. where: PLS is the low-side MOSFET on resistance. RON is the total on resistance of the low-side MOSFET(s). If multiple low-side MOSFETs are used in parallel, use the parallel combination of the on resistances for determining RON to solve this equation. SETTING THE CURRENT LIMIT The current limit is set through the current-limit resistor, RCL. The current sense pin, CSL, sources 50 μA through RCL. This creates an offset voltage of resistance of RCL multiplied by the 50 μA CSL current. When the low-side MOSFET voltage is equal to or greater than the offset voltage, the ADP1822 is in current limit mode and prevents additional on-time cycles. Choose the current limit resistor by the equation The high-side MOSFET transition loss is approximated by PSW V ×I × (t R + t F )× f SW = IN LOAD 2 RCL = 42 μA (12) where: ILPK is the peak inductor current. RONWC is the worst-case (maximum) low-side MOSFET on resistance. The total power dissipation of the high-side MOSFET is the sum of all the previous losses, or where PHS is the total high-side MOSFET power loss. (I LPK )(RONWC ) (9) where: PSW = high-side MOSFET switching loss power. tR = MOSFET rise time. tF = MOSFET fall time. PHS ≅ (PC ) + (PT ) + (PSW ) (11) The internal current-limit circuit measures the voltage across the low-side MOSFET to determine the load current. When the low-side MOSFET current exceeds the current limit, the highside MOSFET is not allowed to turn on until the current drops below the current limit. where: PC = conduction power loss. RON = MOSFET on resistance. PT ≅ (VPVCC )(QG )( f SW ) The low-side MOSFET does not carry the transition losses but does carry the inductor current when the high-side MOSFET is off. For high input and low output voltages, the low-side MOSFET carries the current most of the time, and therefore to achieve high efficiency, it is critical to optimize the low-side MOSFET for low on resistance. In some cases, where the power loss exceeds the MOSFET rating, or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET power loss is (10) The worst-case, low-side MOSFET on resistance can be found in the MOSFET data sheet. Note that MOSFETs typically increase on resistance with increasing die temperature. To determine the worst-case MOSFET on resistance, calculate the worst-case MOSFET temperature (based on the MOSFET power loss) and multiply by the ratio between the typical on resistance at that temperature and the on resistance at 25°C as listed in the MOSFET data sheet. Rev. B | Page 15 of 24 ADP1822 FEEDBACK VOLTAGE DIVIDER The output regulation voltage is set through the feedback voltage divider. The output voltage is reduced through the voltage divider and drives the FB feedback input. The regulation threshold at FB is 0.6 V. For the low-side resistor of the voltage divider, RBOT, use 10 kΩ. A larger value resistor can be used but results in a reduction in output voltage accuracy. Choose RTOP to set the output voltage by ⎛V − VFB ⎞ ⎟ RTOP = RBOT ⎜⎜ OUT ⎟ VFB ⎝ ⎠ (13) where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V. For example, for an output voltage of 1.0 V and a ±5% margin, choose RBOT = 10 kΩ Thus, ⎡V − VFB ⎤ RTOP = RBOT ⎢ OUT ⎥ = 6.67 kΩ ⎣ VFB ⎦ RUP = K MUP = 80 kΩ ⎤ ⎡R ⎤⎡ V RDN = ⎢ TOP ⎥ ⎢1 − FB − K MDN ⎥ = 46.7 kΩ K V OUT ⎣ MDN ⎦ ⎣ ⎦ Choose the high margin resistor by (14) (18) (19) COMPENSATING THE REGULATOR The output of the error amplifier at COMP is used to compensate the regulation control system. Connect a resistor capacitor (RC) network from COMP to FB to compensate the regulator. The first step of selecting the compensation components is determining the desired regulation-control crossover frequency, fCO. Choose a crossover frequency approximately 1/10 of the switching frequency, or f CO = where: RUP is the up-margin resistor from MUP to GND. RBOT is the bottom voltage divider resistor from FB to GND. RTOP is the top voltage divider resistor from FB to the output voltage. KMUP is the high voltage margin as a ratio of the output voltage (for example, margining 4% up would be KMUP = 0.04). f SW 10 (20) The characteristics of the output capacitor affect the compensation required to stabilize the regulator. The output capacitor acts with its ESR to form a zero. Calculate the ESR zero frequency by f ESRZ = 1 2π(COUT )( ESR ) (21) Note that as similar capacitors are placed in parallel, the ESR zero frequency remains the same. Choose the low margin resistor by the equation ⎤ ⎡R ⎤⎡ V RDN = ⎢ TOP ⎥ ⎢1 − FB − K MDN ⎥ ⎣ K MDN ⎦ ⎣ VOUT ⎦ ⎡ (RTOP )(RBOT ) ⎤ ⎢ ⎥ ⎣ RTOP + RBOT ⎦ and The output voltage is margined by connecting a resistor from FB to GND (for the high margin voltage) or FB to the output voltage (for low margin voltage). The switches for margining are supplied inside the ADP1822 and are controlled by the MAR and MSEL inputs (see Table 1). RUP (17) and SETTING THE VOLTAGE MARGIN ⎡ (RTOP )(R BOT ) ⎤ ⎢ ⎥ R + R BOT ⎦ = ⎣ TOP K MUP (16) (15) where: RDN is the down-margin resistor. RTOP is the top voltage divider resistor from FB to the output voltage. VFB is the 0.6 V feedback voltage. VOUT is the nominal output voltage setting. KMDN is the down-margin as a ratio of the nominal output voltage (for example, margining 4% down would be KMDN = 0.04). If fESRZ ≤ fCO/2, use the ESR zero to stabilize the regulator (see the Compensation Using the ESR Zero section). If fESRZ ≥ 2fCO, use a feed-forward network to stabilize the regulator (see the Compensation Using Feed-Forward section). If fCO/2 < fESRZ < 2fCO, then use both the ESR zero and feed-forward zeros to stabilize the regulator (see the Compensation Using Both the ESR and Feed-Forward Zeros section). Rev. B | Page 16 of 24 ADP1822 In all three cases, it is sometimes beneficial, although not required, to add an additional compensation capacitor, CC2, from COMP to FB to reduce high frequency noise. This capacitor forms an extra pole in the loop response. Choose this capacitor such that the pole occurs at approximately 1/2 of the switching frequency, or FPC 2 = f SW 1 = 2 2π(CCOMP // CC 2 )(RCOMP ) f ZC = (28) CCOMP = 4 (29) 2π( f CO )(RCOMP ) In terms of the switching frequency and combining the constants, 2 (23) 2π( f SW )(RCOMP ) Compensation Using the ESR Zero 6.37 CCOMP ≅ ( f SW )(RCOMP ) CCOMP = 2 2π( f LC )(RCOMP ) (30) or CC2 VOUT RCOMP f LC 1 = 2 2π(CCOMP )(RCOMP ) Solving for CCOMP, (22) Assuming CCOMP >> CC2, then solving for CC2, CC 2 = or CCOMP (31) RTOP or whichever is greater. 0.6V INTERNAL ERROR AMPLIFIER Compensation Using Feed-Forward RBOT CC2 VOUT RCOMP CCOMP Figure 18. Compensation Using the ESR Zero RTOP COMP If the output capacitor ESR zero is sufficiently low (less than or equal to 1/2 of the crossover frequency), use the ESR to stabilize the regulator. In this case, use the circuit shown in Figure 16. Choose the compensation resistor to set the desired crossover frequency, typically 1/10 of the switching frequency or RCOMP = (RTOP )(VRAMP )( f ESRZ )( f CO ) 2 VIN ( f LC ) (24) where: RCOMP is the compensation resistor. VRAMP is the internal ramp peak voltage, 1.25 V. fESRZ and fCO are the ESR zero and crossover frequencies. VIN is the dc input voltage. fLC is the characteristic frequency of the output LC filter, or f LC = 1 2π LC (25) 4.9(RTOP )( f ESRZ )( f SW )(L )(C ) VIN f ZC 0.6V RFF RBOT INTERNAL ERROR AMPLIFIER Figure 19. Compensation Using Feed-Forward If the ESR zero is at too high a frequency to be useful in stabilizing the regulator, add a series RC network, as shown in Figure 17, in parallel with the top side voltage divider resistor, RTOP. This adds an additional zero and pole pair that is used to increase the phase at crossover, thus improving stability. Choose the feed-forward zero frequency for 1/7 of the crossover frequency, and the feed-forward pole at 7× the crossover frequency. This sets the ratio of pole-to-zero frequency of approximately 50:1 for optimum stability. RCOMP = (26) Choose the compensation capacitor to set the compensation zero, fZC, to the lesser of 1/4 of the crossover frequency or 1/2 of the LC resonant frequency, or f f 1 = CO = SW = 4 40 2π(CCOMP )(RCOMP ) TO PWM CFF Choose the compensation resistor, RCOMP, to set the crossover frequency by using known constants RCOMP ≅ FB 05311-004 TO PWM FB 05311-003 COMP (RTOP )(VRAMP )( f ZFF )( f CO ) VIN ( f LC )2 (32) where fZFF is the feed-forward zero frequency and is 1/7 of the crossover frequency. Simplify the following equation: (27) Rev. B | Page 17 of 24 RCOMP ≅ 0.0705 (RTOP )( f SW )2 (L )(C ) VIN (33) ADP1822 Choose the compensation capacitor to set the compensation zero, fZC, to the lesser of 1/4 of the crossover frequency or 1/2 of the LC resonant frequency, or f ZC = f CO f SW 1 = = 4 40 2π(CCOMP )(RCOMP ) (34) f LC 1 = 2 2π(CCOMP )(RCOMP ) (35) or f ZC = Compensation Using Both the ESR and Feed-Forward Zeros If the output capacitor ESR zero frequency falls between 1/2 of the crossover frequency to 2× the crossover frequency, use the circuit shown in Figure 18, such that the ESR zero along with a feed-forward network stabilizes the regulator. In this case, the feed-forward zero is set to 1/7 of the crossover frequency, and the feed-forward pole is set to the same frequency as the ESR zero. Choose the compensation resistor, RCOMP, to set the crossover frequency by Solving for CCOMP, CCOMP = 4 2π( f CO )(RCOMP ) RCOMP = (36) In terms of the switching frequency and combining the constants, CCOMP ≅ 6.37 ( f SW )(RCOMP ) 2 2π( f LC )(RCOMP ) RCOMP ≅ 0.0705 (38) f ZC = Choose the feed-forward capacitor, CFF, to set the feed-forward zero at 1/7 of the crossover frequency f CO 7 (39) or f CO = 7 2π(RTOP )(C FF ) 11.14 (RTOP )( f SW ) 1 7(2π )(RFF )(C FF ) RFF f LC 1 = 2 2π(CCOMP )(RCOMP ) CCOMP = (46) 2 2π( f LC )(RCOMP ) (47) Choose the feed-forward capacitor, CFF, to set the feed-forward zero at 1/7 of the crossover frequency f ZFF = f CO = (41) f CO 7 (48) 7 2π(RTOP )(C FF ) (49) Simplifying and solving for CFF, C FF = (42) 11.14 (RTOP )( f SW ) (50) Choose the feed-forward resistor, RFF, to set the condition Simplifying and solving for RFF, 0.227 = ( f SW )(C FF ) (45) or Choose the feed-forward resistor, RFF, to set the condition f CO = VIN Solving for CCOMP, (40) Simplifying and solving for CFF, C FF = (RTOP )( f SW )2 (L )(C ) Choose the compensation capacitor to set the compensation zero, fZC, to 1/2 of the LC resonant frequency, or or whichever is greater. f ZFF = (44) where fZFF is the feed-forward zero frequency and is 1/7 of the crossover frequency. Simplify the following equation: (37) or CCOMP = (RTOP )(VRAMP )( f ZFF )( f CO ) VIN ( f LC )2 f CO = (43) 1 7(2π )(RFF )(C FF ) (51) Simplifying and solving for RFF, RFF = Rev. B | Page 18 of 24 0.227 ( f SW )(C FF ) (52) ADP1822 SETTING THE SOFT START PERIOD The ADP1822 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. The soft start is set by selecting the capacitor, CSS, from SS to GND. The ADP1822 charges CSS to 0.8 V through an internal resistor. The voltage on CSS while it is charging is VCSS 1 ⎛ = 0.8 V⎜1 − e RCSS ⎜ ⎝ ⎞ ⎟ ⎟ ⎠ (53) where R is the internal 100 kΩ resistor. The soft start period, tSS, is achieved when VCSS = 0.6 V, or t SS ⎞ ⎛ 0.6 V = 0.8 V⎜1 − e 100 kΩ (CSS ) ⎟ ⎟ ⎜ ⎠ ⎝ (54) ⎛ t SS 0.6 V ⎞ ⎟ = 1.386 = − ln⎜⎜1 − 100 kΩ(C SS ) 0.8 V ⎟⎠ ⎝ (55) The high-side MOSFET turn-on follows the rising edge of the SYNC input by approximately 320 ns. To prevent erratic switching frequency, make sure that the falling edge of the SYNC input signal does not coincide with the falling edge of the dc-to-dc converter switching, or DSYNC ≠ [(320 ns )( f SW )] + VOUT VIN (57) where DSYNC is the duty cycle of the synchronization waveform. Make sure that in all combinations of frequency, input, and output voltages, the SYNC input fall time does not align with the dc-to-dc converter fall time. SETTING THE OUTPUT VOLTAGE TRACKING SYNCHRONIZING THE CONVERTER The ADP1822 provides a tracking function that limits the output voltage to or below an external tracking voltage. This is useful in systems where multiple dc-to-dc converters are used to power different sections of a circuit, such as a microcontroller or a DSP that has separate I/O and core voltages. In similar circuits, if the nominally lower of the two voltages exceeds the nominally higher voltage at startup or shutdown, the circuit powered may experience problems. To prevent this, use the tracking feature of the ADP1822 to limit the output voltage to or below the tracking voltage at all times. The dc-to-dc converter switching can be synchronized to an external signal. This allows multiple ADP1822 converters to be operated at the same frequency to prevent frequency beating or other interactions. To use the tracking feature, connect TRKP to the output voltage and drive TRKN with the tracking voltage. To ensure that noise does not cause unstable operation, connect a 1 nF capacitor between TRKN and TRKP as close to the ADP1822 as possible. To synchronize the ADP1822 switching to an external signal, drive the SYNC input with the synchronizing signal. The ADP1822 can only synchronize up to 2× the nominal oscillator frequency. If the frequency is set to 300 kHz (FREQ connected to GND), it can synchronize up to 600 kHz. If the frequency is set to 600 kHz (FREQ connected to VCC), it can synchronize to 1.2 MHz. If either the ADP1822 output voltage or the tracking voltage at any time exceeds the voltage at VCC, use equal voltage dividers from the output voltage to TRKP and from the tracking voltage to TRKN to prevent overstress on the TRKP and TRKN inputs. or Solving for CSS and combining constants, CSS = (7.213 × 10−6)tSS (56) Rev. B | Page 19 of 24 ADP1822 APPLICATION CIRCUITS CMOSH-3 VCC 1µF BST VCC ADP1822 0.1µF DH SW SHDN 3.01kΩ CSL FREQ DL SYNC 2.2pF TRKP TRKN COMP MDN SS AGND DGND MUP OUTPUT 1.8V, 15A 20kΩ 1nF 158kΩ MSEL 309pF 4× 1000µF, 4V FB MAR 80.6kΩ 1µH PGND PWGD 15pF 3× IRF3711 INPUT 5V 10kΩ 316kΩ 100nF TRACKING SIGNAL INPUT 05311-019 1µF 2× 180µF 20V 10Ω 10Ω Figure 20. Typical Application Circuit, 5 V Input CMST2222A CMOZ5V6 1.2kΩ CMOSH-3 VCC 1µF CSL FREQ DL SYNC PWGD MAR MSEL 80.6kΩ 0.1µF 3.01kΩ Q1 IRF3711 2.2pF PGND 1µH 2× IRF3711 4× 1000µF, 4V OUTPUT 1.8V, 15A 20kΩ FB TRKP TRKN MDN SS AGND DGND MUP COMP 309pF DH SW SHDN 15pF BST VCC ADP1822 INPUT 12V 1nF 158kΩ 10kΩ 316kΩ 100nF TRACKING SIGNAL INPUT Figure 21. Typical Application Circuit, 12 V Input Rev. B | Page 20 of 24 05311-020 1µF 2× 180µF 20V 10Ω ADP1822 OUTLINE DIMENSIONS 0.345 0.341 0.337 24 13 1 0.158 0.154 0.150 12 0.244 0.236 0.228 PIN 1 0.069 0.053 0.065 0.049 0.010 0.004 0.025 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AE Figure 22. 24-Lead Shrink Small Outline Package [QSOP] (RQ-24) Dimensions shown in inches ORDERING GUIDE Model ADP1822ARQZ-R7 1 1 Temperature Range –40°C to +85°C Package Description 24-Lead Shrink Small Outline Package (QSOP) Z = Pb-free part. Rev. B | Page 21 of 24 Package Option RQ-24 ADP1822 NOTES Rev. B | Page 22 of 24 ADP1822 NOTES Rev. B | Page 23 of 24 ADP1822 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05311-0-8/06(B) Rev. B | Page 24 of 24